Quanta NA1 Schematics

Docking(RQ7)

USB (USB4) 1394 X1 LAN 10/100/1G MODEM Audio/Spdif JACK

DVI

CRT/S-Video Parallel/Serial Port DVI Port PS2 Port *2 Battery Charger

DVI / 7307 Chrontel

PG 41

DDRII-SODIMM1

DDRII-SODIMM2

FINGER PRINT

USB8

Bluetooth

USB6

USB PORT X 4

USB0~1 USB2~3

Modularity

PATA ODD/HDD SATA HDD AUX Battery USB FDD

Internal HDD

(USB5)

PG12, 13

PG 12,13

PG 38

PG 36

PG 35 PG 31

PG 34

TPM

PG 40

SDVO

DDRII 533/667 MHz

2nd

1st

PG 38

FAN

PG 3

PATA SATA

32.768KHz

IT8512

LQFP 128

Touchpad

PG 38

32.768KHz

LPC

Keyboard

Merom

(478 Micro-FCPGA)

Crestline

1299 uFCBGA

ICH8-M

676 BGA

PG 37

SPI FLASH

PG 38

FSB

667/800 MHz

PG 5,6,7,8,9,10,11

DMI LINK

4X PCI-E

PG14,15,16,17

SIO PC87383

PG 37

PG 3,4

PCI-EXPRESS

MDC Module 1.5

PG 39

14.318MHz

CLOCK GEN

ICS9LPRS365 64pins

CPU THERMAL SENSOR

VIDEO RAM *4

DDRII

64bit/256MB

ATI

M71-s/M72-s

27MHz

PG 18,19,20,21,22

FOR Crestline (LCD/CRT/S-VIDEO)

33MHZ, 3.3V PCI

PCI-E Azalia

PG 32

WIRE

RJ11 JACK

PG 28

JACK

HEADPHONE, 2ND HEADPHONE, MIC

Audio Board

PG 2

PG 3

PG 23,24

WIRE

Azalia

STAC9200

PG 31

Amplifier

MAX9789A

PG 31

DVI

LCD Panel

CRT

S-Video

Intel 82566

25MHz

WIRE

RJ45 JACK

PG 28

NA1 BLOCK DIAGRAM

Merom / Crestline / ICH8-M

MAX1993 VGACORE (1.1V/1.2V)

2.5V

SYSTEM POWER(3/5V)

CPU CORE POWER ISL6262A

+1.5V

PG 25

PG 26

MINI PCI-E Card * 2

USB7 USB9

PG 27

SIM Card

PG 33

WIRE

Smart Card

PG 33

PG 30

+1.05V/+1.25V

+1.8VSUS/+0.9V

CHARGER MAX8724 & SELECTER

PG 45,46

DISCHARGE

24.576MHz

CARDBUS / IEEE 1394 CONTROLLER/CF

PCI7612

4 IN 1

CARD READER SD/MMC, MS,XD

PG 30

CARDBUS SLOT X1

PG 29

PCI DEVICES IRQ ROUTING

IDSEL #

DEVICE

CardBus/1394

SizeDocument NumberRev

01 -- Block Diagram

Date:Sheet of

Quanta Computer Inc.

REQ/GNT #

AD25

PROJECT : NA1

155Friday, March 23, 2007

PG 53

PG 52

PG 51

PG 50

PG 49

PG 48

PG 47

PG 44

PG 29

1394 CONN

PG 29

PCI_INT

A,B,C,D

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L43

+3.3V_M

BLM21PG600SN1D

iAMT

SATA_CLKREQ#[16]

MINI1CLK_REQ#[33]

PCI_CLK_8512[37]

PCI_CLK_SIO[39]

PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.

PCI_CLK_7612[29]

CLK_PCI_TPM[38]

PCLK_LPC_DEBUG[33]

PCI4/27_Select: 1=27MHz,0=SRC_100MHz of Pin17 & Pin18.

CLK_PCI_ICH[15]

PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock.If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8(Default is setting to SRC8)

CLK_7612_48M[29]

CLK_ICH_48M[16] CPU_MCH_BSEL0[3,6] CPU_MCH_BSEL1[3,6]

CPU_MCH_BSEL2[3,6] CLK_ICH_14M[16] CLK_SIO_14M[39]

C403

10U/6.3V/X5R_8

+3.3V

Layout Note: XTAL length < 500mils

+3.3V

R627*10K_4@EVR627*10K_4@EV

PCLK_LPC_DEBUG

R32010K_4@IVR32010K_4@IV

R32110K_4R32110K_4

CLK_PCI_ICH

R626*10K_4@NCR626*10K_4@NC

C41033P/50V_4C41033P/50V_4

C41333P/50V_4C41333P/50V_4

SATA_CLKREQ# MINI1CLK_REQ#

R62810K_4R62810K_4

PCI_CLK_8512

PCI_CLK_7612 CLK_PCI_TPM

CLK_7612_48M

CLK_ICH_48M

CLK_ICH_14M CLK_SIO_14M

C4170.1U/10V_4C4170.1U/10V_4

+CK_VDD_MAIN2

C4080.1U/10V_4C4080.1U/10V_4 C419

C419

4.7U/10V/X5R_8

C7040.1U/10V_4C7040.1U/10V_4 C4050.1U/10V_4C4050.1U/10V_4

C4060.1U/10V_4C4060.1U/10V_4

C4160.1U/10V_4C4160.1U/10V_4

14.318MHZ

R36933_4R36933_4

R29533_4R29533_4 R6252.2K_4R6252.2K_4

R60010K_4R60010K_4 R59915_4R59915_4 R60115_4R60115_4

+CK_VDD_MAIN

R278

475_4

R324

475_4

R29015_4R29015_4 R28915_4R28915_4 R29133_4R29133_4 R29233_4R29233_4 R29333_4R29333_4

R29433_4R29433_4

C412

SATACLKREQ#_R MINI1CLK_REQ#_R

PCLK_2_R

PCI_CLK_7612_R

FCTSEL1

FCTSEL1 PCI_ICH CG_XIN CG_XOUT FSA

FSC

C412

4.7U/10V/X5R_8

U14

VDD_PCI

VDD_48

VDD_PLL3

VDD_REF

VDD_SRC

VDD_CPU

VDD_96_IO

VDD_PLL3_IO

VDD_SRC_IO_1

VDD_SRC_IO_2

VDD_CPU_IO

VDD_SRC_IO_3

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/27MHz_Select

PCIF5/ITP_EN

XTAL_IN

XTAL_OUT

USB_48/FSA

FSB/TEST/MODE

REF0/FSC/TESTSEL

VSS_PCI

VSS_48

VSS_IO

VSS_PLL3

VSS_CPU

VSS_SRC1

VSS_SRC2

VSS_SRC3

VSS_REF

C409

0.1U/10V_4

Clock Gen

CK505

EC C-01

SRC1/SE1/27MHz_NonSS

CKPWRGD/PWRDWN#

ICS9LPRS365BGLFT/SLG8SP512

Add capacitor pads for improving WWAN.

C474*27P/50V@NCC474*27P/50V@NC C427*27P/50V@NCC427*27P/50V@NC C693*27P/50V@NCC693*27P/50V@NC C692*27P/50V@NCC692*27P/50V@NC

C42615P/50VC42615P/50V C425*27P/50V@NCC425*27P/50V@NC C424*27P/50V@NCC424*27P/50V@NC C706*27P/50V@NCC706*27P/50V@NC C705*27P/50V@NCC705*27P/50V@NC

C830*33P/50V_4C830*33P/50V_4 C52833P/50V_4C52833P/50V_4 C53033P/50V_4C53033P/50V_4 C53433P/50V_4C53433P/50V_4

CLK_7612_48M CLK_ICH_48M CLK_SIO_14M CLK_ICH_14M

PCI_CLK_8512 PCI_CLK_7612 PCLK_LPC_DEBUG CLK_PCI_TPM CLK_PCI_ICH

CLK_3GPLLREQ# MINI2CLK_REQ# SATA_CLKREQ# MINI1CLK_REQ#

EC B-01

C691

0.1U/10V_4

SCLK

SDA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0#/DOT96#

0.1U/10V_4

C702

CGCLK_SMB_M

CGDAT_SMB_M

63 38

CPU_BCLK

CPU_BCLK#

MCH_BCLK

MCH_BCLK#

CLK_CPU_ITP

CLK_CPU_ITP#

MCH_3GPLL#

MCH_3GPLL

CLK_3GPLLREQ#_R

33 32

PCIE_MINI2

PCIE_MINI2#

PECLK_VGA_R

PECLK_VGA#_R

PCIE_ICH

PCIE_ICH#

PCIE_MINI1

PCIE_MINI1#

28 24

PCIE_SATA

PCIE_SATA#

DREFSSCLK_R

DREFSSCLK#_R

DREFCLK_R

DREFCLK#_R

14 56

C703

0.1U/10V_4

T41T41

+CK_VDD_MAIN

0.1U/10V_4

BLM21PG600SN1D

C414

C407

0.1U/10V_4

CGCLK_SMB_M[12,13] CGDAT_SMB_M[12,13]

R259475_4R259475_4 R296475_4R296475_4

C414 10U/6.3V/X5R_8

10U/6.3V/X5R_8

4 2

2 4

4 2

2 4

4 2

C418

T39T39 T40T40

UMA & Discrete Dis/Enable setting

CPU Clock select

FSCFSB 1330 0 0 0 00 1 100 1 1

L42

+3.3V_M

iAMT

H_STP_PCI#[16]

RP25

0X2

RP26

0X2

RP29

0X2

CLK_3GPLLREQ# MINI2CLK_REQ#MINI2CLK_REQ#_R

RP34

0X2

RP28

*0X2@EV

RP30

0X2

RP33

0X2

RP32

0X2

RP35

0X2@IV

RP31

0X2@IV

RP39

*0X2@EV

FSACPUSRCPCI 1100 10

133

1 1

033 1 1

166 200

266

333

0 0

400

RSVD

H_STP_CPU#[16] CLK_CPU_BCLK[3]

CLK_CPU_BCLK#[3] CLK_MCH_BCLK[5]

CLK_MCH_BCLK#[5]

CLK_MCH_3GPLL#[6] CLK_MCH_3GPLL[6]

CLK_3GPLLREQ#[6] MINI2CLK_REQ#[33]

CLK_PCIE_MINI2[33] CLK_PCIE_MINI2#[33]

CLK_PCIE_VGA[18] CLK_PCIE_VGA#[18]

CLK_PCIE_ICH[15] CLK_PCIE_ICH#[15]

CLK_PCIE_MINI1[33] CLK_PCIE_MINI1#[33]

CLK_PCIE_SATA[14] CLK_PCIE_SATA#[14]

DREF_SSCLK[6] DREF_SSCLK#[6]

MCH_DREFCLK[6] MCH_DREFCLK#[6]

CLK_VGA_27M_NSS[19] CLK_VGA_27M_SS[19]

CLK_PWRGD[16]

100 100 100 100 100

100 100

+3.3V_M[12,13,16,43] +3.3V[3,6,8,9,11,14,15,16,17,19,20,21,25,26,31,33,34,37,38,39,41,43,52]

MINI2CLK_REQ# CLK_3GPLLREQ# SATA_CLKREQ# MINI1CLK_REQ#

iAMT

ICH_SMBDATA[16,33,40]

ICH_SMBCLK[16,33,40]

R29710K_4R29710K_4 R26010K_4R26010K_4 R27710K_4R27710K_4 R32510K_4R32510K_4

Clock Gen I2C

Q16

2N7002W-7-F

Q15

2N7002W-7-F

+3.3V_M

3 1

+3.3V_M

3 1

+3.3V

R262

R262 10K_4

10K_4

R261

R261 10K_4

10K_4

CGDAT_SMB_M

CGCLK_SMB_M

Discrete

UMA & Discrete setting

CLK Discrete / UMA

-------------------------RP28 0 NC RP35 NC 0 RP31 NC 0 RP39 0 NC

33 33 33 33

33 33

GCLK_SEL = FCTSEL1

FCTSEL1 (PIN6)

PIN13PIN18PIN14

0=UMA

1 = External VGA

SRCT0SRCC027Mout-NSS27Mout-SS

PIN17

SRCT1/LCDT_100DOT96C

SRCC1/LCDT_100DOT96T

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SizeDocument NumberRev

Clock Gen

Friday, March 23, 2007

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

255

H_A#[3..16][5]

H_A#[3..16]

CPU(HOST)

+1.05V_VCCP

H_ADSTB#0[5] H_REQ#[0..4][5]

H_A#[17..35][5]

H_ADSTB#1[5]

H_A20M#[14]

H_FERR#[14]

H_IGNNE#[14] H_STPCLK#[14]

H_INTR[14] H_NMI[14] H_SMI#[14]

H_D#[0..63][5]

H_DSTBN#0[5] H_DSTBP#0[5] H_DINV#0[5]

H_D#[0..63][5]

Layout Note: Place voltage divider within

0.5" of GTLREF pin

R12

R12 1K/F_4

1K/F_4

R11*1K_4@NCR11*1K_4@NC R10*1K_4@NCR10*1K_4@NC

T68T68

T84T84

R13

R13 2K/F_4

2K/F_4

R6*0_4@NCR6*0_4@NC

Layout Note: Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.

H_REQ#[0..4]

H_A#[17..35]

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

H_DSTBN#1[5] H_DSTBP#1[5] H_DINV#1[5]

C12*0.1U/10V_4@NCC12*0.1U/10V_4@NC

CPU_MCH_BSEL0[2,6] CPU_MCH_BSEL1[2,6] CPU_MCH_BSEL2[2,6]

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_D#0

H_D#1

H_D#2

H_D#3

H_D#4

H_D#5

H_D#6

H_D#7

H_D#8

H_D#9

H_D#10

H_D#11

H_D#12

H_D#13

H_D#14

H_D#15

H_D#16

H_D#17

H_D#18

H_D#19

H_D#20

H_D#21

H_D#22

H_D#23

H_D#24

H_D#25

H_D#26

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31

H_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

U34A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a U34B

U34B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

ADDR GROUP 0 ADDR GROUP 1

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

DATA GRP 0

DATA GRP 1

MISC

Merom Ball-out Rev 1a

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

DATA GRP 2DATA GRP 3

DSTBN[2]# DSTBP[2]#

DINV[2]#

DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

SLP#

PSI#

H1 E2 G5

H5 F21 E1

F1 D20

B3 H4 C1

F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

D21 A24 B25

A22 A21

H_IERR#

H_RESET#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET#

H_PROCHOT# H_THERMDA H_THERMDC

H_THERMTRIP_R#

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23 AE25 AF24 AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1 E5

B5 D24 D6 D7 AE6

R51356.2/F_4R51356.2/F_4

T22T22 T21T21 T85T85 T20T20 T81T81 T79T79

R50256_4R50256_4

R5240_4R5240_4 R522*56.2/F_4@NCR522*56.2/F_4@NC

CLK_CPU_BCLK[2] CLK_CPU_BCLK#[2]

H_D#[0..63]

R927.4/F_4R927.4/F_4 R854.9/F_4R854.9/F_4 R11027.4/F_4R11027.4/F_4 R11154.9/F_4R11154.9/F_4

H_DPRSTP#[6,14,50] H_DPSLP#[14] H_DPWR#[5] H_PWRGOOD[14] H_CPUSLP#[5] H_PSI#[50]

H_ADS#[5] H_BNR#[5] H_BPRI#[5]

H_DEFER#[5] H_DRDY#[5] H_DBSY#[5]

H_BR0#[5]

+1.05V_VCCP

H_INIT#[14] H_LOCK#[5] H_RESET#[5]

H_RS#0[5] H_RS#1[5] H_RS#2[5] H_TRDY#[5]

H_HIT#[5] H_HITM#[5]

+1.05V_VCCP

*MMST3904-7-F@NC

1 3

Q35

Default PU 56ohm if no use.Serial R NC If connect to power side PU 75ohm.

IMVP6_PROCHOT#[50]

R679

*330@NC

ITP_DBRESET#[16]

+1.05V_VCCP

H_THERMTRIP#[6,14]

+1.05V_VCCP

H_D#[0..63][5]

H_DSTBN#2[5] H_DSTBP#2[5] H_DINV#2[5]

H_D#[0..63][5]

Layout Note: Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.

H_DSTBN#3[5] H_DSTBP#3[5] H_DINV#3[5]

Layout Note: ICH_DPRSTP# need to daisy chain from ICH8 to IMVP6 to CPU.

EC C-02

RV1

EC C-02

RV1

RV2

V-PORT-0603-220K-V05

CPU Thermal monitor

THCLK_SMB[19] THDAT_SMB[19]

Q31

2N7002W-7-F

ABCLK[16,37,45]

2N7002W-7-F

ABDATA[16,37,45]

THERM_ALERT#[16]

SYS_SHDN#[46]

ABDATA

2N7002W-7-F

ABCLK THCLK_SMB

3 1

+3.3V

Q30

3 1

+3.3V

Q29

3 1

+5V

Populate ITP700Flex for bringup

H_RESET#

ITP_TMS ITP_TDI ITP_TDO

ITP_TCK ITP_TRST#

ITP_DBRESET#

EC B-02

R105*51/F_4@NCR105*51/F_4@NC

R10739/F_4R10739/F_4 R109150/F_4R109150/F_4 R10851_4R10851_4

R53927/F_4R53927/F_4 R540649/F_4R540649/F_4

+1.05V_VCCP

R510150/F_4R510150/F_4

+3.3V_S5

Signal

TDI TMS

TRST#

TCK

TDO

RESET#

THDAT_SMB

6648OVERT#

CPU FAN

30 mil

C674

10U/10V/X5R_8

+3.3V

PWM_FAN1[37]

FANSIG1[37]

Resistor Value

500 to 680 ohm 5%

27 ohm 1%

51 ohm 5%

22.6 ohm 1% series resistor and pullup 51 ohm 1%.

+3.3V+3.3V

R490

10K_4

R487*0_4@NCR487*0_4@NC

R592

R592 PBY201209T-600Y-N-3A_8

PBY201209T-600Y-N-3A_8

C678

0.1U/10V_4

R5934.7K_4R5934.7K_4

100P/50V_4

ITP700 layout guidelines

Connect To

∮

SizeDocument NumberRev

Date:Sheet of

R491220_6R491220_6

R486

R488

R489

10K_4

Layout Note: Layout Note:Routing 10:10 mils and away from noise source with ground gard

C676

10K_4

5VFAN1

*10K_4@NC

C677

100P/50V_4

U30

SCLK

SDA

ALERT#

OVERT#

G781P8

ADDRESS: 98H

CN24

FAN

4 3 2 1

Resistor Placement

VCCP150 ohm 5%

Place the pull-up near CPU

VCCP39 ohm 1%

Within 200ps of ITP connector

Place the pull-up near CPU

GND

Connect to TCK pin of CPU and then connect it to FBO pin of ITP connector

GND

in daisy chain. Place the pull-down near TCK0 pin of ITP connector

Place the pull-up near CPU

VCCP

Connect to CPURST# pin of GMCH through the series resistor placed within 200ps of ITP connector. Place the

VCCP

pull-up after the series resistor from ITP connector.

CPU(1 of 2)/FAN/Thermal

Friday, March 23, 2007

PROJECT : NA1

Quanta Computer Inc.

VCC

DXP DXN GND

6648VCC

1 2 3 5

C559

0.1U/10V_4

H_THERMDA

C556

C556 2200P/50V_6

2200P/50V_6

H_THERMDC

355

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CPU(Power)

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

+VCC_CORE

C605

C604

C604 10U/4V/X6S_8

10U/4V/X6S_8

+VCC_CORE

C584

C584 10U/4V/X6S_8

10U/4V/X6S_8

C605 10U/4V/X6S_8

10U/4V/X6S_8

C586

C586 10U/4V/X6S_8

10U/4V/X6S_8

C582

C582 10U/4V/X6S_8

10U/4V/X6S_8

C606

C606 10U/4V/X6S_8

10U/4V/X6S_8

8 inside cavity, north side, secondary layer.

+VCC_CORE

C103

C585

C585 10U/4V/X6S_8

10U/4V/X6S_8

+VCC_CORE

C104

C104 10U/4V/X6S_8

10U/4V/X6S_8

C103 10U/4V/X6S_8

10U/4V/X6S_8

C107

C107 10U/4V/X6S_8

10U/4V/X6S_8

C106

C106 10U/4V/X6S_8

10U/4V/X6S_8

C76

C76 10U/4V/X6S_8

10U/4V/X6S_8

8 inside cavity, south side, secondary layer.

+VCC_CORE

C74

C73

C73 10U/4V/X6S_8

10U/4V/X6S_8

C75

C75 10U/4V/X6S_8

10U/4V/X6S_8

C74 10U/4V/X6S_8

10U/4V/X6S_8

6 inside cavity, north side, primary layer.

+VCC_CORE

C51

C49

C49 10U/4V/X6S_8

10U/4V/X6S_8

6 inside cavity, south side, primary layer.

C50

C50 10U/4V/X6S_8

10U/4V/X6S_8

C51 10U/4V/X6S_8

10U/4V/X6S_8

C608

C608 10U/4V/X6S_8

10U/4V/X6S_8

C609

C609 10U/4V/X6S_8

10U/4V/X6S_8

C105

C105 10U/4V/X6S_8

10U/4V/X6S_8

C54

C54 10U/4V/X6S_8

10U/4V/X6S_8

C101

C101 10U/4V/X6S_8

10U/4V/X6S_8

C52

C52 10U/4V/X6S_8

10U/4V/X6S_8

C100

C100 10U/4V/X6S_8

10U/4V/X6S_8

C71

C71 10U/4V/X6S_8

10U/4V/X6S_8

C607

C607 10U/4V/X6S_8

10U/4V/X6S_8

C583

C583 10U/4V/X6S_8

10U/4V/X6S_8

C72

C72 10U/4V/X6S_8

10U/4V/X6S_8

C587

C587 10U/4V/X6S_8

10U/4V/X6S_8

C102

C102 10U/4V/X6S_8

10U/4V/X6S_8

C53

C53 10U/4V/X6S_8

10U/4V/X6S_8

+VCC_CORE

U34C

VCC[001]

VCC[068]

VCC[002]

VCC[069]

VCC[003]

VCC[070]

VCC[004]

VCC[071]

VCC[005]

VCC[072]

VCC[006]

VCC[073]

VCC[007]

VCC[074]

VCC[008]

VCC[075]

VCC[009]

VCC[076]

VCC[010]

VCC[077]

VCC[011]

VCC[078]

VCC[012]

VCC[079]

VCC[013]

VCC[080]

VCC[014]

VCC[081]

VCC[015]

VCC[082]

VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]

VCC[022]

VCC[089]

VCC[023]

VCC[090]

VCC[024]

VCC[091]

VCC[025]

VCC[092]

VCC[026]

VCC[093]

VCC[027]

VCC[094]

VCC[028]

VCC[095]

VCC[029]

VCC[096]

VCC[030]

VCC[097]

VCC[031]

VCC[098]

VCC[032]

VCC[099]

VCC[033]

VCC[100] VCC[034] VCC[035]

VCCP[01] VCC[036]

VCCP[02] VCC[037]

VCCP[03] VCC[038]

VCCP[04] VCC[039]

VCCP[05] VCC[040]

VCCP[06] VCC[041]

VCCP[07] VCC[042]

VCCP[08] VCC[043]

VCCP[09] VCC[044]

VCCP[10] VCC[045]

VCCP[11] VCC[046]

VCCP[12] VCC[047]

VCCP[13] VCC[048]

VCCP[14] VCC[049]

VCCP[15] VCC[050]

VCCP[16] VCC[051] VCC[052]

VCCA[01] VCC[053]

VCCA[02] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]

VCCSENSE VCC[065] VCC[066] VCC[067]

VSSSENSE

Merom Ball-out Rev 1a

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A9 A10 A12 A13 A15 A17 A18 A20

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E9 E10 E12 E13 E15 E17 E18 E20

F9 F10 F12 F14 F15 F17 F18 F20

AA7 AA9

AB9

<REV.NO. 0.5/REF.NO.19343> Ivcc Max 52A Ivccp Max 6A(VCCP supply before Vcc stable) Max 2A(VCCP supply after Vcc stable) Ivcca Max 130mA

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.

+1.05V_VCCP

C612

C613

0.1U/10V_4

Layout out: Place these inside socket cavity on North side secondary.

VID0[50] VID1[50] VID2[50] VID3[50] VID4[50] VID5[50] VID6[50]

0.1U/10V_4

C614

0.1U/10V_4

+1.05V_VCCP

+VCC_CORE

C557

C557 330U/2.5V/_7343

330U/2.5V/_7343

0.01U/16V_4

R549

R549 100/F_6

100/F_6

R548

R548 100/F_6

100/F_6

0.1U/10V_4

C11

C617

+1.5V

0.1U/10V_4

C616

C615

C10

C10 10U/6.3V/X5R_8

10U/6.3V/X5R_8

C616

0.1U/10V_4

Layout Note: Place C2549 near PIN B26.

VCCSENSE[50]

VSSSENSE[50]

U34D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

VSS[082]

P21

VSS[083]

P24

VSS[084]

VSS[085]

VSS[086]

R22

VSS[087]

R25

VSS[088]

VSS[089]

VSS[090]

T23

VSS[091]

T26

VSS[092]

VSS[093]

VSS[094]

U21

VSS[095]

U24

VSS[096]

VSS[097]

VSS[098]

V22

VSS[099]

V25

VSS[100]

VSS[101]

VSS[102]

W23

VSS[103]

W26

VSS[104]

VSS[105]

VSS[106]

Y21

VSS[107]

Y24

VSS[108]

AA2

VSS[109]

AA5

VSS[110]

AA8

VSS[111]

AA11

VSS[112]

AA14

VSS[113]

AA16

VSS[114]

AA19

VSS[115]

AA22

VSS[116]

AA25

VSS[117]

AB1

VSS[118]

AB4

VSS[119]

AB8

VSS[120]

AB11

VSS[121]

AB13

VSS[122]

AB16

VSS[123]

AB19

VSS[124]

AB23

VSS[125]

AB26

VSS[126]

AC3

VSS[127]

AC6

VSS[128]

AC8

VSS[129]

AC11

VSS[130]

AC14

VSS[131]

AC16

VSS[132]

AC19

VSS[133]

AC21

VSS[134]

AC24

VSS[135]

AD2

VSS[136]

AD5

VSS[137]

AD8

VSS[138]

AD11

VSS[139]

AD13

VSS[140]

AD16

VSS[141]

AD19

VSS[142]

AD22

VSS[143]

AD25

VSS[144]

AE1

VSS[145]

AE4

VSS[146]

AE8

VSS[147]

AE11

VSS[148]

AE14

VSS[149]

AE16

VSS[150]

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

VSS[154]

AF6

VSS[155]

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

A25 AF25

VSS[163]

SizeDocument NumberRev

CPU(2 of 2)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

455Friday, March 23, 2007

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NB(HOST)

H_D#[0..63][3]

+1.05V_VCCP

R25

221/F_4

H_SWING

C46

+1.05V_VCCP

R498

54.9/F_4

H_SCOMP#

R20

24.9/F_4

C46

0.1U/10V_4

H_SCOMP

H_RCOMP

Layout Note:

0.1U close to B3

Layout Note: Impedance 55ohm

Layout Note: 10:20 mils(Width:Spacing)

+1.05V_VCCP

R33

R33 1K/F_4

1K/F_4

R35

C61

2K/F_4

0.1U/10V_4

H_RESET#[3] H_CPUSLP#[3]

H_REF

Layout Note: Place the 0.1 uF decoupling capacitor within 100 mils from GMCH pins.

R22

100/F_4

R497

54.9/F_4

H_D#[0..63]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING

H_RCOMP

H_SCOMP

H_SCOMP#

U35A

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

M10

H_D#_10

N12

H_D#_11

H_D#_12

H_D#_13

P13

H_D#_14

H_D#_15

H_D#_16

W10

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

H_D#_27

H_D#_28

H_D#_29

H_D#_30

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

H_SWING

H_RCOMP

H_SCOMP

H_SCOMP#

H_CPURST#

H_CPUSLP#

H_AVREF

H_DVREF

CRESTLINE_1p0@MV

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HOST

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A#3

J13

H_A#[3..35]

H_ADS#[3] H_ADSTB#0[3] H_ADSTB#1[3] H_BNR#[3] H_BPRI#[3] H_BR0#[3] H_DEFER#[3] H_DBSY#[3] CLK_MCH_BCLK[2] CLK_MCH_BCLK#[2] H_DPWR#[3] H_DRDY#[3] H_HIT#[3] H_HITM#[3] H_LOCK#[3] H_TRDY#[3]

H_DINV#0[3] H_DINV#1[3] H_DINV#2[3] H_DINV#3[3]

H_DSTBN#0[3] H_DSTBN#1[3] H_DSTBN#2[3] H_DSTBN#3[3]

H_DSTBP#0[3] H_DSTBP#1[3] H_DSTBP#2[3] H_DSTBP#3[3]

H_REQ#0[3] H_REQ#1[3] H_REQ#2[3] H_REQ#3[3] H_REQ#4[3]

H_RS#0[3] H_RS#1[3] H_RS#2[3]

H_A#[3..35][3]

SizeDocument NumberRev

GMCH HOST(1 of 6)

Friday, March 23, 2007

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

555

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

+1.8V_SUS

SM_RCOMP_VOH

R81

3.01K/F_4

R64

R64 1K/F_4

1K/F_4

+3.3V

+1.05V_VCCP

CPU_MCH_BSEL0[2,3] CPU_MCH_BSEL1[2,3] CPU_MCH_BSEL2[2,3]

MCH_CFG_5[11]

MCH_CFG_9[11]

MCH_CFG_12[11] MCH_CFG_13[11]

MCH_CFG_16[11]

MCH_CFG_19[11] MCH_CFG_20[11]

PM_BMBUSY#[16] H_DPRSTP#[3,14,50] PM_EXTTS#0[12,13] PM_EXTTS#1[12] DELAY_VR_PG[16,50] PLTRST#_NB[15] H_THERMTRIP#[3,14] PM_DPRSLPVR[16,50]

THRMTRIP#_GMCH

SM_RCOMP_VOL

RV3

RV3 V-PORT-0603-220K-V05

V-PORT-0603-220K-V05

R92

R92 1K/F_4

1K/F_4

C137

0.01U/16V_4

C129

0.01U/16V_4

Santa Rosa Platform MOW WW15 For 4Gb DRAM support, change Pin-BJ29 to DDR_A_MA14, change Pin-BE24 to DDR_B_MA14.

R9910K_4R9910K_4 R8510K_4R8510K_4

EC C-02

DDR_A_MA14[12,13] DDR_B_MA14[12,13]

CRESTLINE new pin define

THRMTRIP#_GMCH

*56.2/F_4@NC

R1260_4R1260_4 R54100_4R54100_4 R550_4R550_4 R780_4R780_4

C142

2.2U/6.3V/X5R_6

C136

2.2U/6.3V/X5R_6

PM_EXTTS#0 PM_EXTTS#1

T14T14 T77T77

T11T11 T8T8 T12T12

T7T7 T13T13

T9T9 T10T10

T15T15 T17T17

T86T86 T23T23

MCH_CFG_3 MCH_CFG_4

MCH_CFG_6 MCH_CFG_7 MCH_CFG_8

MCH_CFG_10 MCH_CFG_11

MCH_CFG_14 MCH_CFG_15

MCH_CFG_17 MCH_CFG_18

PM_EXTTS#0 PM_EXTTS#1

PLTRST#_R THRMTRIP#_GMCH PM_DPRSLPVR_GMCH

T94T94 T93T93 T95T95 T91T91 T87T87 T75T75 T76T76 T71T71 T69T69 T70T70 T73T73 T92T92 T89T89 T90T90 T88T88 T72T72

UMA & Discrete setting

DREF_SSCLK DREF_SSCLK#

MCH_DREFCLK MCH_DREFCLK#

Discrete DREFCLK/ DREFCLK# 0 Discrete DREFSSCLK/ DREFSSCLK# 0 UMA DREFCLK/ DREFCLK# NC Discrete DREFSSCLK/ DREFSSCLK# NC

U35B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

TP_NC1

BJ51

TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11 TP_NC12 TP_NC13 TP_NC14 TP_NC15 TP_NC16

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

NC_10

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0@MV

R124*0_4@EVR124*0_4@EV R116*4.7K_4@EVR116*4.7K_4@EV

R115*0_4@EVR115*0_4@EV R106*4.7K_4@EVR106*4.7K_4@EV

CFGRSVD

+1.05V_VCCP

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF_0

DDR MUXINGCLK

SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GFX_VR_EN

GRAPHICS VID

CL_PWROK

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4

SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

CL_CLK

CL_DATA CL_RST#

CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1 TEST_2

EC B-03

AV29 BB23 BA25 AV23

AW30 BA23 AW25 AW23

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

MCH_DREFCLK

B42

MCH_DREFCLK#

C42

DREF_SSCLK

H48

DREF_SSCLK#

H47 K44

K45

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

E35 A39 C38 B39 E36

AM49 AK50 AT43 AN49 AM50

SDVO_CTRLCLK

H35

SDVO_CTRLDATA

K36 G39 G40

GMCH_TEST1

A37

GMCH_TEST2

R32

SDVO_CTRLCLK SDVO_CTRLDATA

M_CLK_DDR0[13] M_CLK_DDR1[13] M_CLK_DDR3[13] M_CLK_DDR4[13]

M_CLK_DDR#0[13] M_CLK_DDR#1[13] M_CLK_DDR#3[13] M_CLK_DDR#4[13]

DDR_CKE0_DIMMA[12,13] DDR_CKE1_DIMMA[12,13] DDR_CKE3_DIMMB[12,13] DDR_CKE4_DIMMB[12,13]

DDR_CS0_DIMMA#[12,13] DDR_CS1_DIMMA#[12,13] DDR_CS2_DIMMB#[12,13] DDR_CS3_DIMMB#[12,13]

M_ODT0[12,13] M_ODT1[12,13] M_ODT2[12,13] M_ODT3[12,13]

SMRCOMPP SMRCOMPN

SM_RCOMP_VOH SM_RCOMP_VOL

V_DDR_MCH_REF[13,47]

V_DDR_MCH_REF

C38.1U/10V/04C38.1U/10V/04

C37.1U/10V/04C37.1U/10V/04

T18T18 T82T82 T80T80 T83T83 T78T78

MCH_CLVREF

R7420K_4R7420K_4

Discrete 0 UMA NC

*0_4@EV

INT__BKLT_CTRL[25] INT_LVDS_BLON[25]

+1.8V_SUS

MCH_DREFCLK[2] MCH_DREFCLK#[2] DREF_SSCLK[2] DREF_SSCLK#[2]

CLK_MCH_3GPLL[2] CLK_MCH_3GPLL#[2]

DMI_MRX_ITX_N0[15] DMI_MRX_ITX_N1[15] DMI_MRX_ITX_N2[15] DMI_MRX_ITX_N3[15]

DMI_MRX_ITX_P0[15] DMI_MRX_ITX_P1[15] DMI_MRX_ITX_P2[15] DMI_MRX_ITX_P3[15]

DMI_MTX_IRX_N0[15] DMI_MTX_IRX_N1[15] DMI_MTX_IRX_N2[15] DMI_MTX_IRX_N3[15]

DMI_MTX_IRX_P0[15] DMI_MTX_IRX_P1[15] DMI_MTX_IRX_P2[15] DMI_MTX_IRX_P3[15]

INT_HSYNC[26]

Layout Note: HSYNC/VSYNC serial R place close to NB

R97

R94*0_4@EVR94*0_4@EV

INT_VSYNC[26]

+1.25V_M[9,43,48]

CL_CLK0[16]

CL_DATA0[16] ICH_CL_PWROK[16,43] ICH_CL_RST0#[16]

SDVO_CTRLCLK[41]

SDVO_CTRLDATA[41]

CLK_3GPLLREQ#[2]

MCH_ICH_SYNC#[16]

External VGA with @EV part, Internal VGA with @IV part.

*0_4@EV

R98

L_CTRL_CLK

R103*0_4@EV R103*0_4@EV

L_CTRL_DATA

UMA & Discrete setting

+3.3V

INT_LVDS_EDIDCLK[25] INT_LVDS_EDIDDATA[25]

LVDS Discrete / UMA R101 NC 2.4K R102 NC 0

R52

R52 20/F_4

20/F_4

R38

R38 20/F_4

20/F_4

C150

0.1U/10V_4

INT_LVDS_DIGON[25]

INT_TXLCLKOUT-[25] INT_TXLCLKOUT+[25] INT_TXUCLKOUT-[25] INT_TXUCLKOUT+[25]

UMA & Discrete setting

+3.3V

R952.2K_4@IVR952.2K_4@IV R762.2K_4@IVR762.2K_4@IV

TV Discrete / UMA

---------------------------R95/R76 NC 2.2K R86/R93 0 NC

INT_CRT_DDCCLK[26] INT_CRT_DDCDAT[26]

R7030/F_4@IVR7030/F_4@IV R690_4@MVR690_4@MV R7130/F_4@IVR7130/F_4@IV

iAMT

+1.25V_M

LVDS Discrete / UMA R100/R104 NC 10K R98/R103 0 NC

10K_4@IV

R100

R100 R10410K_4@IVR10410K_4@IV

R1012.4K_4@IVR1012.4K_4@IV R1020_4@IVR1020_4@IV

INT_TXLOUT0-[25] INT_TXLOUT1-[25] INT_TXLOUT2-[25]

INT_TXLOUT0+[25] INT_TXLOUT1+[25] INT_TXLOUT2+[25]

INT_TXUOUT0-[25] INT_TXUOUT1-[25] INT_TXUOUT2-[25]

INT_TXUOUT0+[25] INT_TXUOUT1+[25] INT_TXUOUT2+[25]

INT_TV_COMP[26]

INT_TV_Y/G[26] INT_TV_C/R[26]

INT_CRT_BLU[26] INT_CRT_GRN[26] INT_CRT_RED[26]

UMA & Discrete setting

CRT Discrete / UMA

---------------------------R69 0 1.3K/F R70 NC 30 R71 NC 30

UMA & Discrete setting

LVDS/CRT Discrete / UMA

--------------------------R91 0 NC R90 0 NC

R123

R123 1K/F_4

1K/F_4

R128

R128 392/F_4

392/F_4

R96 0 NC R89 0 NC

INT_CRT_DDCCLK INT_CRT_DDCDAT INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA

UMA & Discrete setting

CRT Discrete / UMA

--------------------R82 0 NC R79 0 NC R63 0 150 R60 0 150 R67 0 150 R83 0 150 R72 0 150 R65 0 150

L_CTRL_CLK

L_CTRL_DATA INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA

LVDS_IBG

T19T19

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

TV_DCONSEL_0

TV_DCONSEL_1

R86

*0_4@EV

R93*0_4@EVR93*0_4@EV

INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

INT_CRT_DDCCLK

INT_CRT_DDCDAT INT_HSYNC1 CRTIREF INT_VSYNC1

R82*0_4@EVR82*0_4@EV R79*0_4@EVR79*0_4@EV R630_4@MVR630_4@MV R600_4@MVR600_4@MV R670_4@MVR670_4@MV R830_4@MVR830_4@MV R720_4@MVR720_4@MV R650_4@MVR650_4@MV

U35C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0@MV

R91*0_4@EVR91*0_4@EV R90*0_4@EVR90*0_4@EV R96*0_4@EVR96*0_4@EV R89*0_4@EVR89*0_4@EV

Layout Note: Place 150 ohm termination resistors close to GMCH.

INT_HSYNC1 INT_VSYNC1 INT_TV_COMP INT_TV_Y/G INT_TV_C/R INT_CRT_BLU INT_CRT_GRN INT_CRT_RED

+VCC_PEG[9]

EXP_A_COMPX

N43

PEG_COMPI

PEG_COMPO

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

C_PEG_TXP0 C_PEG_TXN0 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP3 C_PEG_TXN3

PEG_RXP1 PEG_RXN1

SizeDocument NumberRev

Date:Sheet of

M43

PEG_RXN0

J51

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

UMA & Discrete setting FOR SDVO PORT Discrete NC

GMCH DMI/VIDEO(2 of 6)

Friday, March 23, 2007

PEG_RXN1

L51

PEG_RXN2

N47

PEG_RXN3

T45

PEG_RXN4

T50

PEG_RXN5

U40

PEG_RXN6

Y44

PEG_RXN7

Y40

PEG_RXN8

AB51

PEG_RXN9

W49

PEG_RXN10

AD44

PEG_RXN11

AD40

PEG_RXN12

AG46

PEG_RXN13

AH49

PEG_RXN14

AG45

PEG_RXN15

AG41

PEG_RXP0

J50

PEG_RXP1

L50

PEG_RXP2

M47

PEG_RXP3

U44

PEG_RXP4

T49

PEG_RXP5

T41

PEG_RXP6

W45

PEG_RXP7

W41

PEG_RXP8

AB50

PEG_RXP9

Y48

PEG_RXP10

AC45

PEG_RXP11

AC41

PEG_RXP12

AH47

PEG_RXP13

AG49

PEG_RXP14

AH45

PEG_RXP15

AG42

C_PEG_TXN0

N45

C_PEG_TXN1

U39

C_PEG_TXN2

U47

C_PEG_TXN3

N51

C_PEG_TXN4

R50

C_PEG_TXN5

T42

C_PEG_TXN6

Y43

C_PEG_TXN7

W46

C_PEG_TXN8

W38

C_PEG_TXN9

AD39

C_PEG_TXN10

AC46

C_PEG_TXN11

AC49

C_PEG_TXN12

AC42

C_PEG_TXN13

AH39

C_PEG_TXN14

AE49

C_PEG_TXN15

AH44

C_PEG_TXP0

M45

C_PEG_TXP1

T38

C_PEG_TXP2

T46

C_PEG_TXP3

N50

C_PEG_TXP4

R51

C_PEG_TXP5

U43

C_PEG_TXP6

W42

C_PEG_TXP7

Y47

C_PEG_TXP8

Y39

C_PEG_TXP9

AC38

C_PEG_TXP10

AD47

C_PEG_TXP11

AC50

C_PEG_TXP12

AD43

C_PEG_TXP13

AG39

C_PEG_TXP14

AE50

C_PEG_TXP15

AH43

PEG_TXN[15:0][18]

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

C2210.1U/10V_4@IVC2210.1U/10V_4@IV C2220.1U/10V_4@IVC2220.1U/10V_4@IVR5500_4R5500_4 C1950.1U/10V_4@IVC1950.1U/10V_4@IV C1960.1U/10V_4@IVC1960.1U/10V_4@IV C6500.1U/10V_4@IVC6500.1U/10V_4@IV C6490.1U/10V_4@IVC6490.1U/10V_4@IV C1970.1U/10V_4@IVC1970.1U/10V_4@IV C1980.1U/10V_4@IVC1980.1U/10V_4@IV

C2050.1U/10V_4@IVC2050.1U/10V_4@IV C2060.1U/10V_4@IVC2060.1U/10V_4@IV

PROJECT : NA1

Quanta Computer Inc.

R11724.9/F_4R11724.9/F_4

PEG_RXN[15:0][18]

PEG_RXP[15:0][18]

C651*0.1U/10V_4@EVC651*0.1U/10V_4@EV C645*0.1U/10V_4@EVC645*0.1U/10V_4@EV C216*0.1U/10V_4@EVC216*0.1U/10V_4@EV C643*0.1U/10V_4@EVC643*0.1U/10V_4@EV C200*0.1U/10V_4@EVC200*0.1U/10V_4@EV C641*0.1U/10V_4@EVC641*0.1U/10V_4@EV C188*0.1U/10V_4@EVC188*0.1U/10V_4@EV C639*0.1U/10V_4@EVC639*0.1U/10V_4@EV C190*0.1U/10V_4@EVC190*0.1U/10V_4@EV C637*0.1U/10V_4@EVC637*0.1U/10V_4@EV C192*0.1U/10V_4@EVC192*0.1U/10V_4@EV C635*0.1U/10V_4@EVC635*0.1U/10V_4@EV C193*0.1U/10V_4@EVC193*0.1U/10V_4@EV C633*0.1U/10V_4@EVC633*0.1U/10V_4@EV C202*0.1U/10V_4@EVC202*0.1U/10V_4@EV C632*0.1U/10V_4@EVC632*0.1U/10V_4@EV

C652*0.1U/10V_4@EVC652*0.1U/10V_4@EV C646*0.1U/10V_4@EVC646*0.1U/10V_4@EV C215*0.1U/10V_4@EVC215*0.1U/10V_4@EV C644*0.1U/10V_4@EVC644*0.1U/10V_4@EV C199*0.1U/10V_4@EVC199*0.1U/10V_4@EV C642*0.1U/10V_4@EVC642*0.1U/10V_4@EV C187*0.1U/10V_4@EVC187*0.1U/10V_4@EV C640*0.1U/10V_4@EVC640*0.1U/10V_4@EV C189*0.1U/10V_4@EVC189*0.1U/10V_4@EV C638*0.1U/10V_4@EVC638*0.1U/10V_4@EV C191*0.1U/10V_4@EVC191*0.1U/10V_4@EV C636*0.1U/10V_4@EVC636*0.1U/10V_4@EV C194*0.1U/10V_4@EVC194*0.1U/10V_4@EV C634*0.1U/10V_4@EVC634*0.1U/10V_4@EV C201*0.1U/10V_4@EVC201*0.1U/10V_4@EV C647*0.1U/10V_4@EVC647*0.1U/10V_4@EV

UMA & Discrete setting UMA NC

PEG_TXP[15:0][18]

+VCC_PEG

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

SDVOB_R+[41] SDVOB_R-[41] SDVOB_G+[41] SDVOB_G-[41] SDVOB_B+[41] SDVOB_B-[41] SDVOB_CLK+[41] SDVOB_CLK-[41]

SDVOB_INT+[41] SDVOB_INT-[41]

655

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NB(Memory controller)

DDR_A_D[0..63][13] DDR_B_D[0..63][13]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U35D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

CRESTLINE_1p0@MV

DDR_A_BS0

BB19

SA_BS_0 SA_BS_1

SA_BS_2 SA_CAS# SA_DM_0

SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_DM0

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_RAS#

DDR_A_WE#

DDR_A_BS0[12,13] DDR_A_BS1[12,13] DDR_A_BS2[12,13]

DDR_A_CAS#[12,13] DDR_B_CAS#[12,13] DDR_A_DM[0..7][13]

DDR_A_DQS[0..7][13]

DDR_A_DQS#[0..7][13]

DDR_A_MA[0..13][12,13] DDR_B_MA[0..13][12,13]

DDR_A_RAS#[12,13]

T16T16

DDR_A_WE#[12,13]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U35E

AP49

SB_DQ_0

AR51

SB_DQ_1

AW50

SB_DQ_2

AW51

SB_DQ_3

AN51

SB_DQ_4

AN50

SB_DQ_5

AV50

SB_DQ_6

AV49

SB_DQ_7

BA50

SB_DQ_8

BB50

SB_DQ_9

BA49

SB_DQ_10

BE50

SB_DQ_11

BA51

SB_DQ_12

AY49

SB_DQ_13

BF50

SB_DQ_14

BF49

SB_DQ_15

BJ50

SB_DQ_16

BJ44

SB_DQ_17

BJ43

SB_DQ_18

BL43

SB_DQ_19

BK47

SB_DQ_20

BK49

SB_DQ_21

BK43

SB_DQ_22

BK42

SB_DQ_23

BJ41

SB_DQ_24

BL41

SB_DQ_25

BJ37

SB_DQ_26

BJ36

SB_DQ_27

BK41

SB_DQ_28

BJ40

SB_DQ_29

BL35

SB_DQ_30

BK37

SB_DQ_31

BK13

SB_DQ_32

BE11

SB_DQ_33

BK11

SB_DQ_34

BC11

SB_DQ_35

BC13

SB_DQ_36

BE12

SB_DQ_37

BC12

SB_DQ_38

BG12

SB_DQ_39

BJ10

SB_DQ_40

BL9

SB_DQ_41

BK5

SB_DQ_42

BL5

SB_DQ_43

BK9

SB_DQ_44

BK10

SB_DQ_45

BJ8

SB_DQ_46

BJ6

SB_DQ_47

BF4

SB_DQ_48

BH5

SB_DQ_49

BG1

SB_DQ_50

BC2

SB_DQ_51

BK3

SB_DQ_52

BE4

SB_DQ_53

BD3

SB_DQ_54

BJ2

SB_DQ_55

BA3

SB_DQ_56

BB3

SB_DQ_57

AR1

SB_DQ_58

AT3

SB_DQ_59

AY2

SB_DQ_60

AY3

SB_DQ_61

AU2

SB_DQ_62

AT2

SB_DQ_63

CRESTLINE_1p0@MV

DDR_B_BS0

AY17

SB_BS_0 SB_BS_1

SB_BS_2 SB_CAS# SB_DM_0

SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_DM0

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_RAS#

DDR_B_WE#

T6T6

DDR_B_BS0[12,13] DDR_B_BS1[12,13] DDR_B_BS2[12,13]

DDR_B_DM[0..7][13]

DDR_B_DQS[0..7][13]

DDR_B_DQS#[0..7][13]

DDR_B_RAS#[12,13]

DDR_B_WE#[12,13]

<OrgAddr4> SizeDocument NumberRev

SizeDocument NumberRev

GMCH DDR/Strap(3 of 6)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

755Friday, March 23, 2007

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

12.313SUM

+1.8V_SUS

Remark

( 1.3A for external GFX )

for integrated Gfx

FSB VCCP

for PCIEG

for IAMT function

DMI

+1.05V_VCCP

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

U35G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

R30

VCC_13

IVCCSM supply current 1 channel 1.615A 2 channel 3.138A

AU32

VCC_SM_1

AU33

VCC_SM_2

C161

C146

C130

0.1U/10V_4

Layout Note: Place C2630 where LVDS and DDR2 taps.

330U/2.5V_7343

C146

22U/4V/X6S_8

C138

C138 22U/4V/X6S_8

22U/4V/X6S_8

+1.05V_VCCP

AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

W13

W14 AA20

AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R20 T14

Y12

VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

+1.05V_VCCP

Layout Note: 370 mils from edge.

Ivcc_AXG Graphics core supply current 7.7A

C21

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6

VCCSM_LF7

C21

330U/2.5V/_7343@IV

External VGA with @EV part, Internal VGA with @IV part.

C65

0.1U/10V_4

C22

330U/2.5V/_7343@IV

C117

0.1U/10V_4@IV

Layout Note: Inside GMCH cavity for VCC_AXG.

UMA & Discrete setting

VCC_AXG Discrete / UMA

-------------------------------R496 NC 0 C24 NC NC C23 NC NC C21 NC 330U C22 NC 330U C117 NC 0.1U C116 NC 0.1U C77 NC 0.47U C123 NC 1U C30 NC 22U

C66

0.1U/10V_4

+3.3V

C563

220U/2.5V_7343

C23

*330U/2.5V/_7343@NC

C116

0.1U/10V_4@IV

0.47U/10V/X7R_6@IV

C57

0.22U/6.3V/X5R_4

R51410_6R51410_6

+VCC_GMCH_L

D32CH751H-40PTD32CH751H-40PT

Ivcc (External GFX 1.310 A, integrate 1.572 A)

22U/4V/X6S_8

C89

C125

0.22U/6.3V/X5R_4

C149

C139

0.1U/10V_4

EC B-04

Layout Note:

C24

370 mils from edge.

*330U/2.5V/_7343@NC

UMA & Discrete setting

C77

C123

22U/4V/X6S_8@IV

1U/6.3V/X5R_6@IV

C29

C30

10U/6.3V/X5R_8

Ivcc_AXM Controller supply current 540mA

Layout Note: Inside GMCH cavity for VCC_AXG.

+1.05V_M[43,48]

C143

0.1U/10V_4

Layout Note: Place close to GMCH edge.

C148

0.47U/6.3V/X5R_4

C145

C126

0.22U/6.3V/X5R_4

22U/4V/X6S_8

C93

0.22U/6.3V/X5R_4

iAMT

+1.05V_M

C140

Layout Note: Inside GMCH cavity.

+1.05V_VCCP

0.1U/10V_4

C118

0.22U/6.3V/X5R_4

C147

C147 1U/6.3V/X5R_6

1U/6.3V/X5R_6

C133

0.1U/10V_4

C156

C156 1U/6.3V/X5R_6

1U/6.3V/X5R_6

U35F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0@MV

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

VSS NCTF

VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

A3 B2 C1 BL1 BL51 A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

iAMT

+1.05V_M

CRESTLINE_1p0@MV

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

SizeDocument NumberRev

GMCH Power-1(4 of 6)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

855Friday, March 23, 2007

UMA & Discrete setting

PLL Discrete / UMA L13 NC 10uH C184 NC 470U C158 0 0.1U L14 NC 10uH C211 NC 470U C173 0 0.1U

L1310uH/100mA_8@IVL1310uH/100mA_8@IV

+1.25V

470U/2.5V_7343@IV

L14

470U/2.5V_7343@IV

C184

10uH/100mA_8@IV

C211

C158

C158 0_4@MV

0_4@MV

C173

C173 0_4@MV

0_4@MV

L61

BLM18PG181SN1D@IV

+VCC_TVDACA

R620_6@IVR620_6@IV

+3.3V

+3.3V+1.25V

IVCCA_DAC_BG current 0.005A

R590.03/F_2010@IVR590.03/F_2010@IV

EC D-08

+VCCA_CRTDAC

+VCC_TVBG

IVCCA_DPLLA~B current 0.08A

iAMT

+1.25V_M

+1.25V_M[6,43,48]

+3.3V

L59

BLM18PG181SN1D@IV

10U/6.3V/X5R_8@IV

PLL Discrete / UMA

UMA & Discrete setting

----------------------------

L59 NC STUFF C601 NC 10U R521 NC 0 C610 NC NC C603 0 0.1U R531 NC 0 C611 NC NC C619 0 0.1U R534 NC 0 C623 NC NC C622 0 0.1U R73 0 NC R77 NC 0 L60 NC 100 R535 NC 0 C621 NC NC C135 0 1U C481 NC 0.1U

+1.5V

*22nF/3P@NC

L60

100/F_6@IV

0.1U/10V_4@IV

L56BLM11A05SL56BLM11A05S

L55BLM11A05SL55BLM11A05S

C564

22U/4V/X6S_8

+1.25V_M

iAMT

+VCC_TVDACA

C601

R470_4R470_4

123

C114

+VCCQ_TVDAC

C481

+1.5V[4,17,33,43,49]

C566

22U/4V/X6S_8

+VCCA_MPLL_L

C560

100U/10V_7343

iAMT

+1.25V_M

R5210_4@IVR5210_4@IV

*22nF/3P@NC

R5310_4@IVR5310_4@IV

*22nF/3P@NC

R5340_4@IVR5340_4@IV

*22nF/3P@NC

123

C610

123

C611

C623

R73*0_4@EVR73*0_4@EV R770_6@IVR770_6@IV

C603

C603 0_4@MV

0_4@MV

C619

C619 0_4@MV

0_4@MV

C622

C622 0_4@MV

0_4@MV

IVCCD_TVDAC current 0.06A

C91

0.1U/10V_4

IVCC_QDAC current 0.005A

R5350_4@IVR5350_4@IV

123

C621

*22nF/3P@NC

R501

0.5/F_6

EC B-05

22U/4V/X6S_8

C135

C135 0_4@MV

0_4@MV

C572

0.1U/10V_4

C571

0.1U/10V_4

C88

R580_6R580_6

1U/6.3V/X5R_6

IVCCA_HPLL current 0.05A IVCCA_MPLL current 0.15A

C122

+3V_VCCSYNC

IVCC_SYNC current 0.01A

R84

R84 0_4@MV

0_4@MV

IVCCA_CRT_DAC current 0.08A

R5380_4@IVR5380_4@IV

123

C628

*22nF/3P@NC

R5370_4@IVR5370_4@IV

C624

*22nF/3P@NC

UMA & Discrete setting

LVDS Discrete / UMA

--------------------------C630 NC 1000P

+3.3V

C26

4.7U/10V/X5R_8

22U/4V/X6S_8

C131

1U/6.3V/X5R_6

C166

0.1U/10V_4

C28

C28 *22U/4V/X6S_8@NC

*22U/4V/X6S_8@NC

C128

0.1U/10V_4

C626

C626 0_4@MV

0_4@MV

C132

IVCCA_TVA~C_DAC current 0.12A

IVCCD_CRT current 0.06A

+1.25V_M

iAMT

+1.25V

IVCCA/D_PEG_PLL current 0.1A

+1.8V_SUS

IVCCD_HPLL current 0.25A

L15

1 2

BLM21PG221SN1D

+V1.25S_PEGPLL_FB

C175

C175 10U/6.3V/X5R_8

10U/6.3V/X5R_8

R1180_6@IVR1180_6@IV

C565

0.1U/10V_4

R125

R125 1/F_8

1/F_8

IVCCD_LVDS current 0.15A

EC B-06

UMA & Discrete setting

CRT Discrete / UMA

--------------------R62 NC 0 R84 0 0.1U L61 NC STUFF C627 0 0.1U C628 NC NC R538 NC 0 R59 NC 0.02 R537 NC 0

C627

C627 0_4@MV

0_4@MV

IVCCA_LVDS current 0.01A

C624 NC NC C626 0 0.1U

+3V_VCCSYNC +VCCA_CRTDAC_R

+VCC_TVBG_R

+VCCA_DPLLA +VCCA_DPLLB +VCCA_HPLL +VCCA_MPLL

+VCC_TX_LVDS

C630

C630 1000P/16V_4@IV

1000P/16V_4@IV

IVCCA_PEG_BG current 0.04A

+VCCA_PEG_PLL

C92

C92 1U/6.3V/X5R_6

1U/6.3V/X5R_6

+VCCA_SM_CK

+VCC_TVDACA_R +VCC_TVDACB_R +VCC_TVDACC_R

+VCCD_CRT +VCCD_TVDAC_R

+VCCQ_TVDAC_R

+VCCA_PEG_PLL

C167

0.1U/10V_4

C180

0.1U/10V_4

+VCCD_LVDS

C151

C154

0_6@MV

C151 *10U/6.3V/X5R_8@NC

*10U/6.3V/X5R_8@NC

External VGA with @EV part, Internal VGA with @IV part.

U35H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0@MV

If:SDVO Disabled,VCCD_LVDS to GND. If:SDVO Enabled,VCCD_LVDS to +1.8V.

UMA & Discrete setting

LVDS Discrete / UMA

---------------------R118 NC 0 C154 0 1U C151 NC NC

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

VTT_10 VTT_11 VTT_12 VTT_13

VTT

VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

VCC_AXD_1

VCC_AXD_2 VCC_AXD_3

VCC_AXD_4

VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

+3V_VCC_HV

EC B-07

+3V_VCC_HV

U13

VTT_1

U12

VTT_2

U11

VTT_3

VTT_4

VTT_5

VTT_6

VTT_7

VTT_8

VTT_9

U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

0.47U/6.3V/X5R_4

*CH751H-40PT@NC

R5510_6R5510_6

+1.05V_VCCP

C568

4.7U/10V/X5R_8

+VCC_AXD

1U/6.3V/X5R_6

+VCC_SM_CK

+VCC_TX_LVDS

IVCC_HV current 0.1A

C629

0.1U/10V_4

+VTTLF1 +VTTLF2 +VTTLF3

C570

C48

0.47U/6.3V/X5R_4

+1.05V_VCCP

40 mil wide

+3V_VCC_HV_L

R136

R136 *10_6@NC

*10_6@NC

EC B-07

+3.3V

Ivtt_FSB core supply current 0.85A

C80

C567

2.2U/6.3V/X5R_6

4.7U/10V/X5R_8

L100_6L100_6

C121

C119

C119 *22U/4V/X6S_8@NC

*22U/4V/X6S_8@NC

Ivcc_AXD current 0.2A

Ivcc_AXF current 0.35A

C90

C113

1U/6.3V/X5R_6

C90 10U/6.3V/X5R_8

10U/6.3V/X5R_8

Ivcc_DMI current 0.1A

C170

0.1U/10V_4

C120

0.1U/10V_4

Ivcc_SM_CK current 0.2A

L111uH/300mA_8L111uH/300mA_8

R531/F_8R531/F_8

C112

C112 22U/4V/X6S_8

22U/4V/X6S_8

IVCC_TX_LVDS current 0.1A

+3V_VCC_HV

+VCC_PEG

+VCC_PEG[6]

C225

220U/2.5V_7343

C203

*10U/6.3V/X5R_8@NC

SizeDocument NumberRev

GMCH Power-2(5 of 6)

Date:Sheet of

C593

C186

10U/6.3V/X5R_8

C17

C64

0.47U/6.3V/X5R_4

C631

C631 0_4@MV

0_4@MV

220U/2.5V_7343

+V1.8_SMCK_RC

L181uH_8@IVL181uH_8@IV

C165

220U/2.5V_7343@IV

UMA & Discrete setting

LVDS Discrete / UMA

---------------------------L18 NC 1UH C165 NC 220U C631 0 1000P

L1691nH/1.5AL1691nH/1.5A

Ivcc_PEG PCI-E current 1.2A

Ivcc_RX_DMI current 0.25A

L17*91nH/1.5A@NCL17*91nH/1.5A@NC

C157

*220U/2.5V_7343@NC

PROJECT : NA1

Quanta Computer Inc.

+1.25V_M[6,43,48]

+1.25V_M

iAMT

+1.25V

+1.25V[17,43]

+1.25V

+1.8V_SUS

C11122U/4V/X6S_8C11122U/4V/X6S_8

955Friday, March 23, 2007

+1.8V_SUS

+1.05V_VCCP

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

NB(Power-3)

U35I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23

VSS_34

AF24

VSS_35

AF31

VSS_36

AG2

VSS_37

AG38

VSS_38

AG43

VSS_39

AG47

VSS_40

AG50

VSS_41

AH3

VSS_42

AH40

VSS_43

AH41

VSS_44

AH7

VSS_45

AH9

VSS_46

AJ11

VSS_47

AJ13

VSS_48

AJ21

VSS_49

AJ24

VSS_50

AJ29

VSS_51

AJ32

VSS_52

AJ43

VSS_53

AJ45

VSS_54

AJ49

VSS_55

AK20

VSS_56

AK21

VSS_57

AK26

VSS_58

AK28

VSS_59

AK31

VSS_60

AK51

VSS_61

AL1

VSS_62

AM11

VSS_63

AM13

VSS_64

AM3

VSS_65

AM4

VSS_66

AM41

VSS_67

AM45

VSS_68

AN1

VSS_69

AN38

VSS_70

AN39

VSS_71

AN43

VSS_72

AN5

VSS_73

AN7

VSS_74

AP4

VSS_75

AP48

VSS_76

AP50

VSS_77

AR11

VSS_78

AR2

VSS_79

AR39

VSS_80

AR44

VSS_81

AR47

VSS_82

AR7

VSS_83

AT10

VSS_84

AT14

VSS_85

AT41

VSS_86

AT49

VSS_87

AU1

VSS_88

AU23

VSS_89

AU29

VSS_90

AU3

VSS_91

AU36

VSS_92

AU49

VSS_93

AU51

VSS_94

AV39

VSS_95

AV48

VSS_96

AW1

VSS_97

AW12

VSS_98

AW16

VSS_99

CRESTLINE_1p0@MV

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U35J

C46

VSS_199

C50

VSS_200

VSS_201

D13

VSS_202

D24

VSS_203

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

VSS_217

F40

VSS_218

F50

VSS_219

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

VSS_231

H24

VSS_232

H28

VSS_233

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

VSS_247

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

VSS_260

M50

VSS_261

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

VSS_272

P19

VSS_273

VSS_274

P23

VSS_275

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

VSS_285

VSS_286

CRESTLINE_1p0@MV

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

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SizeDocument NumberRev

GMCH Power-3(6 of 6)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

1055Friday, March 23, 2007

Strap table

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up

CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin

Pin NameStrap description

CFG[2:0]

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

CFG[13:12]

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

DMI X2 Select

MCH_CFG_5

MCH_CFG_5[6]

Low = DMIX2 High = IDMIX4(Default)

FSB Frequency Select

Reserved

DMI X2 Select

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

DMI Lane Reversal

MCH_CFG_19

R43

R43 *4.02K/F_4@NC

*4.02K/F_4@NC R87

Low = Normal operation(Default) High = Reverse Lane

MCH_CFG_19[6]

+3.3V

R87 *4.02K/F_4@NC

*4.02K/F_4@NC

SDVO/PCIE Concurrent operation

FSB Dynamic ODT

MCH_CFG_16

MCH_CFG_16[6]

Low = ODT Disable High = ODT Enable(Default)

R44

R44 *4.02K/F_4@NC

*4.02K/F_4@NC

MCH_CFG_20

MCH_CFG_20[6]

Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port

+3.3V

R88

R88 *4.02K/F_4@NC

*4.02K/F_4@NC

Configuration

010 = FSB 800MHz 011 = FSB 667MHz

0 = DMI X2 1 = DMI X4(Default)

0 = Reserved 1 = Mobile CPU(Default)

0 = Normal mode 1 = Low Power mode

0 = Reverse Lanes 1 = Normal operation(Default)

00 = Reserved 01 = XOR Mode Enable 10 = All-Z Mode Enabled 11 = Normal operation(Default)

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default) 1 = SDVO Card Present

0 = Normal operation(Default) 1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

XOR /ALLz /Clock Un-gating

MCH_CFG_12MCH_CFG_13Configuration

MCH_CFG_12[6] MCH_CFG_13[6]

*4.02K/F_4@NC

Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.

Clock gating disable

XOR Mode Enable

ALL-z Mode Enable

Normal operation(Default)

R41

R61

R61 *4.02K/F_4@NC

*4.02K/F_4@NC

PCI Express Graphics

MCH_CFG_9

MCH_CFG_9[6]

SDVO Present

Strap define at External

Low = Reverse Lane High = Normal operation(Default)

R49

R49 *4.02K/F_4@NC

*4.02K/F_4@NC

SizeDocument NumberRev

GMCH Strap Table

Friday, March 23, 2007

Date:Sheet of

DVI control page

PROJECT : NA1

Quanta Computer Inc.

1155

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DDR2 Dual channel A/B PU

+0.9V_DDR_VTT

C244

0.1U/10V_4

+0.9V_DDR_VTT

C178

0.1U/10V_4

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

C237

C152

0.1U/10V_4

C168

C254

0.1U/10V_4

DDRII A CHANNEL

C164

C259

0.1U/10V_4

DDRII B CHANNEL

C177

C171

0.1U/10V_4

C241

C252

0.1U/10V_4

C153

C257

0.1U/10V_4

Please these resistor closely DIMMA,all trace length<750 mil.

C238

C159

0.1U/10V_4

C248

0.1U/10V_4

M_ODT1[6,13]

C258

0.1U/10V_4

C172

0.1U/10V_4

C174

0.1U/10V_4

DDR_A_MA7 DDR_A_MA11

DDR_A_MA4 DDR_A_MA6

DDR_A_MA13

DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA10 DDR_A_BS0

DDR_A_MA0 DDR_A_MA2

DDR_A_MA1

C243

0.1U/10V_4

C181

0.1U/10V_4

DDR_A_MA[0..13][7,13] DDR_B_MA[0..13][7,13]

DDR_A_RAS#[7,13] DDR_A_BS1[7,13]

M_ODT0[6,13]

DDR_A_BS2[7,13]

DDR_A_BS0[7,13]

DDR_A_WE#[7,13] DDR_A_CAS#[7,13]

DDR_CS0_DIMMA#[6,13]

DDR_CS1_DIMMA#[6,13] DDR_CKE0_DIMMA[6,13] DDR_CKE1_DIMMA[6,13]

C249

C258

C238

C245

0.1U/10V_4

C239

C160

0.1U/10V_4

RP2156X2RP2156X2

1 3

RP1756X2RP1756X2

1 3

RP956X2RP956X2

1 3

RP356X2RP356X2

1 3

RP2056X2RP2056X2

1 3

RP1656X2RP1656X2

1 3

RP1256X2RP1256X2

1 3

RP656X2RP656X2

1 3

RP456X2RP456X2

1 3

RP1356X2RP1356X2

1 3

R12756_4R12756_4 R14056_4R14056_4 R13556_4R13556_4 R12956_4R12956_4 R15156_4R15156_4 R15556_4R15556_4 R15356_4R15356_4

C251

0.1U/10V_4

C169

0.1U/10V_4

2 4

+0.9V_DDR_VTT

RP1856X2RP1856X2

RP1456X2RP1456X2

RP856X2RP856X2

RP256X2RP256X2

RP1156X2RP1156X2

RP1956X2RP1956X2

RP1556X2RP1556X2

RP756X2RP756X2

RP556X2RP556X2

RP1056X2RP1056X2

1 3

R13156_4R13156_4 R15456_4R15456_4 R13456_4R13456_4 R13256_4R13256_4 R14956_4R14956_4 R15256_4R15256_4 R14856_4R14856_4

2 4

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA13

DDR_B_MA1 DDR_B_MA3

DDR_B_MA9 DDR_B_MA12

DDR_B_MA5 DDR_B_MA8

DDR_B_MA10

DDR_B_MA2 DDR_B_MA0

+0.9V_DDR_VTT[43,47]

DDR_B_RAS#[7,13] DDR_B_BS1[7,13]

M_ODT2[6,13]

DDR_B_BS0[7,13]

DDR_B_WE#[7,13] DDR_B_CAS#[7,13]

M_ODT3[6,13]

DDR_B_BS2[7,13] DDR_CS2_DIMMB#[6,13] DDR_CS3_DIMMB#[6,13] DDR_CKE3_DIMMB[6,13] DDR_CKE4_DIMMB[6,13] DDR_B_MA14[6,13]DDR_A_MA14[6,13]

Please these resistor closely DIMMB,all trace length<750 mil.

+3.3V_M[2,13,16,43]

*MMBT3904_NL@NC

Q40

UninstallDDR2 Thermal Sensor SO-DIMM 0 & 1

SizeDocument NumberRev

DDR RES. ARRAY

Friday, March 23, 2007

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

+3.3V_M

C253

R171

*220_6@NC

VCC DXP DXN GND

*220_6@NC

LM86_3V

1 2 3 5

SCLK

SDA

ALERT#

OVERT#

*LM86CIMM@NC

CGCLK_SMB_M[2,13] CGDAT_SMB_M[2,13]

PM_EXTTS#0[6,13] PM_EXTTS#1[6]

R170*0_4@NCR170*0_4@NC

*0.1U/10V_4@NC

DDR_THERMDA

C759

C759 *2200P/50V_6@NC

*2200P/50V_6@NC

DDR_THERMDC

C253

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A is required to route to Top SoDIMM for AMT to function.This will need to change for M08

DDR_CKE0_DIMMA[6,12]

DDR_A_BS2[7,12]

DDR_A_BS0[7,12] DDR_A_WE#[7,12]

DDR_A_CAS#[7,12] DDR_CS1_DIMMA#[6,12]

M_ODT1[6,12]

+3.3V_M

iAMT

DDR2 Dual channel A/B CONN

V_DDR_MCH_REF

+1.8V_SUS

DDR_A_D0 DDR_A_D6

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D9 DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15 DDR_A_D11

DDR_A_D20 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23 DDR_A_D19

DDR_A_D25 DDR_A_D24

DDR_A_DM3

DDR_A_D30 DDR_A_D31

DDR_A_MA12 DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_D32 DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D39

DDR_A_D41 DDR_A_D40

DDR_A_DM5 DDR_A_D42

DDR_A_D46 DDR_A_D48

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D51 DDR_A_D50

DDR_A_D57 DDR_A_D61

DDR_A_DM7 DDR_A_D62

DDR_A_D59 CGDAT_SMB_M

CGCLK_SMB_M

CN21

VREF

VSS47

DQ0

DQ1

VSS37

DQS#0

DQS0

VSS48

DQ2

DQ3

VSS38

DQ8

DQ9

VSS49

DQS#1

DQS1

VSS39

DQ10

DQ11

VSS50

VSS18

DQ16

DQ17

VSS1

DQS#2

DQS2

VSS19

DQ18

DQ19

VSS22

DQ24

DQ25

VSS23

DM3

NC4

VSS9

DQ26

DQ27

VSS4

CKE0

VDD7

NC1

A16_BA2

VDD9

A12

VDD5

101

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

DIMM1_9.2

H 9.2

CKE 0,1

CLOCK 0,1

+1.8V_SUS

VSS46

DQ4

DQ5

VSS15

DM0

VSS5

DQ6

DQ7

VSS16

DQ12

DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14

DQ15

VSS54

VSS20

DQ20

DQ21

VSS6

NC3

DM2

VSS21

DQ22

DQ23

VSS24

DQ28

DQ29

VSS25

DQS#3

DQS3

VSS10

DQ30

DQ31

VSS8

CKE1

VDD8

A15

A14

VDD11

A11

VDD4

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

100

102

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

DDR_A_DM[0..7][7] DDR_A_D[0..63][7] DDR_A_DQS[0..7][7] DDR_A_DQS#[0..7][7] DDR_A_MA[0..13][7,12]

DDR_A_D4 DDR_A_D5

DDR_A_DM0 DDR_A_D1

DDR_A_D7 DDR_A_D12

DDR_A_D8 DDR_A_DM1

M_CLK_DDR0[6]

DDR_A_D14 DDR_A_D10

DDR_A_D21 DDR_A_D16

DDR_A_DM2 DDR_A_D18

DDR_A_D22 DDR_A_D29

DDR_A_D28 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D26

DDR_A_D27

DDR_A_MA11 DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2 DDR_A_MA0

DDR_A_MA13

DDR_A_D36 DDR_A_D33

DDR_A_DM4 DDR_A_D35

DDR_A_D38 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D43

DDR_A_D47 DDR_A_D53

DDR_A_D49

DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D56 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D58

DDR_A_D63

R51

R51 10K_4

10K_4

M_CLK_DDR#0[6]

PM_EXTTS#0[6,12] PM_EXTTS#0[6,12]

DDR_CKE1_DIMMA[6,12]

DDR_A_MA14[6,12] DDR_B_MA14[6,12]

DDR_A_BS1[7,12] DDR_A_RAS#[7,12] DDR_CS0_DIMMA#[6,12]

M_ODT0[6,12]

M_CLK_DDR1[6] M_CLK_DDR#1[6]

CGDAT_SMB_M[2,12] CGCLK_SMB_M[2,12]

R57

R57 10K_4

10K_4

+3.3V_M

iAMT

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D7 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D17 DDR_B_D21

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE3_DIMMB[6,12]

DDR_B_BS2[7,12]

DDR_B_CAS#[7,12]

DDR_CS3_DIMMB#[6,12]

DDR_B_MA12 DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10

DDR_B_BS0[7,12] DDR_B_WE#[7,12]

M_ODT3[6,12]

DDR_B_D32 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D46

DDR_B_D47 DDR_B_D48

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55 DDR_B_D50

DDR_B_D57 DDR_B_D60

DDR_B_DM7 DDR_B_D62

DDR_B_D59 CGDAT_SMB_M

CGCLK_SMB_M

+1.8V_SUS

V_DDR_MCH_REF

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

V_DDR_MCH_REF[6,47]

CN22

VREF

VSS47

DQ0

DQ1

VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50

VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)

DIMM2_5.2

H 5.2

+1.8V_SUS

VSS46

DQ4 DQ5

VSS15

DM0

VSS5

DQ6 DQ7

VSS16

DQ12 DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14 DQ15

VSS54 VSS20

DQ20 DQ21 VSS6

NC3 DM2

VSS21

DQ22 DQ23

VSS24

DQ28

DQ29 VSS25 DQS#3

DQS3

VSS10

DQ30

DQ31

VSS8

CKE1

VDD8

A15 A14

VDD11

A11

A7 A6

VDD4

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A4 A2 A0

VDD12

BA1

RAS#

S0# VDD1 ODT0

A13 VDD6

NC2

VSS12

DQ36 DQ37

VSS28

DM4

VSS42

DQ38 DQ39

VSS55

DQ44 DQ45

VSS43 DQS#5

DQS5

VSS56

DQ46 DQ47

VSS44

DQ52 DQ53

VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54 DQ55

VSS35

DQ60 DQ61 VSS7

DQS#7

DQS7

VSS36

DQ62 DQ63

VSS13

SA0 SA1

GND

202

DDR_B_D4

DDR_B_D5

6 8

DDR_B_DM0

10 12

DDR_B_D6

DDR_B_D2

16 18

DDR_B_D12

DDR_B_D13

22 24

DDR_B_DM1

26 28 30 32 34

DDR_B_D14

DDR_B_D15

38 40

DDR_B_D16

DDR_B_D20

46 48 50

DDR_B_DM2

52 54

DDR_B_D18

DDR_B_D19

58 60

DDR_B_D24

DDR_B_D25

64 66

DDR_B_DQS#3

DDR_B_DQS3

70 72

DDR_B_D31

DDR_B_D30

76 78 80 82 84 86 88

DDR_B_MA11

DDR_B_MA7

DDR_B_MA6

94 96

DDR_B_MA4

DDR_B_MA2

100

DDR_B_MA0

102 104 106 108 110 112 114

DDR_B_MA13

116 118 120 122

DDR_B_D37

124

DDR_B_D38

126 128

DDR_B_DM4

130 132

DDR_B_D39

134

DDR_B_D33

136 138

DDR_B_D44

140

DDR_B_D45

142 144

DDR_B_DQS#5

146

DDR_B_DQS5

148 150

DDR_B_D42

152

DDR_B_D43

154 156

DDR_B_D49

158

DDR_B_D53

160 162 164 166 168

DDR_B_DM6

170 172

DDR_B_D54

174

DDR_B_D51

176 178

DDR_B_D56

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D63

192

DDR_B_D58

194 196 198 200

R5610K_4R5610K_4

R50

R50 10K_4

10K_4

DDR_B_DM[0..7][7] DDR_B_D[0..63][7] DDR_B_DQS[0..7][7] DDR_B_DQS#[0..7][7] DDR_B_MA[0..13][7,12]

M_CLK_DDR3[6] M_CLK_DDR#3[6]

DDR_CKE4_DIMMB[6,12]

DDR_B_BS1[7,12] DDR_B_RAS#[7,12] DDR_CS2_DIMMB#[6,12]

M_ODT2[6,12]

M_CLK_DDR4[6] M_CLK_DDR#4[6]

+3.3V_M

iAMT

+1.8V_SUS

Place these Caps near So-Dimm1.

EC C-03

Delete C124

2.2U/6.3V/X5R_6

+1.8V_SUS

C214

0.1U/10V_4

V_DDR_MCH_REF

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6 C236

0.1U/10V_4

C185

0.1U/10V_4

C340

0.1U/10V_4

2.2U/6.3V/X5R_6

+1.8V_SUS

C204

2.2U/6.3V/X5R_6

+1.8V_SUS

C233

V_DDR_MCH_REF

C341

0.1U/10V_4

C183

C235

2.2U/6.3V/X5R_6

C231

0.1U/10V_4

iAMT

+3.3V_M

C108

2.2U/10V/X5R_6

C339

Place these Caps near So-Dimm2.

C212

2.2U/6.3V/X5R_6

C219

C224

0.1U/10V_4

C342

2.2U/6.3V/X5R_6

C234

2.2U/6.3V/X5R_6

C220

0.1U/10V_4

C179

2.2U/6.3V/X5R_6

0.1U/10V_4

iAMT

+3.3V_M

C115

2.2U/10V/X5R_6

C207

2.2U/6.3V/X5R_6

C94

0.1U/10V_4

C162

2.2U/6.3V/X5R_6

C182

C210

C236

C110

0.1U/10V_4

CKE 2,3

SMbus address A0

CLOCK 3,4

+3.3V_M[2,12,16,43]

SMbus address A4

SizeDocument NumberRev

DDR SO-DIMM(200P)

Friday, March 23, 2007

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

1355

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

RTC

+RTC_CELL

+3.3V_ALW

VCCRTC_4

+5V_ALW

Place all series terms close to ICH8 except for SDIN input lines,which should be close to source.Placement of R292, R286, R283 & R289 should equal distance to the T split trace point as R291, R285, R284 & R290 respective. Basically,keep the same distance from T for all series termination resistors.

CH501H-40PT

CH501H-40PT D6

CH501H-40PT

R233

R233 1K_4

1K_4

+1.8V_SUS

CN10

JAE-FI-S2P-HF

R2181.2K_4R2181.2K_4

R219

4.7K_4

R224

R224 15K_4

15K_4

ICH_AZ_MDC_BITCLK[32] ICH_AZ_CODEC_BITCLK[31]

ICH_AZ_MDC_SYNC[32] ICH_AZ_CODEC_SYNC[31] ICH_AZ_MDC_RST#[32] ICH_AZ_CODEC_RST#[31] ICH_AZ_MDC_SDOUT[32] ICH_AZ_CODEC_SDOUT[31]

SATA_TX0-[34] SATA_TX0+[34]

SATA_TX2-[34] SATA_TX2+[34]

Distance between the ICH-8 M and cap on the "P" signal should be identical distance between the ICH-6 M and cap on the "N" signal for same pair.

R220

1M/F_4

*10P/50V_4@NC

+RTC_CELL

R21620K_4R21620K_4

*SHORT_PAD

R2221K_4R2221K_4

C700

C7013900P/25VC7013900P/25V C6983900P/25VC6983900P/25V

C4223900P/25VC4223900P/25V C4213900P/25VC4213900P/25V

C3061U/10V/X5R_6C3061U/10V/X5R_6

VCCRTC_2VCCRTC_1

R61433_4R61433_4 R61333_4R61333_4

C699

C699 *10P/50V_4@NC

*10P/50V_4@NC

R60533_4R60533_4 R61933_4R61933_4 R30833_4R30833_4 R30733_4R30733_4 R30633_4R30633_4 R30533_4R30533_4

SATA_TX0-_C SATA_TX0+_C

SATA_TX2-_C SATA_TX2+_C

VCCRTC_3

C343

1U/10V/X5R_6

Q14

Q14 MMBT3904_NL

MMBT3904_NL

ACZ_BIT_CLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

*10K_4@NC

R608

+3.3V_S5

ENERGY_DET

+1.5V_PCIE_ICH[15,17]

C69618P/50V_4C69618P/50V_4

32.768KHZY632.768KHZ

C69718P/50V_4C69718P/50V_4

+1.5V_PCIE_ICH

EC B-08

+3.3V

1 4

2 3

GLAN_CLK[27]

LAN_RSTSYNC[27]

LAN_RXD0[27] LAN_RXD1[27] LAN_RXD2[27]

LAN_TXD0[27] LAN_TXD1[27] LAN_TXD2[27]

ENERGY_DET[28]

R39524.9/F_4R39524.9/F_4

ICH_AZ_CODEC_SDIN0[31] ICH_AZ_MDC_SDIN1[32]

R642*0_4@NCR642*0_4@NC

R32810K_4R32810K_4 R60310K_4R60310K_4

SATA_LED#[38]

SATA_RX0-[34] SATA_RX0+[34]

SATA_RX2-[34] SATA_RX2+[34]

CLK_PCIE_SATA#[2] CLK_PCIE_SATA[2]

R63024.9/F_4R63024.9/F_4

Layout Note: L<500mils

SB Strap

ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

R622

R622 10M_6

10M_6

ICH_RTCX1 ICH_RTCX2

RTCRST# SM_INTRUDER# ICH_INTVRMEN

LAN100_SLP

ENERGY_DET

GLAN_COMP_SB

ACZ_BIT_CLK ACZ_SYNC

ACZ_RST#

ACZ_SDIN2

T119T119

ACZ_SDIN3

T47T47

ACZ_SDOUT

GPIO33 GPIO34

SATA_LED#

SATA_TX0-_C SATA_TX0+_C

R62910K_4R62910K_4 R62310K_4R62310K_4

SATA_TX2-_C SATA_TX2+_C

SATA_BIAS

+RTC_CELL

R333

R333 332K/F_4

332K/F_4

Low = Internal VR Disabled High = Internal VR Enabled(Default)

U39A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

ICH_INTVRMEN

R330

R330 *0_4@NC

*0_4@NC

ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

FWH0/LAD0

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DD10 DD11 DD12 DD13 DD14 DD15

DCS1# DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

C4 G9

E6 AF13

AG26 AF26

AE26 AD24 AG29 AF27 AE24

AC20 AH14

AD23

NMI

AG28 AA24 AE27 AA23

TP8

DD0

DD1

DD2

DD3

DD4

DD5

AB2

DD6

DD7

DD8

DD9

T4 V6 V5 U1 V2 U6

AA4

DA0

AA1

DA1

AB3

DA2

Y6 Y5

W4 W3 Y2 Y3 Y1 W5

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

CPUPWRGD/GPIO49

IHDA

IDE

SATA

+RTC_CELL

R329

R329 332K/F_4

332K/F_4

LAN100_SLP

R334

R334 *0_4@NC

*0_4@NC

Low = Internal VR Disabled High = Internal VR Enabled(Default)

LDRQ#1

T62T62

GATEA20

H_DPRSTP# H_DPSLP#

H_FERR#

RCIN#

H_THERMTRIP_R

ICH_TP8

T50T50

IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8

IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15

IDE_DD[0..15]

LPC_LAD0[33,37,38,39] LPC_LAD1[33,37,38,39] LPC_LAD2[33,37,38,39] LPC_LAD3[33,37,38,39]

LPC_LFRAME#[33,37,38,39]

LPC_LDRQ0#[39]

GATEA20[37] H_A20M#[3]

H_DPRSTP#[3,6,50] H_DPSLP#[3]

H_FERR#[3] H_PWRGOOD[3] H_IGNNE#[3] H_INIT#[3]

H_INTR[3] RCIN#[37]

H_NMI[3] H_SMI#[3]

H_STPCLK#[3]

R34624/F_6R34624/F_6

IDE_DA0[34] IDE_DA1[34] IDE_DA2[34]

IDE_DCS1#[34] IDE_DCS3#[34]

IDE_DIOR#[34] IDE_DIOW#[34] IDE_DDACK#[34] IDE_IRQ[34] IDE_DIORDY[34] IDE_DDREQ[34]

+1.05V_VCCP

IDE_DD[0..15][34]

R336

*56.2/F_4@NC

H_DPSLP# H_DPRSTP# H_FERR#

R342

Layout Note:

56.2/F_4

Placement close SB L<2"

RV4

RV4 V-PORT-0603-220K-V05

V-PORT-0603-220K-V05

EC C-02

RCIN# GATEA20

R331

*56.2/F_4@NC

+3.3V +3.3V

+1.05V_VCCP

R340

56.2/F_4

R283

R611

10K_4

H_THERMTRIP#[3,6]

XOR Chain Entrance Strap

ICH_RSV0

HDA_SDOUTDescription

RSVD

Enter XOR Chain

Normal opration(Default)

Set PCIE port config bit 1

+3.3V

R335

R335 *1K_4@NC

*1K_4@NC

ACZ_SDOUT

R323

R323 *1K_4@NC

*1K_4@NC

ICH_RSVD[16]

<OrgAddr4> SizeDocument NumberRev

SizeDocument NumberRev

ICH8M HOST(1 of 4)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

1455Friday, March 23, 2007

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

Place TX DC blocking caps close ICH8.

PCIE_TX1-[33] PCIE_TX1+[33]

PCIE_TX2-[33] PCIE_TX2+[33]

PCIE_TX6-/GLAN_TX-[27] PCIE_TX6+/GLAN_TX+[27]

SB-PCI

PCI_AD[0..31][29]

PCI_PIRQB#[29] PCI_PIRQC#[29] PCI_PIRQD#[29]

Cardbus/ CardReader/1394

Smart Card

T124T124

C7110.1U/10V_4C7110.1U/10V_4 C7140.1U/10V_4C7140.1U/10V_4

C7150.1U/10V_4C7150.1U/10V_4 C7160.1U/10V_4C7160.1U/10V_4

C5110.1U/10V_4C5110.1U/10V_4 C5100.1U/10V_4C5100.1U/10V_4

EC B-09

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_C PCIE_TXP2_C

GLAN_TXN_C GLAN_TXP_C

ICH_SPI_CLK[36] ICH_SPI_CS0#[36]

ICH_SPI_DIN[36] ICH_SPI_DO[36]

USB_OC0#[35]

USB_OC4#[40] WLAN_RF_OFF#[33,38]

BAYINS#[34,37]

iAMT

USB_OC2# USB_OC0# USB_OC5# OC9#

+3.3V_S5

+3.3V_S5 +3.3V_S5

U39B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

AD15

C11

AD16

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

AD27

AD28

AD29

AD30

AD31

Interrupt I/F

PIRQA#

PIRQB#

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

PIRQA

GNT0REQ0

PIRQB PIRQC

PIRQD (For R5C853)

PCI

PCIE_RX6-/GLAN_RX-[27] PCIE_RX6+/GLAN_RX+[27]

Rev:B

RP36

6 7 8 9

10P8R-10K

R28410K_4R28410K_4 R28510K_4R28510K_4

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST# DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PCIE_RX1-[33] PCIE_RX1+[33]

MiniWWAN

PCIE_RX2-[33] PCIE_RX2+[33]

MiniWLAN

R42815_4R42815_4 R42915_4R42915_4

R4330_4R4330_4

A4 D7 E18 C18 B19 F18 A11 C10

C17 E15 F16 E17

C8 D9

PAR

G6 D16 A7 B7 F10 C16 C9 A17

AG24 B10 G7

F8 G11 F12 B3

GLAN_TXN_C GLAN_TXP_C

SPI_CS1#_R

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# WLAN_RF_OFF# BAYINS# OC8# OC9#

+3.3V_S5

USB_OC4#

OC8#

WLAN_RF_OFF#

BAYINS#

USB_OC3# USB_OC1#

PCI_REQ0# PCI_GNT0# BOARD_ID1 BOARD_ID2 PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#

PCI_IRDY#

PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#

PLTRST#_NB CLK_PCI_ICH

BAYID0 BAYID1 ICH_GPIO4_PIRQG# ICH_GPIO5_PIRQH#

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_C PCIE_TXP2_C

U39D

AJ19 AG16 AG15 AE15

AF15 AG17 AD12

AJ18 AD14 AH18

P27 P26 N29 N28

M27 M26 L29 L28

K27 K26 J29 J28

H27 H26 G29 G28

F27 F26 E29 E28

D27 D26 C29 C28

C23 B23 E22

D23 F21

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#

ICH8M REV 1.0

USB

PCI-Express

DMI_IRCOMP

SPI

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI_CLKN DMI_CLKP

DMI_ZCOMP

Direct Media Interface

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBRBIAS#

USBRBIAS

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

Y23 Y24

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

F2 F3

ICH8 Boot BIOS select

Boot BIOS Strap

GNT0#SPI_CS1#

No stuff No stuff Stuff

R425

*10_4@NC

C517

No stuff Stuff No stuff

+3.3V

1 2

11LPC PCI SPI1001

R397*1K_4@NCR397*1K_4@NC

SPI_CS1#_R PCI_GNT0# PCI_GNT3#

R403*1K_4@NCR403*1K_4@NC

PCI_REQ0#[29] PCI_GNT0#[29] BOARD_ID1[16] BOARD_ID2[16]

T63T63

PCI_C_BE0#[29] PCI_C_BE1#[29] PCI_C_BE2#[29] PCI_C_BE3#[29]

PCI_IRDY#[29] PCI_PAR[29] PCIRST#[29] PCI_DEVSEL#[29] PCI_PERR#[29]

PCI_SERR#[29] PCI_STOP#[29] PCI_TRDY#[29] PCI_FRAME#[29]

CLK_PCI_ICH[2] ICH_PME#[29]

BAYID0[16,34] BAYID1[34]

CLK_PCI_ICH

Reserved for EMI. Place resister and cap close to ICH.

*10P/50V_4@NC

DMI_MTX_IRX_N0[6] DMI_MTX_IRX_P0[6] DMI_MRX_ITX_N0[6] DMI_MRX_ITX_P0[6]

DMI_MTX_IRX_N1[6] DMI_MTX_IRX_P1[6] DMI_MRX_ITX_N1[6] DMI_MRX_ITX_P1[6]

DMI_MTX_IRX_N2[6] DMI_MTX_IRX_P2[6] DMI_MRX_ITX_N2[6] DMI_MRX_ITX_P2[6]

DMI_MTX_IRX_N3[6] DMI_MTX_IRX_P3[6] DMI_MRX_ITX_N3[6] DMI_MRX_ITX_P3[6]

CLK_PCIE_ICH#[2] CLK_PCIE_ICH[2]

DMI_IRCOMP_R

USBP0-[35] USBP0+[35] USBP1-[31] USBP1+[31] USBP2-[28] USBP2+[28] USBP3-[28] USBP3+[28] USBP4-[40] USBP4+[40] USBP5-[34] USBP5+[34] USBP6-[33] USBP6+[33] USBP7-[33] USBP7+[33] USBP8-[38] USBP8+[38] USBP9-[36] USBP9+[36]

USB_RBIAS_PN

A16 SWAP Override strap

PCI_GNT3#

C4400.1U/10V_4C4400.1U/10V_4

U17

TC7SH08FU(F)

+1.5V_PCIE_ICH

System System System System Docking 1 BAY(FDD) MiniCard 1 WWAN MiniCard 2 WWAN FINGER PRINT BLUETOOTH

Short F2 and F3 at the package

R393

and keep length to less than

22.6/F_6

500mils. Trace Impedance should be 60ohms +/- 15%.

Low = A16 swap override enabled High = Default

R406*1K_4@NCR406*1K_4@NC

PLTRST#_NB[6]

PLTRST#[16,18,33,38,39,41]

R350

R350 100K_4

100K_4

R353

24.9/F_4

Layout Note: DMI_IRCOMP_R<500mils

PCI Pullups

PCI_REQ2# PCI_REQ3# PCI_FRAME#

ICH_GPIO4_PIRQG# BAYID1 PCI_TRDY# PCI_PIRQD#

+3.3V

ICH_GPIO5_PIRQH# PCI_REQ0# PCI_PLOCK# BAYID0

+3.3V

SizeDocument NumberRev

ICH8M PCIE(2 of 4)

Friday, March 23, 2007

Date:Sheet of

Quanta Computer Inc.

R4178.2K_4R4178.2K_4 R4158.2K_4R4158.2K_4 R4198.2K_4R4198.2K_4

RP38

6 7 8 9

8.2KX8

8.2KX8 RP37

RP37

6 7 8 9

8.2KX8

PROJECT : NA1

+3.3V

5 4 3 2 1

+3.3V

5 4 3 2 1

1555

PCI_DEVSEL# PCI_STOP# PCI_IRDY# PCI_SERR#

PCI_PIRQB# PCI_PIRQC# PCI_PIRQA# PCI_PERR#

+3.3V

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

iAMTiAMT

R26910K_4R26910K_4 R31310K_4R31310K_4 R2681K_4R2681K_4

R28610K_4@Non_AMTR28610K_4@Non_AMT

AMT / Non_AMT R286 NC 10K

+3.3V

R304

8.2K_4

R318

*10K_4@NC

PANEL_DET

RST_BAY#[34]

+3.3V_S5

R31210K_4R31210K_4 R30910K_4R30910K_4 R29910K_4R29910K_4 R31710K_4R31710K_4 R63910K_4R63910K_4 R62110K_4R62110K_4 R314*10K_4@NCR314*10K_4@NC R34710K_4R34710K_4

R35210K_4R35210K_4

+3.3V

R3488.2K_4R3488.2K_4 R616*10K_4@NCR616*10K_4@NC R28210K_4R28210K_4

R612*2.2K_4@NCR612*2.2K_4@NC R32710K_4R32710K_4

R6181K_4R6181K_4 R3031K_4R3031K_4 R3431M_4R3431M_4 R61010K_4R61010K_4

CLKRUN#

Option to " Disable " clkrun. Pulling it down will keep the clks running.

Low = 14" Panel High = 15" Panel

R339

100K_4

ICH_RI# SCI# ICH_PCIE_WAKE#

ICH_CL_RST1#

+3.3V

C4390.1U/10V_4 C4390.1U/10V_4

U16

TC7SH08FU(F)

R338*0_4@NCR338*0_4@NC

PM_BATLOW#_R KBSMI# RST_BAY_R# BT_ON# DNBSWON# BAYON# EC_ME_ALERT ME_EC_ALERT

LAN_PHYPC

EC B-11

THERM_ALERT# MCH_ICH_SYNC#_R IRQ_SERIRQ

VR_PWRGD_CLKEN# RSVD_GPIO7

PANEL_DET SIM_DETECT TPM_SENSE# FPBACK#

EC B-11

+3.3V_S5+3.3V_S5

R6202.2K_4R6202.2K_4 R6022.2K_4R6022.2K_4 R26710K_4R26710K_4 R27010K_4R27010K_4

+3.3V_M

R434*10K_4@AMTR434*10K_4@AMT R440*10K_4@AMTR440*10K_4@AMT

ICH_SMBCLK[2,33,40] ICH_SMBDATA[2,33,40]

ICH_CL_RST1#[33]

LPC_PD#[38,39] ITP_DBRESET#[3]

PM_BMBUSY#[6] SCI#[37]

H_STP_PCI#[2] H_STP_CPU#[2]

ICH_PCIE_WAKE#[33]

IRQ_SERIRQ[29,37,38,39]

THERM_ALERT#[3]

FPBACK#[25] KBSMI#[37]

LAN_PHYPC[27]

PANEL_DET[25]

SIM_DETECT[33]

1 2

MCH_ICH_SYNC#[6]

PANEL_DET SIM_DETECT

EC C-04

BT_ON#[36] SATA_CLKREQ#[2]

TPM_SENSE#[38]

ACZ_SPKR[31]

ICH_RSVD[14]

R6040_4R6040_4

VR_PWRGD_CLKEN#[50]

Rev:B

EC C-05

No Reboot strap

HDA_SPKR

+3.3V

PM_DPRSLPVR RSMRST#

PM_LAN_ENABLE_R ICH_CL_PWROK LAN_WOL_EN

Low = Default High = No Reboot

ACZ_SPKR

R337*10K_4@NC R337*10K_4@NC

R606*100K_4@NCR606*100K_4@NC R63210K_4R63210K_4 R300*1M_4@NCR300*1M_4@NC R4001M_4R4001M_4 R326100K_4R326100K_4

ICH_SMBCLK ICH_SMBDATA AMT_SMBCLK AMT_SMBDATA

EC B-10

R65610K_4R65610K_4 R65710K_4R65710K_4

H_STP_PCI# H_STP_CPU#

ICH_SMBCLK ICH_SMBDATA ICH_CL_RST1# AMT_SMBCLK AMT_SMBDATA

ICH_RI# LPC_PD#

SCI# H_STP_PCI#

H_STP_CPU# CLKRUN# ICH_PCIE_WAKE#

IRQ_SERIRQ THERM_ALERT#

T118T118

SWAPBLINK FPBACK# RSVD_GPIO7 KBSMI# LAN_PHYPC BOARD_ID0

BOARD_ID3

BT_ON# RST_BAY_R# SATA_CLKREQ# SWAPLED SWAPLED1

ACZ_SPKR MCH_ICH_SYNC#_R

NL17SZ14DFT2G

U15

1 2

U39C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

+3.3V

C4110.1U/10V_4C4110.1U/10V_4

5 43

R271

100K_4

AMT_SMBCLK

+3.3V_S5

AMT_SMBDATA

SWAPLED

SWAP#

SWAPLED1 SWAP#

+3.3V_S5

SMB

SYS

GPIO

SYS

GPIO

MISC

R27510K_4R27510K_4

R27610K_4R27610K_4

D10

SW1010CPT

Q43

*2N7002W-7-F@AMT

ABCLK

Q42

*2N7002W-7-F@AMT

ABDATA

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36

SATA

GPIO

SATA

GPIO

SATA3GP/GPIO37

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

DELAY_VR_PG[6,50]

+3.3V

R273

R273 100K_4

100K_4

SW1010CPT

ABCLK[3,37,45]

ABDATA[3,37,45]

CLK14

CLK48 SUSCLK SLP_S3#

SLP_S4# SLP_S5#

PWROK

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST#

PWROK[37,43]

+3.3V

R274

R274 100K_4

100K_4

Z1606

iAMT

AJ12 AJ10 AF11 AG11

AG9 G5

D3 AG23

AF21 AD18

AH27 AE23 AJ14 AE21 C2

PM_LAN_ENABLE_RVR_PWRGD_CLKEN

AH20 AG27 E1 E3 AJ25 F23

AE18 F22

AF19 D24

AH23 AJ23 AJ27

AJ24 AF22 AG19

+3.3V

R636

R636 2K_4

2K_4

R637

R637 100K_4

100K_4

Q19

Q19 2N7002E

2N7002E

+3.3V

2 1

U13

TC7SET32FU(T5L,F,T)

CLK_ICH_14M CLK_ICH_48M

ICH_SUSCLK SLP_S3#

SLP_S4# SLP_S5#

ICH_PWROK PM_DPRSLPVR_R PM_BATLOW#_R DNBSWON#

PM_RSMRST#_R

ICH_CL_PWROK

CL_VREF0_SB CL_VREF1_SB

BAYON# ME_EC_ALERT EC_ME_ALERT LAN_WOL_EN

+3.3V_SUS

C7090.1U/10V_4C7090.1U/10V_4

TC7SH08FU(F)

SWAPLED#

R272

R272 100K_4

100K_4

SWAPBLINK

SWAPLED1#

Q18

Q18 2N7002E

2N7002E

R6070_4R6070_4 R6178.2K_4R6178.2K_4

R6098.2K_4R6098.2K_4 R2808.2K_4R2808.2K_4 R2818.2K_4R2818.2K_4

T65T65

R288100/F_4R288100/F_4 R287100/F_4R287100/F_4

T51T51

R615100/FR615100/F

R3110_4R3110_4 R660*0_4@NCR660*0_4@NC R310*0_4@NCR310*0_4@NC R633100/F_4R633100/F_4

U38

EC B-12

ICH_PWROKICH_PWROKVR_PWRGD_CLKENVR_PWRGD_CLKEN

R634

R634 10K_4

10K_4

SWAPLED#[38]

200Hz_LED#[37]

SWAPLED1#[38]

+3.3V

PM_DPRSLPVR

RSMRST#

BAYID0[15,34]

CLK_ICH_14M[2] CLK_ICH_48M[2]

SUSB#[37] SUSC#[37]

S4_STAT#[37]

PM_DPRSLPVR[6,50]CLKRUN#[29,38,39]

DNBSWON#[37] PM_LAN_RST#[27,37] PLTRST#[15,18,33,38,39,41]

RSMRST#[37] CLK_PWRGD[2] ICH_CL_PWROK[6,43] SUSM#[37]

ICH_CL_RST0#[6] BAYON#[34]

ME_EC_ALERT[37] EC_ME_ALERT[37] LAN_WOL_EN[37]

Default

RSV

+3.3V

R430

R430 10K_4

10K_4

R431

R431 *10K_4@NC

*10K_4@NC

Place these close to ICH7.

CLK_ICH_48M CLK_ICH_14M

R638

R638 *10_4@NC

*10_4@NC

C722

C722 *10P/50V_4@NC

*10P/50V_4@NC

If no use internal LAN MAC connect LAN_RST# to PLTRST# Use internal LAN MAC connect LAN_RST# to RSMRST# should go high no sooner than 10 ms after both VccLAN3_3 and VccLAN1_5 have reached their nominal voltages.

+3.3V_S5

CL_CLK0[6] ICH_CL_CLK1[33]

CL_DATA0[6] ICH_CL_DATA1[33]

R316

453/F_4

ID2

ID3

+3.3V +3.3V

R401

R401 10K_4

10K_4

R396

R396 *10K_4@NC

*10K_4@NC

SizeDocument NumberRev

ICH8M GPIO(3 of 4)

Date:Sheet of

+3.3V

R301

R301 10K_4

10K_4

R319

R319 *10K_4@NC

*10K_4@NC

PROJECT : NA1

Quanta Computer Inc.

iAMT

+3.3V_M

R315

3.24K/F_4

C423

0.1U/10V_4

Controller Link 1 VREF for IAMT support only

ID0ID1Board ID

1 00

R341

GPIO[20]--Integrated

1K_4

Pull-Down 20K.

R349

R349 *10K_4@NC

*10K_4@NC

BOARD_ID0 BOARD_ID1 BOARD_ID2

R302

R302 *33_4@NC

*33_4@NC

C415

C415 *10P/50V_4@NC

*10P/50V_4@NC

R384

3.24K/F_4

R390

R390 453/F_4

453/F_4

BOARD_ID3

BOARD_ID1[15] BOARD_ID2[15]

1655Friday, March 23, 2007

C497

0.1U/10V_4

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

+RTC_CELL

C454

1U/10V/X5R_6

R405100_6R405100_6

+5V

2 1

+3.3V

D15CH751H-40PTD15CH751H-40PT

iAMT

+3.3V_S5

+1.5V

FB_330ohm+-25%_100mHz_

1.5A_0.09 ohm DC

+1.5V

R39110_6R39110_6

+5V_S5

2 1

D13CH751H-40PTD13CH751H-40PT

L45BLM21PG331SN1DL45BLM21PG331SN1D

R3220_6R3220_6

+1.5V_APLL_RR

C484

0.1U/10V_4

+1.5V_PCIE_ICH

220U/2.5V_7343

L4410uH/100MAL4410uH/100MA

10U/6.3V/X5R_8

1U/10V/X5R_6

V5REF current 0.001A

C509

0.1U/10V_4

V5REF_SUS current 0.001A

Ivcc1_5_B current 0.657A

C475

C486

C486 22U/6.3V/X5R_8

22U/6.3V/X5R_8

IvccSATAPLL current 0.047A

C420

C459

0.1U/10V_4

C487

C487 22U/6.3V/X5R_8

22U/6.3V/X5R_8

+1.5V

C428

C428 1U/6.3V/X5R_6

1U/6.3V/X5R_6

+1.5V

+ICH_V5REF_RUN +ICH_V5REF_SUS

Ivcc1_5_A current 1.08A

+1.5V

IVCCUSBPLL current 0.01A

+1.5V

T64T64

iAMT

+3.3V_LAN

+1.5V

R4350_6R4350_6

R4581/F_8R4581/F_8

VCCGLANPLL

L52

IvccLAN3_3 current 0.019A

C482

IVCCGLANPLL current 0.023A

0.1U/10V_4

1uH_300mA

C533

10U/6.3V/X5R_8

+1.5V_PCIE_ICH

C516

2.2U/6.3V/X5R_6

T61T61

+3V_VCCLAN

+1.5V_VCCGLANPLL

IVCCGLAN1_5 current 0.08A

IvccGLAN3_3 current 0.001A

C447

0.1U/10V_4

C473

2.2U/6.3V/X5R_6

+1.5V_APLL

C437

C437 1U/6.3V/X5R_6

1U/6.3V/X5R_6

C468

C468 1U/6.3V/X5R_6

1U/6.3V/X5R_6

C493

0.1U/10V_4

C469

0.1U/10V_4

TP_VCCSUSLAN1 TP_VCCSUSLAN2

C479

4.7U/10V/X5R_8

U39F

+3.3V

AD25

AA25 AA26 AA27 AB27 AB28 AB29

AC10

G24

M24 M25

W25

AE7 AG7

AH7

AC1 AC2 AC3 AC4 AC5

AC9 AA5

AA6 G12

G17

AC7 AD7

W23

G18

G20

A16

D28 D29 E25 E26 E27 F24 F25

H23 H24 J23 J24 K24 K25 L23 L24 L25

N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25

Y25 AJ6

AF7

AJ7

F1 L6

L7 M6 M7

F17

F19

A24 A26

A27 B26 B27 B28

B25

VCCRTC V5REF[1]

V5REF[2] V5REF_SUS VCC1_5_B[01]

VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]

VCCSATAPLL VCC1_5_A[01]

VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]

VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]

VCC1_5_A[11] VCC1_5_A[12]

VCC1_5_A[13] VCC1_5_A[14]

VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]

VCC1_5_A[18] VCC1_5_A[19]

VCCUSBPLL VCC1_5_A[20]

VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]

VCC1_5_A[25] VCCLAN1_05[1]

VCCLAN1_05[2] VCCLAN3_3[1]

VCCLAN3_3[2] VCCGLANPLL VCCGLAN1_5[1]

VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2] VCCSUS3_3[01] VCCSUS3_3[02]

VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06] VCCSUS3_3[07]

VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]

VCCDMIPLL VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01] VCC3_3[02] VCC3_3[03]

VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

Ivcc1_05 current 1.13A

A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29 AE28

AE29 AC23

AC24 AF29 AD2 AC8

AD8 AE8 AF8

AA3 U7 V7 W1 W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11

AC12 AD11 J6

AF20 AC16 J7 C3 AC18

AC21 AC22 AG20 AH28

P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6

G22 A22 F20

G21

IvccDMIPLL current 0.023A

IV_CPU_IO current 0.001A

Ivcc3_3 current 0.442A

+VCCSUSHDA TP_VCCSUS1.05_1

TP_VCCSUS1.05_2 TP_VCCSUS1.5_1 TP_VCCSUS1.5_2

+VCCSUS3_3_0-6

0.1U/10V_4

TP_VCCCL1_05 TP_VCCCL1.05 +V3.3M_ICH

+1.05V_VCCP

C500

C465

0.047U/10V_4

C500

0.022U/16V_4

0.01U/16V_4

IvccDMI current 0.05A

C710

22U/6.3V/X5R_8

C430

0.1U/10V_4

C512

0.1U/10V_4

C501

C494

0.1U/10V_4

IvccHDA current 0.032A IvccSUSHDA current 0.011A

T55T55 T46T46

T48T48 T56T56

C432

IvccSUS3_3 current 0.177A

+VCCSUS3_3_7-19

C464

4.7U/10V/X5R_8

T58T58

C514

*0.1U/10V_4@NC

+1.05V_VCCP +1.5V

C470

C455

0.1U/10V_4

C452

0.1U/10V_4

+3.3V

C431

0.1U/10V_4

C450

0.1U/10V_4

R2980_6R2980_6

C443

0.022U/16V_4

R6350_8R6350_8

C518

C518 *1U/6.3V/X5R_6@NC

*1U/6.3V/X5R_6@NC

D34

BAT54SPT

1uH+-20%_1440mA

L47

C462

C462 10U/6.3V/X5R_8

10U/6.3V/X5R_8

+1.25V

C442

0.1U/10V_4

R2790_6R2790_6

C429

0.1U/10V_4

+3.3V_S5

+1.5V_DMIPLL_R+1.5V_DMIPLL

1uH_300mA

C449

4.7U/10V/X5R_8

iAMT

VCC_1.5V_1.05V

R385

+1.05V_VCCP

+3.3V_S5

iAMT

R66810_6R66810_6

+1.5V

1/F_8

+3.3V

C503

0.1U/10V_4

AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29

AE12 AE22 AE25

AF14 AF16 AF18

AH10 AH13 AH16 AH19

AF28 AH22 AH24 AH26

A23

A5 AA2 AA7 A25 AB1

AD3 AD4 AD6 AE1

AE2 AD1 AE5

AE6 AE9

AF3 AF4 AG5 AG6

AH2

AH3 AH4 AH8 AJ5 B11 B14 B17

B2 B20 B22

B8 C24 C26 C27

C6 D12 D15 D18

D4 E21 E24

E4 E9

F15

E23

F28 F29

E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29

H3 H6

J25 J26 J27

J5 K23 K28 K29

U39E

VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]

ICH8M REV 1.0

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]

K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

R4360_6R4360_6

IVCCL3_3 current 0.019A

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

iAMT

+3.3V_LAN

SizeDocument NumberRev

ICH8M Power(4 of 4)

Date:Sheet of

PROJECT : NA1

Quanta Computer Inc.

1755Friday, March 23, 2007

+ 38 hidden pages

Quanta NA1 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual