Quanta N91D Schematic

1

2

3

4

5

6

7

8

Table of Contents

PAGE DESCRIPTION

FRONT PAGE

01

BLOCK DIAGRAM

02

APollo Lake (MEMORY)

03

Apollo Lake (PCIE/USB/SATA/SPI)

04
05

Apollo Lake (HDMI/eDP)
Apollo Lake (GPIO/LPC/I2C/HDA)

06

Apollo Lake (PMU/PMIC/SMB/RTC)

07

Apollo Lake (POWER)

08

A A

Apollo Lake (GND)

09

HARDWARE STRAPS

10

APL XDP

11

Level shift/Thermistor

12

DDR3L DIMM0-RVS(8.0H)

13

DDR3L DIMM1-RVS(8.0H)

14

N16V-GMR (PCIE I/F) /NVDD

15

N16V-GMR (MEMORY/GND)

16
17

N16V-GMR (DISPLAY)

18

N16V-GMR (GPIO/STRAPS)

19

N16V-GMR DDR3 VRAM(BGA96)

20

dGPU Level Shift

21

LVDS converter RTD2136

22

LCD CONN/CCD/TouchPanel

23

HDMI

24

Audio Codec(ALC3252)
RTL8161/RJ45

25

SATA RE-DEIVER

26

eMMC

27

WLAN(NGFF)/HDD/ODD

28

B B

USB3.0 X 2/USB2.0 X 2

29
30

EC (IT8887)

31

Thermal/FAN/LEDs

32

JUMPER/LPCHeader/TPM

33

DC-IN

34

+3VS5/+5VS5(RT6575AGQW)

35

DDR3L (RT8231B)

36

+1.8VS5(RT8068)

37

+1.24VS5/+1.5V(G9661)

38

+1.05V(RT8068)

39

+12V

40

VLED(OZ554)

41

VNN CORE(RT3601EA)

42

VCCGI( RT3601EA)

43

Load switch IC (G5016)

44

GPU CORE (RT8812A)

45

GPU-1.5V / 0.95V

46

Power Block Diagram

47

SMB Block diagram

48

Power sequencce diagram

49

Power on/off sequence

C C

Oahu

Apollo CPU (TDP 10W) SoC

Project Information

Phase: DVT

POWER PLANE

+VIN
VCCRTC
+3V

+3V_ALW
+5V
+5V_S5
+5V_ALW AC/DC Insert enable
+3V_WLAN

+1.35V_S3
+1.8V_S5 S0~S5S5_ON

+VCC_VGGI
+VNN

+3.3V_VGA
+1.05V_VGA
+1.5V_VGA
+VGA_CORE
+12V

+0.65V_DDR_VTT

+1.05V

VOLTAGE

+19V
+3V
+3V
+3V
+3V
+5V
+5V

+3V

+1.8V
+1.8V
~
~

+1.5V MAIN_ON S0+1.5V
+3V DGPU_PWR_EN# S0

+1.5V EN_+1.5V_VGA S0

+0.675V S3_ON S3
+1.05V MAIN_ON S0

CONTROL
SIGNAL

MAIN_ON1
S5_LOAD_CODE+3V_S5

MAIN_ON S0

WLAN_ON

S3_ON+1.35V

VR_ON
VNN_ON S0~S5

1.8VS5_PG

PG_+3.3V_MAIN+1.05V

PG_+3.3V_MAIN~ S0
MAIN_ON+12V S0

Power States
ACTIVE IN

Always
Always
S0
S0~S5
Always (LDO)AC/DC Insert enable

S0~S5S5_ON
Always (LDO)+5V
S0~S5
S0~S5+3V LAN_PWR_ON+3V_LAN
S0~S3

S0MAIN_ON+1.8V
S0~S5

S0~S5+1.24V+1.24V_S5

S0

BOARD ID SETTING

Board ID
(Default = 00)

0
0
1
1 1
0 0
0 1
1 0
1 1

eMMC ID
(Default = 00)

BOARD_ID4BOARD_ID5

0
0
1
1 1

BOARD_ID6BOARD_ID7

0
1
0

Model

All EVT
All DVT
PVT1
PVT2+

MVB,A
1st Major ECN
2nd Major ECN
3rd Major ECN

eMMC

W/O
Hynix
Samsung
Reserved

0
1
0

VRAM ID
(Default = 00)

VRAM

UMA
Hynix
Mircon
Reserved

BOARD_ID2BOARD_ID3 BOARD_ID0BOARD_ID1

0 0
0 1
1 0
1 1

1

Schematic “Value” Definition

Molokai INTEL Platform

3

Auto BOM
Control

V

V

V

V

V V

V

V

By Value
format

XX

*XX

EV@XX

SATA@XX

D D

EMMC@XX

PROTO@XX

MP@XX

1

2

Description

Install
Non-Install
Install

dGPU device
Install

SATA device

Install

EMMC
Install in

pre-production only

Install in
MP only

DB/SI/PV Stage

Oahu

Oahu-U

V

V

V

V

4

V

V

Oahu-UE

V

V

Oahu

V V V

V

V

V

V V V

5

MP

Oahu-U Oahu-UE

V

V

6

PCB AND SILKSCREEN COLOR

Program Phase Color of PCB Silkscreen

EVT
DVT

PVT/MVB /
PRODUCTION

RED

LIGHT BLUE

GREEN

HP Restricted Secret

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

YELLOW
YELLOW
WHITE

FRONT PAGE

FRONT PAGE

FRONT PAGE

1ACustom

1ACustom

1ACustom

1 49Thursday, October 27, 2016

1 49Thursday, October 27, 2016

1 49Thursday, October 27, 2016

8

5

4

N91D Power Schematic EC Tracking Record DB to SI version

3

2

1

D D

C C

B B

EC #

EC-SI-P01

Page Description

34~45 Change default open to default short

EC-SI-P02 41

EC-SI-P03

EC-SI-P04

EC-SI-P05

EC-SI-P06

41

42

42

42

Adjust current response PR214PR39PR40

Change IMON setting

Adjust current response

Adjust Frequency

EC-SI-P07 42 Adjust load line

PJP1~PJP14

PR220Change IMON setting

PR114

PR127PR128

PR304PR149

PR142

Part Affected

A A

Title

Title

Title

<Title>

<Title>

<Title>

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

<Doc> <RevCode>

Custom

<Doc> <RevCode>

Custom

<Doc> <RevCode>

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1 1Thursday, October 27, 2016

1 1Thursday, October 27, 2016

1 1Thursday, October 27, 2016

1

1

www.schematic-x.blogspot.com

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3

4

5

6

7

8

Oahu Intel Apollo Lake Platform Block Diagram

PG.13

PG.14

PG.28

PG.28

1866MT/s

DDR3 L
Channel A

1866MT/s

DDR3 L
Channel B

SATA_P0 6GB/s

SATA_P1 3GB/s

PCI-E x2

PG.38

Intel Apollo Lake

Power : 10 (Watt)

Package : FCBGA 1296

Size : 31X24 (mm)

PCI-E
X4 Lane

PCIE_P0~P3

DDI

USB 3.0 x2

USB3_P0/P1

USB 2.0 x2

USB2_P0/P1

USB 2.0

USB2_P4

N16V-GMR1

Package 23*23mm

16W

27MHz
PAGE 17

eDP

DP to LVDS Converter

DP Port0

PG.15~19 PG.21

RTD 2136

SODIMM1

A A

Max. 8GB

RVS

SODIMM2

RVS

HDD
ODD

B B

25MHz

PAGE 26

PCIE_P5 PCIE_P4

LAN WLAN

RTL8161GSH-CG

Package : QFN32
Size : 4 x 4 (mm)

BT COMBO

PG.25

USB 2.0

PG.3~9

PG.30

FANROM

USB2_P7

eMMC

PORT1

USB 2.0 x4

Touch Screen

USB2_P6 USB2_P2 USB2_P5USB2_P3

USB2.0
conn

PG.22 PG.29 PG.31

Lane0

Lane1

USB3_P0

USB3_P1

CONN. CONN. WLANLAN dGPU HDDODD

MIC

Combo Jack

PG.24

C C

AUDIO
CODEC

Hp

ALC3252

Speaker

PG.24

PG.24

DMIC

Azalia

32.768kHz

PAGE 8

19.2MHz

PAGE 6

LPC

KBC

IT8887

HSPI

Thermal

PG.31 PG.31

D D

USB2_P0 USB2_P1 USB2_P2 USB2_P3 USB2_P4 USB2_P5 USB2_P6 USB2_P7

CONN.
USB3

CONN.
USB3

CONN.
USB2

CONN.
USB2

BT

Crad
Reader

Touch

CCD

PG.30

VRAM DDR3 x 4

Micron:MT41J256M16HA-093G:E
Hynix:H5TC4G63CFR-N0C

2000MT/s

LVDS InterfaceeDP

PG.21 PG.22

256M X 16 X 4

LVDS

HDMI

USB3.0 Ports

PG.23

PCB 6L STACK UP

LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : BOT

+3V_S5/+5V_S5

DDR3L

CPU VGGI

X2

PG.29

CPU VNN

Panel Backlight

WLAN

BT COMBO

Camera

PG.28

DMIC

PG.22

GPU Core

GPU 1.5V/0.95V

+1.05V

eMMC

PG.27

+1.24V

+1.8V
+12V

PG.29

Card Reader

Realtek RTS5145

USB2.0
conn

Lane2 Lane3 Lane4 Lane5 Lane6 Lane7 Lane8 Lane9

PCIE_P5

PCIE_P4 PCIE_P3 PCIE_P2 PCIE_P1 PCIE_P0 SATA_P1 SATA_P0

2

PG.34

PG.35

PG.42

PG.41

PG.40

PG.44

PG.46

PG.45

PG.37

PG.36

PG.39

HP Restricted Secret

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

7

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

8

1ACustom

1ACustom

1ACustom

2 49Thursday, October 27, 2016

2 49Thursday, October 27, 2016

2 49Thursday, October 27, 2016

5

4

3

2

1

APL ULT (DDR3L)

M_A_A0

M_A_A0[13]
M_A_A1[13]

D D

M_A_ODT0[13]
M_A_ODT1[13]

SMDDR_VREF_DQ0_M1[13]

+SMDDR_VREF_DIMM_M1[13]

C C

VREF trace must be at least
20 mils wide and space

Trace length < 500 mils
Trace width = 12 mils
Trace spacing = 20 mils

B B

M_A_A2[13]
M_A_A3[13]
M_A_A4[13]
M_A_A5[13]
M_A_A6[13]
M_A_A7[13]
M_A_A8[13]

M_A_A9[13]
M_A_A10[13]
M_A_A11[13]
M_A_A12[13]
M_A_A13[13]
M_A_A14[13]
M_A_A15[13]

M_A_BS#0[13]
M_A_BS#1[13]
M_A_BS#2[13]

M_A_CAS#[13]
M_A_RAS#[13]

M_A_WE#[13]

M_A_CS#0[13]

M_A_CS#1[13]
M_A_CKE0[13]

M_A_CKE1[13]

1 2

R220 0_4

1 2

R226 0_4

1 2

R521 *0_4

1 2

R525 *0_4

12

R242105/F_4

M_A_CLK0[13]

M_A_CLK0#[13]

M_A_CLK1[13]

M_A_CLK1#[13]

M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8

M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_ODT0_R
M_A_ODT1_R

+VREFDQ
+VREFCA

MEM_CH0_RCOMP

MA_DRAMRST#

BG50

DDR3L_CH0_MA0_LPDDR3_CH0_CAB7

BG51

DDR3L_CH0_MA1_LPDDR3_CH0_CAB9

BH51

DDR3L_CH0_MA2_LPDDR3_CH0_CAB5

BD41

DDR3L_CH0_MA3_LPDDR3_NC

BE41

DDR3L_CH0_MA4_LPDDR3_NC

BJ52

DDR3L_CH0_MA5_LPDDR3_CH0_CAA2

BG53

DDR3L_CH0_MA6_LPDDR3_CH0_CAA0

BG55

DDR3L_CH0_MA7_LPDDR3_CH0_CAA3

BH53

DDR3L_CH0_MA8_LPDDR3_CH0_CAA1

BG52

DDR3L_CH0_MA9_LPDDR3_CH0_CAA4

BH49

DDR3L_CH0_MA10_LPDDR3_CH0_CAB6

BH55

DDR3L_CH0_MA11_LPDDR3_CH0_CAA6

BG54

DDR3L_CH0_MA12_LPDDR3_CH0_CAA5

BG46

DDR3L_CH0_MA13_LPDDR3_CH0_CAB0

BG56

DDR3L_CH0_MA14_LPDDR3_CH0_CAA8

BG57

DDR3L_CH0_MA15_LPDDR3_CH0_CAA9

BJ48

DDR3L_CH0_BA0_LPDDR3_CH0_CAB2

BG49

DDR3L_CH0_BA1_LPDDR3_CH0_CAB8

BH57

DDR3L_CH0_BA2_LPDDR3_CH0_CAA7

BH47

DDR3L_CH0_CAS_N_LPDDR3_CH0_CAB1

BG47

DDR3L_CH0_RAS_N_LPDDR3_CH0_CAB3

BG48

DDR3L_CH0_WE_N_LPDDR3_CH0_CAB4

AR43

DDR3L_CH0_CS0_N_LPDDR3_CH0_CS0A_N

AT43

DDR3L_NC_LPDDR3_CH0_CS1A_N

BB41

DDR3L_NC_LPDDR3_CH0_CS0B_N

BA41

DDR3L_CH0_CS1_N_LPDDR3_CH0_CS1B_N

BH61

DDR3L_CH0_CKE0_LPDDR3_CH0_CKE0A

BH60

DDR3L_CH0_CKE1_LPDDR3_CH0_CKE1A

BH58

DDR3L_NC_LPDDR3_CH0_CKE0B

BJ58

DDR3L_NC_LPDDR3_CH0_CKE1B

AW43

DDR3L_CH0_ODT0_LPDDR3_CH0_ODTA

AW41

DDR3L_CH0_ODT1_LPDDR3_CH0_ODTB

AT34

MEM_CH0_VREFDQ

AR35

MEM_CH0_VREFCA

AV34

MEM_CH0_RCOMP

BD45

DDR3L_CH0_CLKP0_LPDDR3_CH0_CLKP_B

BE45

DDR3L_CH0_CLKN0_LPDDR3_CH0_CLKN_B

BB48

DDR3L_CH0_CLKP1_LPDDR3_CH0_CLKP_A

BD48

DDR3L_CH0_CLKN1_LPDDR3_CH0_CLKN_A

AR34

DDR3L_CH0_RESET_N_LPDDR3_NC

Section 1 of 12

AW48

DDR3L_CH0_CB0_LPDDR3_NC

AW47

DDR3L_CH0_CB1_LPDDR3_NC

BB43

DDR3L_CH0_CB2_LPDDR3_NC

AW45

DDR3L_CH0_CB3_LPDDR3_NC

AV48

DDR3L_CH0_CB4_LPDDR3_NC

AV47

DDR3L_CH0_CB5_LPDDR3_NC

BD43

DDR3L_CH0_CB6_LPDDR3_NC

BA45

DDR3L_CH0_CB7_LPDDR3_NC

BD47

DDR3L_CH0_DQSP8_LPDDR3_NC

BB47

DDR3L_CH0_DQSN8_LPDDR3_NC

DDR3L_CH0_DQ10_LPDDR3_CH0_DQA10
DDR3L_CH0_DQ11_LPDDR3_CH0_DQA11
DDR3L_CH0_DQ12_LPDDR3_CH0_DQA12
DDR3L_CH0_DQ13_LPDDR3_CH0_DQA13
DDR3L_CH0_DQ14_LPDDR3_CH0_DQA14
DDR3L_CH0_DQ15_LPDDR3_CH0_DQA15
DDR3L_CH0_DQ16_LPDDR3_CH0_DQA16
DDR3L_CH0_DQ17_LPDDR3_CH0_DQA17
DDR3L_CH0_DQ18_LPDDR3_CH0_DQA18
DDR3L_CH0_DQ19_LPDDR3_CH0_DQA19
DDR3L_CH0_DQ20_LPDDR3_CH0_DQA20
DDR3L_CH0_DQ21_LPDDR3_CH0_DQA21
DDR3L_CH0_DQ22_LPDDR3_CH0_DQA22
DDR3L_CH0_DQ23_LPDDR3_CH0_DQA23
DDR3L_CH0_DQ24_LPDDR3_CH0_DQA24
DDR3L_CH0_DQ25_LPDDR3_CH0_DQA25
DDR3L_CH0_DQ26_LPDDR3_CH0_DQA26
DDR3L_CH0_DQ27_LPDDR3_CH0_DQA27
DDR3L_CH0_DQ28_LPDDR3_CH0_DQA28
DDR3L_CH0_DQ29_LPDDR3_CH0_DQA29
DDR3L_CH0_DQ30_LPDDR3_CH0_DQA30
DDR3L_CH0_DQ31_LPDDR3_CH0_DQA31

DDR3L_CH0_DQ42_LPDDR3_CH0_DQB10
DDR3L_CH0_DQ43_LPDDR3_CH0_DQB11
DDR3L_CH0_DQ44_LPDDR3_CH0_DQB12
DDR3L_CH0_DQ45_LPDDR3_CH0_DQB13
DDR3L_CH0_DQ46_LPDDR3_CH0_DQB14
DDR3L_CH0_DQ47_LPDDR3_CH0_DQB15
DDR3L_CH0_DQ48_LPDDR3_CH0_DQB16
DDR3L_CH0_DQ49_LPDDR3_CH0_DQB17
DDR3L_CH0_DQ50_LPDDR3_CH0_DQB18
DDR3L_CH0_DQ51_LPDDR3_CH0_DQB19
DDR3L_CH0_DQ52_LPDDR3_CH0_DQB20
DDR3L_CH0_DQ53_LPDDR3_CH0_DQB21
DDR3L_CH0_DQ54_LPDDR3_CH0_DQB22
DDR3L_CH0_DQ55_LPDDR3_CH0_DQB23
DDR3L_CH0_DQ56_LPDDR3_CH0_DQB24
DDR3L_CH0_DQ57_LPDDR3_CH0_DQB25
DDR3L_CH0_DQ58_LPDDR3_CH0_DQB26
DDR3L_CH0_DQ59_LPDDR3_CH0_DQB27
DDR3L_CH0_DQ60_LPDDR3_CH0_DQB28
DDR3L_CH0_DQ61_LPDDR3_CH0_DQB29
DDR3L_CH0_DQ62_LPDDR3_CH0_DQB30
DDR3L_CH0_DQ63_LPDDR3_CH0_DQB31

DDR3L_CH0_DQSP0_LPDDR3_CH0_DQSPA0
DDR3L_CH0_DQSN0_LPDDR3_CH0_DQSNA0
DDR3L_CH0_DQSP1_LPDDR3_CH0_DQSPA1
DDR3L_CH0_DQSN1_LPDDR3_CH0_DQSNA1
DDR3L_CH0_DQSP2_LPDDR3_CH0_DQSPA2
DDR3L_CH0_DQSN2_LPDDR3_CH0_DQSNA2
DDR3L_CH0_DQSP3_LPDDR3_CH0_DQSPA3
DDR3L_CH0_DQSN3_LPDDR3_CH0_DQSNA3
DDR3L_CH0_DQSP4_LPDDR3_CH0_DQSPB0
DDR3L_CH0_DQSN4_LPDDR3_CH0_DQSNB0
DDR3L_CH0_DQSP5_LPDDR3_CH0_DQSPB1
DDR3L_CH0_DQSN5_LPDDR3_CH0_DQSNB1
DDR3L_CH0_DQSP6_LPDDR3_CH0_DQSPB2
DDR3L_CH0_DQSN6_LPDDR3_CH0_DQSNB2
DDR3L_CH0_DQSP7_LPDDR3_CH0_DQSPB3
DDR3L_CH0_DQSN7_LPDDR3_CH0_DQSNB3

BXT_P_SOC_BGA1296U20A

DDR3L_CH0_DQ0_LPDDR3_CH0_DQA0
DDR3L_CH0_DQ1_LPDDR3_CH0_DQA1
DDR3L_CH0_DQ2_LPDDR3_CH0_DQA2
DDR3L_CH0_DQ3_LPDDR3_CH0_DQA3
DDR3L_CH0_DQ4_LPDDR3_CH0_DQA4
DDR3L_CH0_DQ5_LPDDR3_CH0_DQA5
DDR3L_CH0_DQ6_LPDDR3_CH0_DQA6
DDR3L_CH0_DQ7_LPDDR3_CH0_DQA7
DDR3L_CH0_DQ8_LPDDR3_CH0_DQA8
DDR3L_CH0_DQ9_LPDDR3_CH0_DQA9

DDR3L_CH0_DQ32_LPDDR3_CH0_DQB0
DDR3L_CH0_DQ33_LPDDR3_CH0_DQB1
DDR3L_CH0_DQ34_LPDDR3_CH0_DQB2
DDR3L_CH0_DQ35_LPDDR3_CH0_DQB3
DDR3L_CH0_DQ36_LPDDR3_CH0_DQB4
DDR3L_CH0_DQ37_LPDDR3_CH0_DQB5
DDR3L_CH0_DQ38_LPDDR3_CH0_DQB6
DDR3L_CH0_DQ39_LPDDR3_CH0_DQB7
DDR3L_CH0_DQ40_LPDDR3_CH0_DQB8
DDR3L_CH0_DQ41_LPDDR3_CH0_DQB9

AY62
AY61
BE62
BG62
BD63
AW62
AW63
BD62
AV59
AU63
AU62
AV58
AV57
AT55
AT54
AY59
AY57
BB57
BD59
BF59
AV54
AY55
AV52
BD58
BE56
BD54
BF58
BE50
BD50
BB50
BA50
BB54
AR39
AV37
AW37
AR37
AT37
AT41
AR41
AW35
BJ44
BG39
BG40
BJ40
BG43
BG44
BH45
BH41
BA34
BE34
BD34
BD37
BB37
BE39
BD39
BB34
BJ38
BG34
BG33
BH33
BG38
BH37
BG37
BJ34

BB63
BC62
AT59
AT58
BB59
BB58
BD52
BB52
AV39
AW39
BJ42
BG42
BB35
BD35
BG36
BH35

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQSP0

M_A_DQSN0

M_A_DQSP1

M_A_DQSN1

M_A_DQSP2

M_A_DQSN2

M_A_DQSP3

M_A_DQSN3

M_A_DQSP4

M_A_DQSN4

M_A_DQSP5

M_A_DQSN5

M_A_DQSP6

M_A_DQSN6

M_A_DQSP7

M_A_DQSN7

M_A_DQ0 [13]
M_A_DQ1 [13]
M_A_DQ2 [13]
M_A_DQ3 [13]
M_A_DQ4 [13]
M_A_DQ5 [13]
M_A_DQ6 [13]
M_A_DQ7 [13]
M_A_DQ8 [13]

M_A_DQ9 [13]
M_A_DQ10 [13]
M_A_DQ11 [13]
M_A_DQ12 [13]
M_A_DQ13 [13]
M_A_DQ14 [13]
M_A_DQ15 [13]
M_A_DQ16 [13]
M_A_DQ17 [13]
M_A_DQ18 [13]
M_A_DQ19 [13]
M_A_DQ20 [13]
M_A_DQ21 [13]
M_A_DQ22 [13]
M_A_DQ23 [13]
M_A_DQ24 [13]
M_A_DQ25 [13]
M_A_DQ26 [13]
M_A_DQ27 [13]
M_A_DQ28 [13]
M_A_DQ29 [13]
M_A_DQ30 [13]
M_A_DQ31 [13]
M_A_DQ32 [13]
M_A_DQ33 [13]
M_A_DQ34 [13]
M_A_DQ35 [13]
M_A_DQ36 [13]
M_A_DQ37 [13]
M_A_DQ38 [13]
M_A_DQ39 [13]
M_A_DQ40 [13]
M_A_DQ41 [13]
M_A_DQ42 [13]
M_A_DQ43 [13]
M_A_DQ44 [13]
M_A_DQ45 [13]
M_A_DQ46 [13]
M_A_DQ47 [13]
M_A_DQ48 [13]
M_A_DQ49 [13]
M_A_DQ50 [13]
M_A_DQ51 [13]
M_A_DQ52 [13]
M_A_DQ53 [13]
M_A_DQ54 [13]
M_A_DQ55 [13]
M_A_DQ56 [13]
M_A_DQ57 [13]
M_A_DQ58 [13]
M_A_DQ59 [13]
M_A_DQ60 [13]
M_A_DQ61 [13]
M_A_DQ62 [13]
M_A_DQ63 [13]

M_A_DQSP0 [13]
M_A_DQSN0 [13]
M_A_DQSP1 [13]
M_A_DQSN1 [13]
M_A_DQSP2 [13]
M_A_DQSN2 [13]
M_A_DQSP3 [13]
M_A_DQSN3 [13]
M_A_DQSP4 [13]
M_A_DQSN4 [13]
M_A_DQSP5 [13]
M_A_DQSN5 [13]
M_A_DQSP6 [13]
M_A_DQSN6 [13]
M_A_DQSP7 [13]
M_A_DQSN7 [13]

M_B_A0

M_B_A0[14]
M_B_A1[14]
M_B_A2[14]
M_B_A3[14]
M_B_A4[14]
M_B_A5[14]
M_B_A6[14]
M_B_A7[14]
M_B_A8[14]

M_B_A9[14]
M_B_A10[14]
M_B_A11[14]
M_B_A12[14]
M_B_A13[14]
M_B_A14[14]
M_B_A15[14]

M_B_BS#0[14]
M_B_BS#1[14]
M_B_BS#2[14]

M_B_CAS#[14]
M_B_RAS#[14]

M_B_WE#[14]

M_B_CS#0[14]

M_B_CS#1[14]
M_B_CKE0[14]

M_B_CKE1[14]

1 2

M_B_ODT0[14]
M_B_ODT1[14]

SMDDR_VREF_DQ0_M2[14]

+SMDDR_VREF_DIMM_M2[14]

R263 0_4

1 2

R267 0_4

1 2

R528 *0_4

1 2

R531 *0_4

12

R243105/F_4

M_B_CLK0[14]

M_B_CLK0#[14]

M_B_CLK1[14]

M_B_CLK1#[14]

MEM_CH0_RCOMP_2

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8

M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ODT0_R
M_B_ODT1_R

+VREFDQ_2
+VREFCA_2

MB_DRAMRST#

BG9

DDR3L_CH1_MA0_LPDDR3_CH1_CAB7

BG10

DDR3L_CH1_MA1_LPDDR3_CH1_CAB9

BH9

DDR3L_CH1_MA2_LPDDR3_CH1_CAB5

BD16

DDR3L_CH1_MA3_LPDDR3_NC

BB16

DDR3L_CH1_MA4_LPDDR3_NC

BG11

DDR3L_CH1_MA5_LPDDR3_CH1_CAA2

BJ12

DDR3L_CH1_MA6_LPDDR3_CH1_CAA0

BG14

DDR3L_CH1_MA7_LPDDR3_CH1_CAA3

BG12

DDR3L_CH1_MA8_LPDDR3_CH1_CAA1

BH11

DDR3L_CH1_MA9_LPDDR3_CH1_CAA4

BG7

DDR3L_CH1_MA10_LPDDR3_CH1_CAB6

BH13

DDR3L_CH1_MA11_LPDDR3_CH1_CAA6

BG13

DDR3L_CH1_MA12_LPDDR3_CH1_CAA5

BH3

DDR3L_CH1_MA13_LPDDR3_CH1_CAB0

BG15

DDR3L_CH1_MA14_LPDDR3_CH1_CAA8

BG16

DDR3L_CH1_MA15_LPDDR3_CH1_CAA9

BH6

DDR3L_CH1_BA0_LPDDR3_CH1_CAB2

BG8

DDR3L_CH1_BA1_LPDDR3_CH1_CAB8

BH15

DDR3L_CH1_BA2_LPDDR3_CH1_CAA7

BH4

DDR3L_CH1_CAS_N_LPDDR3_CH1_CAB1

BJ6

DDR3L_CH1_RAS_N_LPDDR3_CH1_CAB3

BH7

DDR3L_CH1_WE_N_LPDDR3_CH1_CAB4

BD17

DDR3L_CH1_CS0_N_LPDDR3_CH1_CS0A_N

BB17

DDR3L_NC_LPDDR3_CH1_CS1A_N

AV17

DDR3L_NC_LPDDR3_CH1_CS0B_N

AW17

DDR3L_CH1_CS1_N_LPDDR3_CH1_CS1B_N

BG18

DDR3L_CH1_CKE0_LPDDR3_CH1_CKE0A

BG17

DDR3L_CH1_CKE1_LPDDR3_CH1_CKE1A

BH17

DDR3L_NC_LPDDR3_CH1_CKE0B

BJ16

DDR3L_NC_LPDDR3_CH1_CKE1B

AW16

DDR3L_CH1_ODT0_LPDDR3_CH1_ODTA

AV16

DDR3L_CH1_ODT1_LPDDR3_CH1_ODTB

AT30

MEM_CH1_VREFDQ

AR29

MEM_CH1_VREFCA

AV30

MEM_CH1_RCOMP

BD19

DDR3L_CH1_CLKP0_LPDDR3_CH1_CLKP_B

BE19

DDR3L_CH1_CLKN0_LPDDR3_CH1_CLKN_B

BB21

DDR3L_CH1_CLKP1_LPDDR3_CH1_CLKP_A

BD21

DDR3L_CH1_CLKN1_LPDDR3_CH1_CLKN_A

AR30

DDR3L_CH1_RESET_N_LPDDR3_NC

Section 2 of 12

AR21

DDR3L_CH1_CB0_LPDDR3_NC

AT21

DDR3L_CH1_CB1_LPDDR3_NC

AW23

DDR3L_CH1_CB2_LPDDR3_NC

AW21

DDR3L_CH1_CB3_LPDDR3_NC

BA19

DDR3L_CH1_CB4_LPDDR3_NC

AW19

DDR3L_CH1_CB5_LPDDR3_NC

BA23

DDR3L_CH1_CB6_LPDDR3_NC

BB23

DDR3L_CH1_CB7_LPDDR3_NC

BD23

DDR3L_CH1_DQSP8_LPDDR3_NC

BE23

DDR3L_CH1_DQSN8_LPDDR3_NC

+1.35V_S3[8,13,14,35]

BXT_P_SOC_BGA1296U20B

DDR3L_CH1_DQ0_LPDDR3_CH1_DQA0
DDR3L_CH1_DQ1_LPDDR3_CH1_DQA1
DDR3L_CH1_DQ2_LPDDR3_CH1_DQA2
DDR3L_CH1_DQ3_LPDDR3_CH1_DQA3
DDR3L_CH1_DQ4_LPDDR3_CH1_DQA4
DDR3L_CH1_DQ5_LPDDR3_CH1_DQA5
DDR3L_CH1_DQ6_LPDDR3_CH1_DQA6
DDR3L_CH1_DQ7_LPDDR3_CH1_DQA7
DDR3L_CH1_DQ8_LPDDR3_CH1_DQA8

DDR3L_CH1_DQ9_LPDDR3_CH1_DQA9
DDR3L_CH1_DQ10_LPDDR3_CH1_DQA10
DDR3L_CH1_DQ11_LPDDR3_CH1_DQA11
DDR3L_CH1_DQ12_LPDDR3_CH1_DQA12
DDR3L_CH1_DQ13_LPDDR3_CH1_DQA13
DDR3L_CH1_DQ14_LPDDR3_CH1_DQA14
DDR3L_CH1_DQ15_LPDDR3_CH1_DQA15
DDR3L_CH1_DQ16_LPDDR3_CH1_DQA16
DDR3L_CH1_DQ17_LPDDR3_CH1_DQA17
DDR3L_CH1_DQ18_LPDDR3_CH1_DQA18
DDR3L_CH1_DQ19_LPDDR3_CH1_DQA19
DDR3L_CH1_DQ20_LPDDR3_CH1_DQA20
DDR3L_CH1_DQ21_LPDDR3_CH1_DQA21
DDR3L_CH1_DQ22_LPDDR3_CH1_DQA22
DDR3L_CH1_DQ23_LPDDR3_CH1_DQA23
DDR3L_CH1_DQ24_LPDDR3_CH1_DQA24
DDR3L_CH1_DQ25_LPDDR3_CH1_DQA25
DDR3L_CH1_DQ26_LPDDR3_CH1_DQA26
DDR3L_CH1_DQ27_LPDDR3_CH1_DQA27
DDR3L_CH1_DQ28_LPDDR3_CH1_DQA28
DDR3L_CH1_DQ29_LPDDR3_CH1_DQA29
DDR3L_CH1_DQ30_LPDDR3_CH1_DQA30
DDR3L_CH1_DQ31_LPDDR3_CH1_DQA31

DDR3L_CH1_DQ32_LPDDR3_CH1_DQB0
DDR3L_CH1_DQ33_LPDDR3_CH1_DQB1
DDR3L_CH1_DQ34_LPDDR3_CH1_DQB2
DDR3L_CH1_DQ35_LPDDR3_CH1_DQB3
DDR3L_CH1_DQ36_LPDDR3_CH1_DQB4
DDR3L_CH1_DQ37_LPDDR3_CH1_DQB5
DDR3L_CH1_DQ38_LPDDR3_CH1_DQB6
DDR3L_CH1_DQ39_LPDDR3_CH1_DQB7
DDR3L_CH1_DQ40_LPDDR3_CH1_DQB8

DDR3L_CH1_DQ41_LPDDR3_CH1_DQB9
DDR3L_CH1_DQ42_LPDDR3_CH1_DQB10
DDR3L_CH1_DQ43_LPDDR3_CH1_DQB11
DDR3L_CH1_DQ44_LPDDR3_CH1_DQB12
DDR3L_CH1_DQ45_LPDDR3_CH1_DQB13
DDR3L_CH1_DQ46_LPDDR3_CH1_DQB14
DDR3L_CH1_DQ47_LPDDR3_CH1_DQB15
DDR3L_CH1_DQ48_LPDDR3_CH1_DQB16
DDR3L_CH1_DQ49_LPDDR3_CH1_DQB17
DDR3L_CH1_DQ50_LPDDR3_CH1_DQB18
DDR3L_CH1_DQ51_LPDDR3_CH1_DQB19
DDR3L_CH1_DQ52_LPDDR3_CH1_DQB20
DDR3L_CH1_DQ53_LPDDR3_CH1_DQB21
DDR3L_CH1_DQ54_LPDDR3_CH1_DQB22
DDR3L_CH1_DQ55_LPDDR3_CH1_DQB23
DDR3L_CH1_DQ56_LPDDR3_CH1_DQB24
DDR3L_CH1_DQ57_LPDDR3_CH1_DQB25
DDR3L_CH1_DQ58_LPDDR3_CH1_DQB26
DDR3L_CH1_DQ59_LPDDR3_CH1_DQB27
DDR3L_CH1_DQ60_LPDDR3_CH1_DQB28
DDR3L_CH1_DQ61_LPDDR3_CH1_DQB29
DDR3L_CH1_DQ62_LPDDR3_CH1_DQB30
DDR3L_CH1_DQ63_LPDDR3_CH1_DQB31

DDR3L_CH1_DQSP0_LPDDR3_CH1_DQSPA0
DDR3L_CH1_DQSN0_LPDDR3_CH1_DQSNA0
DDR3L_CH1_DQSP1_LPDDR3_CH1_DQSPA1
DDR3L_CH1_DQSN1_LPDDR3_CH1_DQSNA1
DDR3L_CH1_DQSP2_LPDDR3_CH1_DQSPA2
DDR3L_CH1_DQSN2_LPDDR3_CH1_DQSNA2
DDR3L_CH1_DQSP3_LPDDR3_CH1_DQSPA3
DDR3L_CH1_DQSN3_LPDDR3_CH1_DQSNA3
DDR3L_CH1_DQSP4_LPDDR3_CH1_DQSPB0
DDR3L_CH1_DQSN4_LPDDR3_CH1_DQSNB0
DDR3L_CH1_DQSP5_LPDDR3_CH1_DQSPB1
DDR3L_CH1_DQSN5_LPDDR3_CH1_DQSNB1
DDR3L_CH1_DQSP6_LPDDR3_CH1_DQSPB2
DDR3L_CH1_DQSN6_LPDDR3_CH1_DQSNB2
DDR3L_CH1_DQSP7_LPDDR3_CH1_DQSPB3
DDR3L_CH1_DQSN7_LPDDR3_CH1_DQSNB3

BJ26
BG30
BH31
BG31
BH27
BG27
BG26
BJ30
BA30
BB30
BE30
BD30
BE25
BB27
BD25
BD27
BG24
BJ20
BH23
BJ24
BG20
BG21
BH19
BG25
AT27
AW29
AR27
AT23
AV27
AR25
AR23
AW27
BF6
BD10
BE14
BB10
BA14
BB14
BD14
BE8
AV12
BD6
BD5
BB7
AV10
AY9
AY7
BF5
AU2
AT10
AT9
AU1
AY5
AV5
AV6
AV7
AY2
BD2
BD1
BE2
AW1
AW2
AY3
BG2

BG28
BH29
BD29
BB29
BJ22
BG22
AV25
AW25
BB12
BD12
BB5
BB6
AT5
AT6
BC2
BB1

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQSP0

M_B_DQSN0

M_B_DQSP1

M_B_DQSN1

M_B_DQSP2

M_B_DQSN2

M_B_DQSP3

M_B_DQSN3

M_B_DQSP4

M_B_DQSN4

M_B_DQSP5

M_B_DQSN5

M_B_DQSP6

M_B_DQSN6

M_B_DQSP7

M_B_DQSN7

M_B_DQ0 [14]
M_B_DQ1 [14]
M_B_DQ2 [14]
M_B_DQ3 [14]
M_B_DQ4 [14]
M_B_DQ5 [14]
M_B_DQ6 [14]
M_B_DQ7 [14]
M_B_DQ8 [14]

M_B_DQ9 [14]
M_B_DQ10 [14]
M_B_DQ11 [14]
M_B_DQ12 [14]
M_B_DQ13 [14]
M_B_DQ14 [14]
M_B_DQ15 [14]
M_B_DQ16 [14]
M_B_DQ17 [14]
M_B_DQ18 [14]
M_B_DQ19 [14]
M_B_DQ20 [14]
M_B_DQ21 [14]
M_B_DQ22 [14]
M_B_DQ23 [14]
M_B_DQ24 [14]
M_B_DQ25 [14]
M_B_DQ26 [14]
M_B_DQ27 [14]
M_B_DQ28 [14]
M_B_DQ29 [14]
M_B_DQ30 [14]
M_B_DQ31 [14]
M_B_DQ32 [14]
M_B_DQ33 [14]
M_B_DQ34 [14]
M_B_DQ35 [14]
M_B_DQ36 [14]
M_B_DQ37 [14]
M_B_DQ38 [14]
M_B_DQ39 [14]
M_B_DQ40 [14]
M_B_DQ41 [14]
M_B_DQ42 [14]
M_B_DQ43 [14]
M_B_DQ44 [14]
M_B_DQ45 [14]
M_B_DQ46 [14]
M_B_DQ47 [14]
M_B_DQ48 [14]
M_B_DQ49 [14]
M_B_DQ50 [14]
M_B_DQ51 [14]
M_B_DQ52 [14]
M_B_DQ53 [14]
M_B_DQ54 [14]
M_B_DQ55 [14]
M_B_DQ56 [14]
M_B_DQ57 [14]
M_B_DQ58 [14]
M_B_DQ59 [14]
M_B_DQ60 [14]
M_B_DQ61 [14]
M_B_DQ62 [14]
M_B_DQ63 [14]

M_B_DQSP0 [14]
M_B_DQSN0 [14]
M_B_DQSP1 [14]
M_B_DQSN1 [14]
M_B_DQSP2 [14]
M_B_DQSN2 [14]
M_B_DQSP3 [14]
M_B_DQSN3 [14]
M_B_DQSP4 [14]
M_B_DQSN4 [14]
M_B_DQSP5 [14]
M_B_DQSN5 [14]
M_B_DQSP6 [14]
M_B_DQSN6 [14]
M_B_DQSP7 [14]
M_B_DQSN7 [14]

03

DRAMRST-SODIMM

+1.35V_S3 +1.35V_S3

A A

CPU

MA_DRAMRST#

5

Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15 mils

12

R219
1K/F_4

R218 0_4

4

12

*0.1u/16V_4

C184

SO-DIMM

M_A_DRAMRST# [13]

3

CPU

MB_DRAMRST#

Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15 mils

12

R216
1K/F_4

R223 0_4

12

*0.1u/16V_4

C198

SO-DIMM

M_B_DRAMRST# [14]

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

BXTP(MEMORY)

BXTP(MEMORY)

BXTP(MEMORY)

1

3 49Thursday, October 27, 2016

3 49Thursday, October 27, 2016

3 49Thursday, October 27, 2016

1A

1A

1A

5

4

3

2

1

Apollo lake (SATA , ODD, CLK ,USB,PCIE)

+1.8V_S5[5,6,7,8,10,11,12,20,30,32,36,37,42,43]

D D

+1.8V_S5

R279
*10K_4

R277
0_4

2~8 inch

USB_VBUS_SNS

Combo USB3.0 right

Combo USB3.0 left

USB30_TX0+[29]
USB30_TX0-[29]
USB30_RX0+[29]
USB30_RX0-[29]

USB30_TX1+[29]
USB30_TX1-[29]
USB30_RX1+[29]
USB30_RX1-[29]

R269 137/F_4
R268 113/F_4

1 2

R266 0_4

USB_SSIC_RCOMP
USBCOMP

USB_OTG_ID

USB2COMP󶁪 4-8mils trace width with <1000 mils

SOC_USB_OC0#[29]

+1.8V_S5

GL850_OC#[29]

1 2

R463 10K_4

1 2

R464 10K_4

Combo USB 3/2.0 right
Combo USB 3/2.0 left
USB2 .0

C C

3~12 inch

USB2 .0
BT

Card Reader
Touch Panel
CCD

SATA ODD

SATA HDD

SOC_SPI_SI[32]
SOC_SPI_SO[32]
SOC_SPI_IO3[32]
SOC_SPI_IO2[32]

SOC_SPI_CS0#[32]
SOC_SPI_CLK[32]

TP19

USB2.0_CONN1+[29]

USB2.0_CONN1-[29]

USB2.0_CONN2+[29]

USB2.0_CONN2-[29]

USBP_TOUCH+[22]

USBP_TOUCH-[22]

USBP7_CCD+[22]

USBP7_CCD-[22]

SATA_TXP1[26]
SATA_TXN1[26]
SATA_RXP1[26]
SATA_RXN1[26]
SATA_TXP0[26]
SATA_TXN0[26]
SATA_RXP0[26]
SATA_RXN0[26]

1

*

USBP0+[29]

USBP0-[29]

USBP1+[29]

USBP1-[29]

USBP4+[28]

USBP4-[28]

USB_CARD+[31]

USB_CRAD-[31]

SOC_SPI_SI
SOC_SPI_SO
SOC_SPI_IO3
SOC_SPI_IO2
SOC_SPI_CS1#
SOC_SPI_CS0#
SOC_SPI_CLK

SOC_USB_OC0#
SOC_USB_OC1#

J1

USB3_P0_TXP

J2

USB3_P0_TXN

K9

USB3_P0_RXP

K10

USB3_P0_RXN

K3

USB3_P1_TXP

K2

USB3_P1_TXN

F2

USB3_P1_RXP

G2

USB3_P1_RXN

AC16

USB2_VBUS_SNS

AB15

USB_SSIC_RCOMP

Y15

USB2_RCOMP

AC15

USB2_OTG_ID

AH13

USB_SSIC_0_TX_P

AH12

USB_SSIC_0_TX_N

AG16

USB_SSIC_0_RX_P

AG15

USB_SSIC_0_RX_N

B55

USB2_OC0_N

C55

USB2_OC1_N

V12

USB2_DP0

V10

USB2_DN0

V16

USB2_DP1

V15

USB2_DN1

Y13

USB2_DP2

V13

USB2_DN2

V9

USB2_DP3

V7

USB2_DN3

Y9

USB2_DP4

Y10

USB2_DN4

AB6

USB2_DP5

AB7

USB2_DN5

AC12

USB2_DP6

AC10

USB2_DN6

V5

USB2_DP7

V6

USB2_DN7

W1

SATA_P1_USB3_P5_TXP

W2

SATA_P1_USB3_P5_TXN

T5

SATA_P1_USB3_P5_RXP

T6

SATA_P1_USB3_P5_RXN

Y3

SATA_P0_TXP

Y2

SATA_P0_TXN

T9

SATA_P0_RXP

T7

SATA_P0_RXN

A58

FST_SPI_MOSI_IO0

B58

FST_SPI_MISO_IO1

B61

FST_SPI_IO3

B60

FST_SPI_IO2

C57

FST_SPI_CS1_N

B57

FST_SPI_CS0_N

C56

FST_SPI_CLK

BXT_P_SOC_BGA1296U20C

PCIE_WAKE3_N
PCIE_WAKE2_N
PCIE_WAKE1_N
PCIE_WAKE0_N

PCIE2_USB3_SATA3_RCOMP_P

PCIE2_USB3_SATA3_RCOMP_N

PCIE_P3_USB3_P4_TXP
PCIE_P3_USB3_P4_TXN
PCIE_P3_USB3_P4_RXP

PCIE_P3_USB3_P4_RXN

PCIE_P4_USB3_P3_TXP
PCIE_P4_USB3_P3_TXN
PCIE_P4_USB3_P3_RXP
PCIE_P4_USB3_P3_RXN

PCIE_P5_USB3_P2_TXP
PCIE_P5_USB3_P2_TXN
PCIE_P5_USB3_P2_RXP
PCIE_P5_USB3_P2_RXN

PCIE_P0_TXP
PCIE_P0_TXN
PCIE_P0_RXP

PCIE_P0_RXN

PCIE_P1_TXP
PCIE_P1_TXN
PCIE_P1_RXP
PCIE_P1_RXN

PCIE_P2_TXP
PCIE_P2_TXN
PCIE_P2_RXP
PCIE_P2_RXN

PCIE_CLKREQ0_N
PCIE_CLKREQ1_N
PCIE_CLKREQ2_N
PCIE_CLKREQ3_N

PCIE_CLKOUT0P
PCIE_CLKOUT0N
PCIE_CLKOUT1P
PCIE_CLKOUT1N
PCIE_CLKOUT2P
PCIE_CLKOUT2N
PCIE_CLKOUT3P
PCIE_CLKOUT3N

RSVD_C1

RSVD_F1
RSVD_B4
RSVD_A4

RSVD_A18

Section 3 of 12

RSVD_C19

N62
P61
P62
R62

PCIE_RCOMPP

F6

PCIE_RCOMPN

F5
P3

P2
P12
P10

PCIE_TXP4_WLAN_C

N2

PCIE_TXN4_WLAN_C

M2
H5
H6

L2
L1
K7
M7

V3
V2
P7
P6

R1
R2
T10
T12

T2
T3
M5
M6

PCIE_CLKREQ_VGA#

AK62

PCIE_CLKREQ_WLAN#

AH62

PCIE_CLKREQ_LAN#

AH61

PCIE_CLKREQ3#

AJ62
C11

B11
C10
A10
A7
B8
B7
B5

C1
F1
B4
A4

A18
C19

SOC_PMC_WAKE [12]

12

R273
402/F_4

PEG_TXP3 [15]
PEG_TXN3 [15]
PEG_RXP3 [15]
PEG_RXN3 [15]

1 2

C34 0.1U/16V/X7R_4

1 2

C33 0.1U/16V/X7R_4

PCIE_RXP4_WLAN [28]
PCIE_RXN4_WLAN [28]

PCIE_TXP5_LAN [25]
PCIE_TXN5_LAN [25]
PCIE_RXP5_LAN [25]
PCIE_RXN5_LAN [25]

PEG_TXP0 [15]
PEG_TXN0 [15]
PEG_RXP0 [15]
PEG_RXN0 [15]

PEG_TXP1 [15]
PEG_TXN1 [15]
PEG_RXP1 [15]
PEG_RXN1 [15]

PEG_TXP2 [15]
PEG_TXN2 [15]
PEG_RXP2 [15]
PEG_RXN2 [15]

1

TP38

1

TP40

*PAD

dGPU

2.5~10 inch(Gen2)

PCIE_TXP4_WLAN [28]
PCIE_TXN4_WLAN [28]

LAN 2.5~12 inch(Gen1)

dGPU

2.5~10 inch(Gen2)

*PAD

PCIE_CLKREQ_VGA# [15]
PCIE_CLKREQ_WLAN# [28]
PCIE_CLKREQ_LAN# [25]

CLK_GFX_P [15]
CLK_GFX_N [15]
CLK_PCIE_WLANP [28]
CLK_PCIE_WLANN [28]
CLK_PCIE_LANP [25]
CLK_PCIE_LANN [25]

VGA
WLAN
LAN

WLAN

4~12 inch

2.5~12 inch(Gen1)

PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ3#

R419 10K_4
R408 10K_4
R424 10K_4
R429 10K_4

04

+1.8V

SoC SPI ROM socket

HOLD#

VDD

VSS

+1.8V_S5

8

7
4

12

R169

3.3K_4

1
6
5
2

3

U18

CE#
SCK
SI
SO

WP#

*GD25LB64CSIGR

1 2

R168

3.3K_4

C408

0.1U/16V_4

1 2

R159 *0_4

SOC_SPI_IO3SPI_IO3_A

R137

3.3K_4

SPI_CS#_A
SPI_CLK_A
SPI_SDI_A
SPI_SDO_A

+1.8V_S5

1 2

B B

SHPI_SPI_CS#[30]
SHPI_SPI_CLK[30]
SHPI_SPI_MOSI[30]
SHPI_SPI_MISO[30]

SHPI_SPI_WP#[30]

SHPI_SPI_HOLD#

1 2

R457 0_4

1 2

R462 0_4

1 2

R183 0_4

1 2

R458 0_4

1 2

R461 0_4

1 2

R455 0_4

SOC_SPI_CS0#
SOC_SPI_CLK
SOC_SPI_SI
SOC_SPI_SO

SOC_SPI_IO2 SPI_IO2_A
SOC_SPI_IO3

1 2

R175 *0_4

1 2

R150 *33_4

1 2

R143 *0_4

1 2

R154 *0_4

1 2

R146 *0_4

SPI socket P/N: DFHS08FS023 only for A-TEST

Placment Top side

SPI_CS#_A
SPI_CLK_A
SPI_SDI_A
SPI_SDO_A

A A

SPI_IO3_A
SPI_IO2_A

1

TP13

1

*PAD

TP9

1

*PAD

TP7

1

*PAD

TP10

1

*PAD

TP11

1

*PAD

TP8

*PAD

Colay

5

4

+1.8V_S5

SPI_IO2_A

SPI_IO3_A

SoC SPI ROM

U17

8

VCC

3

WP#

SPI_HOLD7GND

*SPI_FLASH

soic8-6-1_27-pm25lv010a

AKE5EZN0N01

IC FLASH (8P) W25Q64FWSSIQ (SOIC)

SPI_SI

SPI_SO

SPI_SCK

5
2
1

CS#

6

4

SPI_SDI_A
SPI_SDO_A
SPI_CS#_A
SPI_CLK_A

SPI_CS#_A [32]

3

1.8V

Vender Size Quanta P/NSPI ROM Vender P/N

AKE5EZN0N01WND W25Q64FWSSIQ

8MB

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT: HP-Oahu

BXTP(PCIE/USB/SATA/SPI)

BXTP(PCIE/USB/SATA/SPI)

BXTP(PCIE/USB/SATA/SPI)

1A

1A

4 49Thursday, October 27, 2016

4 49Thursday, October 27, 2016

4 49Thursday, October 27, 2016

1

1A

5

4

3

2

1

Apollolake (DISPLAY,eDP)

D D

AF2

DDI1_TXP_0

AF3

DDI1_TXN_0

AD3

DDI1_TXP_1

AD2

DDI1_TXN_1

AC1

DDI1_TXP_2

AC2

DDI1_TXN_2

AB3

DDI1_TXP_3

AB2

DDI1_TXN_3

AK16

DDI1_AUXP

AK15

DDI1_AUXN

IN_D2[23]
IN_D2#[23]

Max 7.5 inch

C C

EDP_PANEL_EN
EDP_BKLT_EN
EDP_BKLTCTL

TP_DETECT#

1 2

R489 *100K/F_4

1 2

R485 *100K/F_4

1 2

R500 *100K/F_4

R249 10K_4

+1.8V_S5

+1.8V_S5

HDMI

DDI0_HPD
DDI1_HPD

IN_D1[23]
IN_D1#[23]
IN_D0[23]

IN_D0#[23]
IN_CLK[23]
IN_CLK#[23]

HDMI_HPD_DC#[23]

INT_EDP_TXP0[21]
INT_EDP_TXN0[21]
INT_EDP_TXP1[21]
INT_EDP_TXN1[21]

1 2

R547 402/F_4

TP24

INT_EDP_TXP0
INT_EDP_TXN0
INT_EDP_TXP1
INT_EDP_TXN1

DDI0_RCOMP_P
DDI0_RCOMP_N

1

*

eDP Panel

1 2

INT_EDP_AUXP[21]

INT_EDP_AUXN[21]

SDVO_DATA[23]

SDVO_CLK[23]

EDP_PANEL_EN[12]
EDP_BKLT_EN[12]

R276 402/F_4

XTAL192_OUT

1

2

Y4

19.2MHZ +-30PPM

4

3

XTAL192_IN

eDP PWM

B B

EDP_BKLTCTL

R501

100K_4

1 2

GND

A A

+1.8V

2

1

Q35
RUC002N05GZT116

1 2

R486 *0_4

4.7K_4

R469

3

12

+3V

PCH_DPST_PWM [21]

<10000 mil

C428 27P/50V_4

C425 27P/50V_4

EDP_RCOMP_P
EDP_RCOMP_N

INT_EDP_AUXP
INT_EDP_AUXN

EDP_PANEL_EN
EDP_BKLT_EN
EDP_BKLTCTL

12

R526

200K/F_4

<1000 mil

5

4

3

AK3

AK2
AM3
AM2
AH3
AH2

AL2

AL1

AM16
AM15

B51

C51
AG1

AG2

C50

A50
AG7

AG9

AG12
AG10

AC6
AC5
AC7
AC9

AG6
AG5

AH10

AH9

C54

A54

C49

B49

C52

B53

C53

C47

B47

C46

AG62

AF61

AG63

AE60
AF62

P29

R27

DDI0_TXP_0
DDI0_TXN_0
DDI0_TXP_1
DDI0_TXN_1
DDI0_TXP_2
DDI0_TXN_2
DDI0_TXP_3
DDI0_TXN_3

DDI0_AUXP
DDI0_AUXN

MIPI_I2C_SDA
MIPI_I2C_SCL

DDI0_RCOMP_P
DDI0_RCOMP_N

GPIO_200
GPIO_199

EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_RCOMP_P
EDP_RCOMP_N

EDP_AUXP
EDP_AUXN

DDI1_DDC_SDA
DDI1_DDC_SCL

DDI0_DDC_SDA
DDI0_DDC_SCL

PNL1_VDDEN
PNL1_BKLTEN
PNL1_BKLTCTL

PNL0_VDDEN
PNL0_BKLTEN
PNL0_BKLTCTL

OSC_CLK_OUT_0
OSC_CLK_OUT_1
OSC_CLK_OUT_2
OSC_CLK_OUT_3
OSC_CLK_OUT_4

OSCOUT
OSCIN

Section 4 of 12

2

+1.8V_S5[4,6,7,8,10,11,12,20,30,32,36,37,42,43]
+1.8V[4,6,7,23,25,27,28,31,43]
+3V[7,12,13,14,15,16,17,18,20,21,22,23,25,26,27,29,30,31,35,37,38,43,44,45]

BXT_P_SOC_BGA1296U20D

MDSI_RCOMP

MDSI_C_DP_0
MDSI_C_DN_0
MDSI_C_DP_1
MDSI_C_DN_1
MDSI_C_DP_2
MDSI_C_DN_2
MDSI_C_DP_3
MDSI_C_DN_3

MDSI_C_CLKP

MDSI_C_CLKN

MDSI_A_DP_0
MDSI_A_DN_0
MDSI_A_DP_1
MDSI_A_DN_1
MDSI_A_DP_2
MDSI_A_DN_2
MDSI_A_DP_3
MDSI_A_DN_3

MDSI_A_CLKP
MDSI_A_CLKN

MCSI_DPHY1.2_RCOMP

MCSI_RX_DATA0_P
MCSI_RX_DATA0_N

MCSI_RX_CLK0_P

MCSI_RX_CLK0_N
MCSI_RX_DATA1_P
MCSI_RX_DATA1_N
MCSI_RX_DATA2_P
MCSI_RX_DATA2_N

MCSI_RX_CLK1_P

MCSI_RX_CLK1_N
MCSI_RX_DATA3_P
MCSI_RX_DATA3_N

MCSI_DPHY1.1_RCOMP

MCSI_DP_0
MCSI_DN_0
MCSI_DP_1
MCSI_DN_1
MCSI_DP_2
MCSI_DN_2
MCSI_DP_3
MCSI_DN_3

MCSI_CLKP_0
MCSI_CLKN_0
MCSI_CLKP_2
MCSI_CLKN_2

GP_CAMERASB0
GP_CAMERASB1
GP_CAMERASB2
GP_CAMERASB3
GP_CAMERASB4
GP_CAMERASB5
GP_CAMERASB6
GP_CAMERASB7
GP_CAMERASB8

GP_CAMERASB9
GP_CAMERASB10
GP_CAMERASB11

MDSI_A_TE
MDSI_C_TE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

MDSI_RCOMP

AP7

AK7
AK6
AM5
AM6
AM12
AM10
AK13
AM13

AM9
AM7

AP12
AP10
AR2
AR1
AP15
AP13
AP6
AP5

AP2
AP3

MCSI_DPHY1.2_RCOMP

F27
M23

P23
L23
J23
J21
H21
M25
L25
F25
E25
H25
J25

MCSI_DPHY1.1_RCOMP

H27
P17

M17
P21
R21
L17
J17
F17
E17

M19
L19
H19
F19

L37
P34

TP_DETECT#

J34
H30
M37
F30
R35
L34
M34
M35
R34
E30

M45
M43

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

BXTP (HDMI/eDP)

BXTP (HDMI/eDP)

BXTP (HDMI/eDP)

1 2

R548 150F_4

R251 150F_4

R252 150F_4

TP_DETECT# [22]

1 2

1 2

1

05

5 49Thursday, October 27, 2016

5 49Thursday, October 27, 2016

5 49Thursday, October 27, 2016

1A

1A

1A

5

4

3

2

1

Apollolake (EMMC/LPC/I2C)

EMMC_D0[27]
EMMC_D1[27]
EMMC_D2[27]
EMMC_D3[27]
EMMC_D4[27]
EMMC_D5[27]

D D

Pull low for normal platform operation
Pull low for normal platform operation

LPC 1.8V/3.3V mode select

Boot BIOS Strap
Pull low for normal platform operation
Pull low for normal platform operation

Pull low for normal platform operation

CLK_33M_KBC

C395

*18P/50V_4

CLK_33M_DEBUG

C C

C397

*18P/50V_4

Top swap override
Pull low for normal platform operation

Pull high for normal platform operation

LAD0[28,30,32]
LAD1[28,30,32]

LPC set 3.3V

LAD2[28,30,32]
LAD3[28,30,32]

CLK_33M_HEADER[32]

CLK_33M_KBC[30]

CLK_33M_DEBUG[28]

CLKRUN#[30]

LFRAME#[28,30,32]

SOC_SERIRQ[12]

Enable CSE(TXE3.0) ROM Bypass

Pull high for normal platform operation

Allow eMMC as a boot source

Allow SPI as a boot source

Force DNX FW Load

Pull high for normal platform operation

B B

SOC_KBC_SMI[12]

EMMC_D6[27]

EMMC_D7[27]
EMMC_RCLK[27]
EMMC_CMD[27]
EMMC_CLK[27]

GPIO_104[10]
GPIO_105[10]

GPIO_110[10]
GPIO_111[10]

GPIO_112[10]
GPIO_113[10]

GPIO_117[10]

GPIO_120[10]
GPIO_121[10]

GPIO_123[10]

R415 22_4
R414 22_4
R430 22_4
R416 22_4
R426 22_4
R427 22_4
R425 22_4

R417 22_4
R432 22_4
R179 22_4

GPIO_39[10]
GPIO_40[10]

GPIO_43[10,11]
GPIO_42[11]
GPIO_44[10]

GPIO_47[10]
GPIO_48[10]

TP21
TP22

TP15

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

TP27
TP29

TP30
TP28

*

*

*

*0.1U/16V_4

1
1

1

*
*

*
*

GPIO_104
GPIO_105

SOC_SPI_CS2#_TPM

GPIO_110
GPIO_111

GPIO_112
GPIO_113

GPIO_117
SOC_OVRIDE
GPIO_120

GPIO_121
GPIO_123

LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R

LPC_CLKOUT0
LPC_CLKOUT1

LPC_CLKRUN#_R
LPC_LFRAME#_R
SOC_SERIRQ_R

GPIO_39

1

GPIO_40

1

GPIO_43
GPIO_42
GPIO_44

1

GPIO_47

1

GPIO_48

C200

V58

EMMC_D0

T58

EMMC_D1

T59

EMMC_D2

V51

EMMC_D3

V52

EMMC_D4

Y49

EMMC_D5

V55

EMMC_D6

V57

EMMC_D7

V54

EMMC_RCLK

Y51

EMMC_CMD

Y58

EMMC_CLK

F54

SIO_SPI_0_CLK

F52

SIO_SPI_0_FS0

H52

SIO_SPI_0_FS1

H54

SIO_SPI_0_RXD

J52

SIO_SPI_0_TXD

F58

SIO_SPI_1_CLK

K55

SIO_SPI_1_FS0

F61

SIO_SPI_1_FS1

H57

SIO_SPI_1_RXD

H58

SIO_SPI_1_TXD

F62

SIO_SPI_2_CLK

D61

SIO_SPI_2_FS0

E56

SIO_SPI_2_FS1

D59

SIO_SPI_2_FS2

C62

SIO_SPI_2_RXD

E62

SIO_SPI_2_TXD

Y61

LPC_AD0

Y62

LPC_AD1

W62

LPC_AD2

W63

LPC_AD3

AB61

LPC_CLKOUT0

AA62

LPC_CLKOUT1

V62

LPC_CLKRUN_N

V61

LPC_FRAME_N

AB62

LPC_SERIRQ

B45

LPSS_UART0_TXD

C45

LPSS_UART0_RXD

A46

LPSS_UART0_RTS_N

C44

LPSS_UART0_CTS_N

B43

LPSS_UART1_TXD

C43

LPSS_UART1_RXD

A42

LPSS_UART1_RTS_N

C42

LPSS_UART1_CTS_N

H41

LPSS_UART2_TXD

J41

LPSS_UART2_RXD

L41

LPSS_UART2_RTS_N

M41

12

LPSS_UART2_CTS_N

P51

SDIO_PWR_DWN_N

T52

SDIO_D0

P57

SDIO_D1

T54

SDIO_D2

T55

SDIO_D3

T57

SDIO_CMD

P58

SDIO_CLK

AB55

SDCARD_LVL_WP

AC49

SDCARD_D0

AC48

SDCARD_D1

AC51

SDCARD_D2

AB51

SDCARD_D3

AC52

SDCARD_CMD

AB58

SDCARD_CLK

AB54

SDCARD_CD_N

BXT_P_SOC_BGA1296U20E

Section 5 of 12

RSVD_V49

GPIO_RCOMP

EMMC_RCOMP

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33

ISH_GPIO_0
ISH_GPIO_1
ISH_GPIO_2
ISH_GPIO_3
ISH_GPIO_4
ISH_GPIO_5
ISH_GPIO_6
ISH_GPIO_7
ISH_GPIO_8
ISH_GPIO_9

LPSS_I2C0_SDA
LPSS_I2C0_SCL

LPSS_I2C1_SDA
LPSS_I2C1_SCL

LPSS_I2C2_SDA
LPSS_I2C2_SCL

LPSS_I2C3_SDA
LPSS_I2C3_SCL

LPSS_I2C4_SDA
LPSS_I2C4_SCL

LPSS_I2C5_SDA
LPSS_I2C5_SCL

LPSS_I2C6_SDA
LPSS_I2C6_SCL

LPSS_I2C7_SDA
LPSS_I2C7_SCL

V49

GPIO_RCOMP

E34

EMMC_RCOMP

V59

A38

BID0

B33

BID1

C39

BID2

B39

BID3

B35

BID4

A34

BID5

B31
H39
B29
A30
L39

1 2

C34

R518

E39

1 2

R228

C30

BID6

C38

BID7

F39

SIM_DET

C36

NGFF_PRE

C35
J39
C33
B27

IERR

C26

SATA_GP0

A26

SATA_GP1

B25

SATA_DEVSLP

C25
C27
C31
C29
B37
H35

DGPU_EVENT#_Q

C37

DGPU_PWR_EN_SOC#

H34

DGPU_HOLD_RST#_Q

F35

DGPU_PWROK_Q

F34

HDA_BCLK_R

AM48

HDA_SYNC_R

AK58
AK51

HDA_SDO_R

AM54
AM51

RF_KILL#_R

AM49
AM57
AM55

SOC_BT_OFF#

AM52
AK57

AR62
AR63

AN62
AM61

AP59
AP58

AM62
AL62

AP52
AP54

AP49
AP51

AL63
AK61

AP62
AP61

1 2

R241 200/F_4

1 2

R190 200/F_4

BID0 [11]
BID1 [11]
BID2 [11]
BID3 [11]
BID4 [11]
BID5 [11]
ACCEL_INTH# [11]
GPIO_7 [11]
GPIO_8 [11]

0_4
*0_4

R283 33_4
R431 33_4

R165 33_4

GPIO_9 [11]

SOC_KBC_SCI [12]

1

TP31

1 2

R529 0_4

1

TP47

1

TP48

1

TP32

1

TP49

BOOT_BLK_WRITE# [32]
CLR_PASSWORD [32]

CLR_BIOS_DATA# [32]
BOOT_BLK_REC# [32]

DGPU_EVENT#_Q [20]
DGPU_PWR_EN_SOC# [20]
DGPU_HOLD_RST#_Q [20]
DGPU_PWROK_Q [20]

1 2
1 2

1 2

1

TP20

1

*

TP17

1

TP18

*
*

3/28 add Res option

SOC_PCI_SERR#

SATA_LED#

BIT_CLK_AUDIO [24]
ACZ_SYNC_AUDIO [24]
ACZ_SDIN0 [24]

ACZ_SDOUT_AUDIO [24]

BT_OFF [28]
ACZ_SPKR [24]

BIT_CLK_AUDIO

SATA_LED# [31]

HDA

+1.8V_S5[4,5,7,8,10,11,12,20,30,32,36,37,42,43]

SOC_PCI_SERR#
ACCEL_INTH#
SOC_KBC_SCI
SOC_KBC_SMI
BT_OFF
NGFF_PRE
SIM_DET
RF_KILL#_R

SATA_LED#

C277
*33p/50V_4

APL Doc.560733(HDA SDI I/O pin issue

APL Doc.560733(HDA SDI I/O pin issue

APL Doc.560733(HDA SDI I/O pin issueAPL Doc.560733(HDA SDI I/O pin issue
Remove these circuit for QS sample

Remove these circuit for QS sample

Remove these circuit for QS sampleRemove these circuit for QS sample

HDA_SYNC_R

DGPU_EVENT#_Q
DGPU_PWROK_Q
DGPU_PWR_EN_SOC#
DGPU_HOLD_RST#_Q

DGPU_EVENT#_Q
DGPU_PWROK_Q
DGPU_PWR_EN_SOC#
DGPU_HOLD_RST#_Q

DGPU_EVENT#_Q
DGPU_HOLD_RST#_Q
DGPU_PWR_EN_SOC#
DGPU_PWROK_Q

R530 *10K_4
R517 10K_4
R238 10K_4
R229 10K_4

R187 *4.7K/F_4

1 2

R515 *10K_4

1 2

R508 *10K_4

1 2

R209 *10K_4

R264 10K_4

PCI_SERR#[30]

R420 *249/F_4

12

R239 *EV@10K_4
R253 *EV@10K_4
R233 *EV@10K_4
R247 *EV@10K_4

R244 *EV@10K_4
R259 *EV@10K_4
R230 EV@10K_4
R246 EV@10K_4

R237 *EV@10K_4
R234 *EV@10K_4
R232 *EV@10K_4
R248 *EV@10K_4

12

SOC_PCI_SERR#

12

R407
*510/F_4

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

06

+1.8V_S5

+1.8V

3

2

Q38
*RK7002BM

1

HDA_SDIN0_AUDIO [24]

+3V_S5

+1.8V_S5

BOARD ID SETTING

EC-SI-04

1 2

Board ID
(Default = 00)

Model

A A

All EVT W/O
All DVT
PVT1
PVT2+

MVB,A
1st Major ECN
2nd Major ECN
3rd Major ECN

0
0
1
1 1
0 0
0 1
1 0
1 1

5

eMMC

0
1

Hynix

0

Samsung
Reserved

Board ID
(Default = 00)

BOARD_BID3BOARD_BID2

0
0
1
1 1

VRAM

0

UMA

1

Hynix

0

Mircon
Samsung

4

Board ID
(Default = 00)

BOARD_BID5BOARD_BID4BOARD_BID1BOARD_BID0

0 0
0 1
1 0
1 1

R63 10K_4

1 2

R64 *10K_4

1 2

R65 10K_4

1 2

R66 10K_4

1 2

R510 10K_4

1 2

R516 10K_4

1 2

R522 *10K_4

1 2

R506 *10K_4

3

BOARD ID SETTING

+1.8V_S5

1 2

R52 *10K_4

BID0
BID1
BID2
BID3
BID4
BID5
BID6
BID7

1 2

R53 10K_4

1 2

R54 *10K_4

1 2

R55 *10K_4

1 2

R511 *10K_4

1 2

R514 *10K_4

1 2

R523 *10K_4

1 2

R507 *10K_4

Override

Flash Descriptor Override (SOC_OVRIDE)

0 = Normal Override(Normal operation)

1 = Override

R85 0_4

3

EN_OVERRIDE[30]

2

2

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.8V_S5

R136

2.2K_4

SOC_OVRIDE

12

Q7
RUC002N05GZT116

GPIO_118 HW Strap

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

BXTP (GPIO/LPC/I2C/HDA)

BXTP (GPIO/LPC/I2C/HDA)

BXTP (GPIO/LPC/I2C/HDA)

SOC_OVRIDE [32]

1A

1A

6 49Thursday, October 27, 2016

6 49Thursday, October 27, 2016

1

6 49Thursday, October 27, 2016

1A

5

SLP_S4#

1

TP14

SLP_S3#

1

PMU set to 3.3V

+3V_S5 +1.8V_S5

R125
0_4

D D

C C

R129
*0_4

1 2

1 2

1 2

R403 *10K_4

12

R152 1K/F_4

1 2

R105 10K_4

1 2

R164 100K_4

1 2

R413 10K_4

12

R172 *1K/F_4

1 2

R423 *10K_4

1 2

R171 *20K/F_4

1 2

R157 20K/F_4

12

R405 1K/F_4

1 2

R406 *10K_4

1 2

R162 *10K_4

+1.8V_S5

check list use 20k

R210 1K/F_4

R205 4.7K/F_4
R206 *1K_4
R434 *1K/F_4
R433 *1K/F_4

R104 *10K_4
R177 100K/F_4

1 2

C168 *0.1U/16V_4

1 2

C160 *0.1U/16V_4

1 2

C165 *0.1U/16V_4

PCH_SUSPWRDNACK
PMC_WAKE#
AC_PRESENT
PCH_BATLOW#
PMU_RSTBTN#
PLTRST#
PMU_SLP_S0#

CORE_PWROK
SMB1ALERT#

PCH_SUS_STAT#
SOC_PWRBTN#

12

12
12
12
12

12
12

SOC_RSMRST#

H_PROCHOT#

RF_OFF

THRMTRIP#_R
SMB_SOC_DAT
SMB_SOC_CLK

AC_PRESENT

PLTRST#

CORE_PWROK

PCH_BATLOW#

SOC_RSMRST#

Pin AG55 is EMMC_PWR_EN_N (CRB 1.0)

Pin AG55 is EMMC_PWR_EN_N (CRB 1.0)

Pin AG55 is EMMC_PWR_EN_N (CRB 1.0)Pin AG55 is EMMC_PWR_EN_N (CRB 1.0)

Pull low for normal platform operation
Pull low for normal platform operation
VCC_1P24V_1P35V_A voltage select

TP37

*
*

SOC_RSMRST#[11,12]
H_PROCHOT#[30,33,41,42]

TP41 *

SLP_S4#[12]
SLP_S3#[12]

PMU_RSTBTN#[11]

SOC_PWRBTN#[11,12]

PLTRST#[11,12,15,25,28,30,32]

EC_PWROK[30]

THRMTRIP#[30]

RF_OFF[28]

+3V_RTC

SMBUS set to 3.3V

R173 330K_4

4

1

1 2

R184 200/F_4

1 2

R170 0_4

1 2

R207 0_4

GPIO_34[10]
GPIO_35[10]
GPIO_36[10]

12

TP23

TP25
TP26

Apollolake (PMU/PMIC/HDA)

PMU Block

Section 6 of 12

BXT_P_SOC_BGA1296U20F

SUSPWRDNACK

AVS_I2S1_WS_SYNC

AVS_I2S1_MCLK
AVS_I2S1_BCLK

AVS_I2S2_MCLK
AVS_I2S2_BCLK

AVS_I2S2_WS_SYNC
AVS_I2S3_WS_SYNC

AVS_I2S3_BCLK

AVS_DMIC_DATA_2
AVS_DMIC_DATA_1
AVS_DMIC_CLK_B1

AVS_DMIC_CLK_AB2

AVS_DMIC_CLK_A1
VCC_RTC_EXTPAD

PCIE_REF_CLK_RCOMP

SVID0_ALERT_N

SOC_RSMRST#
H_PROCHOT#
PMC_WAKE#
PMU_SUSCLK
SLP_S4#
SLP_S3#
PMU_SLP_S0#
PMU_RSTBTN#
PMU_RCOMP
SOC_PWRBTN#
PLTRST#
PCH_BATLOW#
AC_PRESENT

CORE_PWROK
THRMTRIP#_R

RF_OFF

1

*

1

1

*
*

INT_EDP_HPD#

GPIO_34
GPIO_35
GPIO_36

INTRUDER#

SMB_SOC_DAT
SMB_SOC_CLK

SMB1ALERT#

AH49

RTC_TEST_N

AC57

RSM_RST_N

E47

PROCHOT_N

AG55

PMU_WAKE_N

AE62

PMU_SUSCLK

AK54

PMU_SLP_S4_N

AC62

PMU_SLP_S3_N

AD61

PMU_SLP_S0_N

AD62

PMU_RSTBTN_N

AG59

PMU_RCOMP

AK55

PMU_PWRBTN_N

AG57

PMU_PLTRST_N

AH51

PMU_BATLOW_N

AK49

PMU_AC_PRESENT

AG49

SOC_PWROK

J47

PMIC_THERMTRIP_N

J45

PMIC_STDBY

M47

PMIC_SDWN_B_GPIO_213

F48

PMIC_RESET_N

H48

PMIC_PWRGOOD

F47

PMIC_I2C_SDA

H45

PMIC_I2C_SCL

L47

GPIO_214

P47

GPIO_215

H50

PMC_SPI_TXD

J50

PMC_SPI_RXD

M48

PMC_SPI_FS2

P48

PMC_SPI_FS1

L48

PMC_SPI_FS0

E52

PMC_SPI_CLK

B41

PWM0

C41

PWM1

F41

PWM2

E41

PWM3

B21

JTAGX

AC54

INTRUDER

T61

SMB_DATA

T62

SMB_CLK

R63

SMB_ALERT_N

H43

RSVD_H43

AG52

RSVD_AG52

J43

RSVD_J43

AG54

RSVD_AG54

RTC_RST_N

SUS_STAT_N

AVS_I2S1_SDO

AVS_I2S1_SDI

AVS_I2S2_SDO

AVS_I2S2_SDI

AVS_I2S3_SDO

AVS_I2S3_SDI

RTC_X2
RTC_X1

JTAG_PREQ_N

JTAG_PRDY_N

JTAG_PMODE

JTAG_TRST_N

JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

GPIO_219
GPIO_218
GPIO_217
GPIO_216

SVID0_DATA

SVID0_CLK

3

AC55
AC63
AG58

J62
K62
K61
G62
H63

M58
K59
K58
H59
M57

M61
L63
L62
M62

M52
M54
P52
M55
P54

AG51
AC58
AC59

XDP_PREQ#

C20

XDP_PRDY#

C21
B19

XDP_TRST#

C24

XDP_TMS

C23

XDP_TDO

A22

XDP_TDI

C22

XDP_TCK

B23
L30

M30
M29
P30

CLKDRV_RCOMP

E21

SVID_DAT#_R

C18

SVID_CLK#_R

C17

SVID_ALERT#_R

B17

RTC_RST#RTC_TEST#
PCH_SUSPWRDNACK
PCH_SUS_STAT#

GPIO_78

GPIO_88
HDA_RST#_R

GPIO_92

GPIO_82

C171 0.1U/16V_4

RTC_X2
RTC_X1

R535 100/F_4
R536 100/F_4

R258 *51_4
R534 51_4
R532 100/F_4
R533 51_4
R255 51_4

1 2

R402 *10K_4

GPIO_78 [10]

GPIO_88 [10]

GPIO_92 [10]

GPIO_82 [10]

+1.8V_S5

12

R257 60.4/F_4

1 2

R537 0_4

1 2

R541 0_4

12

R545 220_4

VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK

+1.8V_S5

1

TP39

*

SMBus 1.8V/3.3V mode select

PMU 1.8V/3.3V mode select

12

R18033_4

ACZ_RST#_AUDIO [24]

Apollo ED S pin

Apollo ED S pin 腳有錯

Apollo ED S pinApollo EDS p in

Pull low for normal platform operation

Folll ow APL MOW 31

Folll ow AP L MOW 31：：：：

Folll ow AP L MOW 31Folll ow AP L MOW 31
un-stuff 51 ohm pull down resistor on

un-stuff 51 ohm pull down resistor on

un-stuff 51 ohm pull down resistor on un-stuff 51 ohm pull down resistor on
TRST_N pin

TRST_N pin

TRST_N pinTRST_N pin

VR_SVID_DATA [41,42]
VR_SVID_CLK [ 41,42]
VR_SVID_ALERT# [41,42]

+1.05V

12

R543
169/F_4

腳有錯

腳有錯腳有錯

12

12

R546

R542
*84.5/F_4

C258
1000p/50V_4

68_4

2

SMBus No Re-Boot

+1.8V_S5[4,5,6,8,10,11,12,20,30,32,36,37,42,43]
+1.05V[8,38,41,42]
+3V_S5[6,8,12,20,22,25,28,29,30,32,33,34,36,37,38,41,42,43,45]
+3V_ALW[30,34]
+3V_RTC[8]

RTC Clock 32.768KHz (CPU)

XDP_TMS [11]
XDP_TCK [11]
XDP_TDO [11]
XDP_TDI [11]
XDP_TRST# [11]
XDP_PREQ# [11]
XDP_PRDY# [11]

THRMTRIP#_R

C145 15p/50V_4

C144 18P/50V_4

Trace length < 1000 mils

5

12

R466
*10K_4

2

34

*PJT138K
Q33A

GND

Y2

32.768KHz

+3V_ALW

61

1

RTC_X1

12

R174
10M_4

RTC_X2

CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p

R465
*10K_4

THRMTRIP#

Q33B
*PJT138K

07

AC_PRESENT

1 2

R95 0_4

B B

Q8A

34

1 2

R89 *10K_4

+3V_S5

*SSM6N43FU

1 2

AC_PRESENT_EC[30]

R90 *0_4

*SSM6N43FU

5

Q8B

61

2

GND

GND

AC_PRESENT

eDP HPD

INT_EDP_HPD#

RUC002N05GZT116

+1.8V

1 2
3

Q9

1

GND GND

R122
10K_4

EDP_HPD_C

2

R97 0_4

R96
100K_4

1 2

12

EDP_HPD [21]

SMBus

+3V_S5 +3V

A A

SoC

SMB_SOC_DAT

SMB_SOC_CLK

5

R139

R149

1K/F_4

1K/F_4

1 2

1 2

5

2
6

UM6K33NGTN

Q14

43

1

+3V

R153

R155

2.2K_4

2.2K_4

1 2

1 2

SMB_RUN_DAT [13,14]

SMB_RUN_CLK [13,14]

DDR3L

S0 APL S5

4

3

RTC Circuitry (RTC)

EC reset RTC

20MIL

12

+ -

VCCRTC_2

R161 1K/F_4

Trace width = 20 mils

CN19

CONNDIPHOUSING2P

Q12

4 3

1

SSM6N43FU

2

1 2

+3V_ALW +3V_RTC

+3V_RTC_1

1 2

5

R142 *0_4

RTC_RST#

1 2

2

R117 *0_4

RTC_TEST#

6

+3V_RTC
Trace width = 20 mils

D7

R132

1 2

20K/F_4

BAT54C

R131

1 2

20K/F_4

C130
1u/6.3V_4

1 2

R141 10K_4

1 2

R115 10K_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

RTC_RST#

C105
1u/6.3V_4

RTC_TEST#

C121
1u/6.3V_4

EC_RTC_RST [30]

EC_RTC_TEST_RST [30]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

BXTP (PMU/PMIC/SMB/RTC)

BXTP (PMU/PMIC/SMB/RTC)

BXTP (PMU/PMIC/SMB/RTC)

1

1A

1A

7 49Thursday, October 27, 2016

7 49Thursday, October 27, 2016

7 49Thursday, October 27, 2016

1A

5

BOT side cap TOP side cap

+VNN Output Decoupling Recommendations

D D

VDD2_1P24_GLML Output Decoupling Recommendations

22uFx1

VDD2_1P24_DSI_CSI Output Decoupling Recommendations

1uFx2
22uFx1

VDD2_1P24_AUD_ISH_PLL Output Decoupling Recommendations

C C

22uFx1

VDD2_1P24_MPHY Output Decoupling Recommendations

22uFx1

VCCRAM_1P05_IO_3PHASEIO Output Decoupling Recommendations

1uFx4
22uFx1

B B

+VCCDDQ Output Decoupling Recommendations

1uFx2
22uFx8

A A

TOP*1 / BOT*3, inside socket cavity

04021uFx4

TOP, inside socket cavity0603

TOP*1 / BOT*1, inside socket cavity

0402
0603 TOP, inside socket cavity

TOP*1 / BOT*1, inside socket cavity

04021uFx2

TOP, inside socket cavity0603

TOP*1 / BOT*2, inside socket cavity

04021uFx3

TOP, inside socket cavity0603

TOP*2 / BOT*2, inside socket cavity

0402
0603 TOP, inside socket cavity

BOT, inside socket cavity

0402
0603 TOP, inside socket cavity

1uFx3 0402

+1.35V_S3

0603

+1.05V

BOT, inside socket cavity
TOP, inside socket cavity22uFx4

+3V_S5

+1.24V_S5

40mil

R281 0_4

1 2

R280 0_6

1 2

40mil

R285 0_6

1 2

40mil

R284 0_6

1 2

40mil

R286 *0_6

1 2

40mil

+1.8V_S5

100mil

R282 0_6

1 2

C239
22u/6.3V_6

+VDD2_1P24_USB2
+VDD2_1P24_AUD_ISH_PLL

+VDD2_1P24_MPHY

+VDD2_1P24_GLML

+VDD2_1P24_DSI_CSI

VCCRAM_1P05_IO_3PHASEIO

C261

C244

22u/6.3V_6

22u/6.3V_6

C255
22u/6.3V_6

C109
22u/6.3V_6

+3V_RTC

C234
1u/6.3V_4

C260
1u/6.3V_4

C251
1u/6.3V_4

C269
1u/6.3V_4

C226
1u/6.3V_4

C240
1u/6.3V_4

C159
22u/6.3V_6

4

C208
22u/6.3V_6

C187
1u/6.3V_4

C195
1u/6.3V_4

C256
1u/6.3V_4

C242
1u/6.3V_4

C247
1u/6.3V_4

C252
1u/6.3V_4

C176
1u/6.3V_4

R181 0_6

1 2

4/14 C349 change to 1U 0402

C248
1u/6.3V_4

+1.05V

C166
22u/6.3V_6

C108

C107

22u/6.3V_6

22u/6.3V_6

C192
1u/6.3V_4

C188
1u/6.3V_4

C267
22u/6.3V_6

C270
1u/6.3V_4

C220
1u/6.3V_4

C276
1u/6.3V_4

C196
1u/6.3V_4

VRTC_3P3

C254
1u/6.3V_4

R262 0_6

1 2

R265 0_6

1 2

R270 0_6

1 2

C164
22u/6.3V_6

C245
1u/6.3V_4

C201
1u/6.3V_4

VNN_SENSE[41]

C225
1u/6.3V_4

C272
22u/6.3V_6

C213
1u/6.3V_4

+VDD2_1P24_AUD_ISH_PLL

C278
22u/6.3V_6

C182
1u/6.3V_4

C250
1u/6.3V_4

VCCRAM_1P05_FUSE
VCCRAM_1P05_FHV1
VCCRAM_1P05_FHV0

C161
22u/6.3V_6

C175
1u/6.3V_4

+VNN

60mil

C180
22u/6.3V_6

C238
1u/6.3V_4

C271
22u/6.3V_6

C259
22u/6.3V_6

C163
1u/6.3V_4

C268
22u/6.3V_6

3

Apollolake (POWER)

AJ44

RSVD_AJ44

AJ37

VNN_SVID_1

AJ39

VNN_SVID_2

AJ41

VNN_SVID_3

AJ42

VNN_SVID_4

AJ46
AK37
AK39
AK41
AK42
AK44
AK46
AM44

AG48
BG63
AC41

AA42

Y44
V44
V46

AJ25
AK25

AC22
AC20
AG20

AJ20

AJ22
AE18

AE20
AE22
AG22

AM20
AM28
AM37
AK20

AA18

AA20
AK22

V48

AA46
AC46
AE44
AE42
AC42
AC44
AE46
AG25

BJ3

BJ61

AA44

AA22
AC23

V18
Y18
Y20

AA23

P16

AN18
AN20
AN22
AN23
AN41
AN42
AN44
AN46
AR17
AR47

AT13

AT17

AT47

AT51

AV14

AV50
AM32

4.8A

VNN_SVID_5
VNN_SVID_6
VNN_SVID_7
VNN_SVID_8
VNN_SVID_9
VNN_SVID_10
VNN_SVID_11
VNN_SVID_12

VNN_SENSE
RSVD_BG63
VCC_3P3V_A_1

VCC_3P3V_A_2
VCC_3P3V_A_3
VCC_3P3V_A_4
VCC_3P3V_A_5
VCC_3P3V_A_USB_1
VCC_3P3V_A_USB_2

RSVD_AC22
RSVD_AC20
VCC_1P24V_1P35V_A_USB2
VCC_1P24V_1P35V_A_PLL_1

VCC_1P24V_1P35V_A_PLL_2
VCC_1P24V_1P35V_A_MPHY_1

VCC_1P24V_1P35V_A_MPHY_2
VCC_1P24V_1P35V_A_MPHY_3
VCC_1P24V_1P35V_A_MPHY_4

VCC_1P24V_1P35V_A_GLML2LDO_1
VCC_1P24V_1P35V_A_GLML2LDO_2
VCC_1P24V_1P35V_A_GLML2LDO_3
VCC_1P24V_1P35V_A_GLML2

VCC_1P24V_A_1
VCC_1P24V_A_2

VCC_1P24V_1P35V_A_AUD_ISH
RSVD_V48

VCC_1P8V_A_1
VCC_1P8V_A_2
VCC_1P8V_A_3
VCC_1P8V_A_4
VCC_1P8V_A_5
VCC_1P8V_A_6
VCC_1P8V_A_7
VCC_1P8V_A_8

RSVD_BJ3
RSVD_BJ61

VCCRTC_3P3V

D1

RSVD_D1

VCC_1P05V_IO_1
VCC_1P05V_IO_2
VCC_1P05V_IO_3
VCC_1P05V_IO_4
VCC_1P05V_IO_5

VCC_1P05V_3PHASEIO
VCC_1P05V_FUSE

T15

VCC_1P05V_FHV1

T13

VCC_1P05V_FHV0

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7

2.8A

VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16

RSVD_AM32

0.15A

0.4A

Section 8 of 12

Section 9 of 12

2.7A

BXT_P_SOC_BGA1296U20I

VCC_VCGI_SENSE_P
VCC_VCGI_SENSE_N

1.3A

BXT_P_SOC_BGA1296U20H

21A

RSVD_BJ62

VCCIOA_1
VCCIOA_2
VCCIOA_3
VCCIOA_4

RSVD_AN32

VCC_VCGI_1
VCC_VCGI_2
VCC_VCGI_3
VCC_VCGI_4
VCC_VCGI_5
VCC_VCGI_6
VCC_VCGI_7
VCC_VCGI_8

VCC_VCGI_9
VCC_VCGI_10
VCC_VCGI_11
VCC_VCGI_12
VCC_VCGI_13
VCC_VCGI_14
VCC_VCGI_15
VCC_VCGI_16
VCC_VCGI_17
VCC_VCGI_18
VCC_VCGI_19
VCC_VCGI_20
VCC_VCGI_21
VCC_VCGI_22
VCC_VCGI_23
VCC_VCGI_24
VCC_VCGI_25
VCC_VCGI_26
VCC_VCGI_27
VCC_VCGI_28
VCC_VCGI_29
VCC_VCGI_30
VCC_VCGI_31
VCC_VCGI_32
VCC_VCGI_33
VCC_VCGI_34
VCC_VCGI_35
VCC_VCGI_36
VCC_VCGI_37
VCC_VCGI_38
VCC_VCGI_39
VCC_VCGI_40
VCC_VCGI_41
VCC_VCGI_42
VCC_VCGI_43
VCC_VCGI_44
VCC_VCGI_45
VCC_VCGI_46
VCC_VCGI_47
VCC_VCGI_48
VCC_VCGI_49
VCC_VCGI_50
VCC_VCGI_51
VCC_VCGI_52
VCC_VCGI_53
VCC_VCGI_54
VCC_VCGI_55
VCC_VCGI_56
VCC_VCGI_57
VCC_VCGI_58
VCC_VCGI_59
VCC_VCGI_60
VCC_VCGI_61
VCC_VCGI_62
VCC_VCGI_63
VCC_VCGI_64

VCC_1P05V_1
VCC_1P05V_2
VCC_1P05V_3
VCC_1P05V_4
VCC_1P05V_5
VCC_1P05V_6
VCC_1P05V_7
VCC_1P05V_8
VCC_1P05V_9

VCC_1P05V_10
VCC_1P05V_11
VCC_1P05V_12

BJ62
R41
R43

AM23
AM25
AM41
AM42

AN32

2

+VCC_VCGI

AA36
AA37
AA39
AC36
AC37
AE36
AE37
AG36
E43
E45
E48
E50
R45
R47
U36
U37
U39
U41
U42
U44
U46
U47
U48
V36
V37
V39
V41
Y36
Y37
Y39
Y41
AA28
AA30
AA32
AC28
AC30
AC32
AE28
AE30
AE32
AG28
AG30
AG32
AJ28
AJ30
AJ32
AK28
AK30
AK32
AK34
AM30
E29
E35
E37
F29
U28
U30
U32
V28
V30
V32
Y28
Y30
Y32

AA25
AC25
AE25
U22
U23
V22
V23
V25
Y23
Y25
U25
U20

+VCC_VCCGI Output Decoupling Recommendations

22uFx8
47uFx3
330uFx1

C229
22u/6.3V_6

VCCGI_SENSE [42]
VCCGISS_SENSE [42]

+VCCIOA

C203

C172

C190
22u/6.3V_6

22u/6.3V_6

1u/6.3V_4

C424
47u/6.3VS_8

C179
22u/6.3V_6

C174
1u/6.3V_4

04021uFx12
0603
0805
7343

100mil

C230
22u/6.3V_6

C423
47u/6.3VS_8

C191
22u/6.3V_6

C223
1u/6.3V_4

BOT, inside socket cavity
TOP, inside socket cavity
TOP, inside socket cavity
TOP, inside socket cavity

C231
1u/6.3V_4

R236 0_6

1 2

C228
1u/6.3V_4

C422
47u/6.3VS_8

C209
22u/6.3V_6

C199
1u/6.3V_4

+VCCRAM_1P05 Output Decoupling Recommendations

22uFx2 TOP, inside socket cavity0603

C232
1u/6.3V_4

+VNN

+3V_S5[6,7,12,20,22,25,28,29,30,32,33,34 ,36,37,38,41,42,43,45]
+1.24V_S5[37]
+1.8V_S5[4,5,6,7,10,11,12 ,20,30,32,36,37,42,43]
+3V_RTC[7] +1.35V_S3[3,13,14 ,35]

+

C427
*330U_2.5V_3528

C215

C207

C216

22u/6.3V_6

22u/6.3V_6

C205

C210

1u/6.3V_4

1u/6.3V_4

TOP*2 / BOT*2, inside socket cavity

04021uFx4

+VCCRAM_1P05

C233

C241

1u/6.3V_4

1u/6.3V_4

VCCIOA Output Decoupling Recommendations

04021uFx2

22uFx2 TOP, inside socket cavity0603

C224

22u/6.3V_6

22u/6.3V_6

C222

C217

1u/6.3V_4

1u/6.3V_4

R256 0_6

1 2

TOP, inside socket cavity

C186
22u/6.3V_6

C214
1u/6.3V_4

+1.05V

+VNN[41]
+VCC_VCGI[42]
+1.05V[7,38,41,42]

C221
1u/6.3V_4

C183
1u/6.3V_4

1

08

C197

C202

1u/6.3V_4

1u/6.3V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

BXTP (POWER)

BXTP (POWER)

BXTP (POWER)

1

1A

1A

1A

8 4 9Thursday, October 27, 2016

8 4 9Thursday, October 27, 2016

8 4 9Thursday, October 27, 2016

5

4

3

2

1

Apollolake ULT (GND)

1

09

M12
C15
F16
J16
D8
E8
H16
C9
F8
E10
E16
F14
F12
H10
H14
H12
A14
C14
M39
P39
R39
R37
C2
J29
P25
R30
C63
E63
D2
AP57

9 49Thursday, October 27, 2016

9 49Thursday, October 27, 2016

9 49Thursday, October 27, 2016

1A

1A

1A

R29
A12
A16
A20

D D

C C

B B

A A

A24
A28
A32
A36
A40
A44
A48

A5
A52
A56
A62

A9

AA1

AA2
AA27
AA34
AA41
AA63
AB10
AB12
AB16
AB48

AB5
AB52
AB57
AB59

AB9
AC18
AC27
AC34
AC39

AE1
AE10
AE11
AE13
AE14
AE16
AE17

AE2
AE23
AE27
AE34
AE39

AE4
AE41
AE47
AE48

AE5
AE50
AE51
AE53
AE54
AE56
AE57
AE59
AE63

AE7

AE8
AG13
AG18
AG23
AG27
AG34
AG37
AG39
AG41
AG42
AG44
AG46
AH15
AH16
AH48

AH5
AH52
AH54
AH55
AH57

5

BXT_P_SOC_BGA1296U20J

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

Section 10 of 12

AH58
AH59
AH6
AH7
AJ1
AJ18
AJ2
AJ23
AJ27
AJ34
AJ36
AJ63
AK10
AK12
AK18
AK23
AK27
AK36
AK48
AK5
AK52
AK59
AK9
AM18
AM22
AM27
AM34
AM36
AM39
AM46
AN1
AN10
AN11
AN13
AN14
AN16
AN17
AN2
AN25
AN27
AN28
AN30
AN34
AN36
AN37
AN39
AN47
AN48
AN5
AN50
AN51
AN53
AN54
AN56
AN57
AN59
AN63
AN7
AN8
AP55
AP9
AR19
AR32
AR45
AT12
AT16
AT19
AT2
AT25
AT29
AT3
AT35
AT39
AT45
AT48
AT52
AT57
AT61
AT62
AT7
AU32

4

AV19

AV2
AV21
AV23
AV29

AV3
AV32
AV35
AV41
AV43
AV45
AV55
AV61
AV62

AV9

AW14
AW30
AW34
AW50

AY10
AY32
AY54
AY58

AY6

B62

B63

BA1
BA12
BA16
BA17

BA2
BA21
BA25
BA27
BA29
BA32
BA35
BA37
BA39
BA43
BA47
BA48
BA52
BA62
BA63
BB19
BB25

BB3
BB39
BB45
BB61

BC32

BD3

BD32
BD56
BD61

BD8

BE1
BE10
BE12
BE16
BE17
BE21
BE27
BE29
BE35
BE37
BE43
BE47
BE48
BE52
BE54
BE63

BF3
BF32
BF61

BG19
BG23

B2
B3

B9

BXT_P_SOC_BGA1296U20K

VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

Section 11 of 12

BG29
BG32
BG35
BG41
BG45
BH1
BH2
BH21
BH25
BH39
BH43
BH62
BH63
BJ10
BJ14
BJ18
BJ28
BJ32
BJ36
BJ4
BJ46
BJ50
BJ54
BJ56
BJ60
BJ8
C12
C16
C28
C32
C40
C48
D32
D58
D6
E12
E14
E19
E27
E4
E54
F10
F21
F3
F32
F37
F43
F45
F50
F56
F59
F63
G1
G32
H17
H23
H29
H3
H37
H47
H61
H7
J12
J14
J19
J27
J30
J32
J35
J37
J48
J63
K32
K5
K54
K57
K6
L21
L27
L29
L35

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

BXT_P_SOC_BGA1296U20L

VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

Sect 12/12

U2
U27
U34
U5
U50
U51
U53
U54
U56
U57
U59
U62
U63
U7
U8
V20
V27
V34
V42
Y12
Y16
Y22
Y27
Y34
Y42
Y46
Y48
Y5
Y52
Y54
Y55
Y57
Y59
Y6
Y7

VNNSS_SENSE [41]

B13
C13
L16

M16

E23
F23

R25
AB49
AC13
AB13

AM59
AM58

T51
L14

R19

R17

A60
A61
BJ2

BG1

P27

M10

B15

E6
E3

D4

A3

SPARE_9
SPARE_8
SPARE_7
SPARE_6
SPARE_5
SPARE_4
SPARE_3
SPARE_2
SPARE_11
SPARE_10
SPARE_1
SPARE_0

NOCONNECT_1
NOCONNECT_2
NOCONNECT_3
NOCONNECT_4
NOCONNECT_5
NOCONNECT_6
NOCONNECT_7
NOCONNECT_8
NOCONNECT_9
NOCONNECT_10
NOCONNECT_11
NOCONNECT_12
NOCONNECT_13
NOCONNECT_14
NOCONNECT_15

Section 7 of 12

BXT_P_SOC_BGA1296U20G

NOCONNECT_16
NOCONNECT_17
NOCONNECT_18
NOCONNECT_19
NOCONNECT_20
NOCONNECT_21
NOCONNECT_22
NOCONNECT_23
NOCONNECT_24
NOCONNECT_25
NOCONNECT_26
NOCONNECT_27
NOCONNECT_28
NOCONNECT_29
NOCONNECT_30
NOCONNECT_31
NOCONNECT_32
NOCONNECT_33
NOCONNECT_34
NOCONNECT_35
NOCONNECT_36
NOCONNECT_37
NOCONNECT_38
NOCONNECT_39
NOCONNECT_40
NOCONNECT_41
NOCONNECT_42
NOCONNECT_43
NOCONNECT_44
NOCONNECT_45

L43
L45

L50
M14
M21
M27

M3
M32
M50
M59

M9

N1
N32
N63
P13
P19
P35
P37
P41
P43
P45

P5
P55
P59

P9
R23
R32

T49

U1
U10
U11
U13
U14
U16
U17
U18

R212 0_4

R7193, please close Ball AE47.

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BXTP (GND)

BXTP (GND)

BXTP (GND)

5

4

3

2

1

HARDWARE STRAPS

Folllow APL WoW36

Folllow APL WoW36：：：：

Folllow APL WoW36Folllow APL WoW36
Enable boot from SPI

Enable boot from SPI

+1.8V_S5

D D

C C

This rail must be 1.24V for A0 step.
Starting B-step, this rail can be 1.24V or 1.35V

12

1 2

R225
*4.7K/F_4

R224
10K_4

12

1 2

12

R498

R214

*4.7K/F_4

*4.7K/F_4

3/22 change to 4.7k

12

R497

R213

4.7K/F_4

10K_4

12

1 2

R503

4.7K/F_4

R502
*10K_4

12

1 2

R222
*4.7K/F_4

R221
10K_4

1 2

12

R411
*10K_4

R437

4.7K/F_4

1 2

12

R410
*10K_4

R436

4.7K/F_4

12

1 2

R409
*4.7K/F_4

R435
10K_4

12

12

R195
*4.7K/F_4

R199

4.7K/F_4

1 2

12

R412
*10K_4

R438

4.7K/F_4

12

1 2

Enable boot from SPIEnable boot from SPI
GPIO_43=0;GPIO_44=1

GPIO_43=0;GPIO_44=1

GPIO_43=0;GPIO_44=1GPIO_43=0;GPIO_44=1

R468
*4.7K/F_4

GPIO_36
GPIO_39
GPIO_43
GPIO_44
GPIO_47
GPIO_78
GPIO_88
GPIO_92
GPIO_110
GPIO_111

GPIO_120

R467
10K_4

GPIO_36 [7]

GPIO_39 [6]

GPIO_43 [6,11]

GPIO_44 [6]

GPIO_47 [6]

GPIO_78 [7]

GPIO_88 [7]

GPIO_92 [7]

GPIO_110 [6]

GPIO_111 [6]

GPIO_120 [6]

Hardware Strap Strap Description

VCC_1P24V_1P35V_A voltage select

0 = 1.24VGPIO_36

1 = 1.35V
Enable CSE(TXE3.0) ROM Bypass

GPIO_39

GPIO_43

GPIO_44

GPIO_47

GPIO_78

GPIO_88

GPIO_92

GPIO_110

GPIO_111

GPIO_120

0 = Disable bypass

1 = Enable Bypass
Allow eMMC as a boot source

0 = Disable

1 = Enable
Allow SPI as a boot source

0 = Disable

1 = Enable

Force DNX FW Load

0 = Do not force

1 = Force
SMBus 1.8V/3.3V mode select

0=buffers set to 3.3V

1=buffers set to 1.8V
PMU 1.8V/3.3V mode select

0=buffers set to 3.3V mode

1=buffers set to 1.8V mode
SMBus No Re-Boot

0 = Disable (default)

1 = Enable
LPC 1.8V/3.3V mode select

0=buffers set to 3.3V mode

1=buffers set to 1.8V mode
Boot BIOS Strap

0 = Boot from SPI

1 = Do not boot from SPI

Top swap override

0 = Disable

1 = Enable

+1.8V_S5[4,5,6,7,8,11,12,20,30,32,36,37,42,43]

10

Value

0

0

0

1

0

0

0

0

0

0

0

B B

GPIO_123[6]

A A

5

GPIO_123

1 2

R448 10K_4

+1.8V_S5

4

GPIO_34[7]
GPIO_35[7]
GPIO_40[6]
GPIO_48[6]
GPIO_82[7]
GPIO_104[6]
GPIO_105[6]
GPIO_117[6]
GPIO_112[6]
GPIO_113[6]
GPIO_121[6]

GPIO_34
GPIO_35
GPIO_40
GPIO_48
GPIO_82
GPIO_104
GPIO_105
GPIO_117
GPIO_112
GPIO_113
GPIO_121

1 2

R505 10K_4

1 2

R504 10K_4

1 2

R488 4.7K/F_4

1 2

R231 10K_4

1 2

R194 10K_4

1 2

R196 10K_4

1 2

R202 10K_4

1 2

R191 10K_4

1 2

R200 4.7K/F_4

1 2

R192 4.7K/F_4

1 2

R188 10K_4

3

Please ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation.
GPIO_40/GPIO_48/GPIO_104/GPIO_105/GPIO_112/GPIO_113/GPIO_117/GPIO_121 PD
GPIO_106/GPIO_123 PU

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HARDWARE STRAPS

HARDWARE STRAPS

HARDWARE STRAPS

1

1A

1A

10 49Thursday, October 27, 2016

10 49Thursday, October 27, 2016

10 49Thursday, October 27, 2016

1A

5

4

3

2

1

+1.8V_S5[4,5,6,7,8,10,12,20,30,32,36,37,42,43]

+1.8V_S5 +1.8V_S5

D D

XDP_TCK[7]
XDP_TDI[7]

XDP_TRST#[7]
XDP_PRDY#[7]

BID0[6]

TP35

*

BID1[6]
BID2[6]
BID3[6]
BID4[6]
BID5[6]

C C

B B

ACCEL_INTH#[6]

GPIO_7[6]
GPIO_8[6]

GPIO_9[6]

R43 0_41 2

DEBUG38

1

R387 1K/F_4

12

CN1

1

V1P8

3

JTAG_TCK

5

JTAG_TDI

7

PMU_PLTRST_N

9

JTAG_TRST_N

11

JTAG_PRDY_N

13

GPIO_0

15

GPIO_123

17

GND4

19

GPIO_1

21

GPIO_2

23

GPIO_3

25

GPIO_4

27

GPIO_5

29

GPIO_6

31

GPIO_7

33

GPIO_8

35

GPIO_10

37

GPIO_11

39

GPIO_12

41

GPIO_13

43

GPIO_14

45

GPIO_15

47

GPIO_16

49

GPIO_17

51

NC1

53

NC2

55

NC3

57

GND2

59

TRC_CLK3

*Samtec BSH-030-01

PMU_RSTBTN_N

JTAG_PREQ_N

CPU XDP

RESET_BTN_N

PMU_PLTRST_N_2

POWER_BTN_N

UART1_TXD/GPIO_43
UART1_RXD/GPIO_42

NC461NC562NC663NC764NC865NC9

66

JTAG_TMS
JTAG_TDO

TRST_PD

V1P8_2

GPIO_18

GND
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26

GPIO_106

RSMRST_N

GPIO_28
GPIO_29

I2C_SCL
I2C_SDA
GPIO_30

GND3

GPIO_27

2
4
6
8

R5 10K_412

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

PMU_RSTBTN#
DEBUG38

R46 1K/F_412
R1 0_4
R388 1K/F_4

XDP_TMS [7]
XDP_TDO [7]

PMU_RSTBTN# [7]

XDP_PREQ# [7]

1 2

1

TP1

1

TP2

*PAD
*PAD

1

TP3

*PAD

12

GPIO_43 [6,10]
GPIO_42 [6]

PLTRST# [7,12,15,25,28,30,32]
SOC_PWRBTN# [7,12]
SOC_RSMRST# [7,12]

11

A A

Size Document Number Rev

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5

4

3

Date: Sheet of

2

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APL XDP

APL XDP

APL XDP

11 49Thursday, October 27, 2016

11 49Thursday, October 27, 2016

11 49Thursday, October 27, 2016

1

1A

1A

1A

5

4

3

2

1

SERIRQ

12

+3V_S5+1.8V_S5

U24

6

SERIRQ

VCCA1VCCB

3

A

GND2OE

*G2129TL1U

4

B

5

SWITCH_EN

SERIRQ

12

R601 *4.7K_4

SERIRQ [30,32]

+1.8V_S5

SOC_SERIRQ

GND

1 2

R582 0_4

+3V_S5

R581
10K_4

SOC_SERIRQ

SOC_SERIRQ[6]

D D

SUSB/C#

1 2

R113 0_4

Q10A

*PJT138K

SLP_S3#

SLP_S3#[7]

C C

+1.8V_S5

SLP_S4#[7]

SLP_S4#

R119 0_4

Q10B
*PJT138K

1 2

+3V_S5 +3V_ S5

12

12

R118

R107

*10K/F_4

*10K/F_4

34

5

2

61

SUSB# [30]

SUSC# [30]

PWRBTN#/PCIE_WAKE# RSMRST#

21

Q6

1

1 2

SOC_PMC_W AKE

SOC_PMC_W AKEPCIE_WAKE#

R87

R84

1 2

R830_4

1 2

*10K/F_4

+1.8V_S5

SOC_PWR BTN# [7,11]
SOC_PMC_W AKE [4]

10K/F_4

+1.8V_S5

RSMRST#[30]

+3V_S5

1 2

R86 0_ 4

U7

1

DNBSWO N#[30]

GND +3V_S5

PCIE_WAKE#[25,28]

1 2

R91 10K_4

+1.8V_S5

A1

Y1

2

GND

VCC

A23Y2

*74LVC2G07GW

D6 *RB500V-40

3

2

6
5
4

PJA138K

1 2

C323

*0.1U/16V/X7R_4

CPU IO is 3.3V

SOC_RSMRST # [7,11]

R3080_4

SOC_RSMRST #

R307
100K/F_4

1 2

GND GND

SCI#/SMI#

1 2

R513
*10K_4

6
5
4

Q36B
*PJT138K

74LV_VCC

PLTRST#

PLTRST#

R350 *10K/F_4

1 2

1 2

R349 *10K/F_4

R352

1 2

+3V_S5

SIO_EXT_SCI#[30]

B B

SIO_EXT_SMI#[30,32]

+3V_S5

PLTRST#

SOC_PLTRST #[27]

A A

SOC_PLTRST #

SOC_PLTRST #

*10K/F_4

GND

1 2

R339 *10K/F_4

5

5

1 2

U14

1

A1

2

GND
A23Y2

*74LVC2G07GW

1 2

R512
*10K_4

2

34

*PJT138K
Q36A

GND

1 2

R509 0_4

R3510 _4

Y1

VCC

R3380 _4

+3V

61

+1.8V_S5

SOC_KBC_SC I [6]

R340*0_4

+3V_S5

SOC_KBC_SMI [ 6]

+1.8V_S5

PLTRST# [7,11,15,25,28,30,32]

Disp ON/BL ON(OK)

12

EDP_PANEL_EN[5]

GND

12

R484 100K/F_4

GND

4

1

A1

2

GND
A23Y2

74LVC2G07GW

12

R156 100K/F_4

GND

U8

Y1

VCC

3

R126 4.7K_4

6
5

R127 0_4

4

R130 4.7K_4

1 2

12

+3V

PCH_DISP_ON [22]

+1.8V_S5

PCH_EDP_BLO N [22]EDP_BKLT_EN[5]

+3V

+3V[5,7,13,14,15,16,17,18,20,21,22,23,25,26,27, 29,30,31,35,37,38,43,44,45]
+1.8V_S5[4,5,6,7,8,10,11, 20,30,32,36,37,42,43]
+3V_S5[6,7,8,20,22,25,28,29,30,32,33,34,36,37,38,41,42,43,45]

HP Restricted Secret

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Level shift/Thermistor

Level shift/Thermistor

Level shift/Thermistor

1

1A

1A

12 49T hursday, Octob er 27, 2016

12 49T hursday, Octob er 27, 2016

12 49T hursday, Octob er 27, 2016

1A

5

4

3

2

1

M_A_A[15:0][3]

D D

M_A_BS#0[3]
M_A_BS#1[3]
M_A_BS#2[3]
M_A_CS#0[3]
M_A_CS#1[3]
M_A_CLK0[3]
M_A_CLK0#[3]
M_A_CLK1[3]
M_A_CLK1#[3]
M_A_CKE0[3]

R288 *10K/F_4

+3V

R287 10K/F_4
R290 10K/F_4

C C

12

12
12

M_A_CKE1[3]
M_A_CAS#[3]
M_A_RAS#[3]
M_A_WE#[3]

SMB_RUN_CLK[7,14]
SMB_RUN_DAT[7,14]

M_A_ODT0[3]
M_A_ODT1[3]

M_A_DQSP[7:0][3]

M_A_DQSN[7:0][3]

CPU Bracket

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP7
M_A_DQSP6
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN7
M_A_DQSN6

JDIM1A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM0_H=8.0_RVS

ddr-ddrrk-20401-tp8d-204p-ruv

DGMK4000429

IC SOCKET DDR3 SO-DIMM(204P,H8.0,RVS)

black

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

PC2100 DDR3 SDRAM SO-DIMM

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

EZIW

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_A_DQ0
M_A_DQ1
M_A_DQ4
M_A_DQ2
M_A_DQ6
M_A_DQ5
M_A_DQ7

M_A_DQ3
M_A_DQ13
M_A_DQ14
M_A_DQ11
M_A_DQ8
M_A_DQ10
M_A_DQ9
M_A_DQ12
M_A_DQ15

M_A_DQ21

M_A_DQ20

M_A_DQ22

M_A_DQ23

M_A_DQ17

M_A_DQ16

M_A_DQ19

M_A_DQ18
M_A_DQ26
M_A_DQ25
M_A_DQ28
M_A_DQ27
M_A_DQ24
M_A_DQ31
M_A_DQ30
M_A_DQ29

M_A_DQ35

M_A_DQ37

M_A_DQ34

M_A_DQ39

M_A_DQ32

M_A_DQ38

M_A_DQ36

M_A_DQ33
M_A_DQ45
M_A_DQ46
M_A_DQ41
M_A_DQ47
M_A_DQ40
M_A_DQ44
M_A_DQ42
M_A_DQ43

M_A_DQ61

M_A_DQ62

M_A_DQ57

M_A_DQ63

M_A_DQ60

M_A_DQ56

M_A_DQ59

M_A_DQ58
M_A_DQ53
M_A_DQ54
M_A_DQ49
M_A_DQ50
M_A_DQ52
M_A_DQ51
M_A_DQ55
M_A_DQ48

M_A_DQ[63:0] [3]

+5V

EC39 *22U/6.3V/X5R_6
EC44 *22U/6.3V/X5R_6
EC51 *22U/6.3V/X5R_6
EC43 0.1U/16V/X7R_4

M_A_DRAMRST#[3]

+3V

EC20 *22U/6.3V/X5R_6
EC49 *22U/6.3V/X5R_6
EC29 *22U/6.3V/X5R_6
EC6 *22U/6.3V/X5R_6
EC55 *22U/6.3V/X5R_6

RESERVE FOR RF

+1.35V_S3

R289 10K/F_4

+3V

PM_EXTTS#0[14]

EC18 *22U/6.3V/X5R_6
EC16 *22U/6.3V/X5R_6
EC15 *22U/6.3V/X5R_6

+1.35V_S3

2.48A

+3V

1 2

PM_EXTTS#0

C124 *0.1U/16V/X7R_4

+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM0_H=8.0_RVS

ddr-ddrrk-20401-tp8d-204p-ruv

DGMK4000429

IC SOCKET DDR3 SO-DIMM(204P,H8.0,RVS)

black

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

NC3
NC4

(204P)

PC2100 DDR3 SDRAM SO-DIMM

VTT1
VTT2

GND1
GND2

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

207
208

203
204

205
206

+0.65V_DDR_VTT[14,35]

+0.65V_DDR_VTT

+3V[5,7,12,14,15,16,17,18,20,21,22,23,25,26,27,29,30,31,35,37,38,43,44,45]

+1.35V_S3[3,8,14,35]

13

B B

A A

For EMI RESERVE

+1.35V_S3

EC11 *120P/50V/NPO_4
EC12 *120P/50V/NPO_4
EC8 *120P/50V/NPO_4
EC10 120P/50V/NPO_4
EC14 *120P/50V/NPO_4
EC13 *120P/50V/NPO_4
EC9 *120P/50V/NPO_4

+0.65V_DDR_VTT

EC22 *120P/50V/NPO_4
EC48 *120P/50V/NPO_4
EC47 *68p/50V/COG_4

1 2

EC46 *47U/6.3V/X5R_8

+1.35V_S3

EC25 *120P/50V/NPO_4
EC19 *120P/50V/NPO_4
EC26 *120P/50V/NPO_4
EC24 *0.1U/16V/X7R_4
EC7 *0.1U/16V/X7R_4
EC23 *0.1U/16V/X7R_4
EC17 *0.1U/16V/X7R_4

1uF/10uF 4pcs on each side of connector

+1.35V_S3 +0.65V_DDR_VTT

C235 1U/6.3V/X5R_4
C253 1U/6.3V/X5R_4
C193 1U/6.3V/X5R_4
C178 1U/6.3V/X5R_4
C249 1U/6.3V/X5R_4
C212 1U/6.3V/X5R_4
C236 1U/6.3V/X5R_4
C211 1U/6.3V/X5R_4

C257 10U/6.3V/X5R_6
C206 10U/6.3V/X5R_6
C219 10U/6.3V/X5R_6
C263 10U/6.3V/X5R_6
C204 10U/6.3V/X5R_6
C246 10U/6.3V/X5R_6
C243 10U/6.3V/X5R_6
C227 10U/6.3V/X5R_6

C282 1U/6.3V/X5R_4
C281 1U/6.3V/X5R_4
C284 1U/6.3V/X5R_4
C285 1U/6.3V/X5R_4
C283 10U/6.3V/X5R_6
C286 *10U/6.3V/X5R_6

+SMDDR_VREF_DIMM

C265 *0.1U/16V/X7R_4
C262 *2.2U/10V/X5R_4

+SMDDR_VREF_DQ0

C79 *0.1U/16V/X7R_4
C80 *2.2U/10V/X5R_4

+3V

C280 0.1U/16V/X7R_4
C279 2.2U/10V/X5R_4

VREF DQ0 M1 SolutionPlace these Caps near So-Dimm0.

DDR_VTTREF[14,35]

DDR_VTTREF

+1.35V_S3

+

R94 *0_6

R271 *0_6

C430

*330u/2V_7343

12

C264

0.1U/16V/X7R_4

3.65K resistors close to DIMM

Near SO-DIMM

5

4

3

1 2

+1.35V_S3

12

+SMDDR_VREF_DIMM

12

R278 *24.9/F_4

2

+1.35V_S3

R274

3.65K/F_4

R272

3.65K/F_4

12

12

R101

3.65K/F_4

+SMDDR_VREF_DQ0DDR_VTTREF

R100

3.65K/F_4

12

R103 *2/F_6

C89

0.1U/16V/X7R_4
R98 *24.9/F_4

12

1 2

R275 *2/F_6

1 2

C94
*0.022U/25V_4

2 1

SMDDR_VREF_DQ0_M1 [3]

Need to check stuff the BOM 10/17

+SMDDR_VREF_DIMM_M1 [3]

C266
*0.022U/25V_4

2 1

HP Restricted Secret

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT: HP-Oahu

DDR3L DIMM0-RVS(8.0H)

DDR3L DIMM0-RVS(8.0H)

DDR3L DIMM0-RVS(8.0H)

1

13 49Thursday, October 27, 2016

13 49Thursday, October 27, 2016

13 49Thursday, October 27, 2016

2ACustom

2ACustom

2ACustom

5

M_B_A[15:0][3]

D D

M_B_BS#0[3]
M_B_BS#1[3]
M_B_BS#2[3]
M_B_CS#0[3]
M_B_CS#1[3]
M_B_CLK0[3]
M_B_CLK0#[3]
M_B_CLK1[3]
M_B_CLK1#[3]
M_B_CKE0[3]
M_B_CKE1[3]
M_B_CAS#[3]
M_B_RAS#[3]

R302 10K/F_4
R296 *10K/F_4

R303 10K/F_4

+3V

C C

B B

A A

12
12

12

1,35,37,38,43,44,45]

5

M_B_WE#[3]

SMB_RUN_CLK[7,13]
SMB_RUN_DAT[7,13]

M_B_ODT0[3]
M_B_ODT1[3]

M_B_DQSP[7:0][3]

M_B_DQSN[7:0][3]

+1.35V_S3[3,8,13,35]

+0.65V_DDR_VTT[13,35]

+3V

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1

M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSP4
M_B_DQSP2
M_B_DQSP3
M_B_DQSP0
M_B_DQSP1
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSN4
M_B_DQSN2
M_B_DQSN3
M_B_DQSN0
M_B_DQSN1

+1.35V_S3

C295 1U/6.3V/X5R_4
C316 1U/6.3V/X5R_4
C315 1U/6.3V/X5R_4
C306 1U/6.3V/X5R_4
C299 1U/6.3V/X5R_4
C313 1U/6.3V/X5R_4
C292 1U/6.3V/X5R_4
C308 1U/6.3V/X5R_4
C303 10U/6.3V/X5R_6

C293 10U/6.3V/X5R_6
C294 10U/6.3V/X5R_6

C312 10U/6.3V/X5R_6
C296 10U/6.3V/X5R_6

C317 10U/6.3V/X5R_6
C297 10U/6.3V/X5R_6

C314 10U/6.3V/X5R_6

4

JDIM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM0_H=8.0_RVS

ddr-ddrrk-20401-tp8d-204p-ruv

DGMK4000275

IC SOCKET DDR3 SODIMM(204P,H8.0,RVS)

white

1uF/10uF 4pcs on each side of connector

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

PC2100 DDR3 SDRAM SO-DIMM

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

Place these Caps near So-Dimm1.

+0.65V_DDR_VTT

C304 1U/6.3V/X5R_4
C301 1U/6.3V/X5R_4
C291 1U/6.3V/X5R_4
C298 1U/6.3V/X5R_4
C307 10U/6.3V/X5R_6

+3V

C318 0.1U/16V/X7R_4
C319 2.2U/10V/X5R_4

4

M_B_DQ46

5

M_B_DQ40

7

M_B_DQ41

15

M_B_DQ43

17

M_B_DQ45

4

M_B_DQ44

6

M_B_DQ47

16

M_B_DQ42

18

M_B_DQ49

21

M_B_DQ50

23

M_B_DQ55

33

M_B_DQ52

35

M_B_DQ51

22

M_B_DQ48

24

M_B_DQ54

34

M_B_DQ53

36

M_B_DQ56

39

M_B_DQ62

41

M_B_DQ63

51

M_B_DQ59

53

M_B_DQ60

40

M_B_DQ61

42

M_B_DQ57

50

M_B_DQ58

52

M_B_DQ32

57

M_B_DQ35

59

M_B_DQ34

67

M_B_DQ36

69

M_B_DQ33

56

M_B_DQ39

58

M_B_DQ37

68

M_B_DQ38

70

M_B_DQ22

129

M_B_DQ21

131

M_B_DQ23

141

M_B_DQ18

143

M_B_DQ17

130

M_B_DQ20

132

M_B_DQ16

140

M_B_DQ19

142

M_B_DQ26

147

M_B_DQ27

149

M_B_DQ24

157

M_B_DQ31

159

M_B_DQ29

146

M_B_DQ30

148

M_B_DQ28

158

M_B_DQ25

160

M_B_DQ5

163

M_B_DQ4

165

M_B_DQ7

175

M_B_DQ1

177

M_B_DQ0

164

M_B_DQ6

166

M_B_DQ2

174

M_B_DQ3

176

M_B_DQ13

181

M_B_DQ12

183

M_B_DQ10

191

M_B_DQ11

193

M_B_DQ15

180

M_B_DQ14

182

M_B_DQ9

192

M_B_DQ8

194

+SMDDR_VREF_DIMM2

C289 0.1U/16V/X7R_4
C290 2.2U/10V/X5R_4

+SMDDR_VREF_DQ1

C311 0.1U/16V/X7R_4
C310 2.2U/10V/X5R_4

3

M_B_DQ[63:0] [3]

3

PM_EXTTS#0[13]

M_B_DRAMRST#[3]

VREF DQ1 M1 Solution

DDR_VTTREF[13,35]

1 2

R293 *0_6

DDR_VTTREF

+1.35V_S3

12

12

R295

3.65K/F_4

+SMDDR_VREF_DIMM2DDR_VTTREF

R294

3.65K/F_4

2

+1.35V_S3

2.48A

+3V

PM_EXTTS#0

C305 *0.1U/16V/X7R_4

+SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM2

R297 *0_6

1 2

1 2

R292 *2/F_6

R291 *24.9/F_4

12

2

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM0_H=8.0_RVS

ddr-ddrrk-20401-tp8d-204p-ruv

DGMK4000275

IC SOCKET DDR3 SODIMM(204P,H8.0,RVS)

white

+1.35V_S3

12

R300

3.65K/F_4

+SMDDR_VREF_DQ1

12

R301

3.65K/F_4

R299 *24.9/F_4

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

NC3
NC4

(204P)

PC2100 DDR3 SDRAM SO-DIMM

VTT1
VTT2

GND1
GND2

R298 *2/F_6

12

C288
*0.022U/25V_4

2 1

1

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

207
208

203
204

205
206

1 2

+0.65V_DDR_VTT

C309
*0.022U/25V_4

2 1

+SMDDR_VREF_DIMM_M2 [3]

SMDDR_VREF_DQ0_M2 [3]

14

HP Restricted Secret

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT: HP-Oahu

DDR3L DIMM1-RVS(8.0H)

DDR3L DIMM1-RVS(8.0H)

DDR3L DIMM1-RVS(8.0H)

1

14 49Thursday, October 27, 2016

14 49Thursday, October 27, 2016

14 49Thursday, October 27, 2016

1ACustom

1ACustom

1ACustom

1

2

3

4

5

6

7

8

+1.05V_VGA

Near GPU

C100 EV@22U/6.3V/X5R_6
C77 *EV@22U/6.3V/X5R_6
C73 *EV@10U/6.3V/X5R_6
C76 EV@10u/6.3V/X5R_6
C95 EV@4.7U/6.3V/X5R_6

12

C96 EV@1U/6.3V/X5R_4

12

A A

C87 *EV@1U/6.3V/X5R_4

Under GPU

*
*
*
*
*

*
*

PEX_IOVDD + PEX_IOVDDQ = 1.042A

+1.05V_VGA

PEX_PLL_HVDD +
PEX_SVDD_3V3 = 143mA

B B

C C

+1.05V_VGA

Near GPU

C115 EV@1U/6.3V/X5R_4
C114 EV@0.1U/16V/X7R_4

Under GPU

D D

C122 EV@22U/6.3V/X5R_6
C131 *EV@22U/6.3V/X5R_6
C88 *EV@10U/6.3V/X5R_6
C102 EV@10U/6.3VX5R_6
C72 EV@4.7U/6.3V/X5R_6

Near GPU

12

C78 EV@1U/6.3V/X5R_4

12

C74 *EV@1U/6.3V/X5R_4

Under GPU

1 2

C125 EV@0.1U/16V/X7R_4

12

C129 EV@4.7U/6.3V/X5R_6

12

C132 EV@4.7U/6.3V/X5R_6

Near GPU

VGA_VDD_SEN[44]

VGA_GND_SEN[44]

1 2

1 2

R120 EV@0_6

C116 EV@4.7U/6.3V/X5R_6

1 2

12

PEX_PLLVDD = 130mA

R133 EV@10K/F_4

R92 EV@2.49K/F_4

12

1 2

R401*EV@200/F_4

*

*
*

*

PEX_TSTCLK

*

PEX_TSTCLK#

PEX_PLLVDD

*

*

*
*
*
*
*

*
*

+3.3V_VGA

*
*
*

TESTMODE

PEX_TERMP

AA22
AB23
AC24
AD25
AE26
AE27

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AF22
AE22

AA14
AA15

AF25

AA8
AA9

AB8

F2

F1

AD9

COMMON bga595-nvidia-n13p-gv2-s-a2

U16A

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

NC FOR GF119

PEX_PLL_HVDD
PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_PLLVDD
PEX_PLLVDD

TESTMODE

PEX_TERMP

*

1/14 PCI_EXPRESS

NC FOR GM108NC FOR GF117/GK208/GM108

PEX_WAKE_NC

PEX_RST

PEX_CLKREQ

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

AB6

AC7
AC6
AE8

AD8
AC9

AB9
AG6

AG7
AB10

AC10
AF7

AE7
AD11

AC11
AE9

AF9
AC12

AB12
AG9

AG10
AB13

AC13
AF10

AE10
AD14

AC14
AE12

AF12
AC15

AB15
AG12

AG13
AB16

AC16
AF13

AE13
AD17

AC17
AE15

AF15
AC18

AB18
AG15

AG16
AB19

AC19
AF16

AE16
AD20

AC20
AE18

AF18
AC21

AB21
AG18

AG19
AD23

AE23
AF19

AE19
AF24

AE24
AE21

AF21
AG24

AG25
AG21

AG22

C158 *EVG@0.1U/16V/X7R_4

VGA_RST#

R182 EV@0_4

PEX_CLKREQ#

R482 EV@10K/F_4

PEG_RXP0_C

C153 EV@0.1U/16V/X7R_4

PEG_RXN0_C

C154 EV@0.1U/16V/X7R_4

PEG_TXP0_C

C412 EV@0.1U/16V/X7R_4

PEG_TXN0_C

C410 EV@0.1U/16V/X7R_4

PEG_RXP1_C

C151 EV@0.1U/16V/X7R_4

PEG_RXN1_C

C152 EV@0.1U/16V/X7R_4

PEG_TXP1_C

C414 EV@0.1U/16V/X7R_4

PEG_TXN1_C

C413 EV@0.1U/16V/X7R_4

PEG_RXP2_C

C134 EV@0.1U/16V/X7R_4

PEG_RXN2_C

C141 EV@0.1U/16V/X7R_4

PEG_TXP2_C

C405 EV@0.1U/16V/X7R_4

PEG_TXN2_C

C407 EV@0.1U/16V/X7R_4

PEG_RXP3_C

C135 EV@0.1U/16V/X7R_4

PEG_RXN3_C

C142 EV@0.1U/16V/X7R_4

PEG_TXP3_C

C403 EV@0.1U/16V/X7R_4

PEG_TXN3_C

C402 EV@0.1U/16V/X7R_4

GPU_PEX_RST_HOLD#[18]

1 2

12

1 2

DGPU_HOLD_RST#[20]

*
*

*
*

*
*

*
*

*
*

*
*

*
*

*
*

*
*

PLTRST#[7,11,12,25,28,30,32]

For N16V-GM no GC6 2.0 support,
can bypass U22 then stuff R445

SYS_PEX_RST

N16V stuff it, not support GC6 2.0

*

PEGX_RST# [18]
+3.3V_VGA
CLK_GFX_P [4]

CLK_GFX_N [4]

PEG_RXP0 [4]
PEG_RXN0 [4]

PEG_TXP0 [4]
PEG_TXN0 [4]

PEG_RXP1 [4]
PEG_RXN1 [4]

PEG_TXP1 [4]
PEG_TXN1 [4]

For APL

PEG_RXP2 [4]
PEG_RXN2 [4]

PEG_TXP2 [4]
PEG_TXN2 [4]

PEG_RXP3 [4]
PEG_RXN3 [4]

PEG_TXP3 [4]
PEG_TXN3 [4]

+3V

2
1

3 5

EV@MC74VHC1G08DFT2G

*EVG@MC74VHC1G08DFT2G

SYS_PEX_RST_MON#
GPU_PEX_RST_HOLD#

R211 *EVNG@0_4_S

12

NVDD = 32.22 ~ 26.66 A

C137 EV@1U/6.3V/X5R_4
C136 EV@1U/6.3V/X5R_4
C139 EV@1U/6.3V/X5R_4

C138 EV@1U/6.3V/X5R_4
C106 EV@4.7U/6.3V/X5R_6
C123 EV@4.7U/6.3V/X5R_6
C162 EV@4.7U/6.3V/X5R_6
C127 EV@4.7U/6.3V/X5R_6
C120 EV@4.7U/6.3V/X5R_6
C101 EV@4.7U/6.3V/X5R_6
C98 EV@4.7U/6.3V/X5R_6
C111 EV@4.7U/6.3V/X5R_6
C110 EV@4.7U/6.3V/X5R_6
C112 EV@4.7U/6.3V/X5R_6

C218

EV@330u_2.5V_3528

C237 EV@22U/6.3V/X5R_6

C194 EV@47u/6.3V/X5R_8

C173 EV@4.7U/6.3V/X5R_6

C185 EV@4.7U/6.3V/X5R_6

C170 EV@4.7U/6.3V/X5R_6

C177 EV@4.7U/6.3V/X5R_6

C181 EV@4.7U/6.3V/X5R_6

C418
EV@0.1U/16V/X7R_4

1 2

4

U19

U10

*

2
1

3 5

*

12

*

PEGX_RST#

*

12

R217
EV@100K/F_4

1 2

+VGA_CORE

*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*

*
*
*
*
*

*

R499
*EVG@100K/F_4

1 2

*

K10
K12
K14
K16
K18

L11
L13
L15

L17
M10
M12
M14
M16
M18

N11

N13

N15

N17

P10

P12

P14

P16

P18

R11

R13

R15

R17

T10

T12

T14

T16

T18

U11

U13

U15

U17

V10

V12

V14

V16

V18

*

Under GPU

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

+

1 2

Near GPU

R490 *EVG@0_4

*

C189
*EVG@0.1U/16V/X7R_4

1 2

4

+1.05V_VGA [16,17,45]
+3.3V_VGA [17,18,30,44,45]
+3V [5,7,12,13,14,16,17,18,20,21,22,23,25,26,27,29,30,31,35,37,38,43,44,45]
+3V_MAIN [17,18]
+VGA_CORE [44,45]

U16E

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SYS_PEX_RST_MON#SYS_PEX_RST

11/14 NVVDD

*

PEX_CLKREQ#

bga595-nvidia-n13p-gv2-s-a2COMMON

*

U16C

AD10

AD7

1

F11

TP6

*

V5

*

V6

G1
G2
G3
G4
G5
G6
G7

V1
V2

W1
W2
W3
W4

SYS_PEX_RST_MON# [18]

+3.3V_VGA+3V

12

R250
EV@10K/F_4

PEX_CLKREQ#_R

3

Q22
EV@2N7002K

2

1

COMMON bga595-nvidia-n13p-gv2-s-a2

14/14 XVDD/VDD33

NC
NC

GM108

3V3_AON
3V3_AON

3V3AUX_NC

FERMI_RSVD1_NC
FERMI_RSVD2_NC

CONFIGURABLE
POWER CHANNELS
* nc on substrate

XPWR_G1
XPWR_G2
XPWR_G3
XPWR_G4
XPWR_G5
XPWR_G6
XPWR_G7

XPWR_V1
XPWR_V2

XPWR_W1
XPWR_W2
XPWR_W3
XPWR_W4

*

2

*

3

1

VDD33
VDD33
VDD33
VDD33

Q23
EV@2N7002K

VDD33 = 56mA

*

G8
G9
G10
G12

Under GPU

C118 EV@0.1U/16V/X7R_4

C147 EV@4.7U/6.3V/X5R_6
C157 EV@1U/6.3V/X5R_4

PCIE_CLKREQ_VGA# [4]

*

15

+3V_MAIN

1 2

C155 EV@4.7U/6.3V/X5R_6

1 2

C156 EV@1U/6.3V/X5R_4

1 2

C140 EV@0.1U/16V/X7R_4

1 2

C143 EV@0.1U/16V/X7R_4

+3.3V_VGA

1 2

1 2
1 2

Under GPU

Near GPU

*

*
*

*
*

*
*

HP Restricted Secret

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT: HP-Oahu

PROJECT: HP-Oahu

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

PROJECT: HP-Oahu

N16V-GMR (PCIE I/F) /NVDD

N16V-GMR (PCIE I/F) /NVDD

Thursday, October 27, 2016 15 49

Thursday, October 27, 2016 15 49

Thursday, October 27, 2016 15 49

7

N16V-GMR (PCIE I/F) /NVDD

8

1A

1A

1A