Quanta LX3, Pavilion dv6, LX5 (Huror River) Schematic

Dis.

RED":N"UVCEM"WR

NC[GT"3"<"VQR

A A

NC[GT"4"<"UIPF NC[GT"5"<"KP3*Jkij+ NC[GT"6"<"KP4*Nqy+ NC[GT"7"<"UXEE NC[GT"8"<"KP5*Jkij+ NC[GT"9"<"UIPF NC[GT":"<"DQV

B B

DDR III SMDDR_VTERM and GPU+1.5V/+1.0V(RT8207G)

C C

BATTERY SELECTO R (Wireless LAN

SYSTEM CHARGER(P2806)

PAGE 43

PAGE 42

PAGE 44

SYSTEM POWER RT8206B

PAGE 38

1.05V_VTT and GPU

+1.8V/+3V(VT358)

VCCP +1.05V/+1.8V (RT 8204)

PAGE 39

PAGE 41

D D

VGACORE/VDDCI(RT8208/RT9018A)

PAGE 42

CPU CORE (ADP3212)

PAGE 40

DDR3-SODIMM1

DDR3-SODIMM2

UCVC"JFF"3UV

UCVC"JFF"3UVUCVC"JFF"3UV

PAGE 34

UCVC"/"4pf"JFF

UCVC"/"EF/TQO

G/UCVC1WUD"Rqtv

Ceegngtqogvgt JR524FNVT:

URK"TQO

NZ517"*Jwtqp"Tkxgt+"DNQEM"FKCITCO

Lcem"vq Uwd/Yqqhgt

PAGE 31

VRAM GDDR5*8

54,54"qt"86,38

PAGE 20-23

ATI Capliano Pro (128bit)

ATI Robson M2 (128bit)

(FCBGA) 962p 29X29mm

PAGE 15-19

USB2.0 Port

PAGE 32

LAN

Realtek PCIE-LAN

RTL8111(E) GigaLAN

PAGE 33

RJ45

PAGE 33

27MHz

BlueTooth

25MHz

PAGE 32

LVDS CRT HDMI

HDMI CON (1920*1200)

iGPU HDMI LVDS CRT

Webcam w/ Mic

PAGE 32

half size mini-card

Shirley Peak

802.11a/b/g/n)

PAGE 36

PAGE 13

PAGE 14

PAGE 34

PAGE 32

PAGE 30

PAGE 7

Mg{dqctf

Nkijv"Ugpuqt

GMT G991P1U

U[UVGO"HCP

DKQU *U[UVGO"DKQU+

UCVC2"522OD1u

*3+

UODWU

Vqwej"Rcf

PAGE 37

PAGE 36

PAGE 32

DDR3 1066,1333 MT/s

DMI*4

UCVC2"522OD1u

32.768KHz

FOKE

PAGE 30

LPC

ENE KBC

KB3926 D2

PAGE 35

Intel Sandy

CPU 45Watt

35Watt

4 Core

( rPGA 989 )

PAGE 3-6

BCLK133M DMI100M DP120M

PCH 3.5Watt

Platform Controller Hub

PAGE 7-12

Azalia

Cwfkq"Lcem" *Jgcfrjqpg1OKE+

PAGE 30

32.768KHz

PCI-E 100M

Audio

KFV;4JF:2

PAGE 29

Lcem"vq Urgcmgt

PAGE 30

REK/Gzrtguu Igp4"Z"38

PCH CLK 27M

USB2.0 48M

Fingerprint

PAGE 32

Cornkhkgt

VRC5333F3

PAGE 27

Display

Owz

PAGE 24

Card Reader

Realtek RTS5138

PAGE 24

5-in-1 flash media slot(SD/MS/MMC/ XD/MSP)

PAGE 24

PD7

LCD CONN for dual channel (15.6",17")

Fwcn"Ejcppgn"NXFU

CRT

USB2.0 Port

POWER LED HDD LED

8,9

Form 17"

PAGE 32

USB2.0 Port Form 15"

PAGE 32

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

PAGE 25

PAGE 26

USB2.0 Port POWER LED HDD LED Form 15"

PAGE 32

Touchscreen

PAGE 32

BLOCK DIAGRAM

147Friday, October 01, 2010

A A

4/7 DB del for PDC update.

B B

C C

D D

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

PD7

Date: Sheet

Clock Gen(9LRS3197)/HOLES

247Friday, October 01, 2010

Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG)

CPU_DRAMRST#

R23

4.99K/F_4

U31A

DMI_TXN0[7] DMI_TXN1[7] DMI_TXN2[7] DMI_TXN3[7]

D D

C C

B B

DMI_TXP0[7] DMI_TXP1[7] DMI_TXP2[7] DMI_TXP3[7]

DMI_RXN0[7] DMI_RXN1[7] DMI_RXN2[7] DMI_RXN3[7]

DMI_RXP0[7] DMI_RXP1[7] DMI_RXP2[7] DMI_RXP3[7]

FDI_TXN0[7] FDI_TXN1[7] FDI_TXN2[7] FDI_TXN3[7] FDI_TXN4[7] FDI_TXN5[7] FDI_TXN6[7] FDI_TXN7[7]

FDI_TXP0[7] FDI_TXP1[7] FDI_TXP2[7] FDI_TXP3[7] FDI_TXP4[7] FDI_TXP5[7] FDI_TXP6[7] FDI_TXP7[7]

FDI_FSYNC0[7] FDI_FSYNC1[7]

FDI_INT[7]

FDI_LSYNC0[7] FDI_LSYNC1[7]

eDP_COMP INT_eDP_HPD_Q

eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. eDP_COMP connect to P IN A17 W:12mils/S:15mils/L: 500mi ls.

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Brid ge_rPGA_Rev0 p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15

C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15

PEG_COMP connect t o PIN H22&J22 W:4mils/S:15mils/L: 500mils. PEG_COMP connect t o PIN J21 W:12mils/S:15mils/L: 500mils.

H_SNB_IVB#[8]

SNB_IVB# N.A at SNB EDS #27637 0.7v1

Placement close to EC.

R99 43_4R99 43_4

R141 56.2/F_4R141 56.2/F_4 R136 140/F_4R136 140/F_4

R523 *0_4/SR523 *0_4/S

R503 *0_4/SR503 *0_4/S

R514 *0_4/SR514 *0_4/ R513 10K_4R513 10K_4

PEG_RX[0..15] [15]

EC_PECI[35]

H_PROCHOT#[35,40]

PM_THRMTRIP#[10,35]

PM_SYNC[7]

H_PWRGOOD[10]

3/26 DB del for DG update.

8/16 PV Modify

CPU RESET#

PLTRST#[9,33,35,36,37]

2 1

SM_DRAMPWROK Processor Input. DDR3 DRAM RESET

3/26 DB del for DG update.

+1.05V_VTT

U37

GND3OUT IN

74LVC1G07GW

R529 *1.5K/F_4R529 *1.5K/F_4

+3VS5 +3VS5

CPU_PLTRST# CPU_PLTRST#_RCPU_PLTRST#_R

+3VS5

VCC5NC

8/6 PV NA.

R16

R16 *10K_4

*10K_4

PM_DRAM_PWRGD_PU

R19

R19 *0_4

*0_4

PM_DRAM_PWRGD [7]

R9 *0_4/SR9 *0_4/S

C685

0.1U/10V_4

R527 75_4R527 75_4 R524 43_4R524 43_4

1 2

IN GND3OUT

*74LVC1G07GW

PM_DRAM_PWRGD_C

R10

10/13 MV Modify.

*3K/F_4

TP12TP12

TP11TP11

VCC5NC

SKTOCC#

TP_CATERR#

H_PECI

H_PROCHOT#_R

PM_THRMTRIP#_R

PM_SYNC_R

H_PWRGOOD_R

PM_DRAM_PWRGD_R

R521

R521 *750/F_4

*750/F_4

4/20 DB add.4/20 DB add.

C24

C24 *0.1U/10V_4

*0.1U/10V_4

PM_DRAM_PWRGD_C

Q2 *2N7002Q2*2N7002

6/4 DB2 Modify.

U31B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

+1.5V_CPU

R4 200/F_4R4200/F_4

R15 130/F_4R15 130/F_4

R13

6/4 DB2 Modify.

MAIN_ONG [5,45]

*39_4

MISCTHERMALPWR MANAGEMENT

PM_DRAM_PWRGD_R

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

DDR3_DRAMRST#[13,14]

DRAMRST_CNTRL_PCH[9]

3/26 DB for H/W modify.

A28 A27

A16 A15

AK1 A5 A4

SM_RCOMP[0] W:20mils/S:20mils/L: 500mils, SM_RCOMP[1] W:20mils/S:20mils/L: 500mils, SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

+1.5VSUS

+1.05V_VTT [5,11,39,40] +1.5V_CPU [5] +3VS5 [7,8,9,10,11,45] +3V [7,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47]

CLK_CPU_BCLKP [9]PEG_RX#[0..15] [15] CLK_CPU_BCLKN [9]

CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R

CPU_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO

XDP_DBRST#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

R356 26.1/F_4R356 26.1/F_4 R355 200/F_4R355 200/F_4

R501 *1K_4R501 *1K_4

R32 1K_4R32 1K_4

R33 1K_4R33 1K_4

CPU_DRAMRST#_R

R24 *0_4/SR24 *0_4/S

TP52TP52 TP15TP15

TP50TP50 TP47TP47 TP46TP46

TP14TP14 TP42TP42

XDP_DBRST# [7]

TP49TP49 TP45TP45 TP53TP53 TP43TP43 TP41TP41 TP44TP44 TP51TP51 TP48TP48

R29 *0_4R29 *0_4

C23

0.047U/10V_4

CPU XDP

+3V

2N7002Q42N7002

FDI disable (DIS only stuff)

8/17: PV Modify.

R436 0_4R436 0_4 R422 0_4R422 0_4

A A

R441 0_4R441 0_4

R427 1K_4R427 1K_4 R447 1K_4R447 1K_4

FDI_FSYNC can gang all these 4 signals togeth er and tie them with only one 1K resistor to GND (DG V0.5 Ch2.2.9).

FDI_INT FDI_FSYNC0

FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

PEG x16 disable (UMA only remove)

PEG_TX[0..15][15] PEG_TX#[0..15][15]

C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15

C690 0.1U/10V_4C690 0.1U/10V_4 C686 0.1U/10V_4C686 0.1U/10V_4 C682 0.1U/10V_4C682 0.1U/10V_4 C676 0.1U/10V_4C676 0.1U/10V_4 C671 0.1U/10V_4C671 0.1U/10V_4 C668 0.1U/10V_4C668 0.1U/10V_4 C658 0.1U/10V_4C658 0.1U/10V_4 C662 0.1U/10V_4C662 0.1U/10V_4 C650 0.1U/10V_4C650 0.1U/10V_4 C640 0.1U/10V_4C640 0.1U/10V_4 C638 0.1U/10V_4C638 0.1U/10V_4 C632 0.1U/10V_4C632 0.1U/10V_4 C627 0.1U/10V_4C627 0.1U/10V_4 C626 0.1U/10V_4C626 0.1U/10V_4 C619 0.1U/10V_4C619 0.1U/10V_4 C599 0.1U/10V_4C599 0.1U/10V_4

0.22uF AC coupling Caps for PCIE GEN1/2/3

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15

C694 0.1U/10V_4C694 0.1U/10V_4 C689 0.1U/10V_4C689 0.1U/10V_4 C684 0.1U/10V_4C684 0.1U/10V_4 C681 0.1U/10V_4C681 0.1U/10V_4 C675 0.1U/10V_4C675 0.1U/10V_4 C674 0.1U/10V_4C674 0.1U/10V_4 C664 0.1U/10V_4C664 0.1U/10V_4 C665 0.1U/10V_4C665 0.1U/10V_4 C661 0.1U/10V_4C661 0.1U/10V_4 C646 0.1U/10V_4C646 0.1U/10V_4 C642 0.1U/10V_4C642 0.1U/10V_4 C636 0.1U/10V_4C636 0.1U/10V_4 C633 0.1U/10V_4C633 0.1U/10V_4 C631 0.1U/10V_4C631 0.1U/10V_4 C621 0.1U/10V_4C621 0.1U/10V_4 C612 0.1U/10V_4C612 0.1U/10V_4

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

0.22uF AC coupling Caps for PCIE GEN1/2/3

Embedded Display P LL Clock

8/17: PV Modify.

CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R

SG/UMA

Ra Rb Rc NCDIS Stuff

RP12

3 1

*0_4P2R_4

R365 0_4R365 0_4

R364 0_4R364 0_4

Stuff Stuff NC

3/26 DB change Part reference.

CLK_DPLL_SSCLKP [9]

CLK_DPLL_SSCLKN [9]

DP & PEG Compensation

+1.05V_VTT

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

+1.05V_VTT

PEG_ICOMPI and RCOMPO signals should be routed within 500 mils typical impedance = 43 mohms PEG_ICOMPO signals should be routed within 500 mils typical impedance = 14.5 mohms

R360 10K_4R360 10K_4

R361 24.9/F_4R361 24.9/F_4

R58 24.9/F_4R58 24.9/F_4

INT_eDP_HPD_Q

eDP_COMP

PEG_COMP

PD7

Processor pull-up (CPU)

H_PROCHOT# XDP_TDO XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST#

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

Date: Sheet

R145 62_4R145 62_4 R534 51_4R534 51_4 R535 51_4R535 51_4 R156 51_4R156 51_4 R158 *51_4R158 *51_4 R162 51_4R162 51_4 R526 51_4R526 51_4

SNB 1/4 (PCIE&DMI&FDI)

+1.05V_VTT

347Wednesday, October 13, 2010

Sandy Bridge Processor (DDR3)

U31C

D D

M_A_DQ[63:0][13]

C C

B B

M_A_BS#0[13] M_A_BS#1[13] M_A_BS#2[13]

M_A_CAS#[13] M_A_RAS#[13] M_A_WE#[13]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

AE8 AD9 AF9

F10

C5 D5 D3 D2 D6 C6 C2 C3

F7 G8 G7

K2 M8

N7 M9

N9 M7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0]

SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_CLKP0 [13] M_A_CLKN0 [13] M_A_CKE0 [13]

M_A_CLKP1 [13] M_A_CLKN1 [13] M_A_CKE1 [13]

M_A_CS#0 [13] M_A_CS#1 [13]

M_A_ODT0 [13] M_A_ODT1 [13]

M_A_DQSN[7:0] [13]

M_A_DQSP[7:0] [13]

M_A_A[15:0] [13]

M_B_DQ[63:0][14]

M_B_BS#0[14] M_B_BS#1[14] M_B_BS#2[14]

M_B_CAS#[14] M_B_RAS#[14] M_B_WE#[14]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9

AA7

AA10

AB8

AB9

J10

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2

J7 J8

K8 K7 M5 N4 N2 N1 M4 N5 M2 M1

U31D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

M_B_DQSN0

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_CLKP0 [14] M_B_CLKN0 [14] M_B_CKE0 [14]

M_B_CLKP1 [14] M_B_CLKN1 [14] M_B_CKE1 [14]

M_B_CS#0 [14] M_B_CS#1 [14]

M_B_ODT0 [14] M_B_ODT1 [14]

M_B_DQSN[7:0] [14]

M_B_DQSP[7:0] [14]

M_B_A[15:0] [14]

Sandy Brid ge_rPGA_Rev0 p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

A A

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Sandy Bridge_r PG A_Re v0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

PD7

Date: Sheet

SNB 2/4 (DDR3 I/F)

447Wednesday, October 13, 2010

Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER)

9/29 MV for Power Mod ify.

U31G

U31F

SNB: 55A

C596

D D

22U/6.3V_8

C574

C574 22U/6.3V_8

22U/6.3V_8

C577

C577 22U/6.3V_8

22U/6.3V_8

C179

C179 22U/6.3V_8

22U/6.3V_8

C C

C67

C67 22U/6.3V_8

22U/6.3V_8

C126

C126 22U/6.3V_8

22U/6.3V_8

C122

C122 22U/6.3V_8

22U/6.3V_8

C643

C643 *22U/6.3VS_8

*22U/6.3VS_8

B B

C576

C576 22U/6.3V_8

22U/6.3V_8

C477

C477 22U/6.3VS_8

22U/6.3VS_8

22uF_8 x8 Socket TOP cavity 22uF_8 x10 Socket BOT cavi ty 22uF_8 x8 Socket TOP edge 470uF_7343 x4

C623

C623 22U/6.3V_8

22U/6.3V_8

C564

C564 22U/6.3V_8

22U/6.3V_8

C575

C575 22U/6.3V_8

22U/6.3V_8

C95

C95 22U/6.3V_8

22U/6.3V_8

C635

C635 *22U/6.3VS_8

*22U/6.3VS_8

C106

C106 22U/6.3V_8

22U/6.3V_8

C99

C99 22U/6.3V_8

22U/6.3V_8

C672

C672 *22U/6.3VS_8

*22U/6.3VS_8

C617

C617 22U/6.3V_8

22U/6.3V_8

C557

C557 22U/6.3VS_8

22U/6.3VS_8

+VCC_CORE

C586

C586 22U/6.3V_8

22U/6.3V_8

C555

C555 22U/6.3V_8

22U/6.3V_8

C132

C132 22U/6.3V_8

22U/6.3V_8

C587

C587 22U/6.3V_8

22U/6.3V_8

C85

C85 22U/6.3V_8

22U/6.3V_8

C147

C147 22U/6.3V_8

22U/6.3V_8

C76

C76 22U/6.3V_8

22U/6.3V_8

C558

C558 22U/6.3V_8

22U/6.3V_8

C110

C110 22U/6.3V_8

22U/6.3V_8

C660

C660 *22U/6.3VS_8

*22U/6.3VS_8

3/26 DB change 10U FP to 0805.

A A

+VCC_CORE [40] +VCC_GFX [40] +VCCSA [41] +1.05V_VTT [3,11,39,40] +1.5V_CPU [3] +1.5V_CPU [3] +1.5VSUS [3,11,13,14,43,45]

U31F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32

PEG AND DDR

VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

CORE SUPPLY

VCCIO_SENSE

SENSE LINES SVID

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VSSIO_SENSE

AH13

SNB: 8.5A

AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

3/26 DB Modify.

AJ35 AJ34

B10 A10

C71

C71 22U/6.3VS_8

22U/6.3VS_8

C131

C131 22U/6.3VS_8

22U/6.3VS_8

C70

C70 *22U/6.3VS_8

*22U/6.3VS_8

C597

C597 *22U/6.3VS_8

*22U/6.3VS_8

C547

C547 22U/6.3VS_8

22U/6.3VS_8

C68

C68 *22U/6.3VS_8

*22U/6.3VS_8

C573

C573 *22U/6.3VS_8

*22U/6.3VS_8

22uF_8 x7 Socket TOP cavity 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2

+1.05V_VTT_40

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R59 *0_4/SR59 *0_4/S

R137 100_4R137 100_4

R135 100_4R135 100_4

VSSP_SENSE

Trace Route to Po wer IC area.

+1.05V_VTT

C69

C69 22U/6.3VS_8

22U/6.3VS_8

C86

C86 22U/6.3VS_8

22U/6.3VS_8

C105

C105 22U/6.3VS_8

22U/6.3VS_8

C94

C94 *22U/6.3VS_8

*22U/6.3VS_8

5/14 modify

C31

*22U/6.3VS_8

C563

C563 22U/6.3VS_8

22U/6.3VS_8

C552

C552 22U/6.3VS_8

22U/6.3VS_8

+1.05V_VTT

+VCC_CORE

VCC_SENSE [40,46] VSS_SENSE [40,46]

VCCP_SENSE [39]

C541

C541 22U/6.3VS_8

22U/6.3VS_8

C176

C176 22U/6.3VS_8

22U/6.3VS_8

C585

C585 22U/6.3VS_8

22U/6.3VS_8

C30

C30 *22U/6.3VS_8

*22U/6.3VS_8

C149

C149 *22U/6.3VS_8

*22U/6.3VS_8

C120

C120 *22U/6.3VS_8

*22U/6.3VS_8

C63

C63 22U/6.3VS_8

22U/6.3VS_8

5/4: add C8260/ C8322

6/7 DB2 Modify

TP37TP37

22uF_8 x2 Socket TOP cavity 22uF_8 x2 Socket BOT cavi ty 22uF_8 x4 Socket TOP edge 22uF_8 x4 Socket BOT edge 470uF_7343 x2

9/26: MV Modify

+VCC_GFX

8/17: PV Modify

+1.8V

SNB: 1.5A

C492

C495

10U/6.3V_6

1U/6.3V_4

330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge.

3/26 DB change 10U FP to 0805.

Layout note: need routing together and ALERT need between CLK and DATA.

H_CPU_SVIDCLK

Place PU resistor close to CPU

H_CPU_SVIDDAT

Place PU resistor close to CP U

H_CPU_SVIDALRT#

SNB: 21.5A

C130

R522 0_4R522 0_4

C130 *22U/6.3V_8

*22U/6.3V_8

C177

C177 *22U/6.3V_8

*22U/6.3V_8

C590

C590 *22U/6.3V_8

*22U/6.3V_8

C123

C123 *22U/6.3V_8

*22U/6.3V_8

C121

C121 *22U/6.3V_8

*22U/6.3V_8

C598

C598 *22U/6.3V_8

*22U/6.3V_8

C591

C591 *22U/6.3V_8

*22U/6.3V_8

C145

C145 *22U/6.3V_8

*22U/6.3V_8

C143

C143 *22U/6.3V_8

*22U/6.3V_8

C178

C178 *22U/6.3V_8

*22U/6.3V_8

C589

C589 *22U/6.3V_8

*22U/6.3V_8

C133

C133 *22U/6.3V_8

*22U/6.3V_8

DISNCSG/UMA

Ra Stuff

C494

C494 1U/6.3V_4

1U/6.3V_4

3/26 DB Modify.

+1.05V_VTT +1.05V_VTT

C921 *0.1U/10V_4C921 *0.1U/10V_4

+1.05V_VTT

C486

330U/2V_7343

R108

R108 130/F_4

130/F_4

3/26 DB Modify.

R96 75_4R96 75_4

R89 43_4R89 43_4

U31G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

VCCPLL1

VCCPLL2

VCCPLL3

Sandy Bridge_r PG A_Re v0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Place PU resistor close to VR

R120 *54.9/F_4R120 *54.9/F_4

Place PU resistor

R100

close to VR

*130/F_4

5/12: modify

10/01: modify

3/26 DB Modify.

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

1.8V RAIL

+1.5V_CPU +1.5V

SVID CLK

+1.05V_VTT

VR_SVID_CLK [40]

SVID DATA

4/27: layout modify

VR_SVID_DATA [40]

SVID ALERT

VR_SVID_ALERT# [40]

VAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

VCCSA_VID1

R747 0_8R747 0_8

5/13: modify

3/26 DB Modify.

AK35 AK34

R130 *100_4R130 *100_4

R124 100_4R124 100_4

DISNCSG/UMA

VCC_AXG_SENSE [40,46] VSS_AXG_SENSE [40,46]

R130 Stuff

CAD Note: +VDDR_REF_CPU should have 10 mil trace width

R175 *0_8R175 *0_8

Q13

Q13 2N7002

2N7002

MAIND

SNB: 5A

C109

C109 10U/6.3V_8

10U/6.3V_8

5/14 modify

C89

C89 10U/6.3V_6

10U/6.3V_6

4/27: layout modify

C174

C174 10U/6.3V_6

10U/6.3V_6

C127

C127 10U/6.3V_6

10U/6.3V_6

330uF x1, 10uF_8 x6 Socket BO T edge.

3/26 DB change 10U FP to 0805.

AL1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

+VDDR_REF_CPU

R170

R170 100K_4

100K_4

SNB: 6A

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

C549

C549 10U/6.3V_8

10U/6.3V_8

VCCUSA_SENSE_R

H_FC_C22

C482

C482 10U/6.3V_8

10U/6.3V_8

330uF x1, 10uF_8 x1 Socket BO T edge,

F_8 x2 Socket BOT cavity.

10u

3/26 DB change 10U FP to 0805.

R358 *0_4/SR358 *0_4/S

R363 10K_4R363 10K_4

R357 10K_4R357 10K_4

5/11: Add for intel CRB

40mile routing

JP1

JP1 *SOLDERJUMPER-2

*SOLDERJUMPER-2

Q39

Q39 AON7410

AON7410

5 2

MAIND

PD7

Custom

+1.5V_CPU+1.5VSUS

220_8R2220_8

3/26 DB add for Intel.

C18

C18 *470P/50V_4

*470P/50V_4

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Date: Sheet

SNB 3/4 (POWER)

Placement close to CPU.

2N7002Q12N7002

+VCC_GFX

DDR_VTTREF [13,14,43]

MAIND [45]

+1.5V_CPU

C155

C112

10U/6.3V_6

5/23: na

C714

C714 *330U_2.5V_5.0x5.9_ESR10m

*330U_2.5V_5.0x5.9_ESR10m

+VCCSA

C545

C485

10U/6.3V_8

*10U/6.3V_8

VCCUSA_SENSE [41]

VCCSA_SEL [41]

+1.5VSUS

C710 0.1U/10V_4C710 0.1U/10V_4 C712 0.1U/10V_4C712 0.1U/10V_4 C715 0.1U/10V_4C715 0.1U/10V_4 C699 0.1U/10V_4C699 0.1U/10V_4

MAIN_ONG [3,45]

5/6: modify

CPU VDDQ

547Wednesday, October 13, 2010

Sandy Bridge Processor (GND)

U31H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

D D

C C

B B

AT16 AT13 AT10

AR25 AR22 AR19 AR16 AR13 AR10

AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AJ25

AT7 AT4 AT3

AR7 AR4 AR2

AP7 AP4 AP1

AN7 AN4

AL7 AL4 AL2

AK7 AK4

VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

U31I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

VSS171

VSS172

VSS173

VSS174

VSS175

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186 VSS187

L33

VSS188

L30

VSS189

L27

VSS190

VSS191

VSS192

VSS193

VSS194

VSS195

VSS196

VSS197

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

VSS214

VSS215

VSS216

VSS217

VSS218

VSS219

VSS220

VSS221

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SMDDR_VREF_DQ0_M3[13] SMDDR_VREF_DQ1_M3[14]

H_VTTVID1[39]

Sandy Bridge Processor (RESERVED, CFG)

U31E

For CPU debug.

TP9TP9 TP10TP10

TP13TP13

R359

R359 *1K_4

*1K_4

R362 *0_4/SR362 *0_4/S

CFG0 CFG2 CFG4

CFG5 CFG6 CFG7CFG7

R354

R354 *1K_4

*1K_4

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

RSVD6

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

J15

RSVD27

Sandy Bridge_r PG A_Re v0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

RESERVED

RSVD28

AG7

RSVD29

AE7

RSVD30

AK2

RSVD31

RSVD32

AT26

RSVD33

AM33

RSVD34

AJ27

RSVD35

RSVD37

J16

RSVD38

H16

RSVD39

G16

RSVD40

AR35

RSVD41

AT34

RSVD42

AT33

RSVD43

AP35

RSVD44

AR34

RSVD45

B34

RSVD46

A33

RSVD47

A34

RSVD48

B35

RSVD49

C35

RSVD50

AJ32

RSVD51

AK32

RSVD52

AH27

RSVD53

AN35

RSVD54

AM35

RSVD55

#27636 SNB EDS0.7v1 no function.

AT2

RSVD56

AT1

RSVD57

AR1

RSVD58

For rPGA socket, RSVD59 pin should be left NC.

KEY

TP40TP40 TP39TP39

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Processor Strapping

The CFG signals have a default value of '1' if not terminated on t he board.

A A

CFG2 (PEG Static Lane Reversal)

CFG4 (DP Presence Strap)

CFG7 (PEG Defer Training)

Normal Operation Lane Reversed

Disable; No physical DP attached to eDP

PEG train immediately following xxRESETB de assertion

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

CFG2

R151 1K_4R151 1K_4

CFG4

R149 *1K_4R149 *1K_4

CFG7

R144 *1K_4R144 *1K_4

CFG5

R139 *1K_4R139 *1K_4

CFG6

R146 *1K_4R146 *1K_4

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

PD7

Date: Sheet

SNB 4/4 (GND)

647Wednesday, October 13, 2010

Cougar Point (DMI,FDI,PM)

U44C

DMI_RXN0[3] DMI_RXN1[3] DMI_RXN2[3] DMI_RXN3[3]

DMI_RXP0[3]

D D

SUS_PWR_ACK_R

C C

B B

5/7: DEL R8293 for SUSACK# From EC

XDP_DBRST#[3]

SYS_PWROK

EC_PWROK[25,35]

EC_PWROK_R

PM_DRAM_PWRGD[3]

RSMRST#[35]

SUS_PWR_ACK[35]

DNBSWON#[35]

AC_PRESENT[35]

DMI_RXP1[3] DMI_RXP2[3] DMI_RXP3[3]

DMI_TXN0[3] DMI_TXN1[3] DMI_TXN2[3] DMI_TXN3[3]

DMI_TXP0[3] DMI_TXP1[3] DMI_TXP2[3] DMI_TXP3[3]

R282 49.9/F_4R282 49.9/F_4

+1.05V

R276 750/F_4R276 750/F_4

R623 *0_4/SR623 *0_4/S

R625 *0_4/SR625 *0_4/S R617 *0_4R617 *0_4

R618 *0_4/SR618 *0_4/S

R256 *0_4/SR256 *0_4/S

R624 *0_4/SR624 *0_4/S

R638 *0_4/SR638 *0_4/S

R630 *0_4R630 *0_4

8/6: PV modify

DMI_COMP DMI_RBIAS

SUSACK#_R

XDP_DBRST#

SYS_PWROK_R

EC_PWROK_R

APWROK_R

PM_DRAM_PWRGD

RSMRST#

SUS_PWR_ACK_R

DNBSWON#_R

AC_PRESENT_R

PM_BATLOW#

PM_RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

3VS5)

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

(DSW)

H20

ACPRESENT / GPIO31

(+3VS5)

E10

BATLOW# / G P IO72

A10

RI#

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

DMI

FDI

DMI

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

DPWROK

WAKE#

(+3V)

(+3VS5)

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

(+3VS5)

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

N14

D10

G10

G16

AP14

K14

DSWVREN

R642 *0_4/SR642 *0_4/S

PCIE_WAKE#

CLKRUN#

PCH_SUSCLK_L

R219 *0_4/SR219 *0_4/S

R600 *0_4/SR600 *0_4/S

SLP_LAN#

TP66TP66

R271 *0_4/SR271 *0_4/S

TP54TP54

5/7: DEL R8304 , Add TP9041

FDI_TXN0 [3] FDI_TXN1 [3] FDI_TXN2 [3] FDI_TXN3 [3] FDI_TXN4 [3] FDI_TXN5 [3] FDI_TXN6 [3] FDI_TXN7 [3]

FDI_TXP0 [3] FDI_TXP1 [3] FDI_TXP2 [3] FDI_TXP3 [3] FDI_TXP4 [3] FDI_TXP5 [3] FDI_TXP6 [3] FDI_TXP7 [3]

FDI_INT [3] FDI_FSYNC0 [3] FDI_FSYNC1 [3] FDI_LSYNC0 [3] FDI_LSYNC1 [3]

TP67TP67

R645 *0_4/SR645 *0_4/S

DPWROK

PCIE_WAKE# [33,36]

CLKRUN# [35]

TP26TP26

TP29TP29

SLP_S5 [35]

SUSC# [35]

SUSB# [35]

5/11: add TP9048

TP25TP25

PM_SYNC [3]

6/30 : add TP

RSMRST#

5/12: modify

PCH_SUSCLK [35]

PCH_LVDS_BLON[24]

PCH_DISP_ON[24]

PCH_DPST_PWM[24]

PCH_EDIDCLK[24] PCH_EDIDDATA[24]

3/26 DB change net name.

PCH_LA_CLK#[24]

PCH_LA_CLK[24]

PCH_LA_DATAN0[24] PCH_LA_DATAN1[24] PCH_LA_DATAN2[24]

PCH_LA_DATAP0[24] PCH_LA_DATAP1[24] PCH_LA_DATAP2[24]

PCH_LB_CLK#[24] PCH_LB_CLK[24]

PCH_LB_DATAN0[24] PCH_LB_DATAN1[24] PCH_LB_DATAN2[24]

PCH_LB_DATAP0[24] PCH_LB_DATAP1[24] PCH_LB_DATAP2[24]

PCH_CRT_B[24] PCH_CRT_G[24] PCH_CRT_R[24]

PCH_DDCCLK[24] PCH_DDCDATA[24]

8/13: PV add

C916

C915

*220P/50V_4

PCH_CRT_B PCH_CRT_G PCH_CRT_R

C917

*220P/50V_4

PCH_EDIDCLK PCH_EDIDDAT

CTRL_CLK CTRL_DATA

LVD_IBG

PCH_LA_CLK# PCH_LA_CLK

PCH_LA_DATAN0 PCH_LA_DATAN1 PCH_LA_DATAN2

PCH_LA_DATAP0 PCH_LA_DATAP1 PCH_LA_DATAP2

PCH_LB_CLK# PCH_LB_CLK

PCH_LB_DATAN0 PCH_LB_DATAN1 PCH_LB_DATAN2

PCH_LB_DATAP0 PCH_LB_DATAP1 PCH_LB_DATAP2

PCH_CRT_B PCH_CRT_G PCH_CRT_R

PCH_HSYNC_R PCH_VSYNC_R

Cougar Point (LVDS,DDI)

U44D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

T2T2

DAC_IREF

R689

R689 1K/F_4

1K/F_4

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJ H FCBGA TOP B/S

LVDS

CRT

+1.05V [8,9,11,34,35,41] +3V_RTC [8,11] +3V_DSW [8,11] +3VPCU [8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3VS5 [3,8,9,10,11,45] +3V [3,8,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5V [8,11,19,25,26,27,29,30,32,34,36,37,45]

SDVO_CTRLDATA

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLDATA

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_CLK [27] SDVO_DATA [27]

DPB_HPD_Q DPB_LANE0_N

DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P

INT. HDMI

PCH Pull-high/low(CLG)

PM_RI# PM_BATLOW# PCIE_WAKE# SLP_LAN# SUS_PWR_ACK AC_PRESENT_R

A A

CLKRUN# XDP_DBRST#

RSMRST# SYS_PWROK

R615 10K_4R615 10K_4 R616 *8.2K_4R616 *8.2K_4 R614 10K_4R614 10K_4 R632 *10K_4R632 *10K_4 R627 10K_4R627 10K_4 R629 10K_4R629 10K_4

R591 8.2K_4R591 8.2K_4 R583 10K_4R583 10K_4 R576 *1K_4R576 *1K_4 R647 10K_4R647 10K_4 R621 *10K_4R621 *10K_4

7/2 SI modify

+3VS5 +3VPCU+3VS5

+3V

INT LVDS & CRT disable (DIS only remove)

8/17: PV modify

+3V

PCH_HSYNC[24] PCH_VSYNC[24]

PD Res place close to PCH PCH to Res routeing 50 ohm Impedance.

Res to connector filter routeing 37.5ohm Impedance.

R313 *150/F_4R313 *150/F_4 R318 *150/F_4R318 *150/F_4 R321 *150/F_4R321 *150/F_4

3/26 DB change net name.

R690 *2.2K_4R690 *2.2K_4 R691 *2.2K_4R691 *2.2K_4

R294 *2.37K/F_4R294 *2.37K/F_4

R323 *33_4R323 *33_4 R325 *33_4R325 *33_4

CTRL_CLK CTRL_DATA

LVD_IBG

PCH_HSYNC_R PCH_VSYNC_R

4/29 modify

PCH_CRT_B PCH_CRT_G PCH_CRT_R

DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P

C420 *0_4/SC420 *0_4/S C421 *0_4/SC421 *0_4/S C422 *0_4/SC422 *0_4/S C426 *0_4/SC426 *0_4/S C433 *0_4/SC433 *0_4/S C432 *0_4/SC432 *0_4/S C434 *0_4/SC434 *0_4/S C435 *0_4/SC435 *0_4/S

INT HDMI Detect Function

R715 *0_4R715 *0_4

DPB_HPD_Q

R711

R711 *100K_4

*100K_4

Q47

*2N7002K

+5V

9/26: MV modify

R707

R707 *100K_4

*100K_4

IN_D2# [27] IN_D2 [27] IN_D1# [27] IN_D1 [27] IN_D0# [27] IN_D0 [27] IN_CLK# [27] IN_CLK [27]

HDMI_HPD_CON [27]

System PWR_OK(CLG)

C779 *0.1U/10V_4C779 *0.1U/10V_4

SYS_PWROK

+3V_RTC

U43

U43 *TC7SH08FU

*TC7SH08FU

4/20 DB update.

8/13 PV update.

R246 0_4R246 0_4

R633 330K_4R633 330K_4

2 1

3 5

DSWVREN

On Die DSW VR Enable High = Enable ( Def ault)

Low = Disable

IMVP_PWRGD [40]

EC_PWROK

R620

R620 100K_4

100K_4

6/4 :DB2 modify

R637 *330K_4R637 *330K_4

DPWROK FOR DSWINT HDMI disable (DIS only remove)

+3VPCU

+3VS5

+3VPCU

5/12: modify

+3V_DSW

D16

*RB500V-40

*RB500V-40 D17

D17

*RB500V-40

Q44

Q44 *PDTC144EU

*PDTC144EU

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

PD7

Date: Sheet

R631

R631 *10K_4

*10K_4

1 3

PCH 1/6 (DMI/FDI/VIDEO)

R626

R626 *10K_4

*10K_4

Q43

Q43 *2N7002

*2N7002

DPWROK

C780

C780 *0.1U/10V_4

*0.1U/10V_4

add cap to timing tune

747Wednesday, October 13, 2010

TP68TP68 TP69TP69

6/30 SI Modify

TP74TP74

R275 1M_4R275 1M_4

D D

C C

B B

+3V_RTC

6/30 SI Modify

+3VPCU

PCH Strap Table

Pin Name Strap descriptio n Sampled Co n fi g uration

SPKR

TP70TP70

SPKR[29]

ACZ_SDIN0[29]

TP32TP32

TP31TP31

TP23TP23 TP18TP18 TP17TP17 TP16TP16

R572 *10K_4R572 *10K_4

Different from Calpella

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN

ACZ_BCLK ACZ_SYNC SPKR ACZ_RST#

ACZ_SDOUT

GPIO33

PCH_JTAG_TCK_R PCH_JTAG_TMS PCH_JTAG_TDI_R PCH_JTAG_TDO_R

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO

No reboot mode setting PWROK

GNT3# / GPIO55 T

Cougar Point (HDA,JTAG,SATA)

U44A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

(+3V)

C36

HDA_DOCK_EN# / GPIO33

(+3VS5)

N32

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

Y14

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

op-Block Swap Override

PWROK

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up HDA_DOCK_EN#/GPIO33 GNT1# / GPIO51

GPIO19

Different from Calpella

GNT2# / GPIO53 NV_ALE

NV_CLE

A A

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

Flash Descriptor Security

Only for Interposer

Boot BIOS Selection 1 [bit-1] Boot BIOS Selection 0 [bit-0] ESI strap (Server only)

Intel Anti-Theft HDD protection

Only for Interposer

DMI Termin a tion voltage

HDA_SDO PW GPIO8

GPIO28

Different from Calpella

Integrated Clock Chip Enable Should be pull-down (weak pull-up 20K)RSMRST# On-die PLL Voltage Regulator RSMRST#

PWROK PWROK PWROK PWROK PWROK 0 = Disable (Internal pull-down 20kohm)

PWROK

ROKFlash Descriptor Security

SPI_MOSI iTPM function Disable APWROK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

RTCIHDA

SPI JTAG

LDRQ0#

LDRQ1# / GPIO23

(+3V)

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

(+3V)

SATA0GP / GPIO21

(+3V)

SATA1GP / GPIO19

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

0 = Override

1 = Default (weak pull-up 20K)

GNT0#GNT1#

11 00

Should not be pull-down (weak pull-up 20K)

weak pull-down 20kohm

0 = Support by 1.8V (weak pull-down) 1 = Support by 1.5V

0 = Override

1 = Default (weak pull-up 20K)

0 = Disable

1 = Enable (Default) 0 = Default (weak pull-down 20K)

1 = Enable

4/29 DB change net name.

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

Boot Location

3/26 DB change net name.

LAD0 [35,36] LAD1 [35,36] LAD2 [35,36] LAD3 [35,36]

PCH_DRQ#0 PCH_DRQ#1

SERIRQ

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C

LFRAME# [35,36]

TP33TP33 TP34TP34

R245 8.2K_4R245 8.2K_4

C882 0.01U/25V_4C882 0.01U/25V_4 C881 0.01U/25V_4C881 0.01U/25V_4 C368 0.01U/25V_4C368 0.01U/25V_4 C363 0.01U/25V_4C363 0.01U/25V_4

C688 0.01U/25V_4C688 0.01U/25V_4 C683 0.01U/25V_4C683 0.01U/25V_4 C375 0.01U/25V_4C375 0.01U/25V_4 C373 0.01U/25V_4C373 0.01U/25V_4

3/26 DB modify for pl acement.

DG recommended that AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality.

SATA_RXN4_C SATA_RXP4_C SATA_TXN4_C SATA_TXP4_C

SATA_RXN5_C SATA_RXP5_C SATA_TXN5_C SATA_TXP5_C

C562 0.01U/25V_4C562 0.01U/25V_4 C566 0.01U/25V_4C566 0.01U/25V_4 C365 0.01U/25V_4C365 0.01U/25V_4 C366 0.01U/25V_4C366 0.01U/25V_4

C716 0.01U/25V_4C716 0.01U/25V_4 C713 0.01U/25V_4C713 0.01U/25V_4 C372 0.01U/25V_4C372 0.01U/25V_4 C371 0.01U/25V_4C371 0.01U/25V_4

3/26 DB modify for pl acement.

SATA_COMP

SATA3_COMP

SATA3_RBIAS

DGT_STOP# BBS_BIT0

SPI

LPC

R260 37.4/F_4R260 37.4/F_4

R263 49.9/F_4R263 49.9/F_4

R597 750/F_4R597 750/F_4

R590 10K_4R590 10K_4

+3V

DGT_STOP# [32]

SPKR

R687 *1K_4R687 *1K_4 R700 10K_4R700 10K_4

PCH_INVRMEN

GPIO33

[Need external pull-down for LPC BIOS] Default weak pull-up on GNT 0/1#

USE GPIO PIN

+1.8V

4/29 modify

+1.8V

+3VS5

GPIO33_E[35]

PCH_SPI_SI

R595 2.2K_4R595 2.2K_4

+1.05V [7,9,11,34,35,41] +1.8V [5,11,39,45] +3V_RTC [7,11] +3V_DSW [7,11] +3VPCU [7,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,9,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +V3.3A_1.5A_HDA_IO [11]

+3V SERIRQ [35]

SATA_RXN0 [34] SATA_RXP0 [34] SATA_TXN0 [34] SATA_TXP0 [34]

SATA_RXN1 [34] SATA_RXP1 [34] SATA_TXN1 [34] SATA_TXP1 [34]

SATA_RXN4 [34] SATA_RXP4 [34] SATA_TXN4 [34] SATA_TXP4 [34]

SATA_RXN5 [32] SATA_RXP5 [32] SATA_TXN5 [32] SATA_TXP5 [32]

+1.05V

SATA_LED# [32]

5/6: modify

HDD0 (SATA3 6.0Gb/s)

5/6: modify

HDD1 (SATA3 6.0Gb/s)

5/6: modify

ODD (SATA1 1.5Gb/s)

4/29: modify

E-SATA

Bios swap GPIO 4/23.

DGT_STOP#

R215 10K_4R215 10K_4

+3V

Circuit

R568 *1K_4R568 *1K_4

R640 330K_4R640 330K_4

R659 0_4R659 0_4

1 2

R573 *1K_4R573 *1K_4 R686 *1K_4R686 *1K_4

R596 *1K_4R596 *1K_4

R307 1K_4R307 1K_4

ACZ_SDOUT

R619 *1K_4R619 *1K_4

R608 *1K_4R608 *1K_4

R634 1K_4R634 1K_4

+3V

PCI_GNT3# [9]

Bios request, for can't boot Capella 4/23.

+3V_RTC

BIOS_WP#

R609 4.7K_4R609 4.7K_4

4/29 reserve.

BBS_BIT0

BBS_BIT1 [9]

NV_ALE [9]

ACZ_SYNC

R662 *1K_4R662 *1K_4

ICC_EN# [10]

PLL_ODVR_EN [10]

+3V

9/30: MV modify

NV_CLE [9] H_SNB_IVB# [3]

8/12 PV Modify.

N.A at CPT EDS 0.7

+V3.3A_1.5A_HDA_IO

RTC Circuitry(RTC)

5/12: modify

R319 *0_6R319 *0_6

+3V_DSW

R330 *0_6/SR330 *0_6/S

+3VPCU

+3V_RTC_0

R328 1K_4R328 1K_4

CN29

CN29 BAT_CONN

BAT_CONN

RTC Power trace width 20mils.

6/9 : DB2 Modify Footprint

HDA Bus(CLG)

BIT_CLK_AUDIO[29] ACZ_RST#_AUDIO[29] ACZ_SDOUT_AUDIO[29]

+5V

ACZ_SYNC_AUDIO[29]

9/30 : MV Modify

6/28 SI modify

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO PCH_SPI1_SO_R

R299 33_4R299 33_4 R666 33_4R666 33_4 R656 33_4R656 33_4

R748 10K_4R748 10K_4

R661 33_4R661 33_4

R785 *1M_4R785 *1M_4

6/4 : DB2 Modify

R636 *0_4/SR636 *0_4/S R635 *0_4/SR635 *0_4/S R606 *0_4/SR606 *0_4/S

R603 3.3K_4R603 3.3K_4

+3V

TP64TP64 TP65TP65

RTC Clock 32.768KHz

C789 18P/50V_4C789 18P/50V_4

C788 18P/50V_4C788 18P/50V_4

30mils

+3V_RTC

FOR DSW

+3V_RTC_2 +3V_RTC_1

D6 BAT54CD6BAT54C

ACZ_BCLK ACZ_RST# ACZ_SDOUTACZ_SDOUT

ACZ_SYNC

Q48

Q48 2N7002K

2N7002K

6/23: SI modify

Vender EON Winbond Socket

TP57TP57 TP58TP58

PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R

C783

C783 *22P/50V_4

*22P/50V_4

BIOS_WP#

TP59TP59

Size 4MB 4MB

PD7

P/N AKE39FN0Q00 (EN25F32-100HIP) AKE391P0N00 (W25Q32BVSSIG) DG008000031

Size Document Number Rev

Custom

Date: Sheet

R297 *0_6R297 *0_6

+3VS5

R208

R208 *210/F_4

*210/F_4

R209

R209 *100/F_4

*100/F_4

VDD

VSS

RTC_X1

R641

R641 10M_4

10M_4

RTC_X2

C438

C438 1U/6.3V_4

1U/6.3V_4

C428

C428 1U/6.3V_4

1U/6.3V_4

5/3 : modify

10/13: MV modify

4/29: modify

R204

R204 *210/F_4

*210/F_4

PCH_JTAG_TMS PCH_JTAG_TDI_R PCH_JTAG_TDO_R

R205

R205 *100/F_4

*100/F_4

R639 3.3K_4R639 3.3K_4

7 4

0.1U/10V_4

RTC_RST#

J2 *SOLDERJUMPER-2

*SOLDERJUMPER-2

SRTC_RST#

J1 *SOLDERJUMPER-2

*SOLDERJUMPER-2

SRTC_RST#RTC_RST#

PCH_JTAG_TCK_R

R233

R233 *51_4

*51_4

C784

847Wednesday, October 13, 2010

+3V

32.768KHZ

4 1

R327

20K/F_4

R317

R317 20K/F_4

20K/F_4

C440

C440 1U/6.3V_4

1U/6.3V_4

4/20 DB add.

PCH JTAG Debug(CLG)

R239

R239 *210/F_4

*210/F_4

R240

R240 *100/F_4

*100/F_4

PCH SPI ROM(CLG)

U42

CE#

SCK

HOLD#

WP#

SPI Flash Socket

9/30: MV modify

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

PCH 2/6 (SATA/HDA/SPI)

Cougar Point-M (PCI,USB,NVRAM)

U44E

PCI/USBOC# Pull-up(CLG)

3/26 DB change Part reference.

DGPU_HOLD_RST#

INTH#

BT_COMBO_EN#

DGPU_SELECT#

3/26 DB change Part reference.

USB_OC6#

USB_OC0#

USB_OC7#

USB_OC5#

C897 *27P/50V_4C897 *27P/50V_4 C898 *27P/50V_4C898 *27P/50V_4

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

BT_COMBO_EN# DGPU_SELECT#

BBS_BIT1 PWM_SELECT# PCI_GNT3#

MPC_PWR_CTRL# LCD_BK DGPU_HOLD_RST# INTH#

TP24TP24

PCI_PLTRST#

CLK_PCI_TPM_R CLK_PCI_CARD_R

R324 22_4R324 22_4 R316 22_4R316 22_4

R315 22_4R315 22_4

CLK_PCI_FB_R CLK_PCI_LPC_R CLK_PCI_EC_R

PLTRST#

R212

R212 100K_4

100K_4

+3V

PCI_PIRQA#

R310 8.2K_4R310 8.2K_4

PCI_PIRQB#

R670 8.2K_4R670 8.2K_4

PCI_PIRQC#

R296 8.2K_4R296 8.2K_4

PCI_PIRQD#

USB_OC4# USB_OC1# USB_OC2# USB_OC3#

R302 8.2K_4R302 8.2K_4

+3V

RP21

9 8 7 4

10K_10P8R_6

+3VS5

RP20

9 8 7 4

10K_10P8R_6

D D

MPC_PWR_CTRL# EDID_SELECT#

LCD_BK

MPC Switch Control

MPC_PWR_CTRL#

C C

CLK_33M_DEBUG

L63 *33nH/600mA_6L63 *33nH/600mA_6

CLK_33M_KBC

L64 *33nH/600mA_6L64 *33nH/600mA_6

Low = MPC ON High = MPC OFF (Default)

R682 *1K_4R682 *1K_4

6/28: DB2 reserve

BT_COMBO_EN#[36] DGPU_SELECT#

EDID_SELECT#

BBS_BIT1[8]

PWM_SELECT#

PCI_GNT3#[8]

LCD_BK[25]

DGPU_HOLD_RST#[37]

INTH#[30]

B B

TP56TP56

CLK_33M_KBC[35]

CLK_PCI_FB

+3VS5

2 1

3 5

TP36TP36

C362 *0.1U/10V_4C362 *0.1U/10V_4

U18

U18 *TC7SH08FU

*TC7SH08FU

PLTRST# [3,33,35,36,37]

CLK_33M_DEBUG[36]

PLTRST#(CLG)

PCI_PLTRST#

R228

4/29 modify

*0_4/S

A A

PLTRST#

PEG Clock detect (SG only)

DGPU_PWROK_1 [43]

CLK_PEGA_REQ#

Q29

Q29 *2N7002

*2N7002

6/9: modify

PCI_PME#

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

RSVD

(+3V) (+3V) (+3V)

(+3V) (+3V) (+3V) (+3V)

SMBus/Pull-up(CLG)

4/20 modify

SMB_PCH_DAT

SMB_PCH_CLK

MBCLK2[14,30,35]

MBDATA2[14,30,35]

Q18

Q18 2N7002K

2N7002K

Q14

+3V

Q15

2N7002K

+3V

PCI

(+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5)

2 2

R300 4.7K_4R300 4.7K_4 R298 4.7K_4R298 4.7K_4

Q17

Q17 2N7002K

2N7002K

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RCOMP

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

USB

USBRBIAS#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

SMB_ME1_CLK

R257 2.2K_4R257 2.2K_4

R270 2.2K_4R270 2.2K_4

SMB_ME1_DAT

SMB_RUN_DAT [13,14]

SMB_RUN_CLK [13,14]

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS

+3VS5

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AY1

AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

WLAN

LAN

NV_ALE NV_CLE

3/26 DB change from Port5 & Port6 to Port12 & Port13 for DF PCH.

USB_BIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

NV_ALE [8] NV_CLE [8]

USBP0- [32] USBP0+ [32] USBP1- [32] USBP1+ [32] USBP2- [32] USBP2+ [32] USBP3- [32] USBP3+ [32] USBP4- [25] USBP4+ [25]

USBP8- [32] USBP8+ [32] USBP9- [32] USBP9+ [32] USBP10- [36] USBP10+ [36] USBP11- [32] USBP11+ [32] USBP5- [28] USBP5+ [28] USBP6- [32] USBP6+ [32]

R654

22.6/F_4

CLK_REQ/Strap Pin(CLG)

CLK_PCIE_REQ1# CLK_PCIE_REQ2#

CLK_PCIE_REQ0# CLK_PCIE_REQ3# CLK_PCIE_REQ4#

CLK_PEGB_REQ# CLK_PEGA_REQ# CLK_PEGA_REQ#

CLK_BUF_BCLK_N CLK_BUF_BCLK_P

CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL CLK_BUF_DREFCLK# CLK_BUF_DREFCLK CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK CLK_PCH_14M

CLOCK TERMINATION for FCIM

PCIE_RXN2_LAN[33]

PCIE_RXP2_LAN[33] PCIE_TXN2_LAN[33] PCIE_TXP2_LAN[33]

C892 *.1U/10V_4C892 *.1U/10V_4

PCH_CLK_27M_1

Left_USB E-Sata Fingerprint Touchscreen Webcam

Right_USB 17" Right_USB 15" WLAN Right_USB 15" Card Reaer Blue tooth

Ra Rb

PCIE_RXN1[36] PCIE_RXP1[36]

PCIE_TXN1[36] PCIE_TXP1[36]

R238 10K_4R238 10K_4 R229 10K_4R229 10K_4

R599 10K_4R599 10K_4 R610 10K_4R610 10K_4 R247 10K_4R247 10K_4

R244 10K_4R244 10K_4 R236 *10K_4R236 *10K_4 R227 10K_4R227 10K_4

SG : Rb ; UMA : Ra

R289 10K_4R289 10K_4 R288 10K_4R288 10K_4

R269 10K_4R269 10K_4 R265 10K_4R265 10K_4 R290 10K_4R290 10K_4 R286 10K_4R286 10K_4 R242 10K_4R242 10K_4 R243 10K_4R243 10K_4 R309 10K_4R309 10K_4

C414 0.1U/10V_4C414 0.1U/10V_4 C410 0.1U/10V_4C410 0.1U/10V_4

C418 0.1U/10V_4C418 0.1U/10V_4 C419 0.1U/10V_4C419 0.1U/10V_4

5/13: add for leakage

7/2 : Modify +3v

9/26: MV modify

+3V

DGPU_PWROK [10,35,42,43,47]

U49

2 4

*74LVC1G126

Bios swap GPIO 4/23.Bios swap GPIO 4/23.

TP22TP22

+3V

+3VS5

Cougar Point-M (PCI-E,SMBUS,CLK)

U44B

BG34

PERN1

BJ34

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_LAN_C PCIE_TXP2_LAN_C

PCH_CLK_27M [18]

CLK_PCH_SRC0N CLK_PCH_SRC0P

CLK_PCIE_REQ0#

CLK_PCH_SRC2N CLK_PCH_SRC2P

CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

BOARD_ID0[10]

CLK_PEGB_REQ#

BOARD_ID1[10] BOARD_ID2[10]

TP30TP30 TP27TP27

CLK_PCH_ITPN CLK_PCH_ITPP

PCIE Clock

WLAN

LAN

GPU

CLK_PCIE_WLANN[36] CLK_PCIE_WLANP[36]

PCIE_CLKREQ_WLAN#[36]

CLK_PCIE_LANN[33] CLK_PCIE_LANP[33]

PCIE_CLKREQ_LAN#[33]

CLK_PCIE_VGA#[15]

CLK_PCIE_VGA[15]

+3VS5 [3,7,8,10,11,45] +3V [3,7,8,10,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47]

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

(+3VS5)

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

(+3V)

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

(+3V)

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

(+3VS5)

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

(+3VS5)

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

(+3VS5)

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

(+3VS5)

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

(+3VS5)

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

(+3VS5)

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

PCI-E*

3/26 DB change Part reference.

R577 *0_4/SR577 *0_4/S

3/26 DB change Part reference.

R589 *0_4/SR589 *0_4/S

3/26 DB change Part reference.

RP14

0_4P2R_4

Remove for UMA only.

(+3VS5)

SMBALERT# / GPIO11

SMBCLK

SMBDATA

(+3VS5)

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

Link

PEG_A_CLKRQ# / GPIO47

CLOCKS

FLEX CLOCKS

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

CLK_PCH_SRC0N CLK_PCH_SRC0P

CLK_PCIE_REQ0#

CLK_PCH_SRC2N CLK_PCH_SRC2P

CLK_PCIE_REQ1#

CLK_PCH_PEGAN

CLK_PCH_PEGAP

SML0CLK

SML0DATA

(+3VS5) (+3VS5)

SML1CLK / GPIO58

(+3VS5)

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

(+3VS5)

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

(+3V)

CLKOUTFLEX0 / GPIO64

(+3V)

CLKOUTFLEX1 / GPIO65

(+3V)

CLKOUTFLEX2 / GPIO66

(+3V)

CLKOUTFLEX3 / GPIO67

SMBALERT#

E12

SMB_PCH_CLK

H14

SMB_PCH_DAT

DRAMRST_CNTRL_PCH

A12

SMB_ME0_CLK

SMB_ME0_DAT

G12

SML1ALERT#_R

C13

SMB_ME1_CLK

E14

SMB_ME1_DAT

M16

CL_CLK_R

CL_DAT_R

T11

CL_RST#_R

P10

CLK_PEGA_REQ#

M10

CLK_PCH_PEGAN

AB37

CLK_PCH_PEGAP

AB38

AV22 AU22

AM12 AM13

CLK_BUF_PCIE_3GPLL#

BF18

CLK_BUF_PCIE_3GPLL

BE18

CLK_BUF_BCLK_N

BJ30

CLK_BUF_BCLK_P

BG30

CLK_BUF_DREFCLK#

G24

CLK_BUF_DREFCLK

E24

CLK_BUF_DREFSSCLK#

AK7

CLK_BUF_DREFSSCLK

AK5

CLK_PCH_14M

K45

CLK_PCI_FB

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_FLEX0

K43

CLK_FLEX1

F47

CLK_FLEX2

H47

CLK_FLEX3

K49

DRAMRST_CNTRL_PCH [3]

TP28TP28

TP19TP19

TP21TP21

TP20TP20

CLK_CPU_BCLKN [3] CLK_CPU_BCLKP [3]

CLK_DPLL_SSCLKN [3] CLK_DPLL_SSCLKP [3]

3/26 DB del external clock generator.

TP71TP71

C830

C830 18P/50V_4

18P/50V_4

R683

1M_4

25MHzY525MHz

C829

C829 18P/50V_4

18P/50V_4

R688 90.9/F_4R688 90.9/F_4

4/29: remove CLK_27M_VGA

TP35TP35

5/13: modify CLK_48M to CLK_FLEX1

R304 22_4R304 22_4

R692 *22_4R692 *22_4

Remove Ra, Rb for UMA & SG. 27MHz support DIS only.

+3VS5

R250 1K_4R250 1K_4 R252 10K_4R252 10K_4

R268 2.2K_4R268 2.2K_4 R264 2.2K_4R264 2.2K_4 R607 2.2K_4R607 2.2K_4 R261 2.2K_4R261 2.2K_4 R258 10K_4R258 10K_4

Size Document Number Rev

Custom

PD7

Date: Sheet

TP72TP72

+1.05V

CLK_48M_CR [28]

TP55TP55

PCH_CLK_27M_1

SMBus/Pull-up(CLG)

DRAMRST_CNTRL_PCH SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

PCH 3/6 (PCIE/USB/CLK)

947Wednesday, October 13, 2010

にイオわらェえへイゑィォえぐはへぱぷごまほほょぶにぼのごぺほまぬけ

5/23: stuff for bios

Bios swap GPIO 4/23.

PCI_SERR#[35] SIO_EXT_SMI#[35] SIO_EXT_SCI#[35]

BT_OFF#[32,36]

D D

Reserve

ACCLED_EN[32]

ICC_EN#[8]

LAN_DISABLE#[33]

RF_OFF#[36]

ODD_PRSNT#[34]

DGPU_PWROK[9,35,42,43,47]

R222 *0_4/SR222 *0_4/S

4/29 modify

R248 *0_4/SR248 *0_4/S

R580 *0_4R580 *0_4

R213 *0_4R213 *0_4

Bios swap GPIO 4/23.

PLL_ODVR_EN[8]

9/26: MV Modify

DGPU_PWR_EN[35,42,43]

C C

R613 *0_4/SR613 *0_4/S

R231 *0_4R231 *0_4

Bios swap GPIO 4/23.

DGT_RESET[32]

B B

+3VS5 [3,7,8,9,11,45] +3V [3,7,8,9,11,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47]

S_GPIO SIO_EXT_SMI# SIO_EXT_SCI# BT_OFF# ICC_EN# LAN_DISABLE#_R RF_OFF#

ODD_PRSNT#_R

DGPU_PWROK BIOS_REC BOARD_ID5 GPIO27 PLL_ODVR_EN_R BOARD_ID3 BOARD_ID4 DGPU_PWR_EN_R FDI_OVRVLTG MFG_MODE DGPU_PRSNT# TEST_SET_UP DGT_RESET SV_DET

にイオわらェえへイゑィォえぐはへぱぷごまほほょぶにぼのごぺほまぬけにイオわらェえへイゑィォえぐはへぱぷごまほほょぶにぼのごぺほまぬけ

U44F

BMBUSY# / GPIO0

(+3V)

A42

TACH1 / GPIO1

(+3V)

H36

TACH2 / GPIO6

(+3V)

E38

TACH3 / GPIO7

(+3V)

C10

GPIO8

(+3VS5)

LAN_PHY_PWR_CTRL / GPIO12

(+3VS5)

GPIO15

(+3VS5)

SATA4GP / GPIO16

(+3V)

D40

TACH0 / GPIO17

(+3V)

SCLOCK / GPIO22

(+3V)

GPIO24 / MEM_LED

(+3VS5)

E16

GPIO27

(DSW)

GPIO28

(+3VS5)

STP_PCI# / GPIO34

(+3V)

GPIO35

(+3V)

SATA2GP / GPIO36

(+3V)

SATA3GP / GPIO37

(+3V)

SLOAD / GPIO38

(+3V)

SDATAOUT0 / GPIO39

(+3V)

V13

SDATAOUT1 / GPIO48

(+3V)

SATA5GP / GPIO49

(+3V)

GPIO57

(+3VS5)

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

BOARD ID SETTING

BOARD_ID4

Model

LX3 UMA

LX5 UMA 0

N Z

Z N

A A

5 Z

LX3 Capilano

- SG

LX5 Capilano

- SG

LX5 Capilano XT -

G/Subwoofer

T E

LX5 DISCRETE

Subwoofer

V G

G V

V G

BOARD_ID5

000

BOARD_ID1BOARD_ID2BOARD_ID3

BOARD_ID0

00000

TACH4 / GPIO68

(+3V)

TACH5 / GPIO69

(+3V)

TACH6 / GPIO70

(+3V)

TACH7 / GPIO71

(+3V)

A20GATE

PECI

RCIN#

PROCPWRGD

CPU/MISC

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

NCTF

VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

BOARD_ID5

THRMTRIP#

INIT3_3V#

NC_1 NC_2 NC_3 NC_4 NC_5

BOARD_ID0 BOARD_ID1 BOARD_ID2

GPIO

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

BOARD_ID0[9] BOARD_ID1[9] BOARD_ID2[9]

RD0

R611 *10K_4R611 *10K_4

RD1

R220 *10K_4R220 *10K_4

RD2

R255 10K_4R255 10K_4

RD3

R594 10K_4R594 10K_4

RD4

R567 10K_4R567 10K_4

RD5

R311 10K_4R311 10K_4

5/11 stuff R9144

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14

AH8 AK11 AH10 AK10 P37

GPIO68 GPIO69 GPIO70 GPIO71

EC_RCIN#

PCH_THRMTRIP#

R675 10K_4R675 10K_4 R676 1.5K/F_4R676 1.5K/F_4

R680 *1.5K/F_4R680 *1.5K/F_4

R253 390_4R253 390_4

R249 *0_4/SR249 *0_4/S

+3V

EC_A20GATE [35]

EC_RCIN# [35] H_PWRGOOD [3] PM_THRMTRIP# [3,35]

DG rev0.9 suggest to TS_VSS connect to GND 4/23.

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

RU0

R612 10K_4R612 10K_4

RU1

R226 10K_4R226 10K_4

RU2

R254 *10K_4R254 *10K_4

RU3

R592 *10K_4R592 *10K_4

RU4

R566 *10K_4R566 *10K_4

RU5

R301 *10K_4R301 *10K_4

4/29 modify

+3VS5

+3V

+3VS5

Intel ME Crypto Transport Layer Security (TLS) cipher suite

Low = Disable (Default) High = Enable

R234 *0_4R234 *0_4

SV_SET_UP

High = Strong (Default)

DMI TERMINATION VOLTAGE OVERRIDE

R581 *100K_4R581 *100K_4

MFG-TEST

MFG_MODE

Bios swap GPIO 4/23.

S_GPIO

RF_OFF#

TEST_SET_UP

Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT)

R575 10K_4R575 10K_4 R574 *0_4R574 *0_4

R221 10K_4R221 10K_4 R216 *0_4R216 *0_4

R598 1K_4R598 1K_4

R232 10K_4R232 10K_4

R230 200K/F_4R230 200K/F_4

GFX Present

SG Ra Rb

RaRb

R582 10K_4R582 10K_4

UMA Rb Ra

DGPU_PRSNT#

Stu

Clock Gen Power OK (CLG)

3/26 DB del external clock generator.

GPIO Pull-up/Pull-down(CLG)

+3V

LAN_DISABLE#_R ACCLED_EN

SIO_EXT_SCI# SIO_EXT_SMI# BT_OFF# EC_A20GATE EC_RCIN# DGT_RESET

+3V

+3VS5

GPIO70 GPIO71 ODD_PRSNT#_R DGPU_PWROK

DGPU_PWROK GPIO27

R206 *0_4R206 *0_4

BIOS RECOVERY High = Disable (Default)

+3V

R602 100K_4R602 100K_4

+3V +3V

R218 100K_4R218 100K_4

FDI TERMINATION VOLTAGE OVERRIDE

+3V

Size Document Number Rev

Custom

PD7

Date: Sheet

R579 10K_4R579 10K_4 R251 10K_4R251 10K_4

R305 10K_4R305 10K_4 R679 10K_4R679 10K_4 R308 10K_4R308 10K_4 R223 10K_4R223 10K_4 R224 10K_4R224 10K_4 R578 10K_4R578 10K_4 R673 1.5K/F_4R673 1.5K/F_4 R668 1.5K/F_4R668 1.5K/F_4 R214 10K_4R214 10K_4 R303 10K_4R303 10K_4

R306 *10K_4R306 *10K_4 R267 10K_4R267 10K_4

4/29 modify

BIOS_REC

R207 10K_4R207 10K_4

Low = Enable

SV_DET

R601 *10K_4R601 *10K_4

TEST DETECT

Low = Default

FDI_OVRVLTGDGPU_PWR_EN_R

LOW - Tx, Rx terminated to same voltage

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

PCH 4/6 (GPIO/MISC)

+3VS5

+3V

R217 *1K_4R217 *1K_4

+3V

10 47Wednesday, October 13, 2010

Cougar Point-M (POWER)

COUGAR POINT (POWER)

U44G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

C831 1U/6.3V_4C831 1U/6.3V_4

C867 *220U/2.5V_3528

C818 1U/6.3V_4C818 1U/6.3V_4

C824 *220U/2.5V_3528

5/14 modify

C852 1U/6.3V_4C852 1U/6.3V_4

L55

L55 10uH/100mA_8

10uH/100mA_8

C853 10U/6.3VS_6C853 10U/6.3VS_6

CRTLVDS

VCC CORE

VCCIO

DMI

NAND / SPI HVCMOS

FDI

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCCPNAND[1]

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCC3_3[6] VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

+5V_PCH_VCC5REF

V5REF= 1mA

+5V_PCH_VCC5REFSUS

VCC5REFSUS=1mA

PD7

8/17: PV modify

+3V+3V_VCC_GIO

R277 *0_4/SR277 *0_4/S

C390

C390 1U/6.3V_4

1U/6.3V_4

+1.8V+VCCP_NAND

+3V+3V_VCCME_SPI

+3V

+1.8V+VCC_TX_LVDS

+1.05V_VTT+1.1V_VCC_DMI

+5V +3V

+5VS5 +3VS5

11 47Wednesday, October 13, 2010

1mA (10mils)

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

SG & UMA : Ra DIS : Rb

V33 V34

+VCCA_DAC_1_2

1mA (10mils)

+VCCALVDS +3V

60mA (10mils)

L52

HCB1608KF-181T15/1.5A_6

C846 10U/6.3VS_6C846 10U/6.3VS_6 C837 0.1U/10V_4C837 0.1U/10V_4 C844 0.01U/25V_4C844 0.01U/25V_4 R703 *0_6R703 *0_6

R665 *0_4R665 *0_4

R667 0_4R667 0_4

L51

*0.1uH/250mA_8

R693 0_4R693 0_4 C832 *22U/6.3VS_8C832 *22U/6.3VS_8 C836 *0.01U/25V_4C836 *0.01U/25V_4 C826 *0.01U/25V_4C826 *0.01U/25V_4

R669 *0_6/SR669 *0_6/S

C813

0.1U/10V_4

42mA (10mils)

+VCCAFDI_VRM

AT16 AT20

+1.1V_VCC_DMI_CCI

AB36

C870

C855

*10U/6.3V_6

1U/6.3V_4

190 mA (15mils)

AG16

AG17

AJ16

AJ17

R237 *0_8/SR237 *0_8/S

C385

0.1U/10V_4

20mA (10mils)

Size Document Number Rev

Custom

Date: Sheet

R571 *0_6/SR571 *0_6/S

C774

C774 1U/6.3V_4

1U/6.3V_4

R295 10_4R295 10_4 D5 RB500V-40D5 RB500V-40

C407

C407 1U/6.3V_4

1U/6.3V_4

R291 10_4R291 10_4 D4 RB500V-40D4 RB500V-40

C405

0.1U/10V_4

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

PCH 5/6 (POWER)

119mA (20mils)

+3V

+1.05V+1.05V_VCCUSBCORE

+3VS5

+1.05V

+3VS5

+3V

+1.05V

+1.5VSUS +3VS5

+1.05V +1.05V_PCH_VCC

6/9: DB2 modify

7/1: SI DEL

+1.05V +1.05V_VCCAPLL_EXP

+1.05V +1.05V_VCCIO

6/9: DB2 modify

7/1: SI DEL

(Mobile 1.5V)

+1.5V

+1.05V

+1.05V +VCC_DMI_CCI +1.1V_VCC_DMI_CCI

+1.05V_PCH_VCCDPLL_EXP+1.05V

R283

*0_6/S

L48

*1uH/25mA_6

C416

C416 10U/6.3VS_6

10U/6.3VS_6

R646 *0_8/SR646 *0_8/S

R708 *0_6/SR708 *0_6/S R709 *0_6R709 *0_6

+1.05V_VTT

+1.05V

L53

L53 10uH/100MA_8

10uH/100MA_8

L50

L50 10uH/100MA_8

10uH/100MA_8

+3V

R714 *0_6R714 *0_6 R720 1/F_4R720 1/F_4

R724 *1/F_4R724 *1/F_4 R730 *0_4/SR730 *0_4/S

1.3 A (60mils)

C400

C400 1U/6.3V_4

1U/6.3V_4

C391

C391 10U/6.3VS_6

10U/6.3VS_6

C791

C791 *10U/6.3V_6

*10U/6.3V_6

2.925 A (140mils)

C412

C412 1U/6.3V_4

1U/6.3V_4

C398

C398 1U/6.3V_4

1U/6.3V_4

+3V_VCC_EXP+3V

160mA (15mils)

+VCCAFDI_VRM

+1.05V

20mA (10mils)

C394

C394 1U/6.3V_4

1U/6.3V_4

C399

C399 1U/6.3V_4

1U/6.3V_4

C411

C411 1U/6.3V_4

1U/6.3V_4

C404

C404 1U/6.3V_4

1U/6.3V_4

C799

0.1U/10V_4

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

R588 *0_8R588 *0_8 R259 *0_8/SR259 *0_8/S

+1.05V_VCCDPLL_FDI

65mA (10mils)

+1.05V_VCCA_A_DPL

(10mils)

8mA

+1.05V_VCCA_B_DPL

+3V_SUS_CLKF33 +3V_SUS_CLKF33_R

L54

L54 *10uH/100mA_8

*10uH/100mA_8

U44J

R695 *0_8R695 *0_8

+1.05V

R274 *0_4/SR274 *0_4/S

+3VS5

R281 *0_4R281 *0_4

+3V_DSW

C389

5/12: modify

D D

+1.05V

8/6: PV modify

L49

*10uH/100mA_8

+1.05V

R293

*0_6/S

+1.05V +1.05V_VCCEPW

6/9: DB2 modify

7/1: SI DEL

C C

R604 *0_6/SR604 *0_6/S

+1.05V

R699 *0_6/SR699 *0_6/S

+1.05V

B B

R685 *0_6/SR685 *0_6/S

+1.05V

R278 *0_6R278 *0_6

+1.05V

R273 *0_4/SR273 *0_4/S

+1.05V_VTT

V_PROC_IO=1mA (10mils)

A A

+3V_RTC

VCCRTC<1mA (10mils)

C389

0.1U/10V_4

+VCCAPLL_CPY_PCH

C795

C795 *10U/6.3V_6

*10U/6.3V_6

C401

C401 1U/6.3V_4

1U/6.3V_4

C777

1U/6.3V_4

C840

1U/6.3V_4

C833

1U/6.3V_4

C387

*1U/6.3V_4

C785

4.7U/6.3V_6

C808

C808 1U/6.3V_4

1U/6.3V_4

1.01A (60mils)

+1.05V [7,8,9,34,35,41] +1.05V_VTT [3,5,39,40] +1.5VSUS [3,5,13,14,43,45] +1.8V [5,8,39,45]

+VCCACLK

+VCCPDSW

3mA (10mils)

C377

PCH_VCCDSW

*0.1U/10V_4

+3V_SUS_CLKF33

4/29: modify

+VCCDPLL_CPY

+VCCSUS1

C786

C786 *1U/6.3V_4

*1U/6.3V_4

C402

C395

1U/6.3V_4

C409

C408

C408 22U/6.3VS_8

22U/6.3VS_8

C409 22U/6.3VS_8

22U/6.3VS_8

C380

0.1U/10V_4

+VCCAFDI_VRM

160mA (20mils)

+1.05V_VCCA_A_DPL

65mA (10mils)

+1.05V_VCCA_B_DPL

8mA (10mils)

+VCCDIFFCLK +VCCDIFFCLKN

55mA (10mils)

+V1.05V_SSCVCC

95mA (10mils)

C383

0.1U/10V_4

+V1.05M_VCCSUS +VTT_VCCPCPU

C778

0.1U/10V_4

C807

0.1U/10V_4

+VCCRTCEXT

+VCCSST

C781

0.1U/10V_4

C806

0.1U/10V_4

U44J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJ0QNJH0T03

IC CTRL(989P)PCH-HM65 QNJH FCBGA TOP B/S

Clock and Miscellaneous

CPURTC

+3V_RTC [7,8] +3V_DSW [7,8] +3VS5 [3,7,8,9,10,45] +3V [3,7,8,9,10,13,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VS5 [45] +5V [7,8,19,25,26,27,29,30,32,34,36,37,45]

PCI/GPIO/LPCMISC

SATA USB

HDA

VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5] VCCIO[12] VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

N26 P26 P28 T27 T29

+3V_VCCPUSB

T23 T24 V23 V24

+3V_VCCAUBG

P24

+VCCAUPLL

T26

+5V_PCH_VCC5REFSUS

M26

+VCCA_USBSUS

AN23

+3V_VCCPSUS

AN24

+5V_PCH_VCC5REF

P34

N20 N22

119mA (15mils)

+3V_VCCPSUS

P20 P22

AA16

266mA (20mils)

+3V_VCCPCORE

W16 T34

AJ2

AF13 AH13 AH14 AF14

+V1.1LAN_VCCAPLL

AK1

+VCCAFDI_VRM

AF11

AC16

+1.05V_VCCIO1

AC17 AD17

1.01A (60mils)

+1.05V_VCCEPW

T21

V21

T19

P32

+3V

C775

0.1U/10V_4

+V1.05S_SATA3

10mA (10mils)

+V3.3A_1.5A_HDA_IO

C798

0.1U/10V_4

R684 *0_8/SR684 *0_8/S

C828

C828 1U/6.3V_4

1U/6.3V_4

R280 *0_6/SR280 *0_6/S

C396

0.1U/10V_4

R279 *0_6/SR279 *0_6/S

C403

0.1U/10V_4

R287 *0_6/SR287 *0_6/S

C392 *1U/6.3V_4C392 *1U/6.3V_4

R272 *0_6/SR272 *0_6/S

C393

C393 1U/6.3V_4

1U/6.3V_4

R210 *0_6/SR210 *0_6/S

C360

0.1U/10V_4

C406

0.1U/10V_4

R241 *0_8/SR241 *0_8/S

C374

C374 1U/6.3V_4

1U/6.3V_4

L45

L45 *10uH/100mA_8

*10uH/100mA_8 C772

C772 *10U/6.3V_6

*10U/6.3V_6

R225 *0_6/SR225 *0_6/S

C384

C384 1U/6.3V_4

1U/6.3V_4

R652 *0_4R652 *0_4 R651 *0_4/SR651 *0_4/S C405

C800

C800 *1U/6.3V_4

*1U/6.3V_4

IBEX PEAK-M (GND)

U44I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

D D

C C

B B

A A

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

VSS[258]

CougarPoint_Rev_0p7

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

IBEX PEAK-M (GND)

U44H

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

CougarPoint_Rev_0p7

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

PD7

Date: Sheet

PCH 6/6 (GND)

12 47Wednesday, October 13, 2010

JDIM1A

M_A_A[15:0][4]

D D

M_A_BS#0[4] M_A_BS#1[4] M_A_BS#2[4] M_A_CS#0[4] M_A_CS#1[4] M_A_CLKP0[4] M_A_CLKN0[4] M_A_CLKP1[4] M_A_CLKN1[4] M_A_CKE0[4] M_A_CKE1[4] M_A_CAS#[4] M_A_RAS#[4]

R153 10K_4R153 10K_4 R152 10K_4R152 10K_4

C C

B B

M_A_WE#[4]

SMB_RUN_CLK[9,14] SMB_RUN_DAT[9,14]

M_A_ODT0[4] M_A_ODT1[4]

M_A_DQSP[7:0][4]

M_A_DQSN[7:0][4]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT

M_A_DM1

M_A_DM2

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

JDIM1A

107

A10/AP

A11

A12/BC#

119

A13

A14

A15

109

BA0

108

BA1

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

CKE0

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

DM0

DM1

DM2

DM3

136

DM4

153

DM5

170

DM6

187

DM7

DQS0

DQS1

DQS2

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

DQS#0

DQS#1

DQS#2

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM0_H=5.2_RVS

DDR-78279-001-RVS-204P

DGMK4000125

IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)

PC2100 DDR3 SDRAM SO-DIMM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46

(204P)

DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_A_DQ4

M_A_DQ5

M_A_DQ7

M_A_DQ6

M_A_DQ1

M_A_DQ0

M_A_DQ3

M_A_DQ2

M_A_DQ9

M_A_DQ8

M_A_DQ15

M_A_DQ10

M_A_DQ12

M_A_DQ13

M_A_DQ14

M_A_DQ11

M_A_DQ21

M_A_DQ16

M_A_DQ19

M_A_DQ18

M_A_DQ20

M_A_DQ17

M_A_DQ23

M_A_DQ22

M_A_DQ25

M_A_DQ24

M_A_DQ30

M_A_DQ26

M_A_DQ28

M_A_DQ29

M_A_DQ31

M_A_DQ27

M_A_DQ36

129

M_A_DQ37

131

M_A_DQ34

141

M_A_DQ38

143

M_A_DQ32

130

M_A_DQ33

132

M_A_DQ35

140

M_A_DQ39

142

M_A_DQ41

147

M_A_DQ45

149

M_A_DQ47

157

M_A_DQ46

159

M_A_DQ40

146

M_A_DQ44

148

M_A_DQ42

158

M_A_DQ43

160

M_A_DQ49

163

M_A_DQ48

165

M_A_DQ54

175

M_A_DQ55

177

M_A_DQ53

164

M_A_DQ52

166

M_A_DQ50

174

M_A_DQ51

176

M_A_DQ61

181

M_A_DQ60

183

M_A_DQ62

191

M_A_DQ63

193

M_A_DQ56

180

M_A_DQ57

182

M_A_DQ59

192

M_A_DQ58

194

M_A_DQ[63:0] [4]

+3V

PM_EXTTS#0[14]

DDR3_DRAMRST#[3,14]

SMDDR_VREF_DQ0_M3[6]

SMDDR_VREF_DQ0_M3

R27 0_6R27 0_6 R17 *0_6R17 *0_6

6/28: SI add for RF

+1.5V

C893 2.2U/6.3V_6C893 2.2U/6.3V_6 C894 2.2U/6.3V_6C894 2.2U/6.3V_6 C895 2.2U/6.3V_6C895 2.2U/6.3V_6 C896 2.2U/6.3V_6C896 2.2U/6.3V_6

+1.5VSUS

2.48A

+3V

R133 10K_4R133 10K_4

PM_EXTTS#0

+SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M1 +SMDDR_VREF_DIMM

+1.5VSUS

+0.75V_DDR_VTT [14,43,45] +1.5VSUS [3,5,11,14,43,45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,8,9,10,11,14,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VPCU [32,35,38,39,40,41,42,43,44,45]

JDIM1B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

NC1

122

NC2

125

NCTEST

198

EVENT#

RESET#

VREF_DQ

126

VREF_CA

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

DDR3-DIMM0_H=5.2_RVS

DDR-78279-001-RVS-204P

DGMK4000125

IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

GND GND

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

+0.75V_DDR_VTT

VREF DQ0 M2 Solution VREF DQ0 M1 SolutionPlace these Caps near So-Dimm0.

R112 *0_6R112 *0_6

+1.5VSUS

R31

R31 1K/F_4

1K/F_4

R106

R106 1K/F_4

1K/F_4

+1.5VSUS

R125 *0_6R125 *0_6

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

Date: Sheet

DDR3 DIMM0-RVS (5.2H)

PD7

DDR_VTTREF[5,14,43]

R97

R97 10K_4

10K_4

+SMDDR_VREF_DIMM

C157

R95

470P/50V_4

10K_4

13 47Wednesday, October 13, 2010

+1.5VSUS +0.75V_DDR_VTT

C88 1U/6.3V_4C88 1U/6.3V_4 C93 1U/6.3V_4C93 1U/6.3V_4 C72 1U/6.3V_4C72 1U/6.3V_4 C56 1U/6.3V_4C56 1U/6.3V_4 C98 10U/6.3VS_6C98 10U/6.3VS_6 C61 10U/6.3VS_6C61 10U/6.3VS_6

6/23 : Del M2 solution

A A

4/29: reserve M2 solution

C46 10U/6.3VS_6C46 10U/6.3VS_6 C52 10U/6.3VS_6C52 10U/6.3VS_6 C83 10U/6.3VS_6C83 10U/6.3VS_6 C65 10U/6.3VS_6C65 10U/6.3VS_6 C47 *10U/6.3V_6C47 *10U/6.3V_6 C40 10U/6.3V_8C40 10U/6.3V_8 C38 10U/6.3V_8C38 10U/6.3V_8

4/27: layout modify

5/23: na

6/28: SI del C717

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ0

C645 1U/6.3V_4C645 1U/6.3V_4 C639 1U/6.3V_4C639 1U/6.3V_4 C634 1U/6.3V_4C634 1U/6.3V_4 C628 1U/6.3V_4C628 1U/6.3V_4 C622 10U/6.3V_6C622 10U/6.3V_6 C657 *10U/6.3V_6C657 *10U/6.3V_6

C186 0.1U/10V_4C186 0.1U/10V_4 C136 2.2U/6.3V_6C136 2.2U/6.3V_6

C21 0.1U/10V_4C21 0.1U/10V_4 C26 2.2U/6.3V_6C26 2.2U/6.3V_6

+3V

C198 0.1U/10V_4C198 0.1U/10V_4 C258 2.2U/6.3V_6C258 2.2U/6.3V_6

DDR_VTTREF SMDDR_VREF_DQ0_M1

2.48A

+3V

R511 10K_4R511 10K_4

PM_EXTTS#0

+SMDDR_VREF_DQ1

MBCLK2 MBDATA2 PM_EXTTS#0 PM_EXTTS#0_EC

R134 10K_4R134 10K_4

+1.5VSUS

JDIM2B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

NC1

122

NC2

125

NCTEST

198

EVENT#

RESET#

VREF_DQ

126

VREF_CA

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

DDR3-DIMM1_H=9.2_RVS

DDR-AS0A626-UARN-7F-204P

DGMK4000126

IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS)

DDR3 Thermal Sensor

U11

SCLK

SDA

ALERT#

OVERT#

G780P81U

PC2100 DDR3 SDRAM SO-DIMM

VCC DXP DXN GND

(204P)

VTT1 VTT2

GND GND

1 2 3 5

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

C261 0.01U/25V_4C261 0.01U/25V_4

DDR_THERMDA

C206

C206 2200P/50V_4

2200P/50V_4

DDR_THERMDC

+0.75V_DDR_VTT

+3V

Q10

Q10 MMBT3904-7-F

MMBT3904-7-F

1 3

JDIM2A

M_B_A[15:0][4]

D D

M_B_BS#0[4] M_B_BS#1[4] M_B_BS#2[4] M_B_CS#0[4] M_B_CS#1[4] M_B_CLKP0[4] M_B_CLKN0[4] M_B_CLKP1[4] M_B_CLKN1[4] M_B_CKE0[4] M_B_CKE1[4] M_B_CAS#[4] M_B_RAS#[4]

R154 10K_4R154 10K_4 R512 10K_4R512 10K_4

+3V

C C

B B

+0.75V_DDR_VTT [13,43,45] +1.5VSUS [3,5,11,13,43,45] +3VPCU [7,8,25,32,34,35,36,37,38,39,40,42,44,45,47] +3V [3,7,8,9,10,11,13,18,19,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,45,46,47] +5VPCU [32,35,38,39,40,41,42,43,44,45]

M_B_WE#[4]

SMB_RUN_CLK[9,13] SMB_RUN_DAT[9,13]

M_B_ODT0[4] M_B_ODT1[4]

M_B_DQSP[7:0][4]

M_B_DQSN[7:0][4]

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DIMM1_SA0 DIMM1_SA1

M_B_DM1

M_B_DM2

M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

JDIM2A

107

A10/AP

A11

A12/BC#

119

A13

A14

A15

109

BA0

108

BA1

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

CKE0

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

DM0

DM1

DM2

DM3

136

DM4

153

DM5

170

DM6

187

DM7

DQS0

DQS1

DQS2

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

DQS#0

DQS#1

DQS#2

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM1_H=9.2_RVS

DDR-AS0A626-UARN-7F-204P

DGMK4000126

IC SOCKET DDRIII SO-DIMM(204P,H9.2,RVS)

PC2100 DDR3 SDRAM SO-DIMM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46

(204P)

DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ5

M_B_DQ4

M_B_DQ3

M_B_DQ2

M_B_DQ0

M_B_DQ1

M_B_DQ6

M_B_DQ7

M_B_DQ12

M_B_DQ13

M_B_DQ14

M_B_DQ10

M_B_DQ8

M_B_DQ9

M_B_DQ11

M_B_DQ15

M_B_DQ20

M_B_DQ21

M_B_DQ18

M_B_DQ22

M_B_DQ17

M_B_DQ16

M_B_DQ19

M_B_DQ23

M_B_DQ25

M_B_DQ29

M_B_DQ27

M_B_DQ26

M_B_DQ28

M_B_DQ24

M_B_DQ31

M_B_DQ30

M_B_DQ36

129

M_B_DQ37

131

M_B_DQ35

141

M_B_DQ34

143

M_B_DQ33

130

M_B_DQ32

132

M_B_DQ39

140

M_B_DQ38

142

M_B_DQ44

147

M_B_DQ40

149

M_B_DQ42

157

M_B_DQ43

159

M_B_DQ45

146

M_B_DQ41

148

M_B_DQ46

158

M_B_DQ47

160

M_B_DQ49

163

M_B_DQ48

165

M_B_DQ54

175

M_B_DQ55

177

M_B_DQ52

164

M_B_DQ53

166

M_B_DQ50

174

M_B_DQ51

176

M_B_DQ61

181

M_B_DQ56

183

M_B_DQ62

191

M_B_DQ63

193

M_B_DQ57

180

M_B_DQ60

182

M_B_DQ59

192

M_B_DQ58

194

M_B_DQ[63:0] [4]

SMDDR_VREF_DQ1_M3[6]

SMDDR_VREF_DQ1_M1 SMDDR_VREF_DQ1_M3

DDR3_DRAMRST#[3,13]

R483 0_6R483 0_6 R71 *0_6R71 *0_6

+3V

+SMDDR_VREF_DIMM

MBCLK2[9,30,35]

MBDATA2[9,30,35]

PM_EXTTS#0[13]

+3V

VREF DQ1 M2 Solution

+1.5VSUS

C84 1U/6.3V_4C84 1U/6.3V_4 C39 1U/6.3V_4C39 1U/6.3V_4 C66 1U/6.3V_4C66 1U/6.3V_4 C64 1U/6.3V_4C64 1U/6.3V_4

6/23 : Del M2 solution

A A

4/29 reserve M2 solution

C59 10U/6.3VS_6C59 10U/6.3VS_6 C111 10U/6.3VS_6C111 10U/6.3VS_6 C104 10U/6.3VS_6C104 10U/6.3VS_6 C53 10U/6.3VS_6C53 10U/6.3VS_6 C90 10U/6.3VS_6C90 10U/6.3VS_6 C96 10U/6.3VS_6C96 10U/6.3VS_6 C74 *10U/6.3V_6C74 *10U/6.3V_6 C125 10U/6.3V_8C125 10U/6.3V_8 C103 10U/6.3V_8C103 10U/6.3V_8

Place these Caps near So-Dimm1.

+0.75V_DDR_VTT

C254 1U/6.3V_4C254 1U/6.3V_4 C246 1U/6.3V_4C246 1U/6.3V_4 C238 1U/6.3V_4C238 1U/6.3V_4 C265 1U/6.3V_4C265 1U/6.3V_4 C260 10U/6.3V_6C260 10U/6.3V_6 C225 *10U/6.3V_6C225 *10U/6.3V_6

+3V

C669 0.1U/10V_4C669 0.1U/10V_4 C670 2.2U/6.3V_6C670 2.2U/6.3V_6

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ1

C195 0.1U/10V_4C195 0.1U/10V_4 C156 2.2U/6.3V_6C156 2.2U/6.3V_6

C594 0.1U/10V_4C594 0.1U/10V_4 C582 2.2U/6.3V_6C582 2.2U/6.3V_6

VREF DQ1 M1 Solution

DDR_VTTREF[5,13,43]

PD7

R90 *0_6R90 *0_6

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Custom

Date: Sheet

+1.5VSUS

R490

R490 1K/F_4

1K/F_4

SMDDR_VREF_DQ1_M1

R84

R84 1K/F_4

1K/F_4

DDR3 DIMM1-RVS (9.2H)

14 47Wednesday, October 13, 2010

U33H

U33A

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AJ21

NC#1

AK21

NC#2

AH16

PWRGOOD

AA30

PERSTB

Capilano Pro/Robson_M2

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP PCIE_CALRN

Y32

W33 W32

U33 U32

U30 U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30 Y29

C_PEG_RXN15

C_PEG_RXP14 C_PEG_RXN14

C_PEG_RXP13 C_PEG_RXN13

C_PEG_RXP12 C_PEG_RXN12

C_PEG_RXP11 C_PEG_RXN11

C_PEG_RXP10 C_PEG_RXN10

C_PEG_RXP9 C_PEG_RXN9

C_PEG_RXP8 C_PEG_RXN8

C_PEG_RXP7 C_PEG_RXN7

C_PEG_RXP6 C_PEG_RXN6

C_PEG_RXP5 C_PEG_RXN5

C_PEG_RXP4 C_PEG_RXN4

C_PEG_RXP3 C_PEG_RXN3

C_PEG_RXP2 C_PEG_RXN2

C_PEG_RXP1 C_PEG_RXN1

C_PEG_RXP0 C_PEG_RXN0

PCIE_CALRP PCIE_CALRNPWRGOOD_BUF

C_PEG_RXP15

Y33

C187 0.1U/10V_4C187 0.1U/10V_4 C193 0.1U/10V_4C193 0.1U/10V_4

C175 0.1U/10V_4C175 0.1U/10V_4 C189 0.1U/10V_4C189 0.1U/10V_4

C207 0.1U/10V_4C207 0.1U/10V_4 C215 0.1U/10V_4C215 0.1U/10V_4

C202 0.1U/10V_4C202 0.1U/10V_4 C208 0.1U/10V_4C208 0.1U/10V_4

C213 0.1U/10V_4C213 0.1U/10V_4 C224 0.1U/10V_4C224 0.1U/10V_4

C233 0.1U/10V_4C233 0.1U/10V_4 C245 0.1U/10V_4C245 0.1U/10V_4

C227 0.1U/10V_4C227 0.1U/10V_4 C239 0.1U/10V_4C239 0.1U/10V_4

C231 0.1U/10V_4C231 0.1U/10V_4 C242 0.1U/10V_4C242 0.1U/10V_4

C247 0.1U/10V_4C247 0.1U/10V_4 C256 0.1U/10V_4C256 0.1U/10V_4

C255 0.1U/10V_4C255 0.1U/10V_4 C259 0.1U/10V_4C259 0.1U/10V_4

C262 0.1U/10V_4C262 0.1U/10V_4 C264 0.1U/10V_4C264 0.1U/10V_4

C263 0.1U/10V_4C263 0.1U/10V_4 C270 0.1U/10V_4C270 0.1U/10V_4

C266 0.1U/10V_4C266 0.1U/10V_4 C271 0.1U/10V_4C271 0.1U/10V_4

C273 0.1U/10V_4C273 0.1U/10V_4 C275 0.1U/10V_4C275 0.1U/10V_4

C278 0.1U/10V_4C278 0.1U/10V_4 C279 0.1U/10V_4C279 0.1U/10V_4

C276 0.1U/10V_4C276 0.1U/10V_4 C277 0.1U/10V_4C277 0.1U/10V_4

R102 1.27K/F_4R102 1.27K/F_4 R94 2K/F_4R94 2K/F_4

+1.0V_VGA

PEG_RX15 [3] PEG_RX#15 [3]

PEG_RX14 [3] PEG_RX#14 [3]

PEG_RX13 [3] PEG_RX#13 [3]

PEG_RX12 [3] PEG_RX#12 [3]

PEG_RX11 [3] PEG_RX#11 [3]

PEG_RX10 [3] PEG_RX#10 [3]

PEG_RX9 [3] PEG_RX#9 [3]

PEG_RX8 [3] PEG_RX#8 [3]

PEG_RX7 [3] PEG_RX#7 [3]

PEG_RX6 [3] PEG_RX#6 [3]

PEG_RX5 [3] PEG_RX#5 [3]

PEG_RX4 [3] PEG_RX#4 [3]

PEG_RX3 [3] PEG_RX#3 [3]

PEG_RX2 [3] PEG_RX#2 [3]

PEG_RX1 [3] PEG_RX#1 [3]

PEG_RX0 [3] PEG_RX#0 [3]

+1.8V_DPC_VDD18 +1.8V_DPA_VDD18

+1.0V_DPC_VDD10

+1.8V_DPC_VDD18

+1.0V_DPC_VDD10

R426 150/F_4R426 150/F_4 R424 150/F_4R424 150/F_4

+1.8V_DPE_VDD18

+1.0V_DPE_VDD10

+1.8V_DPE_VDD18

+1.0V_DPE_VDD10

R460 150/F_4R460 150/F_4

DPCD_CALR

DPEF_CALR

CLK_PCIE_VGA CLK_PCIE_VGA#

R198 *0_4/SR198 *0_4/S

PEG_TX15 PEG_TX#15

PEG_TX14 PEG_TX#14

PEG_TX13 PEG_TX#13

PEG_TX12 PEG_TX#12

PEG_TX11 PEG_TX#11

PEG_TX10 PEG_TX#10

PEG_TX9 PEG_TX#9

PEG_TX8 PEG_TX#8

PEG_TX7 PEG_TX#7

PEG_TX6 PEG_TX#6

PEG_TX5 PEG_TX#5

PEG_TX4 PEG_TX#4

PEG_TX3 PEG_TX#3

PEG_TX2 PEG_TX#2

PEG_TX1 PEG_TX#1

PEG_TX0 PEG_TX#0

VGA_RST#

PEG_TX15[3] PEG_TX#15[3]

D D

C C

B B

Seymour/Whistler:SWAPLOCKA Madison/Capilano :NC

R62

R62 10K/F_4

10K/F_4

PEG_TX14[3] PEG_TX#14[3]

PEG_TX13[3] PEG_TX#13[3]

PEG_TX12[3] PEG_TX#12[3]

PEG_TX11[3] PEG_TX#11[3]

PEG_TX10[3] PEG_TX#10[3]

PEG_TX9[3] PEG_TX#9[3]

PEG_TX8[3] PEG_TX#8[3]

PEG_TX7[3]

PEG_TX#7[3]

PEG_TX6[3]

PEG_TX#6[3]

PEG_TX5[3]

PEG_TX#5[3]

PEG_TX4[3]

PEG_TX#4[3]

PEG_TX3[3]

PEG_TX#3[3]

PEG_TX2[3]

PEG_TX#2[3]

PEG_TX1[3]

PEG_TX#1[3]

PEG_TX0[3]

PEG_TX#0[3]

CLK_PCIE_VGA[9]

CLK_PCIE_VGA#[9]

PEGX_RST#[37]

PV Change to Short Pad

U33H

AP20

DPC_VDD18#1

AP21

DPC_VDD18#2

AP13

DPC_VDD10#1

AT13

DPC_VDD10#2

AN17

DPC_VSSR#1

AP16

DPC_VSSR#2

AP17

DPC_VSSR#3

AW14

DPC_VSSR#4

AW16

DPC_VSSR#5

AP22

DPD_VDD18#1

AP23

DPD_VDD18#2

AP14

DPD_VDD10#1

AP15

DPD_VDD10#2

AN19

DPD_VSSR#1

AP18

DPD_VSSR#2

AP19

DPD_VSSR#3

AW20

DPD_VSSR#4

AW22

DPD_VSSR#5

AW18

DPCD_CALR

DP E/F POWER

AH34

DPE_VDD18#1

AJ34

DPE_VDD18#2

AL33

DPE_VDD10#1

AM33

DPE_VDD10#2

AN34

DPE_VSSR#1

AP39

DPE_VSSR#2

AR39

DPE_VSSR#3

AU37

DPE_VSSR#4

AF34

DPF_VDD18#1

AG34

DPF_VDD18#2

AK33

DPF_VDD10#1

AK34

DPF_VDD10#2

AF39

DPF_VSSR#1

AH39

DPF_VSSR#2

AK39

DPF_VSSR#3

AL34

DPF_VSSR#4

AM34

DPF_VSSR#5

AM39

DPEF_CALR

Capilano Pro/Robson_M2

DP A/B POWERDP C/D POWER

DPA_VDD18#1 DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

DPB_VDD18#1 DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPC_PVDD

DPD_PVDD

NC_DPF_PVDD NC_DPF_PVSS

DPA_PVDD DPA_PVSS

DPB_PVDD DPB_PVSS

DPC_PVSS

DPD_PVSS

DPE_PVDD DPE_PVSS

AN24 AP24

AP31 AP32

AN27 AP27 AP28 AW24 AW26

AP25 AP26

AN33 AP33

AN29 AP29 AP30 AW30 AW32

AW28

AU28 AV27

AV29 AR28

AU18 AV17

AV19 AR18

AM37 AN38

AL38 AM35

DPAB_CALR

( DPA/B_VDD10 : 1.0V @ 115mA+115mA)

+1.0V_DPA_VDD10

C92

C91

10U/6.3V_8

+1.8V_DPA_VDD18

C91

1U/6.3V_4

( DPA/B_PVDD : 1.8V@20mA+20mA)

+1.8V_DPB_PVDD

C51

C540

10U/6.3V_8

C540

1U/6.3V_4

( DPC/D_PVDD:1.8V@20mA+20mA)

+1.8V_DPC_PVDD

( DPE/F_PVDD1.8V@20mA+20mA)

+1.8V_DPE_PVDD

C568

C565

10U/6.3V_8

C568

0.1U/10V_4

C100

0.1U/10V_4

C531

0.1U/10V_4

C569

0.1U/10V_4

+1.0V_VGA

HCB1608KF-181T15/1.5A_6

+1.8V_VGA

HCB1608KF-181T15/1.5A_6

+1.8V_VGA

L35

HCB1608KF-181T15/1.5A_6

( DPE/F_VDD18 : 1.8V@200mA+200mA)

+1.8V_DPE_VDD18

C581

10U/6.3V_8

+1.8V_DPA_VDD18

C528

C528 10U/6.3VS_6

10U/6.3VS_6

SI Change

+1.8V_DPC_VDD18

C583

C580

1U/6.3V_4

C583

0.1U/10V_4

( DPA/B_VDD18 : 1.8V@200mA+200mA)

C532

0.1U/10V_4

1U/6.3V_4

( DPC/D_VDD18 : 1.8V@200mA+200mA)

+1.8V_VGA+1.8V_VGA+1.8V_VGA

C124

0.1U/10V_4

A A

MV EMI Request

C588

C773

0.1U/10V_4

SI Del R43,R38,C57

( VDD10 M97 1.0V/M96 1.1V)

( DPE/F_VDD10 : 1.0V@115mA+115mA )

+1.0V_DPE_VDD10

C118

C119

C113

1U/6.3V_4

10U/6.3V_8

1U/6.3V_4

( DPC/D_VDD10 : 1.0V@115mA+115mA)

+1.0V_DPC_VDD10

C119

0.1U/10V_4

+1.0V_VGA

L14

HCB1608KF-181T15/1.5A_6

+1.0V_VGA

C542

L37

HCB1608KF-181T15/1.5A_6

+1.8V_VGA

L31

+1.0V_VGA [17,19,43] +1.8V_VGA [17,19,42]

+1.8V_VGA

PD7

RTQLGEV"<"NZ517*Jwtqp"Tkxgt+

Swcpvc"Eqorwvgt"Kpe0

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

CATI APILANO-PRO (MEM)1/5

15 47Wednesday, October 13, 2010

+ 33 hidden pages

Quanta LX3, Pavilion dv6, LX5 (Huror River) Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual