Quanta LG9 Schematic
5
www.schematic-x.blogspot.com
4
3
2
1
DIS (15")
D D
DDR4 2133MHz SODIMM1
8GB Max.
DDR4 2133MHz SODIMM2
8GB Max. DDR CHB
C C
B B
Intel SKL/KBL ULT Platform Block Diagram
PAGE 17
PAGE 18
M.2 2280-S3 SSD
PAGE 32
SATA HDD
2.5" 7.2/9.5mm
PAGE 29
System BIOS
SPI ROM
PAGE 10
DDR4 2133MHz
DDR4 2133MHz
6GB/s
PCIEx2 / SATAx1
6GB/s
DDR CHA
SATA
PCIE
SATA
SPI
LPC
SKL/KBL U
Processor
Processor : Daul Core
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
HDA
PAGE 2~16
PCIE
Azalia
USB3.0
USB2.0
PCIE Gen 1 x 1 Lane
PCIE
eDP
DDI
PCI-E
X4 Lane
eDP x2
USB2.0 CONN
Port 6
LCD Connector
DB PAGE 27
LG9
N16S-GTR-S
N16V-GTR1
25W, 23x23mm
PAGE 19~22
PAGE 25
USB3.0
CONN
Port 1 Port 1 Port 2 Port 2 Port 3 & 4 Port 4
PAGE 26
USB3.0
CONN
PAGE 26
Camera
Port 3
VRAM GDDR3 x 4pcs
256Mx16 900MHz
TOP
USB3.0 Type C
PAGE 25
HDMI
PCB 6L STACK UP
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : BOT
PAGE 23
PAGE 26
PAGE 28
01
Keyboard
Touch Pad
FAN
PAGE 29
PAGE 29
Embedded Controller
iTE 8987
Power :
Package : LQPF128
Size : 14 x 14 (mm)
PAGE 34
Audio Codec
ALC255-CG
Package : MQFN48
Size : 6 x 6 (mm)
PAGE 27
Card Reader
RTS5227S-GRT
Power :
Package :
Size :
PAGE 30
LAN Controller
RTL8111H-CG(Giga)
Power :
Package :
PAGE 33
NGFF Card
WLAN / BT Combo
Port 7
PAGE 34
PAGE 29
Speaker
A A
Combo Jack
5
4
3
PAGE 29
PAGE 27
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet of
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
1
1 49Wednesday, July 20, 2016
1 49Wednesday, July 20, 2016
1 49Wednesday, July 20, 2016
1A
1A
1A
of
of
5
[4,10..13,15..21,25..27,29,30,32,33,35,41,45,46]
+3V
[4,6,16,34,35,40]
+1.0V
[4..6,9,13,40,41]
+VCCSTPLL
D D
C C
HDMI 1.4
0317 CQ
Del R868 & R869 2.2K PU +3V (
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 ohms
SDVO_CLK[26]
SDVO_DATA[26]
+1.0V
IN_D2#[26]
IN_D2[26]
IN_D1#[26]
IN_D1[26]
IN_D0#[26]
IN_D0[26]
IN_CLK#[26]
IN_CLK[26]
4
R3 24.9/F_4
3
?
IN_D2#
IN_D2
IN_D1#
IN_D1
IN_D0#
IN_D0
IN_CLK#
IN_CLK
)
EDP_RCOMP
U1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
Need apply PN
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
INT_EDP_TXN0
C47
INT_EDP_TXP0
C46
INT_EDP_TXN1
D46
INT_EDP_TXP1
C45
A45
B45
A47
need surport to FHD 2 Lane
B47
INT_EDP_AUXN
E45
INT_EDP_AUXP
F45
EDP_DISP_UTIL
B52
G50
F50
0224 CQ
E48
Del INT_HDMI_AUXN & INT_HDMI_AUXN
F48
HDMI 1.4
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
?1 OF 20
HDMI_HPD_CON
ULT_EDP_HPD
PCH_EDP_BLON
PCH_DPST_PWM
PCH_DISP_ON
2
INT_EDP_TXN0 [25]
INT_EDP_TXP0 [25]
INT_EDP_TXN1 [25]
INT_EDP_TXP1 [25]
INT_EDP_AUXN [25]
INT_EDP_AUXP
TP1
HDMI_HPD_CON
PCH_EDP_BLON [25]
PCH_DPST_PWM [25]
PCH_DISP_ON [25]
[25]
0309 CQ
HDMI_HPD_CON PU 10K +3V (R1) & PD 100K (R2)
ULT_EDP_HPD (
+3V
[26]
R1
*10K_4
R2
100K_4
ULT_EDP_HPD [25]
Reserve EDP_HPD opposites circuit!
1
02
)
Close to EC
+VCCSTPLL
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
B B
R51K_4
PM_THRMTRIP#
EC_PECI[35]
H_PROCHOT#[35,41]
PM_THRMTRIP#[35]
XDP_BPM0[16]
XDP_BPM1[16]
+VCCSTPLL
R6 *49.9/F_4
R4 499/F_4
R8 49.9/F_4
R11 49.9/F_4
R12 49.9/F_4
R14 49.9/F_4
TP8504
TP8505
TP200
TP4
TP5
TP6
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
3D_FW_GPIO_R
CPU_GP1
CPU_GP2
CPU_GP3
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
H66
H65
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
Rcomp < 600mil
A A
5
4
U1D
*SKL_ULT
REV = 1
SKL_ULT
CPU MISC
3
?
4 OF 20
Need apply PN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
BOM
XDP_TCK0
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST#_CPU
B59
JTAG_TCK_PCH
B56
JTAG_TDI_PCH
D59
JTAG_TDO_PCH
A56
JTAG_TMS_PCH
C59
XDP_TRST#_CPU
C61
JTAGX_PCH
A59
XDP_TCK0
XDP_TDI_CPU
XDP_TDO_CPU
XDP_TMS_CPU
XDP_TRST#_CPU
JTAG_TCK_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TMS_PCH
XDP_TRST#_CPU
JTAGX_PCH
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
2
[16]
[16]
[16]
[16]
[2,16]
[16]
[16]
[16]
[16]
[2,16]
[16]
PLACE NEAR CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TDO_CPU
R10*51_4
R1351_4
R1551_4
R1651_4
R1851_4
Close to Chipset
+1.0V
R17 *51_4
R19 *51_4
R20 *51_4
H_PROCHOT#
XDP_TCK0
XDP_TRST#_CPU
R21 1K_4
R22 51_4
R23 51_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+1.0V
+1.0V
SKL-01 [eDP/DDI/MISC]
SKL-01 [eDP/DDI/MISC]
SKL-01 [eDP/DDI/MISC]
1
1A
1A
2 49Wednesday, July 20, 2016
2 49Wednesday, July 20, 2016
2 49Wednesday, July 20, 2016
1A
of
of
of
5
[17]
M_A_DQSN[7:0]
[17]
M_A_DQSP[7:0]
[18]
M_B_DQSN[7:0]
[18]
M_B_DQSP[7:0]
[17]
M_A_DQ[63:0]
[18]
M_B_DQ[63:0]
[6,17,18,38,40,48]
D D
C C
B B
+1.2VSUS
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
*SKL_ULT
REV = 1
Need apply PN
?
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
NIL-DDR CH A
2 OF 20
4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
3
2
SkyLake ULT Processor (DDR4)
Non-Interleave / side by side
?
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
M_A_A5
BA51
M_A_A9
BB54
M_A_A6
BA52
M_A_A8
AY52
M_A_A7
AW52
M_A_BG#0
AY55
M_A_A12
AW54
M_A_A11
BA54
BA55
AY54
M_A_A13
AU46
AU48
AT46
AU50
AU52
M_A_A2
AY51
AT48
M_A_A10
AT50
M_A_A1
BB50
M_A_A0
AY50
M_A_A3
BA50
M_A_A4
BB52
M_A_DQSN0
AM70
M_A_DQSP0
AM69
M_A_DQSN1
AT69
M_A_DQSP1
AT70
M_A_DQSN2
AH66
M_A_DQSP2
AH65
M_A_DQSN3
AG69
M_A_DQSP3
AG70
M_A_DQSN4
BA64
M_A_DQSP4
AY64
M_A_DQSN5
AY60
M_A_DQSP5
BA60
M_A_DQSN6
AR66
M_A_DQSP6
AR65
M_A_DQSN7
AR61
M_A_DQSP7
AR60
M_A_ALERT#
AW50
M_A_PARITY M_B_ALERT#
AT52
SM_VREF
AY67
SMDDR_VREF_DQ0_M3
AY68
SMDDR_VREF_DQ1_M3
BA67
DDR_VTT_CNTL
AW67
M_A_CLKN0 [17]
M_A_CLKP0 [17]
M_A_CLKN1 [17]
M_A_CLKP1 [17]
M_A_CKE0 [17]
M_A_CKE1 [17]
M_A_CS#0
M_A_CS#1
M_A_DIM0_ODT0
M_A_DIM0_ODT1
M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7
M_A_BG#0
M_A_A12
M_A_A11
M_A_ACT#
M_A_BG#1
M_A_A13
M_A_CAS#
M_A_WE#
M_A_RAS#
M_A_BS#0
M_A_A2
M_A_BS#1
M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
[17]
M_A_ALERT#
M_A_PARITY
SM_VREF [17]
TP7
SMDDR_VREF_DQ1_M3 [18]
DDR_VTT_CNTL [4,18]
[17]
[17]
20mils width
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U1C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
REV = 1
SKL_ULT
Need apply PN
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
NIL-DDR CH B
3 OF 20
BOM
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_A13
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_B_DQSN0
M_B_DQSP0
M_B_DQSN1
M_B_DQSP1
M_B_DQSN2
M_B_DQSP2
M_B_DQSN3
M_B_DQSP3
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7
M_B_DQSP7
M_B_PARITY
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
M_B_CLKN0
M_B_CLKN1
M_B_CLKP0
M_B_CLKP1
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
M_B_DIM0_ODT0
M_B_DIM0_ODT1
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_BG#0
M_B_A12
M_B_A11
M_B_ACT#
M_B_BG#1
M_B_A13
M_B_CAS#
M_B_WE#
M_B_RAS#
M_B_BS#0
M_B_A2
M_B_BS#1
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_B_ALERT#
M_B_PARITY
R25 121/F_4
R26 80.6/F_4
R27 100/F_4
DG 543016 page162
1
03
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
[18]
+1.2VSUS
R24
470/F_4
[18]
[18]
DDR4_DRAMRST# [17,18]
A A
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL-02 [DDR4]
SKL-02 [DDR4]
SKL-02 [DDR4]
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
3 49Wednesday, July 20, 2016
3 49Wednesday, July 20, 2016
3 49Wednesday, July 20, 2016
1A
1A
1A
of
of
of
5
+3V_DEEP_SUS[10..12,14..16,18]
SYS_PWROK[16]
SUSWARN#_EC[35]
DDR_VTT_CNTL[3,18]
+VCCSTPLL[2,5,6,9,13,40,41]
+3V_RTC_2
PLTRST#[16,19,30..33,35]
SYS_RESET#
EC_PWROK[16,35]
PCIE_WAKE#[30,31,33,35]
+3V
+3VS5[10,15,16,27,31,32,35,37..40,44,45,48]
+1.0V
DSWROK_EC_R
R29 *10K_4
C1 *0.1U/16V_4
R33 *0_4/S
R17755 *0_4
0701 CQ
Add R17755 0ohm (
[2,10..13,15..21,25..27,29,30,32,33,35,41,45,46]
[2,6,16,34,35,40]
[13,15,34]
D D
C C
B B
RSMRST#[35]
SUSWARN#
SUSACK#_EC[35]
PLTRST#(CLG)
Rise/Fall time less than 100ns
R34 *0_4/S
0713 CQ
Change F/P S0402
For DS3 -->Ra
Non-DS3 -->Rb
DSWROK_EC[35]
RSMRST#
R32*0_4
PLTRST#
R52
100K/F_4
EC1
*220P/50V_4
Rb
R42 0_4
R46 *0_4
Ra
0712 CQ
R42 for sequence
[16]
System PWR_OK(CLG)
R53 *0_4/S
EC_PWROKSYS_PWROK
R54
10K/F_4
4
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
EC_PWROK
DSWROK_EC_R
SUSWARN#
SUSACK#
PCIE_WAKE#
LAN_WAKE#
DDR_VTT_CNTL_R
)
U1K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
REV = 1
?
SKL_ULT
+1.0V +3VS5+5VS5
R43
15K_4
+1.0V_PWRGD_G1
C2
0.1U/16V_4
11 OF 20
R51
100K_4
HWPG[16,35,37..39]
2
Need apply PN
1 3
3
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
GPP_B2/VRALERT#
R44
100K_4
+1.0V_PWRGD_G2
0317 CQ
Add Net name
Q2
METR3904-G
INTRUDER#
GPP_B11/EXT_PW R_GATE#
2
1
04
PCH_SLP_S0_N
AT11
AP15
BA16
AY16
SLP_SUS#_EC
AN15
AW15
BB17
GPD9
AN16
BA15
DNBSWON#
AC_PRESENT_EC
AY15
RF_OFF_PCH
AU13
AU11
INTRUDER#_R
AP16
AM10
GPP_B2
AM11
?
R45
10K_4
3
Q1
2
2N7002K
1
R49
100K_4
R305 1M_4
TP8
TP9
D1 MEK500V-40
PCH_SLP_S0_N [16,35]
[16,35]
SUSB#
[16,35]
SUSC#
[16]
SLP_S5#
SLP_SUS#_EC
[16]
SLP_A#
DNBSWON# [35]
AC_PRESENT_EC
RF_OFF_PCH
+3V_RTC_2
21
H_VCCST_PWRGD_R
[35]
[35]
[31]
PCH Pull-high/low(CLG)
SUSWARN#
SUSACK#
RF_OFF_PCH
PCIE_WAKE#
AC_PRESENT_EC
LAN_WAKE#
SYS_RESET#
RSMRST#
DSWROK_EC
+1.0V
+VCCSTPLL
R47
R48
1K_4
*1K_4
C3
*10P/50V_4
H_VCCST_PWRGD trace 0.3" - 1.5"
R28 *10K_4
R30 10K_4
R31 10K_4
R35 1K_4
R37 *10K_4
R38 *10K_4
R39 10K_4
R40 10K_4
R41 100K/F_4
R50 60.4/F_4
+3V_DEEP_SUS
+3VS5
+3V
H_VCCST_PWRGD
A A
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet of
SKL-03 [PowerManger]
SKL-03 [PowerManger]
SKL-03 [PowerManger]
1
4 49Wednesday, July 20, 2016
4 49Wednesday, July 20, 2016
4 49Wednesday, July 20, 2016
1A
1A
1A
of
of
5
[43]
[2,4,6,16,34,35,40]
[6]
[2,4,6,9,13,40,41]
Under CPU
C9
C4
D D
C C
10U/6.3V_6
C19
10U/6.3V_4
C34
22U/6.3V_6
+VCC_EDRAM
+VCC_EDRAM
22U/6.3V_6
C20
10U/6.3V_4
C35
22U/6.3V_6
C292
*1U/6.3V_4
22U/6.3V_6
C21
10U/6.3V_4
C36
22U/6.3V_6
C291
*1U/6.3V_4
+VCC_EOPIO
+VCC_CORE
+1.0V
+VCCSTG
+VCCSTPLL
0508 CQ
Change C14 FP to R0805
C14
C5
47U/6.3VS_8
22U/6.3V_6
C22
C23
10U/6.3V_4
10U/6.3V_4
C38
C37
22U/6.3V_6
22U/6.3V_6
+1.8V_DEEP_SUS
C290
*1U/6.3V_4
C293
*1U/6.3V_4
C298
*10U/6.3V_4
C299
*10U/6.3V_4
R275 *0_4
0328 CQ
Add VID[0:1]_VCC_EDRAM to Power page
C16
22U/6.3V_6
C24
10U/6.3V_4
C39
22U/6.3V_6
VID0_VCC_EDRAM[44]
VID1_VCC_EDRAM[44]
[9,15,39]
[44]
[44]
C17
22U/6.3V_6
C25
10U/6.3V_4
VCCOPC_1.8
Close CPU
C295
C294
*1U/6.3V_4
*10U/6.3V_4
GT3e => Stuff
GT2 => Un-Stuff
C296
*1U/6.3V_4
C297
*1U/6.3V_4
+VCC_CORE
+VCC_CORE
C40
47U/6.3VS_8
+1.8V_DEEP_SUS
+VCC_EOPIO
+VCC_EDRAM
C18
22U/6.3V_6
C41
47U/6.3VS_8
4
?
SKL_ULT
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
C42
47U/6.3VS_8
U1L
VCC_A30
VCC_A34
32A
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
*SKL_ULT
REV = 1
C43
47U/6.3VS_8
+VCC_CORE +VCC_CORE
CPU POWER 1 OF 4
3.2A
50mA
2A
12 OF 20
C44
47U/6.3VS_8
Need apply PN
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
BOM
C46
C45
47U/6.3VS_8
47U/6.3VS_8
?
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
47U/6.3VS_8
3
C6
1U/6.3V_4
C26
1U/6.3V_4
H_CPU_SVIDALRT#
VR_SVID_CLK_R
H_CPU_SVIDDAT
C47
C7
1U/6.3V_4
C27
1U/6.3V_4
R55 100/F_4
R56 100/F_4
+VCCSTG
2
Under CPU
C8
1U/6.3V_4C10
C28
1U/6.3V_4
C11
1U/6.3V_4
C29
1U/6.3V_4
+VCC_CORE
VCC_SENSE [41]
VSS_SENSE [41]
C12
1U/6.3V_4
C30
1U/6.3V_4
C13
1U/6.3V_4
C31
1U/6.3V_4
Close CPU
C15
1U/6.3V_4
C32
1U/6.3V_4
100- ±1%
pull-up to VCC
near processor.
C33
1U/6.3V_4
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
R58 220/F_4
R57
56.2/F_4
C48
*0.1U/16V_4
SVID ALERT
1
05
VR_SVID_ALERT# [41]
R61
100/F_4
+VCCSTPLL
R59
*54.9/F_4
SVID CLK
VR_SVID_CLK [41]
0713 CQ
Change F/P S0402
R62 *0_4/S
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet of
SVID DATA
VR_SVID_DATA [41]
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKL-04 [POWER-1]
SKL-04 [POWER-1]
SKL-04 [POWER-1]
1
1A
1A
5 49Wednesday, July 20, 2016
5 49Wednesday, July 20, 2016
5 49Wednesday, July 20, 2016
1A
of
of
C54
C55
C52
10U/6.3V_4
C53
10U/6.3V_4
10U/6.3V_4
C49
B B
A A
5
10U/6.3V_4
C50
10U/6.3V_4
C51
10U/6.3V_4
4
10U/6.3V_4
C56
10U/6.3V_4
3
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
VR_SVID_CLK_R
H_CPU_SVIDDAT
2
R60 *0_4/S
+VCCSTPLL
5
C61
10U/6.3V_6
C75
10U/6.3V_6
[2,4,5,9,13,40,41]
[41,43]
[3,17,18,38,40,48]
[9,15,16,39,40]
[2,4,16,34,35,40]
[13,29,31,34..37,44]
[40]
C62
1U/6.3V_4
C76
10U/6.3V_6
+VCCSTG
+VCCPLL_OC+1.2VSUS
+VCCPLL+VCCSTPLL
+1.2VSUS
C58
C57
1U/6.3V_4
1U/6.3V_4
*10U/6.3V_6
C91
1U/6.3V_4
C92
1U/6.3V_4
Close CPU Under CPU
+3VPCU
R71
20K/F_4
For 75 degree, 1.2v limit, (HW)
THER_CPU
R74
100K_4 NTC
C101
0.1U/16V_4
1 2
C59
+VCCSTPLL
+VCCSA
+1.2VSUS
+1.0V_DEEP_SUS
+1.0V
+3VPCU
+1.2V_VCCPLL_OC
Under CPU
D D
10U/6.3V_6
C60
10U/6.3V_6
C74
C73
10U/6.3V_6
Close CPU
+VCCSTPLL
+1.0V
+VCCIO
C C
+1.2V_VCCPLL_OC
R63 *0_4/S
R64 *0_4
R65 *0_4
0713 CQ
Change F/P S0402
R68 *0_4
R69 *0_4/S
R70 *0_4/S
Under CPU
+VCCSTG +VCCPLL_OC
C99
1U/6.3V_4
C100
1U/6.3V_4
Close A18 Ball
+VCCSTPLL
B B
C104
*1U/6.3V_4
C105
*22U/6.3V_6
4
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
THRM_MOINTOR2 [35]
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
SKL_ULT
U1N
CPU POWER 3 OF 4
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
*SKL_ULT
REV = 1
Need apply PN
?
2.8A
60mA
20mA
120mA
130mA
14 OF 20
VCCIO
3.1A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
5.1A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
3
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C63
1U/6.3V_4
+VCCSA
C77
1U/6.3V_4
C64
1U/6.3V_4
C78
1U/6.3V_4
C93
10U/6.3V_4
IO Thrm Protect
For PIPE USEFor CPU USE
+3VPCU
R73
20K/F_4
For 75 degree, 1.2v limit, (HW)
THER_PIPE
R76
100K_4 NTC
C103
0.1U/16V_4
1 2
2
Under CPU Close CPU
C68
C65
1U/6.3V_4
C66
10U/6.3V_4
C67
10U/6.3V_4
10U/6.3V_4
C69
1U/6.3V_4
Under CPU
C79
1U/6.3V_4
C80
1U/6.3V_4
C81
1U/6.3V_4
C82
1U/6.3V_4
C83
1U/6.3V_4
C84
10U/6.3V_4
Close CPU
C95
10U/6.3V_4
C96
10U/6.3V_4
C97
10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C98
10U/6.3V_4
C94
10U/6.3V_4
VSSSA_SENSE [41]
VCCSA_SENSE [41]
THRM_MOINTOR1 [35]
C70
1U/6.3V_4
C85
10U/6.3V_4
R66 100/F_4
R67 100/F_4
C71
1U/6.3V_4
+VCCIO
C86
10U/6.3V_4
C72
1U/6.3V_4
+VCCIO
C87
10U/6.3V_4
C88
10U/6.3V_4
1
C89
10U/6.3V_4
C90
10U/6.3V_4
06
Close CPU
C107
1U/6.3V_4
C109
10U/6.3V_6
+VCCPLL
5
C110
10U/6.3V_6
C111
10U/6.3V_6
C112
10U/6.3V_6
C113
10U/6.3V_6
C114
1U/6.3V_4
C115
1U/6.3V_4
4
C116
1U/6.3V_4
C117
1U/6.3V_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet of
SKL-05 [POWER-2]
SKL-05 [POWER-2]
SKL-05 [POWER-2]
1
6 49Wednesday, July 20, 2016
6 49Wednesday, July 20, 2016
6 49Wednesday, July 20, 2016
1A
1A
1A
of
of
+VCCSTPLL
C106
1U/6.3V_4
+1.2VSUS
A A
C108
10U/6.3V_6
Close to CPU
5
[41,42]
+VCCGT
[5,43]
+VCC_CORE
[3,6,17,18,38,40,48]
+1.2VSUS
Under CPU
D D
C146
1U/6.3V_4
C152
C C
B B
1U/6.3V_4
C119
10U/6.3V_4
C130
10U/6.3V_4
C147
1U/6.3V_4
C153
1U/6.3V_4
C120
10U/6.3V_4
C131
10U/6.3V_4
C148
1U/6.3V_4
C154
1U/6.3V_4
C121
10U/6.3V_4
C137
10U/6.3V_4
C149
1U/6.3V_4
C155
1U/6.3V_4
4
?
SKL_ULT
57A
BOM
13 OF 20
7A
Need apply PN
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
U1M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
REV = 1
+VCCGT
C118
10U/6.3V_4
C138
10U/6.3V_4
C150
1U/6.3V_4
C156
1U/6.3V_4
VCCGT_SENSE[41]
VSSGT_SENSE[41]
C128
10U/6.3V_4
C139
10U/6.3V_4
C151
1U/6.3V_4
C157
1U/6.3V_4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
3
+VCCGT
Close CPU
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
C122
47U/6.3VS_8
C129
22U/6.3V_6
C142
22U/6.3V_6
+VCCGTX
C300
*22U/6.3V_6
GT3e => Stuff
GT2 => Un-Stuff
C123
47U/6.3VS_8
C132
22U/6.3V_6
C143
22U/6.3V_6
C301
*22U/6.3V_6
R276 *0_8
R277 *0_8
C124
47U/6.3VS_8
C133
22U/6.3V_6
C144
22U/6.3V_6
C302
*22U/6.3V_6
+VCCGT+VCCGTX
C125
47U/6.3VS_8
C134
22U/6.3V_6
C145
22U/6.3V_6
C303
*22U/6.3V_6
2
C126
47U/6.3VS_8
C135
22U/6.3V_6
C304
*22U/6.3V_6
C127
47U/6.3VS_8
C136
22U/6.3V_6
C140
22U/6.3V_6
C141
22U/6.3V_6
1
07
A A
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet of
SKL-06 [POWER-3]
SKL-06 [POWER-3]
SKL-06 [POWER-3]
1
7 49Wednesday, July 20, 2016
7 49Wednesday, July 20, 2016
7 49Wednesday, July 20, 2016
1A
1A
1A
of
of
5
4
3
2
1
08
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AA2
AA4
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
U1P
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 1 OF 3
Need apply PN
?
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
?
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
BA45
U1Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F68
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 2 OF 3
?
17 OF 20
Need apply PNNeed apply PN
BA49
VSS
BA53
VSS
BA57
VSS
BA6
VSS
BA62
VSS
BA66
VSS
BA71
VSS
BB18
VSS
BB26
VSS
BB30
VSS
BB34
VSS
BB38
VSS
BB43
VSS
BB55
VSS
BB6
VSS
BB60
VSS
BB64
VSS
BB67
VSS
BB70
VSS
C1
VSS
C25
VSS
C5
VSS
D10
VSS
D11
VSS
D14
VSS
D18
VSS
D22
VSS
D25
VSS
D26
VSS
D30
VSS
D34
VSS
D39
VSS
D44
VSS
D45
VSS
D47
VSS
D48
VSS
D53
VSS
D58
VSS
D6
VSS
D62
VSS
D66
VSS
D69
VSS
E11
VSS
E15
VSS
E18
VSS
E21
VSS
E46
VSS
E50
VSS
E53
VSS
E56
VSS
E6
VSS
E65
VSS
E71
VSS
F1
VSS
F13
VSS
F2
VSS
F22
VSS
F23
VSS
F27
VSS
F28
VSS
F32
VSS
F33
VSS
F35
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F37
F38
F4
F40
F42
BA41
XGND
0720 CQ
Change J35 & F37 GND to XGND
BOM
?
U1R
?
D D
XGND
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
18 OF 20
*SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
?
A A
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet of
SKL-07 [GND]
SKL-07 [GND]
SKL-07 [GND]
1
8 49Wednesday, July 20, 2016
8 49Wednesday, July 20, 2016
8 49Wednesday, July 20, 2016
1A
1A
1A
of
of
5
+1.8V_DEEP_SUS[5,15,39]
+1.0V_DEEP_SUS[15,16,39,40]
TP8506
D D
C C
B B
TP8507
TP8508
TP8509
TP8511
TP8510
TP8512
TP8514
TP8513
TP8515
TP8517
TP8516
TP8518
TP8520
TP8519
TP8521
TP8523
TP8522
CFG0
CFG1
CFG2
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
+1.0V_DEEP_SUS
CFG0-19 need Reserve TP
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
[16]
R78 49.9/F_4
R79 *1K_4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
4
3
2
1
09
?
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
U1S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
*SKL_ULT
REV = 1
SKL_ULT
RESERVED SIGNALS-1
BOM
19 OF 20
Need apply PN
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
RSVD_TP_AW71
RSVD_TP_AW70
PROC_SELECT#
TP5
TP6
TP4
TP1
TP2
ZVM#
MSM#
?
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
R80 *0_4/S
D71
C70
C54
D54
0713 CQ
Change F/P S0402
AY4
BB3
AY71
R81 *0_4/S
AR56
AW71
0311 CQ
AW70
platform use SKL /KBL Iris CPU and merge +VCC_EDRAM and +VCC_EOPIO power design
SOC side control pin ZVM# need contact power IC side LP#
AP56
C64
R82 *100K/F_4
+VCCSTPLL
+1.8V_DEEP_SUS
R77 *0_4
LP#
C158
*1U/6.3V_4
Close to CPU
within 100mil
[44]
AW69
AW68
AU56
AW48
C7
U12
U11
H11
U1T
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
*SKL_ULT
REV = 1
SKL_ULT
?
SPARE
20 OF 20
Need apply PN
F6
RSVD_F6
E3
RSVD_E3
C11
RSVD_C11
B11
RSVD_B11
A11
RSVD_A11
D12
RSVD_D12
C12
RSVD_C12
F52
RSVD_F52
?
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R83 *1K_4
R84 1K_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
SKL-08 [RSV]
SKL-08 [RSV]
SKL-08 [RSV]
1
9 49Wednesday, July 20, 2016
9 49Wednesday, July 20, 2016
9 49Wednesday, July 20, 2016
1A
1A
1A
of
of
of
5
+3V_DEEP_SUS [4,11,12,14..16,18]
+3V [2,4,11..13,15..21,25..27,29,30,32,33,35,41,45,46]
+5V [26,27,29,45]
+1.0V [2,4,6,16,34,35,40]
+3VS5 [4,15,16,27,31,32,35,37..40,44,45,48]
D D
C C
4
3
2
1
10
?
U1E
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
TP13
SIO_EXT_SMI#[35]
PCI_SERR#[35]
TP14
TP15
TP16
EC_RCIN#[35]
SERIRQ[30,35]
SPI1_CLK
SIO_EXT_SMI#
PCI_SERR#
SPI1_IO2
SPI1_IO3
SPI1_CS#
AW3
AW2
AW13
AY11
AV2
SPI0_CLK
SPI0_MISO
AV3
SPI0_MOSI
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
*SKL_ULT
REV = 1
SPI - FLASH
SPI - TOUCH
C LINK
SKL_ULT
LPC
PDC
5 OF 20
Need apply PN
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
?
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SMB_PCH_CLK
SMB_PCH_DAT
SML0ALERT#
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
GPP_B23
CLK_PCI_EC_R
CLK_PCI_LPC_R
CLKRUN#
LAD0 [30,31,35]
LAD1 [30,31,35]
LAD2 [30,31,35]
LAD3 [30,31,35]
LFRAME# [30,31,35]
CLKRUN# [35]
SML0ALERT#
SML1ALERT#
TP12
R85 22/F_4
R86 33_4
[11]
[11]
EC2 33P/50V_4
EC3 33P/50V_4
CLK_24M_KBC [35]
CLK_PCI_TPM [30,31]
EMI(near PCH)
GPIO Pull UP
+3V +3V_DEEP_SUS
ACC_LED#[12]
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
R89 2.2K_4
R91 2.2K_4
R93 499/F_4
R95 499/F_4
R97 1K_4
R98 1K_4
R99 10K_4
SERIRQ
CLKRUN#
SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#
B B
R88 10K_4
R90 8.2K/F_4
R92 10K_4
R94 10K_4
R96 10K_4
PCH SPI ROM(CLG)
3/31 CQ
Fix ROM PN
Vender P/N
Winbond
Socket
Size
PCH_SPI_CS0#_R[35]
PCH_SPI1_CLK_R[35]
PCH_SPI1_SI_R[35]
PCH_SPI1_SO_R[35]
AKE3DZN0N01 - IC FLASH(8P) W25Q128FVSIQ(SOIC)16MB
AKE3DF00Q00 - IC FLASH(8P)GD25B128CSIGR(SOP)GGD 16MB
DFHS08FS023
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
need place to TOP
PCH_SPI_CS0#_R
TP17
PCH_SPI1_CLK_R
TP18
PCH_SPI1_SI_R
TP19
PCH_SPI1_SO_R
TP20
BIOS_WP#
TP21
HOLD#
TP22
SMBus/Pull-up(CLG)
Q3
[18,35]
MBCLK2
[18,35]
MBDATA2
A A
R110 4.7K_4
SMB_RUN_DAT
SMB_RUN_CLK
5
+3V
+3V
R111 4.7K_4
[16..18,29]
[16..18,29]
4 3
1
*2N7002DW
Q4
4 3
1
2N7002KDW
+3V
5
SMB_ME1_CLK
2
SMB_ME1_DAT
6
+3V
5
SMB_PCH_DAT
2
SMB_PCH_CLK
6
CPU heat pipe local thermal sensor
DDR thermal sensor
RTD2136
EC
Touch Pad
XDP
DDR4
4
3
PCH_SPI_CS0#
PCH_SPI1_CLK
R102/R103/R104/R105/R106/R107 close to U3 pin
C161 1U/6.3V_4
+3VSPI
PCH_SPI_IO2
R102 15/F_4
R103 15/F_4
R104 15/F_4
R106 15/F_4
R108 1K_4
R109 15/F_4
PCH SPI ROM(CLG)
+3V_DEEP_SUS
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_RPCH_SPI1_SO
C159
22P/50V_4
U3
1
CE#
6
SCK
5
SI
2
SO
3
WP#
WND 16M ROM
AKE3DZN0N01
SOCKET footprint
0713 CQ
PV use ROM P/N
2
+3VS5
HOLD#
VDD
VSS
R100 *0_4
R101 0_4
8
+3VSPI
7
HOLD#
4
PCH_SPI_IO3BIOS_WP#
R105 1K_4
R107 15/F_4
C160
0.1U/16V_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL-09 [SPI/LPC/SM]
SKL-09 [SPI/LPC/SM]
SKL-09 [SPI/LPC/SM]
Date: Sheet of
Date: Sheet
Date: Sheet
1
10 49Wednesday, July 20, 2016
10 49Wednesday, July 20, 2016
10 49Wednesday, July 20, 2016
1A
1A
1A
of
of
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR[14,27]
C C
B B
GSPI1_MOSI[14]
ACZ_SPKR
SML0ALERT#
GSPI1_MOSI
R112
*20K/F_4
+3V_DEEP_SUS
R115
1K_4
R117
*20K/F_4
R120
*20K/F_4
Functional Strap Definitions
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
[35]
ACZ_SDOUT[14]
GPIO33_EC
GPP_B18[14]SML0ALERT#[10]
SML1ALERT#[10]
ACZ_SDOUT
R114 1K_4
GPP_B18
+3V_DEEP_SUS
SML1ALERT#
+3V_DEEP_SUS
R113
*4.7K_4
ACZ_SDOUT
+3V
R116
*4.7K_4
R118
10K_4
R119
*10K_4
R121
20K/F_4
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
A A
5
4
+3V [2,4,10,12,13,15..21,25..27,29,30,32,33,35,41,45,46]
+3VS5 [4,10,15,16,27,31,32,35,37..40,44,45,48]
+3V_DEEP_SUS [4,10,12,14..16,18]
3
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
SKL-10 [HDA]
SKL-10 [HDA]
SKL-10 [HDA]
1
11 49Wednesday, July 20, 2016
11 49Wednesday, July 20, 2016
11 49Wednesday, July 20, 2016
1A
1A
1A
of
of
of
5
+3V [2,4,10,11,13,15..21,25..27,29,30,32,33,35,41,45,46]
+3VS5 [4,10,15,16,27,31,32,35,37..40,44,45,48]
+3V_DEEP_SUS [4,10,11,14..16,18]
PEG_RXN1[19]
DIS only
PEG_RXP1[19]
PEG_TXN1[19]
D D
dGPU
0306 CQ
Cardreader PCIE net
LG9 use USB funciton
0311 CQ
PCIE Cardreafer
Cardreader
LAN
HDD
C C
0525 CQ
WLAN port9 move to port8
WLAN
0525 CQ
Add PICe SSD to 4ch
TP8524
TP8525
SSD PCIE x2
B B
A A
XDP_PRDY#_CPU
XDP_PREQ#_CPU
[32]
[32]
PEG_TXP1[19]
PEG_RXN2[19]
PEG_RXP2[19]
PEG_TXN2[19]
PEG_TXP2[19]
PEG_RXN3[19]
PEG_RXP3[19]
PEG_TXN3[19]
PEG_TXP3[19]
PEG_RXN4[19]
PEG_RXP4[19]
PEG_TXN4[19]
PEG_TXP4[19]
PCIE_RXN5_CARD[30]
PCIE_RXP5_CARD[30]
PCIE_TXN5_CARD[30]
PCIE_TXP5_CARD[30]
PCIE_RXN8_LAN[33]
PCIE_RXP8_LAN[33]
PCIE_TXN8_LAN[33]
PCIE_TXP8_LAN[33]
SATA_RXN0
[29]
SATA_RXP0
[29]
SATA_TXN0[29]
SATA_TXP0[29]
PCIE_RXN6_WLAN[31]
PCIE_RXP6_WLAN[31]
PCIE_TXN6_WLAN[31]
[31]
PCIE_TXP6_WLAN
PCIE_RXN9_SSD[32]
PCIE_RXP9_SSD[32]
PCIE_TXN9_SSD[32]
PCIE_TXP9_SSD[32]
PCIE_RXN10_SSD[32]
PCIE_RXP10_SSD[32]
PCIE_TXN10_SSD[32]
PCIE_TXP10_SSD[32]
0315 CQ
XDP_PRDY#_CPU
XDP_PREQ#_CPU
+3V_DEEP_SUS
PCIE_RXN11_SSD[32]
PCIE_RXP11_SSD[32]
PCIE_TXN11_SSD[32]
PCIE_TXP11_SSD[32]
PCIE_RXN12_SSD[32]
PCIE_RXP12_SSD[32]
PCIE_TXN12_SSD
PCIE_TXP12_SSD
5
Add Net name
[16]
[16]
0225 CQ
Del PCIE SSD port 11
0311 CQ
Add PCIE SSD port 11 for LG request
C162 0.22U/10V_4
C163 0.22U/10V_4
C164 0.22U/10V_4
C165 0.22U/10V_4
C167 0.22U/10V_4
C166 0.22U/10V_4
C168 0.22U/10V_4
C169 0.22U/10V_4
C170 0.1U/16V_4
C171 0.1U/16V_4
C174 0.1U/16V_4
C175 0.1U/16V_4
C172 0.1U/16V_4
C173 0.1U/16V_4
R131 100/F_4
R132 10K_4
PCIE_TXN5_CARD_C
PCIE_TXP5_CARD_C
PCIE_TXN8_LAN_C
PCIE_TXP8_LAN_C
PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C
PCIE_RXN9_SSD
PCIE_RXP9_SSD
PCIE_TXN9_SSD
PCIE_TXP9_SSD
PCIE_RXN10_SSD
PCIE_RXP10_SSD
PCIE_TXN10_SSD
PCIE_TXP10_SSD
PIRQA#
PCIE_RXN11_SSD
PCIE_RXP11_SSD
PCIE_TXN11_SSD
PCIE_TXP11_SSD
PCIE_RXN12_SSD
PCIE_RXP12_SSD
PCIE_TXN12_SSD
PCIE_TXP12_SSD
SSD SATA*1
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
PEG_TXN4_C
PEG_TXP4_C
PCIE_RCOMPN
PCIE_RCOMPP
BB11
H13
G13
B17
A17
G11
F11
D16
C16
H16
G16
D17
C17
G15
F15
B19
A19
F16
E16
C19
D19
G18
F18
D20
C20
F20
E20
B21
A21
G21
F21
D21
C21
E22
E23
B23
A23
F25
E25
D23
C23
F5
E5
D56
D61
E28
E27
D24
C24
E30
F30
A25
B25
4
?
U1H
PCIE/USB3/SATA
PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
PCIE1_TXN/USB3_5_TXN
PCIE1_TXP/USB3_5_TXP
PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
PCIE2_TXN/USB3_6_TXN
PCIE2_TXP/USB3_6_TXP
PCIE3_RXN
PCIE3_RXP
PCIE3_TXN
PCIE3_TXP
PCIE4_RXN
PCIE4_RXP
PCIE4_TXN
PCIE4_TXP
PCIE5_RXN
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP
PCIE6_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
PCIE8_RXN/SATA1A_RXN
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
PROC_PREQ#
GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/SATA2_RXP
PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
*SKL_ULT
PCI-E Port Mapping Table
PCI-E Port
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Function
dGPU
dGPU
dGPU
dGPU
CardReader
LAN
HDD
SKL_ULT
PDC
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
Port8
Port9
WLAN
Port10
Port11
Port12 SATA2
4
Need apply PN
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
Function
VGA
NA
WLAN
LAN
CardReader
Un-used
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
? 8 OF 20REV = 1
3
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USB30_RX4USB30_RX4+
USB30_TX4USB30_TX4+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
0225 CQ
Del IR Camera function (USB5- & USB5+)
USBP6USBP6+
USBP7USBP7+
0225 CQ
Del Touch screen function (USB8- & USB8+)
0311 CQ
Del CR USB net (USBP10- & USBP10+)
USB2_COMP
USB2_ID
USB2_VBUSSENSE
DGPU_HOLD_RST#
GPU_EVENT#
DGPU_PWR_EN
DGPU_PWROK
OCP_OC#
GC6_FB_EN
DEVSLP1
GPIO35_R
0309 CQ
Del ODD_PRSNT#_R & R128 (PU 10K +3V)
R130 113/F_4
R303 1K_4
R304 1K_4
R302 *0_4/S
R134 *0_4/S
0713 CQ
Change F/P S0402
Ra
TP35
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USB30_RX4USB30_RX4+
USB30_TX4USB30_TX4+
USBP1- [26]
USBP1+ [26]
USBP2- [26]
USBP2+ [26]
USBP3- [25]
USBP3+ [25]
USBP4- [28]
USBP4+ [28]
USBP6- [26]
USBP6+ [26]
USBP7- [31]
USBP7+ [31]
DGPU_HOLD_RST#
GPU_EVENT#
DGPU_PWR_EN
DGPU_PWROK
GC6_FB_EN
DEVSLP1 [32]
DB modify
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
USB3.0 MB-1
PORT-2
PORT-3
PORT-4
3
USB3.0 TYPE C
USB3.0 TYPE C Cobime USB3.0 TYPE C
[26]
[26]
[26]
[26]
[26]
[26]
[26]
[26]
[28]
[28]
[28]
[28]
[28]
[28]
[28]
[28]
Modify 0922
DB modify swap
[20,22]
SATA_LED#SATA_LED#_R
2
USB3.0 (M/B-1)
USB3.0 (M/B-2)
USB3.0 TYPE C
0128 Add USB3.0 TYPE C
Combo USB3.0 MB-1
Combo USB3.0 MB-2
Camera
Cobime USB3.0 TYPE C
USB2.0 MB
WLAN
CardReader
PLACE 'Ra' WITHIN 500 MILS
[19]
[22]
[20,48]
[21,35,47]
ACC_LED# [10]
GPIO35 [32]
SATA_LED# [29]
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
If OTG is not implemented on the platform,
then USB2_ID and USB2_VBUSSENSE should both
be connected to ground.
GPIO35:
SSD SATA IF => High
SSD PCIE IF => Low
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
2
GPU_EVENT#
DGPU_HOLD_RST#
DGPU_PWR_EN
DGPU_PWROK
SATA_LED#
GC6_FB_EN
GPIO35
R122 *10K_4
R123 *10K_4
R124 10K_4
R125 10K_4
R126 10K_4
R127 *10K_4
R400 10K_4
1002 Pull high
DGPU_HOLD_RST#
Cobime USB3.0 MB-1
Cobime USB3.0 MB-2USB3.0 MB-2
Camera
NC
USB2.0 MB
WLAN
NC
NC
NC
R129 100K_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
SKL-11 [PCIE/USB]
SKL-11 [PCIE/USB]
SKL-11 [PCIE/USB]
1
12
+3V
DIS ONLY
1A
1A
12 49Wednesday, July 20, 2016
12 49Wednesday, July 20, 2016
1
12 49Wednesday, July 20, 2016
1A
of
of
of
5
4
3
2
1
+1.0V_DEEP_SUS [9,15,16,39,40]
+BAT_RTC [31]
+1.8V_DEEP_SUS [5,9,15,39]
+3V [2,4,10..12,15..21,25..27,29,30,32,33,35,41,45,46]
+3VPCU [6,29,31,34..37,44]
?
10 OF 20
?
PDC
9 OF 20
Need apply PN
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XCLK_BIASREF
TBT
Need apply PN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
?
XTAL24_IN
XTAL24_OUT
SRTCRST#
U1J
0226 CQ
D D
Del CLK_PCIE_SSDN & CLK_PCIE_SSDP
Change net name PCIE_CLKREQ_SSD# to PCIE_CLKREQ1#
0311 CQ
Add CLK_PCIE_SSDN & CLK_PCIE_SSDP for LG request
Change net name PCIE_CLKREQ1# to PCIE_CLKREQ_SSD#
CLK_REQ/Strap Pin(CLG)
+3V
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_SSD#
PCIE_CLKREQ5#
C C
B B
R136 10K_4
R138 10K_4
R139 10K_4
R140 10K_4
R141 10K_4
R142 10K_4
VGA
SSD
WLAN
LAN
Cardreader
0307 CQ
Change net name PCIE_CLKREQ_CR#
to PCIE_CLKREQ4#
0311 CQ
Add CLK_PCIE_CRN & CLK_PCIE_CRP
Change net name PCIE_CLKREQ4# to PCIE_CLKREQ_CR#
CLK_VGA_N[19]
CLK_VGA_P[19]
PCIE_CLKREQ_VGA#[19]
CLK_PCIE_SSDN[32]
CLK_PCIE_SSDP[32]
PCIE_CLKREQ_SSD#[32]
CLK_PCIE_WLANN[31]
CLK_PCIE_WLANP[31]
PCIE_CLKREQ_WLAN#[31]
CLK_PCIE_LANN[33]
CLK_PCIE_LANP[33]
PCIE_CLKREQ_LAN#[33]
CLK_PCIE_CRN[30]
CLK_PCIE_CRP[30]
PCIE_CLKREQ_CR#[30]
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#
CLK_PCIE_SSDN
CLK_PCIE_SSDP
PCIE_CLKREQ_SSD#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
CLK_PCIE_CRN
CLK_PCIE_CRP
PCIE_CLKREQ_CR#
PCIE_CLKREQ5#
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
*SKL_ULT
REV = 1
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
U1I
CSI-2
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
*SKL_ULT
SKL_ULT
CLOCK SIGNALS
SKL_ULT
REV = 1
0305 CQ
Change net name
CK_XDP_N_R to CK_XDP_N
CK_XDP_P_R to CK_XDP_P
0307 CQ
Add 0 ohm contact to page16 xDP
XDP_N & XDP_P
Del TP
F43
E43
BA17
E37
E35
E42
AM18
RTCX1
AM20
RTCX2
AN18
AM16
RTCRST#
?
C37
D37
C32
D32
C29
D29
B26
A26
E13
GPP_D4
B7
AP2
AP1
AP3
AN3
AN1
AN2
1001 Del TP
AM4
AM1
AM2
AM3
AP4
EMMC_RCOMP
AT1
CK_XDP_N
CK_XDP_P
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST#
RTC_RST#
R143 100/F_4
R144 200/F_4
R17731 *0_4/S
R17732 *0_4/S
TP203
TP38
TP39
0713 CQ
Change F/P S0402
RTC_RST# [16]
XDP_N [16]
XDP_P [16]
XCLK_BIASREF
1027 modify for eazy layout
+VCCSTPLL
R135
2.7K/F_4
R137
*60.4/F_4
13
1
Q7705
2N7002K
+3V_RTC_2[4,15,34]
R151
10K_4
2
2
EC_RTC_RST [35]
RTC_RST#
3
EC_SRTC_RST [35]
3
R8506
*10K_4
RTC Clock 32.768KHz
0301 CQ
Add GCLK XTALIN (CLKGEN_RTC_X1) & 0ohm
[34]
CLKGEN_RTC_X1
C177 12P/50V_4
32.768KHZ
C179 12P/50V_4
A A
R17724*0_4
RTC_X1
4
12
Y1
R147
10M_4
3
RTC_X2
5
RTC Circuitry(RTC)
Coin BAT -->Rb Rb Ra
Modify 0922
+3V_RTC_0
+3V_RTC_0
12
RTC Power trace width 20mils.
R150
1K_4
CN11
BAT_CONN
DFHS02FS080
bat-ap-aaa-bat-054-k01-2p-smt
4
+3VPCU
+3V_RTC_1
D2
BAT54CW-7-F
1U/6.3V_4
30mils
C181
+BAT_RTC+3V_RTC_2
R307
*0_4
R146
20K/F_4
R149
20K/F_4
R145 *0_6
RTC_RST#
C178
1U/6.3V_4
SRTC_RST#
C182
1U/6.3V_4
3
1
Q7706
*2N7002K
SRTC_RST#
0413 CQ
Change Q5 circuit (Follow G31 MV)
0523 CQ
Del Q5 , add Q7705 & Q7706 (Q7706
0526 CQ
Change Q7705 & Q7706 pin define
External Crystal
The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U
needs to be replaced by 38.4 MHz (30 Ohm ESR) XTAL
for Cannonlake-U.
TP51
C176 27P/50V_4
1
XTAL24_IN
XTAL24_OUT
0720 CQ
Del R17722 & R17723
Change 24M X'tal GND to XGND
Add R17757 contact XGND & GND
R148
1M_4
2
24MHZ +-20PPM
Y2
4
3
C180 27P/50V_4
TP52
)
2
XGND
0524 CQ
Change 24M X'tal P/N & F/P "BG624000112"
"xtl-2x1_6-1_35x1_05"
XGND
R17757
*0_4
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL-12 [CLK/EMMC]
SKL-12 [CLK/EMMC]
SKL-12 [CLK/EMMC]
Date: Sheet
Date: Sheet
Date: Sheet of
1
13 49Wednesday, July 20, 2016
13 49Wednesday, July 20, 2016
13 49Wednesday, July 20, 2016
of
of
1A
1A
1A
5
+3V [2,4,10..13,15..21,25..27,29,30,32,33,35,41,45,46]
+3V_DEEP_SUS [4,10..12,15,16,18]
D D
BT_OFF
PCH_TEMPALERT#
SIO_EXT_SCI#
UART2_RXD
UART2_TXD
C C
R154 10K_4
R155 10K_4
R156 10K_4
R157 49.9K/F_4
R158 49.9K/F_4
+3V_DEEP_SUS
0309 CQ
Del ACCEL_INTA# (GPP_C22) & R159 (PU 10K +3V)
LG9
G-sensor
HDA Bus(CLG)
HDA Bus(CLG)
B B
[11,27]
ACZ_SYNC
ACZ_SYNC
R168 33_4
R162 33_4
ACZ_SPKR
0324 CQ
Del TP
ACZ_SYNC
ACZ_BCLK
ACZ_RST#
ACZ_SPKR
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
U1G
*SKL_ULT
+3V_DEEP_SUS
ACZ_SYNC_AUDIO[27]
BIT_CLK_AUDIO[27]
ACZ_SDOUT_AUDIO[27]
[11]
ACZ_SDOUT
ACZ_SDIN0[27]
ACZ_RST#_AUDIO[27]
A A
R160 *1K_4
R161 33_4
C183 *10P/50V_4
R165 33_4
ACZ_SDOUT
ACZ_SDIN0
5
AUDIO
SIO_EXT_SCI#[35]
4
GPP_B18[11]
GSPI1_MOSI[11]
REV = 1
4
SKL_ULT
3
Skylake (GPIO)
?
SKL_ULT
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
6 OF 20
BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5
GPP_G1 GPP_G2 GPP_G3 GPP_G4 GPP_G5GPP_G0
LG : 0
CB : 1
0
0324 CQ
Del TP
GPP_B18
0324 CQ
Del TP
GSPI1_MOSI
0324 CQ
Del TP
UART2_RXD
UART2_TXD
TP8612
SIO_EXT_SCI#
0324 CQ
Del TP
GPP_C22
Model
LG9 + UMA
U1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
*SKL_ULT
REV = 1
LPSS ISH
BOARD_ID0
LG9 : 0
LG9A : 1
LG9 + dGPU + N16S-GTR 0 0 00
0
1
LG9A + dGPU + N16S-GTR 0
1
1
?
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
7 OF 20
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
?
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
GPP_A16
GPP_F23
3
1
1
1
0226 CQ
0520 CQ
Board ID 4 ,
TP8564
R183 200/F_4
TP100
LG & CB board ID
Need apply PN
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
N16V : 0
N16S : 1
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
UMA : 0
dGPU : 1
11
1
11
1
+3V_DEEP_SUS
R164*10K_4
R167*10K_4
R17010K_4
R17210K_4
R174*10K_4
R176*10K_4
R178*10K_4
R180*10K_4
R182*10K_4
?
2
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
LG9 : 0
LG9A : 1
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
2
GPP_D10
ISH_I2C0_SDA
ISH_I2C0_SCL
0324 CQ
Del TP
PCH_TEMPALERT#
SML0BDATA
SML0BCLK
SML0BALERT#
0324 CQ
Del TP
0 000LG9 + dGPU + N16V-GMR1
1
1
1
TP92
TP61
TP62
TP71
TP72
TP73
TP74
No Define
00000
000LG9A + UMA
00LG9A + dGPU + N16V-GMR1
R16310K_4
R16610K_4
R169*10K_4
R171*10K_4
R17310K_4
R17510K_4
R17710K_4
R17910K_4
R18110K_4
1
0309 CQ
Del SPK_ID & R401 (PU 10K +3V_DEEP_SUS)
BT_OFF
BOARD_ID6
GPP_G6
No Define
0
0
0
0
0
0
BOARD_ID7
GPP_G7
No Define
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet
Date: Sheet
[31]
BT_OFF
BOARD_ID8
GPP_G8
No Define
0
0
0
0
0
0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKL-13 [GPIO]
SKL-13 [GPIO]
SKL-13 [GPIO]
1
14
0
0
0
0
0
0
1A
1A
1A
of
of
14 49Wednesday, July 20, 2016
14 49Wednesday, July 20, 2016
14 49Wednesday, July 20, 2016
5
4
+3V_DEEP_SUS[4,10..12,14,16,18]
+1.0V_DEEP_SUS[9,16,39,40]
+1.8V_DEEP_SUS[5,9,39]
+3VS5[4,10,16,27,31,32,35,37..40,44,45,48]
+3V_RTC_2[4,13,34]
3
2
1
15
D D
+VCCPRIM
C184 1U/6.3V_4
+1.0V_DEEP_SUS
Ca and Cb close to CPU less then 100 mils
PCH Internal VRM
C C
B B
0713 CQ
Change F/P S0402
+V3.3DX_1.5DX_ADO +1.0V_DEEP_SUS
+VCCDSW_1.0V
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
R201 *0_4/S
+3VS5
+V3.3DX_1.5DX_ADO
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
R210 *0_4/S
Ca
C185 1U/6.3V_4
C187 1U/6.3V_4
R188 *0_4/S
C188 1U/6.3V_4
C189 1U/6.3V_4
C190 47U/6.3VS_8
R194 *0_6/S
C192 1U/6.3V_4
R196 *0_4/S
R199 *0_6/S
C193 1U/6.3V_4
C194 1U/6.3V_4
R205 *0_4/S
R206 *0_6/S
C196 1U/6.3V_4
R207 *0_4/S
R208 *0_6/S
R209 *0_4/S
C197 1U/6.3V_4
C203
*1U/6.3V_4
+3V
+VCCMPHYAON_1P0
22mA
+VCCAMPHYPLL_1P0
+VCCAPLL_1.0V
26mA
+VCCPRIM
+3VS5_AD17
+VCCSPI
11mA
+VCCSRAM_1.0V
700mA
+VCCPRIM_3.3V
75mA
+VCCPRIM_1.0V
700mA
+VCCAPLLEBB
33mA
C204
*22U/6.3V_6
0711 CQ
R211 100K change to 10K for 1.8V_DEEP_SUS issue
SLP_SUS_ON[35,39,40]
U1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
*SKL_ULT
REV = 1
R211
10K_4
CPU POWER 4 OF 4
C210
*10P/50V_4
?
SKL_ULT
2.899A
2.57A
0.03A
C205
1U/6.3V_4
0.09A
Need apply PN
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
1.714A
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
U4
5
IN
4
IN
3
ON/OFF
IC OTHER(5P) G5245AT11U
0409 CQ
Chagne P/N AL005245000 (RDC suggest)
?
OUT
GND
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
1
2
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPF
+VCCPGPPG
+VCCPRIM_1.0V_T1
+VCCATS_1.8V
+VCCRTCPRIM_3.3V
DCPRTC
+VCCCLK1
+VCCCLK2
+VCCCLK3
+VCCCLK4
+VCCCLK5
+VCCCLK6
CORE_VID0
CORE_VID1
+3V_DEEP_SUS+3VS5
C209
0.1U/16V_4
6mA
1mA
Cb
C186 1U/6.3V_4
R187 *0_6/S
R190 *0_4/S
R192 *0_4/S
C191 0.1U/16V_4
R195 *0_4/S
R198 *0_4/S
R200 *0_4/S
R202 *0_4/S
R203 *0_4/S
R204 *0_4/S
C195 1U/6.3V_4
TP102
TP103
1U/6.3V_4
1U/6.3V_4
+VCCPGPPA
20mA
+VCCPGPPB
20mils
4mA
6mA
8mA
6mA
41mA
160mA
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPG
+VCCPGPPF
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+3V_DEEP_SUS
+3V_RTC_2
+1.0V_DEEP_SUS
35mA
29mA
24mA
33mA
4mA
10mA
C200
1U/6.3V_4
+VCCRTCPRIM_3.3V+VCCATS_1.8V
C201
1U/6.3V_4
C208
1U/6.3V_4
+3V_RTC_2
C198
+VCCPGPPB +VCCPGPPC +VCCPGPPE
C206
C199
0.1U/16V_4
1U/6.3V_4
C207
C202
0.1U/16V_4
+3V_DEEP_SUS
R184 *0_4/S
R185 *0_4/S
R186 *0_4/S
R189 *0_4/S
R191 *0_4/S
R193 *0_4/S
+1.8V_DEEP_SUS
R197 *0_4/S
A A
PROJECT : LG9
PROJECT : LG9
PROJECT : LG9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet of
SKL-14 [PCH Power]
SKL-14 [PCH Power]
SKL-14 [PCH Power]
1
15 49Wednesday, July 20, 2016
15 49Wednesday, July 20, 2016
15 49Wednesday, July 20, 2016
1A
1A
1A
of
of
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