How it Works
QUANTA
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JWV
Schematics
44 pgs2.3 Mb0

QUANTA TWB, JWV Schematics

5
4
3
2
1
01
TWB + JWV Intel Boardwell ULT Platform Block Diagram
D D
DDR3L SO-DIMM-0 Maxima 8GBs
Front Side / STD Type
DDR3L SO-DIMM-1 Maxima 8GBs
Rear Side / REV Type
SATA HDD Package : 9.5 (mm)
SATA ODD Board for TWB Package : 12.7 (mm)
C C
SATA ODD Package : 12.7 (mm)
NGFF SSD
Package : 2280 & 2242
Full mini-PCIe Card - SSD
www.rosefix.com
USB3.0 Port
Left / Front Side
USB3.0 Port
Left / Rear Side
B B
A A
USB Board
USB2.0 Port USB2.0 Port-1
Right Side
Combo Jack Ext. Headphone & MIC
Speaker 4Ω , Normal 1.5W
Digital MIC with Camera
TPS2546
Package : QFN-40
USB3.0 Port-1 & USB2.0 Port-0
USB3.0 Port-2 & USB2.0 Port-5
Audio Codec
ALC282-CG
Package : MQFN48 Size : 6 x 6 (mm)
DDR3L CH-A
DDR3L CH-B
SATA0 6GB/s Port-0
SATA1 3GB/s Port-1
SATA2 6GB/s Port-2
Azalia
SPI
System BIOS & EC F/W
PAGE 7
Broadwell Mobile 2+1 U-Processor
Broadwell Mobile 2+2 U-Processor
QGZ4 - AJ0QGZ4UT01 QGZ3 - AJ0QGZ3UT01 QGZ5 - AJ0QGZ5VT00
Processor : Daul Core
TDP : 15 (Watt)
Package : BGA, 1168-PIN
Size : 40 X 24 X 1.3 (mm)
Embedded ControllerSPI ROM 8MByte
ENE IC CTRL(128P) KB9010QF C4
Package : LQFP Size : 14 x 14 (mm)
PAGE-2~10
PCI-E X4 Lane
Port-5
eDP X 2
eDP Port-0 & 1
DDI Port-1
DDI Port-2
PCIE Gen 1 x 1 Lane Port-2
PCIE Gen 1 x 1 Lane Port-4
PCIE Gen 1 x 1 Lane Port-3
LPC
NVIDIA N16V-GM / GT920M N16S-GT / GT940M
Power : 25 (Watt)
Package : S3 Size : 23 x 23 (mm)
PAGE-14~17
27MHz
RTD2136
Package : QFN-32
eDP
ANX6210
Package : QFN-40
Card Reader
Package : QFN32 Size : 4 x 4 (mm)
LAN Controller
Package : OFN32
NGFF WLAN
Half mini-PCIe Card WLAN & BT Combo Card
USB2.0 Port-6
JWV Power Button Board TWB Power Button Board LID Switch
27MHz
One-Channell 64Bit
Graphics 4Gb DDR3 SDRAM
1.0GHz / 16-Bit
LVDS (2-CH)
Camera
USB2.0 Port-2
HDMI
CRT
RTS5227E-GRT
RTL8111GS-CG(Giga)
Package : 2230
PAGE-18
TWB
Card Slot SD Card MMC Card
RJ45
JWV
PCB 6L STACK UP
LAYER-1 : TOP LAYER-2 : SGND LAYER-3 : IN1(High) LAYER-4 : IN2(Low) LAYER-5 : SVCC LAYER-6 : BOT
w w w . c h i n a f i x . c o m
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Keyboard
5
4
Touch Pad
3
FAN
BATTERY
2
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
Block Diagram
Block Diagram
Block Diagram
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Rev.Size
Rev.Size
Rev.Size
2A
2A
Sheet :
Sheet :
Sheet :
1 44
1 44
1
1 44
2A
of
of
of
5
4
3
2
1
02
D D
The PECI interface is a controlled and reliable one-wire bi-directional signal which is used to communicate the temperature of the Broadwell processor digital thermometer to the PECI host controller or to monitor and control the Broadwell processor information such as energy, power limits, status and DDR temperature.
U26A *I7-5500U 2.4G QH3E
IN_D2#[20]
IN_D1#[20]
IN_D0#[20]
IN_CLK#[20]
IN_D2[20]
IN_D1[20]
IN_D0[20]
IN_CLK[20]
DDI2_CRT_TX0N[21]
eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mΩ
C C
+VCCIOA_OUT
DDI2_CRT_TX0P[21] H_PROCHOT#[30,36]
R163 24.9/F_4
backlight modulation control
eDP_RCOMP
170.81 MIL
EDP_DISP_UTIL[6]
INT_eDP_AUXP[19] INT_eDP_AUXN[19]
INT_eDP_TXP0[19]
INT_eDP_TXP1[19]
INT_eDP_TXN0[19]
INT_eDP_TXN1[19]
C54 B58 B55 A57 C55 C58 A55 B57
C51 C53 C49 A53 C50 B54 B50 B53
D20 A43
B45 A45
B46 B47 C46 B49
C45 A47 C47 A49
DDI1_TXN0 DDI1_TXN1 DDI1_TXN2 DDI1_TXN3 DDI1_TXP0 DDI1_TXP1 DDI1_TXP2 DDI1_TXP3
DDI2_TXN0 DDI2_TXN1 DDI2_TXN2 DDI2_TXN3 DDI2_TXP0 DDI2_TXP1 DDI2_TXP2 DDI2_TXP3
EDP_RCOMP EDP_DISP_UTIL
EDP_AUXP EDP_AUXN
eDP_TXP0 eDP_TXP1 eDP_TXP2 eDP_TXP3
eDP_TXN0 eDP_TXN1 eDP_TXN2 eDP_TXN3
EC_PECI[30]
+V1.05S_VCCST
R145 62_4
R529 56.2/F_4
Allows EC to initiate Thermal Control Circuit (TCC) on the processor for overall platform thermal management. Similarly, this allows the VR to the initiate VR thermal protection.
eDP
TP108 TP112
TP100
PROC_DETECT#
CATERR#
PROCPWRGD
R499 10K/F_4
PCI EXPRESS* - GRAPHICS
U26B *I7-5500U 2.4G QH3E
D61
PROC_DETECT#
K61
CATERR#
N62
PECI
K63
PROCHOT#
C61
PROCPWRGD
MISCTHERMALPWR MANAGEMENT
AV15
PRDY# PREQ#
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
AU60 AV60 AU61
AV61
J62 K62
E60 E61 E59
F63 F62
J60 H60 H61 H62 K59 H63 K60 J61
SM_DRAMRST# SM_RCOMP_0
SM_RCOMP_1 SM_RCOMP_2PROCHOT#
BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
SM_DRAMRST#
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
DDR3JTAG & BPM
SM_PG_CNTL1
PROC_TCK PROC_TMS
PROC_TRST#
PROC_TDI
PROC_TDO
R284 *0_4/S R275 200/F_4
R274 121/F_4 R273 100/F_4
TP13 TP22
XDP_TDO_CPU XDP_TDI_CPU XDP_TMS_CPU
XDP_TRST#_CPU XDP_TCK0
TP111 TP15 TP21 TP20 TP25 TP16
+1.35VSUS
R288 470/F_4
R523 51_4 R520 *51_4 R511 *51_4
R600 *51_4 R166 51_4
DDR3_DRAMRST# [12,13]
DDR_PG_CNTL [13]
XDP_PRDY#_CPU [11]
XDP_PREQ#_CPU [11]
+V1.05S_VCCST
XDP_TCK0 [11]
XDP_TMS_CPU [11]
XDP_TRST#_CPU [7,11]
XDP_TDI_CPU [11]
XDP_TDO_CPU [11]
XDP_BPM0 [11] XDP_BPM1 [11]
Processor pull-up (CPU)
B B
A A
Date:
Date:
5
4
3
2
Date:
+VCCIOA_OUT[4]
+V1.05S_VCCST[4,9,11,36]
+1.35VSUS[4,12,13,31,35]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
ULT 1/9 (eDP/DDI)
ULT 1/9 (eDP/DDI)
ULT 1/9 (eDP/DDI)
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Sheet :
Sheet :
Sheet :
1
+VCCIOA_OUT +V1.05S_VCCST +1.35VSUS
2 44
2 44
2 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
of
of
of
5
4
3
2
1
03
M_A_DQ[63:0][12] M_B_DQ[63:0][13]
M_A_DQSN[7:0][12] M_A_DQSP[7:0][12]
M_B_DQSN[7:0][13]
D D
M_B_DQSP[7:0][13]
Haswell ULT Processor (DDR3L)
U26C *I7-5500U 2.4G QH3E
AH63
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13
C C
B B
M_A_BS#1[12] M_A_BS#2[12]
M_A_CAS#[12] M_A_RAS#[12] M_A_WE#[12]
M_B_DQ14 M_B_DQ15
M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31
M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31
AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58
AW58
AY56
AW56
AV58 AU58 AV56 AU56 AY54
AW54
AY52
AW52
AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51
AU35 AV35 AY41
AU34 AY34
AW34
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_BA0 SA_BA1 SA_BA2
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0 SA_CS#1
SA_ODT0
SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7
SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1
AV37 AU37 AU43
AY36 AW36 AW43
AY42
AY43
AP33 AR32
AP32
AJ61
M_A_DQSN0
AN62
M_A_DQSN1
AM58
M_B_DQSN0
AM55
M_B_DQSN1
AV57
M_A_DQSN2
AV53
M_A_DQSN3
AL43
M_B_DQSN2
AL48
M_B_DQSN3
AJ62
M_A_DQSP0
AN61
M_A_DQSP1
AN58
M_B_DQSP0
AN55
M_B_DQSP1
AW57
M_A_DQSP2
AW53
M_A_DQSP3
AL42
M_B_DQSP2
AL49
M_B_DQSP3
AU36
M_A_A0
AY37
M_A_A1
AR38
M_A_A2
AP36
M_A_A3
AU39
M_A_A4
AR36
M_A_A5
AV40
M_A_A6
AW39
M_A_A7
AY39
M_A_A8
AU40
M_A_A9
AP35
M_A_A10
AW41
M_A_A11
AU41
M_A_A12
AR35
M_A_A13
AV42
M_A_A14
AU42
M_A_A15
AP49 AR51 AP51
20mils width
VREF_CA : Command / Address Reference Voltage. VREF_DQ_A, VREF_DQ_B : Data Reference Voltage.
M_A_CLKP0 [12] M_A_CLKN0 [12]
M_A_CKE0 [12]
M_A_CLKP1 [12] M_A_CLKN1 [12]
M_A_CKE1 [12]
M_A_CS#0 [12] M_A_CS#1 [12]
TP66 TP54
VIA: VIA20D10A25 check match 20mil?
M_A_A[15:0] [12] M_B_A[15:0] [13]
SM_VREF [12] SMDDR_VREF_DQ0_M3 [12] SMDDR_VREF_DQ1_M3 [13]
M_B_BS#0[13]M_A_BS#0[12] M_B_BS#1[13] M_B_BS#2[13]
M_B_CAS#[13] M_B_RAS#[13] M_B_WE#[13]
M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47
M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47
M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
AY31
AW31
AY29
AW29
AV31 AU31 AV29 AU29 AY27
AW27
AY25
AW25
AV27 AU27 AV25 AU25 AM29 AK29
AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25
AL25 AY23
AW23
AY21
AW21
AV23 AU23 AV21 AU21 AY19
AW19
AY17
AW17
AV19 AU19 AV17 AU17 AR21 AR22
AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18
AL18 AK20 AM20 AR18 AP18
AL35 AM36 AU49
AM33 AM35 AK35
U26D *I7-5500U 2.4G QH3E
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_BA0 SB_BA1 SB_BA2
SB_CAS# SB_RAS# SB_WE#
AN38
SB_CLK0
AM38
SB_CLK#0
AY49
SB_CKE0
AL38
SB_CLK1
AK38
SB_CLK#1
AU50
SB_CKE1
AW49
SB_CKE2
AV50
SB_CKE3
AM32
SB_CS#0
AK32
SB_CS#1
AL32
SB_ODT0
AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18
AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18
AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46
M_A_DQSN4 M_A_DQSN5
M_B_DQSN4 M_B_DQSN5
M_A_DQSN6 M_A_DQSN7
M_B_DQSN6 M_B_DQSN7
M_A_DQSP4 M_A_DQSP5
M_B_DQSP4 M_B_DQSP5
M_A_DQSP6 M_A_DQSP7
M_B_DQSP6 M_B_DQSP7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7
SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7
SB_MA0 SB_MA1 SB_MA2 SB_MA3
DDR SYSTEM MEMORY B
SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
M_B_CLKP0 [13] M_B_CLKN0 [13]
M_B_CKE0 [13]
M_B_CLKP1 [13] M_B_CLKN1 [13]
M_B_CKE1 [13]
M_B_CS#0 [13] M_B_CS#1 [13]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
ULT 2/9 (DDR3L I/F)
ULT 2/9 (DDR3L I/F)
ULT 2/9 (DDR3L I/F)
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
5
4
3
2
Wednesday, October 29, 2014
Sheet :
Sheet :
Sheet :
3 44
3 44
1
3 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
of
of
of
5
4
3
2
1
TP102 TP103
TP23
04
R609
49.9/F_4
C664 10U/6.3V_6
C663 10U/6.3V_6
C667 10U/6.3V_6
Close to CPU
C657 2.2U/6.3V_4
Direct tie to CPU VCC/VSS-Ball
R266 *0_8
C345
4.7U/6.3V_6
+VCCIOA_OUT
R141 *0_4/S
2 1
D2 *RB500V-40
H_VCCST_PWRGD_R
+VCC_CORE
R512 100/F_4
R521 100/F_4
+1.35VSUS
C665 10U/6.3V_6
C668 10U/6.3V_6
C666 10U/6.3V_6
C658 2.2U/6.3V_4
C660 2.2U/6.3V_4
C656 2.2U/6.3V_4
100- ±1% pull-up to VCC near processor.
VCC_SENSE [36]
VSS_SENSE [36]
Check result : Routing together.
Layout note: need routing together and ALERT need between CLK and DATA.
H_CPU_SVIDALRT#
VR_SVID_CLK : One segs without routing with DATA/CLK.
VR_SVID_CLK
H_CPU_SVIDDAT
H_VR_ENABLE_MCP [36]
IMVP_PWRGD_R [30]
R537 43_4
R150 *0_4/S
IMVP_PWRGD [6,36]
R501 *0_4/S
C339 *22U/6.3V_8
+V1.05S_VCCST
R493 10K_4
2 1
D9 RB500V-40
C636 *10P/50V_4
+V1.05S_VCCST
R542 75/F_4
SVID ALERT
C234 *0.1U/10V_4
VR_SVID_ALERT# [36]
SVID CLK
+V1.05S_VCCST
Place PU resistor close to VR
R148 130/F_4
SVID DATA
VR_SVID_DATA [36]
+V1.05S_VCCST
R492 150/F_4
TP24
R491 *10K_4
+V1.05S_VCCST +1.05V
R265 *0_8/S
C333 *1U/6.3V_4
H_VCCST_PWRGD [11]
VR_SVID_CLK [36]
PWR_DEBUG [11]
HWPG [11,30,33,34,35]
CFG0-19 need Reserve TP
CFG0[11] CFG1[11] CFG2[11] CFG3[11] CFG4[11] CFG5[11] CFG6[11] CFG7[11] CFG8[11] CFG9[11] CFG10[11] CFG11[11] CFG12[11] CFG13[11] CFG14[11] CFG15[11] CFG16[11] CFG17[11] CFG18[11] CFG19[11]
R552 49.9/F_4
R498 8.2K/F_4
TP61 TP65 TP58 TP46 TP68 TP42 TP43 TP41 TP36 TP30 TP51 TP32 TP34 TP28 TP27 TP40 TP64 TP67 TP31 TP33
CFG_RCOMP
224.05 MIL
TD_IREF
276.38 MIL
TP128 TP124
TP109 TP101
U26E *I7-5500U 2.4G QH3E
AC60
CFG0
CFG0
AC62
CFG1
CFG1
AC63
CFG2
CFG2
AA63
CFG3
CFG3
AA60
CFG4
CFG4
Y62
CFG5
CFG5
Y61
CFG6
CFG6
Y60
CFG7
CFG7
V62
CFG8
CFG8
V61
CFG9
CFG9
V60
CFG10
CFG10
U60
CFG11
CFG11
T63
CFG12
CFG12
T62
CFG13
CFG13
T61
CFG14
CFG14
T60
CFG15
CFG15
AA62
CFG16
CFG16
AA61
CFG17
CFG17
U63
CFG18
CFG18
U62
CFG19
CFG19
V63
CFG_RCOMP
A5
RSVD
E1
RSVD
D1
RSVD
J20
RSVD
H18
RSVD
B12
TD_IREF
AV63
RSVD_TP
AU63
RSVD_TP
C63
RSVD_TP
C62
RSVD_TP
B43
RSVD
+3VPCU
IO Thrm Protect
R86
16.5K/F_4
For 65 degree, 1.8v limit, (SW)
R89
3.3K/F_4
For 75 degree, 1.2v limit, (HW)
R91 *0_4/S
THER_CPU
R87 100K_4 NTC
C144
0.1U/10V_4
1 2
C157
0.1U/10V_4
1 2
RSVD_TP RSVD_TP
RSVD_TP
PROC_OPI_RCOMP
RESERVED
THRM_MOINTOR [30]
THRM_MOINTOR1 [30]
RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD
A51 B51
L60
N60 W23 Y22
AY15
PROC_OPI_RCOMP
242.63 MIL
AV62 D58
P22
VSS
N21
VSS
P20 R20
U26F
+VCC_CORE
C262 22U/6.3V_8
C244 22U/6.3V_8
C214 22U/6.3V_8
C226 22U/6.3V_8
C265 22U/6.3V_8
C245 22U/6.3V_8
D D
C257 22U/6.3V_8
C225 22U/6.3V_8
C242 22U/6.3V_8
C277 22U/6.3V_8
C219 22U/6.3V_8
C218 22U/6.3V_8
C C
C254 22U/6.3V_8
C264 22U/6.3V_8
C213 22U/6.3V_8
C227 22U/6.3V_8
B B
C256 22U/6.3V_8 C220 *22U/6.3VS_8_T100
C258 22U/6.3V_8
C243 22U/6.3V_8
C252 22U/6.3V_8
C255 22U/6.3V_8
C291 22U/6.3V_8
C241 22U/6.3V_8
C221 22U/6.3V_8
C223 22U/6.3V_8
C215 *22U/6.3VS_8_T100C240 22U/6.3V_8
C216 *22U/6.3VS_8_T100
C217 *22U/6.3VS_8_T100
*I7-5500U 2.4G QH3E
C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23
J23 K23 K57 L22 M23 M57 P57 U57
W57 AB57 AD57 AG57
C24 C28 C32
F59
L59
J58
N58 AC58 AB23 AD23 AA23 AE59
AT2 AU44 AV44
D15
F22
H22
J21 N23 R23 T23 U10 AL1
AM11
AP7
AU10 AU15
POWER
VCC VCC
32A 1.4A
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
HSW ULT POWER
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
VCCIO_OUT
VCCIOA_OUT
VIDALERT#
VIDSCLK
VIDSOUT
PWR_DEBUG#
VR_EN
VR_READY
VCCST VCCST VCCST
VCCST_PWRGD
RSVD_TP RSVD_TP RSVD_TP RSVD_TP
VCC_SENSE VSS_SENSE
RSVD RSVD
AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50
D63
VSS
P62
VSS
T59 AD60 AD59 AA59 AE60 AC59 AG58 U59
+VCCIO_OUT +1.05V
V59
A59 E20
L62 N63 L63
H59
F60 C59
R500 10K_4
AC22 AE22 AE23
B59
P60
TP17
P61
TP59
N59
TP55
N61
TP57
E63 E62
AW14
TP70
AY14
TP71
Processor Strapping
CFG3 (Physcial Debug Enable)
A A
5
DFX Privacy
CFG4 (DP Presence Strap)
The CFG signals have a default value of '1' if not terminated on the board.
1 0
CFG3
CFG4
R554 *1K_4
R246 1K_4
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
* The CFG signals have a default value of "1" if not terminated on the board. * CFG[3] : MSR Privacy Bit Feature,
( " 1 " = Debug capability is determined by IA32_Debug_Interface_MSR (C80h) bit[0] setting. " 0 " = IA32_Debug_Interface_MSR (C80h) bit[0] default setting overridden. )
* CFG[4] : eDP enable, ( " 1 " = Disabled, " 0 " = Enabled )
4
Enable; An ext DP device is connected to eDP
3
Circuit
C
C
C
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
2
Wednesday, October 29, 2014
+VCCIOA_OUT[2] +3VPCU[7,25,27,28,29,30,32,33] +VCC_CORE[36] +VCCIO_OUT[6] +V1.05S_VCCST[2,9,11,36] +1.05V[7,10,11,21,27,30,34,37,39] +1.35VSUS[2,12,13,31,35]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
ULT 3/9 (POWER-1)
ULT 3/9 (POWER-1)
ULT 3/9 (POWER-1)
1
Sheet :
Sheet :
Sheet :
+VCCIOA_OUT +3VPCU +VCC_CORE +VCCIO_OUT +V1.05S_VCCST +1.05V +1.35VSUS
of
of
of
4 44
4 44
4 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
5
4
3
2
1
05
D D
U26I
U26H U26G *I7-5500U 2.4G QH3E
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
VSS
C C
B B
AF11 AF12 AF14 AF15 AF17 AF18
AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57
AJ13 AJ14 AJ23 AJ25 AJ27 AJ29
VSS VSS VSS VSS VSS VSS
AG1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
AJ35
VSS
AJ39
VSS
AJ41
VSS
AJ43
VSS
AJ45
VSS
AJ47
VSS
AJ50
VSS
AJ52
VSS
AJ54
VSS
AJ56
VSS
AJ58
VSS
AJ60
VSS
AJ63
VSS
AK23
VSS
AK3
VSS
AK52
VSS
AL10
VSS
AL13
VSS
AL17
VSS
AL20
VSS
AL22
VSS
AL23
VSS
AL26
VSS
AL29
VSS
AL31
VSS
AL33
VSS
AL36
VSS
AL39
VSS
AL40
VSS
AL45
VSS
AL46
VSS
AL51
VSS
AL52
VSS
AL54
VSS
AL57
VSS
AL60
VSS
AL61
VSS
AM1
VSS
AM17
VSS
AM23
VSS
AM31
VSS
AM52
VSS
AN17
VSS
AN23
VSS
AN31
VSS
AN32
VSS
AN35
VSS
AN36
VSS
AN39
VSS
AN40
VSS
AN42
VSS
AN43
VSS
AN45
VSS
AN46
VSS
AN48
VSS
AN49
VSS
AN51
VSS
AN52
VSS
AN60
VSS
AN63
VSS
AN7
VSS
AP10
VSS
AP17
VSS
AP20
VSS
*I7-5500U 2.4G QH3E
AP22 AP23 AP26 AP29
AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49
AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63
AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
INT
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
TP104
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
*I7-5500U 2.4G QH3E
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
AY2
DAISY_CHAIN_NTCF_AY2
AY3
DAISY_CHAIN_NTCF_AY3
AY60
DAISY_CHAIN_NTCF_AY60
AY61
DAISY_CHAIN_NTCF_AY61
AY62
DAISY_CHAIN_NTCF_AY62
B2
DAISY_CHAIN_NTCF_B2
B3
DAISY_CHAIN_NTCF_B3
B61
DAISY_CHAIN_NTCF_B61
B62
DAISY_CHAIN_NTCF_B62
B63
DAISY_CHAIN_NTCF_B63
C1
DAISY_CHAIN_NTCF_C1
C2
DAISY_CHAIN_NTCF_C2
VSS
DAISY_CHAIN_NTCF_A3
DAISY_CHAIN_NTCF_A4 DAISY_CHAIN_NTCF_A60 DAISY_CHAIN_NTCF_A61 DAISY_CHAIN_NTCF_A62
DAISY_CHAIN_NTCF_AV1 DAISY_CHAIN_NTCF_AW1 DAISY_CHAIN_NTCF_AW2 DAISY_CHAIN_NTCF_AW3
DAISY_CHAIN_NTCF_AW61 DAISY_CHAIN_NTCF_AW62 DAISY_CHAIN_NTCF_AW63
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63 V58 AH46 V23 AH16
A3
DC_TEST_A3_B3
A4
TEST_A4
A60
TEST_A60
A61
DC_TEST_A61_B61
A62
TEST_A62
AV1
TEST_AV1
AW1
TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
TEST_AW63
TP106 TP107TP127
TP105 TP122 TP121
TP126
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
ULT 4/9 (RSV,GND)
ULT 4/9 (RSV,GND)
ULT 4/9 (RSV,GND)
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
5
4
3
2
Wednesday, October 29, 2014
Sheet :
Sheet :
Sheet :
5 44
5 44
1
5 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
of
of
of
5
4
3
2
1
SUSWARN#
+3VS5
R203 *0_4
R211 *0_4/S
+3V
RSMRST#
R194 *0_4/S
R245 *0_4/S
R199 *0_4/S
R237 10K_4
TP63
R560 10K_4
SYS_RESET#
R561 *1K_4
C319 *0.1U/10V_4
R590 10K_4
R178 100K_4 R614 10K_4
SUSACK#
SUSWARN#
DNBSWON#_R
AC_PRESENT_R
PM_BATLOW# PCH_SLP_S0_N PCH_SLP_WLAN_N
Lynx Point-LP Platform Controller Hub (LVDS,DDI)
DSWVRMEN
U26L *I7-5500U 2.4G QH3E
AK2
SUSACK#
AC3
SYS_RESET#
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST#
AW6
RSMRST#
AV4
SUSWARN#/SUSPWRDNACK/GPIO30(SUS)
AL7
PWRBTN#
AJ8
ACPRESENT / GPIO31(DSW)
AN4
BATLOW# / GPIO72(DSW)
AF3
SLP_S0#
AM5
SLP_WLAN#/ GPIO29(DSW)
DSWVRMEN
CLKRUN#/ GPIO32
SUS_STAT# / GPIO61 (SUS)
SUSCLK / GPIO62 (SUS)
SLP_S5# / GPIO63 ( DSW)
System Power Management
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
SLP_LAN#
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
DPWROK
+3VS5
CLKRUN#
SUS_STAT#
PCH_SUSCLK_L
SLP_SUS#
SLP_LAN#
R615 *0_4
R616 *0_4/S
For DS3 -->Ra Non-DS3 -->Rb
R189 1K_4
R576 *0_4/S
R224 *0_4/S
Rb
Ra
RSMRST#
R617 100K_4
DPWROK : Deep Sleep Well Power OK DPWROK need to be shorted to RSMRST# when Deep S4/S5 state is not support.
TP45
TP120
TP53
TP56
DSWVRMEN [7]
DPWROK_EC [30]
PCIE_WAKE# [23,24,25,30]
CLKRUN# [28,30]
PCH_SUSCLK [25,30]
SLP_S5# [11]
SUSC# [11,30]
SUSB# [11,30]
SLP_SUS#_EC [30]
SUSCLK is a square waveform signal output from the RTC oscillation circuit. Square Waveform, 32.7KHz, Vpp=3.3V.
for DS3
for DS3
SUSACK#_EC[30]
System PWR_OK(CLG)
SYS_PWROK is used to inform the Lynx Point that power is
D D
C C
stable to some other system component(s) and the system is ready to start the exit from reset.
SYS_PWROK[11]
C651 *0.1U/10V_4
IMVP_PWRGD[4,36]
EC_PWROK[30]
SUSPWRDNACK / SUSWARN# This signal is Active-high and is driven low by the IntelR ME when it requires the PCH Suspend Well to be powered.
2 1
PWROK (PCH_PWROK) is an indication to the Lynx Point that all of its core power rails have been stable for 5 ms.
APWROK should be should be asserted when all IntelR Management Engine (IntelR ME) power-rails are up and stable.
+3VS5
3 5
for DS3
U28 *TC7SH08FU
SYS_RESET# Input to PCH M cannot float. This pin forces an internal reset to the PCH.
SYS_RESET#[11]
4
SYS_PWROK
R596 *0_4/S
EC_PWROK
PLTRST#[11,14,21,23,24,25,28,30]
RSMRST#[30] SUSWARN#_EC[30]
DNBSWON#[11,30] SLP_A# [11]
AC_PRESENT_EC[30]
PCH_SLP_S0_N[11,30]
SLP_S0# is a PCH signal which indicates the system is in the S0ix State. SLP_S0# stays high in Sx and during Sx entry/exit. This signal will be low during low power state.
U26M *I7-5500U 2.4G QH3E
06
PCH_LVDS_BLON[20] PCH_DISP_ON[20] PCH_DPST_PWM[19,20]
B B
A A
5
EDP_DISP_UTIL[2]
+5V[20,21,22,25,28,29,31,37] +3V_DEEP_SUS[7,8,9,10,11] +VCCIO_OUT[4] +3V[7,8,9,10,11,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +3VS5[9,10,11,22,25,28,31,33,34,37,39]
R495 *0_4
+5V +3V_DEEP_SUS +VCCIO_OUT +3V +3VS5
A9
EDP_BKLEN
C6
EDP_VDDEN
B8
EDP_BKLCTL
DDPB_CTRLCLK
DDPB_CTRLDATA
EDP SIDEBAND
DDPC_CTRLCLK
DDPC_CTRLDATA
DISPLAY
4
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPC_AUXN DDPC_AUXP
DDPC_HPD
EDP_HPD
B9 C9
C5 B5 C8
D9
DDPC_CTRLCLK
D11
DDPC_CTRLDATA
B6 A6 A8
D6
EDP_HPD need pull down via 100KΩ, so combine with RTD2136 pin-1 DP_HPD pull down resistor. If only for eDP panel, EDP_HPD must stuff one 100KΩ.
SDVO_CLK [20]
SDVO_DATA [20]
HDMI_HPD_CON [20]
From HDMI
From CRT (ANX6210)
INT_eDP_HPD_Q
+3V
R154 *2.2K_4
DDI2_CRT_AUXN [21] DDI2_CRT_AUXP [21]
DDI2_CRT_HPD_Q [21]
+5V
3
R155
2.2K_4
2
INT. HDMI DP TO VGA
3
Q11 *2N7002K
1
R254 *0_4/S
R248 *100K_4
+VCCIO_OUT
R264
DG V0.7 -> 10K
*10K/F_4
SCH V0.7 -> 1K
INT_eDP_HPD
R262 *100K_4
R261 *0_4/S
3
Q10 *2N7002K
2
1
Reserve EDP_HPD opposites circuit!
2
ULT_EDP_HPD [19,20]
From PANEL
PCH Pull-high/low(CLG)
SUSACK# SUSWARN#
Check SUSWARN# need PU?
DNBSWON#_R AC_PRESENT_R
PWRBTN# internally PU in PCH to 3.3V_DSW
SYS_PWROK CLKRUN#
C
C
C
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
R210 10K_4 R190 10K_4
R249 *10K_4 R196 *10K_4
R243 *1K_4 R559 8.2K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
ULT 5/9 (Power Manger)
ULT 5/9 (Power Manger)
ULT 5/9 (Power Manger)
1
+3V_DEEP_SUS
Sheet :
Sheet :
Sheet :
for DS3
+3VS5
+3V
6 44
6 44
6 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
of
of
of
5
4
3
2
1
RTC Clock 32.768KHz No stuff for use Green Clock.
R385 20K/F_4
C483 1U/6.3V_4
C503 1U/6.3V_4
BIT_CLK_AUDIO[22]
Output 24MHz
ACZ_SYNC_AUDIO[22] ACZ_RST#_AUDIO[22] ACZ_SDIN0[22] ACZ_SDOUT_AUDIO[22]
2.598V
C502 1U/6.3V_4
30mils
+3V_RTC
RC delay circuit. Delay range 18ms ~ 25ms.
R373 20K/F_4
RC delay circuit. Delay range 18ms ~ 25ms.
RTC Circuitry(RTC) RTC Power trace width 20mils.
D D
3.049V
CN7 BAT_CONN
+3V_RTC_0
12
+3V_RTC_1
3.049V
D3 DB3X313N0L
+3VPCU
R362 1K_4
No-Stuff when Green CLK support & Non-rechargeable cell.
CLKGEN_RTC_X1[27]
R381 *0_6
RTC_RST#[11]
C670 *10P/50V_4
C659 *18P/50V_4
C669 *18P/50V_4
R613 33_4
R281 33_4 R283 33_4
R611 33_4
HDA Bus(CLG)
C C
+3V_DEEP_SUS +3VSPI
R581 *0_4/S
B B
R584 3.3K/F_4
C647 0.1U/10V_4
HOLD#
PCH SPI ROM(CLG)
Vender AMIC Winbond
GigaDevice
Socket
PCH_SPI_CS0#_R[30] PCH_SPI1_CLK_R[30] PCH_SPI1_SI_R[30] PCH_SPI1_SO_R[30]
U25
8
7 4
1
CE#
VDD
6
SCK
5
SI
2
SO
HOLD#
3
WP#
VSS
GD25B64BSIGR
AKE3EGN0Q01
Size 8MB AKE3EFN0800 (A25LQ64M-F) 8MB 8MB
+3VSPI
BIOS_WP#
R518
3.3K/F_4
P/N
AKE3EFP0N07 (W25Q64FVSSIQ) AKE3EGN0Q01 (GD25B64BSIGR) DFHS08FS023
R604 0_4
12
Y7 *32.768KHz
R603 1M_4
+3V_RTC
+3V_DEEP_SUS
R282 *1K_4
XDP_TRST#_CPU[2,11] JTAG_TCK_PCH[11] JTAG_TDI_PCH[11] JTAG_TDO_PCH[11] JTAG_TMS_PCH[11]
JTAGX_PCH[11]
20140904A-Confirm SMT ICT. BIOS PIN-1,2,5,6 TP must on SS (TOP side). TP Size : TP2675
TP14
R515 15/F_4
TP44
R585 15/F_4
TP38
R555 15/F_4 R516 15/F_4
TP12
C648 22P/50V_4
C646 1U/10V_4
R517 15/F_4
TP110
R583 15/F_4
TP119
R605 *10M_4
RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN
ACZ_BCLK ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
XDP_TRST#_CPU JTAG_TCK_PCH JTAG_TDI_PCH JTAG_TDO_PCH JTAG_TMS_PCH
JTAGX_PCH
PCH Strap Table
Pin Name Strap description Sampled Configuration
SPKR
SDIO_D0 /GPIO66
INTVRMEN
HDA_SDO /I2S0_TXD
A A
GSPI0_MOSI /GPIO86
GPIO15
DSWVRMEN
5
No reboot mode setting
Top-Block Swap
Integrated 1.05V VRM enable
Flash Descriptor Security
Only for Interposer
Boot BIOS Selection
TLS Confidentiality
Deep Sx Well On-Die Voltage Regulator Enable
PWROK 0 = Default (weak pull-down 20K)
PWROK
1 = Setting to No-Reboot mode
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
ALWAYS Should be always pull-up
0 = Default (weak pull-down 20K)PWROK
1 = Can be Overridden
GNT0#
Boot Location
PWROK
PWROK
1
LPC
0
SPI(Default)
0 = ME Crypto Transport Layer Security cipher suite with no confidentiality(Default)
1 = Intel ME Crypto TLS cipher suite with confidentiality
ALWAYS Should be always pull-up
4
Circuit
+3V
+3V_RTC
GPIO33_EC[30]
+3V_DEEP_SUS
+3V_RTC
R557 *1K_4 R494 *1K_4 R505 *1K_4
R601 330K_4
R610 1K_4
R177 *1K_4
R602 330K_4
3
PCH_INVRMEN
Lynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)
U26J *I7-5500U 2.4G QH3E
TP77
PCH_SPI1_CLK PCH_SPI_CS0#
PCH_SPI1_SI PCH_SPI1_SO PCH_SPI_IO2
PCH_SPI_IO3
AW5
AY5 AU7 AV6 AU6 AV7
AW8
AV11
AU8
AY10 AU12 AU11
AW10
AV10
AY8
AU62 AE62 AD61 AE61 AD62
AL11
AC4
AE63
AV2
AA3
Y7 Y4
AC2 AA2 AA4
Y6
AF1
SPKR [9]
GPIO66_ULT [9]
ACZ_SDOUT
GPIO15_ULT [9]
DSWVRMEN [6]
RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN
HDA_BCLK / I2S0_SCLK HDA_SYNC/ I2S0_SFRM
HDA_RST#/ I2S_MCLK
HDA_SDIN0/ I2S0_RXD HDA_SDIN1/ I2S1_RXD HDA_SDO/ I2S0_TXD HDA_DOCK_EN# / I2S1_TXD HDA_DOCK_RST/ I2S1_SFRM I2S1_SCLK
PCH_TRST# PCH_TCK PCH_TDI PCH_TDO PCH_TMS
RSVD RSVD
JTAGX RSVD
SPI_CLK SPI_CS0# SPI_CS1#
SPI_CS2# SPI_MOSI SPI_MISO SPI_IO2
SPI_IO3
RTC
LPC
SATA_RN0/ PERN6_L3 SATA_RP0/ PERP6_L3 SATA_TN0/ PETN6_L3
SATA_TP0/ PETP6_L3
SATA_RN1/ PERN6_L2 SATA_RP1/ PERP6_L2 SATA_TN1/ PETN6_L2
SATA_TP1/ PETP6_L2
SATA_RN2/ PERN6_L1 SATA_RP2/ PERP6_L1 SATA_TN2/ PETN6_L1
SATA_TP2/ PETP6_L1
SATA_RN3/ PERN6_L0
AUDIO
SATA_RP3/ PERP6_L0 SATA_TN3/ PETN6_L0
SATA_TP3/ PETP6_L0
SATA0GP/ GPIO34 SATA1GP/ GPIO35 SATA2GP/ GPIO36 SATA3GP/ GPIO37
SATA
SPI JTAG
LAD0 LAD1 LAD2 LAD3
LFRAME#
SATA_RCOMP
SATA_IREF
SATALED#
RSVD RSVD
2
AU14 AW12 AY12 AW11
AV12
J5 H5 B15 A15
J8 H8 A17 B17
J6 H6 B14 C15
F5 E5 C17 D17
V1
SATA0GP_ACC_LED#
U1
SIO_EXT_SMI#
V6
PCI_SERR#
AC1
SATA3GP
C12
SATA_RCOMP
293.51 MIL
A12
SATA_IREF
391.37 MIL
U3
L11 K10
R553 10K_4
LAD0 [25,28,30] LAD1 [25,28,30] LAD2 [25,28,30] LAD3 [25,28,30]
LFRAME# [25,28,30]
SATA_RXN0 [28]
SATA_RXP0 [28] SATA_TXN0 [28]
SATA_TXP0 [28]
SATA_RXN1 [28]
SATA_RXP1 [28] SATA_TXN1 [28]
SATA_TXP1 [28]
SATA_RXN2 [26]
SATA_RXP2 [26] SATA_TXN2 [26]
SATA_TXP2 [26]
DG recommended that SATA AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality.
TP117 TP116 TP114
TP118
R507 3.01K/F_4
R506 *0_6/S
GPIO Pull UP
ACC_LED#
R174 *10K_4
SIO_EXT_SMI#
R546 10K_4
PCI_SERR#
R550 10K_4
SATA3GP
R574 10K_4
JTAGX_PCH
R572 *51_4
JTAG_TMS_PCH
R569 51_4
JTAG_TDI_PCH
R563 51_4
JTAG_TDO_PCH
R252 51_4
JTAG_TCK_PCH
R580 *51_4
Close to Chipset
HDD0 (SATA0 6.0Gb/s)
ODD (SATA1 6.0Gb/s)
mSATA (SATA2 6Gb/s)
R169 *200/F_6
SIO_EXT_SMI# [30]
PCI_SERR# [30]
+V1.05S_ASATA3PLL
+3V
SATA_LED# [29]
+3V
+1.05VS5 +1.05V
+3V_RTC[10,27] +3VPCU[4,25,27,28,29,30,32,33] +3V_RTC_0[27] +3V_DEEP_SUS[6,8,9,10,11] +3VSPI +3V[6,8,9,10,11,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +V1.05S_ASATA3PLL[10] +1.05V[4,10,11,21,27,30,34,37,39] +1.05VS5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
ULT 6/9 (SATA/HDA)
ULT 6/9 (SATA/HDA)
ULT 6/9 (SATA/HDA)
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
ACC_LED#
R255 *0_4
1
Sheet :
Sheet :
Sheet :
TP29
07
+3V_RTC +3VPCU +3V_RTC_0 +3V_DEEP_SUS +3VSPI +3V +V1.05S_ASATA3PLL +1.05V +1.05VS5
of
of
of
7 44
7 44
7 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
5
Lynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)
U26K *I7-5500U 2.4G QH3E
D D
PCIE_RXN2_CARD[24]
Card Reader
WLAN
LAN
VGA
PCIE_RXP2_CARD[24] PCIE_TXN2_CARD[24] PCIE_TXP2_CARD[24]
PCIE_RXN3_WLAN[25] PCIE_RXP3_WLAN[25] PCIE_TXN3_WLAN[25] PCIE_TXP3_WLAN[25]
PCIE_RXN4_LAN[23] PCIE_RXP4_LAN[23] PCIE_TXN4_LAN[23] PCIE_TXP4_LAN[23]
PEG_RXN0[14] PEG_RXP0[14] PEG_TXN0[14] PEG_TXP0[14]
PEG_RXN1[14] PEG_RXP1[14] PEG_TXN1[14] PEG_TXP1[14]
PEG_RXN2[14] PEG_RXP2[14] PEG_TXN2[14] PEG_TXP2[14]
PEG_RXN3[14] PEG_RXP3[14] PEG_TXN3[14] PEG_TXP3[14]
+V1.05S_AUSB3PLL
CLK_PCIE_CRN[24] CLK_PCIE_CRP[24]
PCIE_CLKREQ_CR#[24] CLK_PCIE_WLANN[25]
CLK_PCIE_WLANP[25] PCIE_CLKREQ_WLAN#[25] CLK_PCIE_LANN[23]
CLK_PCIE_LANP[23] PCIE_CLKREQ_LAN#[23] CLK_VGA_N[14]
CLK_VGA_P[14] PCIE_CLKREQ_VGA#[14]
C229 0.1U/10V_4 C228 0.1U/10V_4
C625 0.1U/10V_4 C624 0.1U/10V_4
C627 0.1U/10V_4 C626 0.1U/10V_4
C621 0.22U/10V_4
C632 0.22U/10V_4 C633 0.22U/10V_4
C634 0.22U/10V_4 C635 0.22U/10V_4
C622 0.22U/10V_4 C623 0.22U/10V_4
R143 *0_4/S R144 3.01K/F_4
PCIE_TXN2_CARD_C PCIE_TXP2_CARD_C
PCIE_TXN3_WLAN_C PCIE_TXP3_WLAN_C
PCIE_TXN4_LAN_C PCIE_TXP4_LAN_C
PEG_TXN0_C PEG_TXP0_C
PEG_TXN1_C PEG_TXP1_C
PEG_TXN2_C PEG_TXP2_C
PEG_TXN3_C PEG_TXP3_C
PCIE_RCOMP
PCIE_CLKREQ0#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_VGA#
PCIE_CLKREQ5#
Cardreader
WLAN
LAN
GPU
C C
B B
CLK_REQ/Strap Pin(CLG)
+3V
R551 10K_4 R544 10K_4 R582 10K_4 R536 10K_4 R167 10K_4 R526 10K_4
A A
USB_OC1# USB_OC2# USB_OC3# USB_OC4#
5
PCIE_CLKREQ0# PCIE_CLKREQ5# PCIE_CLKREQ_WLAN# PCIE_CLKREQ_LAN# PCIE_CLKREQ_CR# PCIE_CLKREQ_VGA#
for DS3
R258 10K_4 R277 10K_4 R216 10K_4 R599 10K_4
+3V_DEEP_SUS
G17
PERN1 / USB3RN3
F17
PERP1 / USB3RP3
C30
PETN1 / USB3TN3
C31
PETP1 / USB3TP3
F15
PERN2/ USB3RN4
G15
PERP2/ USB3RP4
B31
PETN2/ USB3TN4
A31
PETP2/ USB3TP4
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
B27
PCIE_IREF
A27
PCIE_RCOMP
E15
199.35 MIL
RSVD
E13
RSVD
C43
CLKOUT_PCIE0N
C42
CLKOUT_PCIE0P
U2
PCIECLKRQ0# / GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1# / GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2# / GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCI_P3
N1
PCIECLKRQ3# / GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4# / GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5# / GPIO23
PCI/USBOC# Pull-up(CLG)
TS_INTB# PIRQC# PIRQD# GPIO77_ULT GPIO52_ULT GPIO53_ULT GPIO55_ULT
4
R541 10K_4 R532 10K_4 R535 10K_4 R531 10K_4 R528 10K_4 R525 10K_4 R161 10K_4
+V1.05S_AXCK_LCPLL[10] +V1.05S_AUSB3PLL[10] +3V_DEEP_SUS[6,7,9,10,11] +3V[6,7,9,10,11,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38]
4
SMBALERT# / GPIO11(SUS)
SMBUS
SML0ALERT# / GPIO60(SUS)
SML1ALERT# / PCHHOT# / GPIO73(SUS)
PCI-E*
CLOCK SIGNALS
+3V
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK / GPIO75(SUS)
SML1DATA / GPIO74(SUS)
XTAL24_IN
XTAL24_OUT
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
CLKOUT_LPC_0 CLKOUT_LPC_1
DIFFCLK_BIASREF
RSVD
RSVD TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8
+V1.05S_AXCK_LCPLL +V1.05S_AUSB3PLL +3V_DEEP_SUS +3V
3
+3V_DEEP_SUS
R588 2.2K_4
R244 2.2K_4
R289 10K_4
R589 1K_4
AN2 AP2 AH1
AL2 AN1 AK1
AU4 AU3 AH3
A25 B25
B35 A35
SMBALERT# SMB_PCH_CLK SMB_PCH_DAT
SML0ALERT# SMB_ME0_CLK SMB_ME0_DAT
SML1ALERT# SMB_ME1_CLK SMB_ME1_DAT
XTAL24_IN XTAL24_OUT
CK_XDP_N_R CK_XDP_P_R
R595 10K_4
TP99 TP98
RP3 *0_4P2R_4
R586 2.2K_4
R175 2.2K_4
TP78
R497 0_4C620 0.22U/10V_4
1
R496 *1M_4
3
2
1
4
3
Stuff for XDP
AN15
CLK_PCI_EC_R
AP15
CLK_PCI_LPC_RPCIE_IREF
C26
XCLK_BIASREF
296.11 MIL
K21 M21 C35
R503 10K/F_4
C34
R504 10K/F_4
AK8
R280 10K/F_4
AL8
R218 10K/F_4
DGPU_PWR_EN[17,37]
DGPU_HOLD_RST#[14]
R606 22_4 R607 22_4
EC62 18P/50V_4
R269 *22_4
R142 3.01K/F_4
+3V
R538 *10K_4
R508 *510/F_4
+3V
R534 *10K_4
R522 100K_4
20141027A-DGPU_HOLD_RST# will make VGA_RST# has a pulse during boot when PU +3V. So change to PD.
3
for DS3
R587 2.2K_4
C629 *12P/50V_4
2
4
C628 *12P/50V_4
USB2.0(M/B-1)
USB2.0/USB3.0 MB Front Side
USB2.0(M/B-2)
USB2.0/USB3.0 MB Rear Side
SMBus/Pull-up(CLG)
R593 2.2K_4
+3V
PCH_XTAL24_IN [27]
Y6 *24MHZ +-30PPM
CLK_24M_DEBUG [25]
EC63
EMI(near PCH)
18P/50V_4
EC17
EMI(near PCH)
*18P/50V_4
+V1.05S_AXCK_LCPLL
USB3.0
20111130 Modify USB3.0 for HM70
R530 0_4 R513 0_4
Q7
2N7002KDW
6 2
5
Q8
*2N7002KDW
5
2 6
CK_XDP_N [11] CK_XDP_P [11]
CLK_24M_KBC [30]
CLK_PCI_TPM [28]
USB30_RX1-[27] USB30_RX1+[27] USB30_TX1-[27] USB30_TX1+[27]
USB30_RX2-[27] USB30_RX2+[27] USB30_TX2-[27] USB30_TX2+[27]
GPIO77_ULT TS_INTB# PIRQC# PIRQD#
GPIO52_ULT DGPU_PWR_EN_R
DGPU_HOLD_RST#_R GPIO53_ULT GPIO55_ULT
PCI_PME#
TP37
2
+3V
1
08
R162
R168
4.7K_4
4.7K_4
1
43
43
1
U26N *I7-5500U 2.4G QH3E
G20
USB3RN1
H20
USB3RP1
C33
USB3TN1
B34
USB3TP1
E18
USB3RN2
F18
USB3RP2
B33
USB3TN2
A33
USB3TP2
U6
PIRQA#/ GPIO77
P4
PIRQB#/ GPIO78
N4
PIRQC#/ GPIO79
N2
PIRQD#/ GPIO80
L1
GPIO52
L3
GPIO54
R5
GPIO51
L4
GPIO53
U7
GPIO55
AD4
PME#
2
SMB_RUN_CLK [11,12,13,19,29]
SMB_RUN_DAT [11,12,13,19,29]
MBCLK2 [19,30]
MBDATA2 [19,30]
CL_CLK
C- Link
CL_DATA CL_RST#
USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7
PCI
USBRBIAS#
USB
USBRBIAS
RSVD RSVD
OC0# / GPIO40(SUS) OC1# / GPIO41(SUS) OC2# / GPIO42(SUS) OC3# / GPIO43(SUS)
AF2 AD2 AF4
AN8 AM8 AR7 AT7 AR8 AP8 AR10 AT10 AM15 AL15 AM13 AN13 AP11 AN11 AR13 AP13
AJ10 AJ11
AN10 AM10
AL3 AT1 AH2 AV3
C
C
C
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
USBP0- [27]
USBP0+ [27]
USBP1- [22]
USBP1+ [22]
USBP2- [20]
USBP2+ [20]
USBP3- [26]
USBP3+ [26]
USBP4- [28]
USBP4+ [28]
USBP5- [27]
USBP5+ [27]
USBP6- [25]
USBP6+ [25]
USBP7­USBP7+
TIE TRACES TOGETHER CLOSE TO PINS WITH LENGTH TO RESISTOR
USB_BIAS
575.6 MIL
USB_OC1# USB_OC2# USB_OC3# USB_OC4#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
ULT 7/9 (PCIE/USB/CLK)
ULT 7/9 (PCIE/USB/CLK)
ULT 7/9 (PCIE/USB/CLK)
USB2.0(M/B-1)
USB2.0/USB3.0 MB Front Side
USB2.0 Small board
USB2.0/USB3.0 Daughter Board
Camera
FMC mSATA SSD Finger Print
USB2.0(M/B-2)
USB2.0/USB3.0 MB Rear Side
WLAN
Co-layout HMC/NGFF 2230
TP74 TP75
R225 22.6/F_4
TP69 TP76 TP50 TP123
Sheet :
Sheet :
Sheet :
1
Touch Screen ( Cancel )
of
of
of
8 44
8 44
8 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
5
4
3
2
1
09
Close to EC
+V1.05S_VCCST
Lynx Point-LP Platform Controller Hub
Lynx Point-LP Platform Controller Hub
Lynx Point-LP Platform Controller HubLynx Point-LP Platform Controller Hub (HDA,JTAG,SATA)
(HDA,JTAG,SATA)
D D
SIO_EXT_SCI#[30] BT_OFF[25] RF_OFF[25]
GPIO15_ULT[7] ZERO_ODD_DP#[28] DGPU_PWROK[16,30,40]
DEVSLP1[26]
R241 10K_4
+3V_DEEP_SUS
for DS3
Reserve
C C
TP72 TP60 TP47
TP49
R568 *0_4
TP19
TP73
20140708A-Cancel G-sensor Circuit.
TP62
No Function.
B B
BOARD_ID0
Model
TWB : 0 JWV : 1
TWB + UMA
TWB + dGPU + N16S
A A
JWV + UMA
JWV + dGPU + N16S
JWV + dGPU + N16V
BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5
GPIO57 GPIO58 GPIO59 GPIO45 GPIO47GPIO56
No Define N16V : 0
0
0 0 0 0
0
1 1 1 1 1
BT_COMBO_EN#[25] GC6_FB_EN[17] GPU_EVENT#[17]
MPHY_PWREN[37]
ACZ_SPKR[22] SPKR[7]
N16S : 1
1
0 0 0 0
TP115 R573 0_4 R539 0_4
TP125
TP113
R558 *0_4/S
No Define No Define
(HDA,JTAG,SATA)(HDA,JTAG,SATA)
Haswell (GPIO)
U26O *I7-5500U 2.4G QH3E
SPKR
AU2
GPIO8(SUS)
AM3
GPIO9(SUS)
AM2
GPIO10(SUS)
AM7
LAN_PHY_PWR_CTRL / GPIO12(DSW)
AT3
GPIO13(SUS)
AH4
GPIO14(SUS)
AD6
GPIO15(SUS)
Y1
GPIO16
T3
GPIO17
AD5
GPIO24 (SUS)
AM4
GPIO25(DSW)
AN3
GPIO26(SUS)
AN5
GPIO27(DSW)
AD7
GPIO28(SUS)
P2
DEVSLP0/ GPIO33
L2
DEVSLP1/ GPIO38
N5
DEVSLP2/ GPIO39
AK4
GPIO44(SUS)
AG5
GPIO45(SUS)
AG3
GPIO46(SUS)
AB6
GPIO47(SUS)
U4
GPIO48
Y3
GPIO49
P3
GPIO50
AG6
GPIO56(SUS)
AP1
GPIO57(SUS)
AL4
GPIO58(SUS)
AT5
GPIO59(SUS)
C4
SDIO_POWER_EN/ GPIO70
Y2
HSIOPC/ GPIO71
P1
BMBUSY# / GPIO76
V2
SPKR/ GPIO81
UMA : 0 dGPU : 1
00000
11 1
00000
SIO_EXT_SCI# BT_OFF RF_OFF LAN_DISABLE# GPIO13_ULT
ODD_PRSNT#_R
GPIO24_ULT GPIO25_ULT GPIO26_ULT GPIO27_ULT GPIO28_ULT DEVSLP0 DEVSLP1 DEVSLP2 GPIO44_ULT BOARD_ID4 ACCEL_INTA# BOARD_ID5 BT_COMBO_EN#
GC6_FB_EN_C GPU_EVENT#_C
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 GPIO70_ULT MPHY_PWREN
GPIO76_ULT
0000TWB + dGPU + N16V
000
GPIO
SERIAL IO
THRMTRIP#
RCIN#/ GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
CPU/MISC
RSVD
GSPI0_CS/ GPIO83
GSPI0_CLK/ GPIO84 GSPI0_MISO/ GPIO85 GSPI0_MOSI/ GPIO86
GSPI1_CS/ GPIO87
GSPI1_CLK/ GPIO88 GSPI1_MISO/ GPIO89 GSPI1_MOSI/ GPIO90
UART0_RXD/ GPIO91 UART0_TXD/ GPIO92 UART0_RTS/ GPIO93 UART0_CTS/ GPIO94
UART1_RXD/ GPIO0
UART1_TXD/ GPIO1
UART1_RST/ GPIO2
UART1_CTS/ GPIO3
I2C0_SDA/ GPIO4
I2C0_SCL/ GPIO5
I2C1_SDA/ GPIO6
I2C1_SCL/ GPIO7
SDIO_CLK/ GPIO64
SDIO_CMD/ GPIO65
SDIO_D0/ GPIO66 SDIO_D1/ GPIO67 SDIO_D2/ GPIO68 SDIO_D3/ GPIO69
R578 10K_4
R240 10K_4
R235 *10K_4
R285 10K_4
R579 10K_4
R562 *10K_4
D60
V4 T4
AW15 AF20 AB21
R6 L6 N6 L8
R7 L5 N7 K2
J1 K3 J2 G1
K4 G2 J3 J4
F2 F3 G4 F1
E3 F4 D3 E4 C3 E2
PCH_THRMTRIP#
EC_RCIN#
SERIRQ
PCH_OPI_RCOMPGPIO14_ULT
253.21 MIL
GSPI0_CS GSPI0_CLK GSPI0_MISO GPIO86_ULT
GSPI1_CS GSPI1_CLK GSPI1_MISO GSPI1_MOSI
UART0_RXD UART0_TXD UART0_RTS UART0_CTS
UART1_RXD UART1_TXD UART1_RST UART1_CTS
I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL
SDIO_CLK SDIO_CMD
SDIO_D1 SDIO_D2 SDIO_D3
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
R509 *0_4/S
+3V
R549 10K_4
R608
49.9/F_4
TP26
GPIO66_ULT [7]
R577 *10K_4
R238 *10K_4
R236 10K_4
R290 *10K_4
R575 *10K_4
RaRb
R566 10K_4
20141008A-BIOS request for SVID, N16S-GT need PU GPIO58 ( BOARD_ID2 ).
5
4
3
R200 1K_4
SERIRQ [28,30]
+3V_DEEP_SUS
PM_THRMTRIP# [30]
EC_RCIN# [30]
+V1.05S_VCCST[2,4,11,36] +3V_DEEP_SUS[6,7,8,10,11] +3V[6,7,8,10,11,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +3VS5[6,10,11,22,25,28,31,33,34,37,39]
GPIO12 LAN_DISABLE# SUS -->Check list +3V -->Datasheet
2
+V1.05S_VCCST +3V_DEEP_SUS +3V +3VS5
RP16 10K_10P8R_6
10
1
UART1_RXD I2C1_SDA GSPI0_CLK GSPI1_CLK
UART0_RXD UART1_CTS GSPI0_CS GSPI1_CS
GSPI1_MOSI GSPI0_MISO GSPI1_MISO UART0_TXD
9 8 7 4
RP18 10K_10P8R_6
10
9 8 7 4
RP17 10K_10P8R_6
10
9 8 7 4
2
3
56
1
2
3
56
1
2
3
56
SDIO_D2 SDIO_D1 SDIO_CMD SDIO_CLK
+3V
UART1_RST UART0_RTS UART0_CTS UART1_TXD
+3V
I2C0_SCL I2C1_SCL I2C0_SDA SDIO_D3
+3V
GPIO Pull-up/Pull-down(CLG)
SIO_EXT_SCI# BT_OFF RF_OFF GPIO13_ULT GPIO14_ULT GPIO24_ULT GPIO26_ULT GPIO28_ULT GPIO44_ULT ACCEL_INTA#
GC6_FB_EN GPU_EVENT#
ODD_PRSNT#_R DGPU_PWROK DEVSLP0 DEVSLP1 DEVSLP2 BT_COMBO_EN# GPIO70_ULT EC_RCIN# GPIO76_ULT
MPHY_PWREN
GPIO25_ULT GPIO27_ULT LAN_DISABLE#
Date:
Date:
Date:
R278 10K_4 R215 10K_4 R213 10K_4 R242 10K_4 R195 10K_4 R191 10K_4 R257 10K_4 R179 10K_4 R220 10K_4 R219 10K_4
R149 *10K_4 R146 *10K_4 R570 10K_4 R547 10K_4 R527 10K_4 R524 10K_4 R533 10K_4 R548 10K_4 R502 10K_4 R545 10K_4 R540 10K_4 R565 100K_4 R564 *10K_4
R198 10K_4 R279 10K_4 R197 10K_4
C
C
C
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
+3V_DEEP_SUS
+3VS5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
ULT 8/9 (GPIO/MISC)
ULT 8/9 (GPIO/MISC)
ULT 8/9 (GPIO/MISC)
+3V
Rev.Size
Rev.Size
Rev.Size
2A
2A
Sheet :
Sheet :
Sheet :
9 44
9 44
1
9 44
2A
of
of
of
5
4
3
2
1
Lynx Point-LP Platform Controller Hub
10
(HDA,JTAG,SATA)(POWER)
AH11
AG10
AE7
Y8
J18 K19
A20
J17
R21 T21
K18 M20 V21
AE20 AE21
J15
K14 K16
Y20 AA21 W21
U8 T9
AB8
AC20
AG16 AG17
+VCCRTCEXT
+V3.3A_DSW_PRTCSUS
C359 1U/6.3V_4
C661 1U/6.3V_4 C671 0.1U/10V_4 C299 0.1U/10V_4
C276 0.1U/10V_4
+V3.3M_PSPI
C263 *0.1U/10V_4
+V1.05S_AXCK_DCB
C260 1U/6.3V_4 C269 47U/6.3VS_8_T100 C268 47U/6.3VS_8_T100
+V1.05S_AXCK_LCPLL
C630 1U/6.3V_4 C614 47U/6.3VS_8_T100 C613 47U/6.3VS_8_T100
+V1.05S_SSCF100
C239 1U/6.3V_4
+V1.05S_SSCFF
C253 1U/6.3V_4
+3V_DEEP_SUS
+V1.5S_ATS +V3.3S_PTS
C643 0.1U/10V_4
+V1.05S_APLLOPI
C275 1U/6.3V_4 C281 *47U/6.3VS_8_T100 C282 *47U/6.3VS_8_T100
+V3.3S_1.8S_SDIO_PCH
C259 1U/6.3V_4
+V1.05A_AOSCSUS
C278 1U/6.3V_4
+V1.05S_DUSB
C293 1U/6.3V_4
2.2uH PN CV-2205JZ00
L14 *0_6/S
D D
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05
VCC1_05=1.741A
DCPSUSBYP DCPSUSBYP
VCCASW VCCASW VCCASW
VCCASW=658mA
VCCASW VCCASW
DCPSUS1=109mA
DCPSUS1 DCPSUS1
VCCHSIO VCCHSIO VCCHSIO
VCCHSIO=1.838A
VCC1_05
VCCMPHY
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
VCCSATA3PLL=42mA
USB3
DCPSUS3
DCPSUS3=10mA
HDA
VCCHDA
VCCHDA=11mA
VRM
DCPSUS2=25mA
DCPSUS2
GPIO/ LCC
VCCSUS3_3 VCCSUS3_3
VCCSUS3_3=63mA
VCCDSW3_3
VCCDSW3_3=114mA
VCC3_3 VCC3_3
POWER
CORE
RTC
VCCRTC < 1mA
SPI
VCCSPI=18mA
VCCACLKPLL
ICC
VCCACLKPLL=31mA
VCCCLK=200mA
THERMAL SENSOR
VCCTS1_5=3mA
VCC3_3=41mA
OPI
VCCAPLL=57mA
SERIAL IO
VCCSDIO=17mA
SUS OSCILLATOR
DCPSUS4=1mA
USB2
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCCLK VCCCLK
VCCCLK
VCCCLK VCCCLK
RSVD RSVD RSVD
VCCSUS3_3 VCCSUS3_3
VCCTS1_5
VCC3_3 VCC3_3
RSVD VCCAPLL VCCAPLL
VCCSDIO VCCSDIO
DCPSUS4
RSVD
VCC1_05 VCC1_05
150.72 MIL
U26P *I7-5500U 2.4G QH3E
J11 H11 H15 AE8
AF22
AG19 AG20
AE9 AF9
AG8
AG14 AG13
AD10
AD8
K9
L10
M9
N8
P9
B18
B11
J13
AH14
AH13
AC9 AA9
AH10
V8
W9
+1.05V
C298
+3.3V_A_DSW_P +PCH_VCCDSW
0411: net : +3.3V_A_DSW_P trace width to 30 mil location: PC347 near to ball AG19,AG20
0.47U/6.3V_4
C307 1U/6.3V_4
+1.05V
+1.05V
OUT GND
+V1.05DX_MODPHY_PCH
+V1.05S_AUSB3PLL
20mil
+V1.05S_ASATA3PLL
20mil
SI Change to 22uF for Intel recommend
R192 *0_4/S
+1.5V
R188 *0_4
+3V
+3V_DEEP_SUS+3VS5
+3VS5
1 2
+3V
C655
0.1U/10V_4
C249 1U/6.3V_4 C238 1U/6.3V_4 C251 *1U/6.3V_4
C631 1U/6.3V_4 C615 22U/6.3VS_8_T100 C616 22U/6.3VS_8_T100
C637 1U/6.3V_4 C618 22U/6.3VS_8_T100 C617 22U/6.3VS_8_T100
+V3.3DX_1.5DX_ADO
+3VS5
+3V
VCCHSIO : It's power supply for HSIO device. If support HSIO, this power trace must follow design guide.
C C
+1.05V_MODPHY
+1.05V_MODPHY
L35 2.2uH/500mA_6
L33 2.2uH/500mA_6
+1.5V +3V
B B
for DS3
SLP_SUS_ON[30]
+3VS5 +3V_DEEP_SUS
R594 100K_4
R591 *0_4/S
C653 *10P/50V_4
R592 *0_6
C650 1U/6.3V_4
U27
5
IN
4
IN
3
ON/OFF
IC(5P) G5243AT11U
+V1.05S_CORE_PCH
+1.05V
C290 1U/6.3V_4 C283 1U/6.3V_4 C247 10U/6.3VS_6_T47
TP52
+1.05V
C289 1U/6.3V_4 C649 *22U/6.3VS_8_T100
+1.05V
TP39
TP18
+V3.3DX_1.5DX_PAZSUS_PCH
C288 1U/6.3V_4
TP48
C279 22U/6.3VS_8_T100
C305 *1U/6.3V_4
C248 22U/6.3VS_8_T100
+PCH_VCCDSW
+V1.05M_ASW
+V1.05M_FHV0 +V1.05M_FHV1
+V1.05A_SUS_PCH
+1.05V
+V1.05S_AIDLE
C266 *1U/6.3V_4
1001.87 MIL
914.84 MIL
+V1.05A_VCCUSB3SUS
231.72 MIL
+V1.05A_USB2SUS
+3V_DEEP_SUS
+3.3V_A_DSW_P
+V3.3S_PCORE
+3V_DEEP_SUS
+3V_RTC
R173 *0_4/S R172 *0_4
L13 2.2uH/500mA_6
+V1.05S_AXCK_LCPLL
L34 2.2uH/500mA_6
R170 *0_6/S
R176 *0_6/S
+1.5V +3V
+3V
TP35
+1.05V
+3V_DEEP_SUS
+3V_RTC
+1.05V
+1.05V
+1.05V
+1.05V
+3V_DEEP_SUS
+1.5V +3V
+1.05V
+1.05V
+3V
+1.05V
+3V_DEEP_SUS
+3V_DEEP_SUS +3V
+3V
+1.05V
+1.05V
+1.05V
+1.05V
+V1.05DX_MODPHY_PCH[37] +1.05V_MODPHY[37] +V1.05S_AXCK_LCPLL[8]
A A
5
4
3
+V3.3DX_1.5DX_ADO +V1.05S_AUSB3PLL[8] +V1.05S_ASATA3PLL[7] +3V_DEEP_SUS[6,7,8,9,11]
+1.5V[22,25,26,34] +3V[6,7,8,9,11,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +3VS5[6,9,11,22,25,28,31,33,34,37,39] +3V_RTC[7,27] +1.05V[4,7,11,21,27,30,34,37,39]
2
+V1.05DX_MODPHY_PCH +1.05V_MODPHY +V1.05S_AXCK_LCPLL +V3.3DX_1.5DX_ADO +V1.05S_AUSB3PLL +V1.05S_ASATA3PLL +3V_DEEP_SUS +1.5V +3V +3VS5 +3V_RTC +1.05V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
ULT 9/9 (POWER-2)
ULT 9/9 (POWER-2)
ULT 9/9 (POWER-2)
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Rev.Size
Rev.Size
Rev.Size
2A
2A
Sheet :
Sheet :
Sheet :
10 44
10 44
1
10 44
2A
of
of
of
5
4
3
2
1
11
D D
CN5 *SEC_BSH-030-01-L-D-A-TR
XDP_PREQ#_CPU[2] XDP_PRDY#_CPU[2]
CFG0[4] CFG1[4]
CFG2[4] CFG3[4]
XDP_BPM0[2] XDP_BPM1[2]
CFG4[4] CFG5[4]
CFG6[4] CFG7[4]
+3VS5
R618 *0_4/S R621 *0_4/S
R622 *0_4/S R623 *0_4/S
R624 *0_4/S R626 *0_4/S R627 *0_4/S R629 *0_4
R631 *0_4/S
R171 *1K_4
PWR_DEBUG[4]
SMB_RUN_DAT[8,12,13,19,29] SMB_RUN_CLK[8,12,13,19,29]
JTAG_TCK_PCH[7]
XDP_TCK0[2]
JTAGX_PCH[7]
JTAG_TMS_PCH[7]
+1.05V
C331 *0.1U/10V_4
C C
SYS_PWROK[6]
B B
A A
R232 *0_4/S
H_VCCST_PWRGD[4]
+3V_DEEP_SUS
APS
CN19 *ACES_88511-180N
R164 *1K_4
C250 *0.1U/10V_4
10 11 12 13 14 15 16 17 18
+3V_DEEP_SUS
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18
R212 *1K_4
CFG1 CFG2
CFG3 OBSFN_B0
OBSFN_B1 CFG4
CFG5 CFG6
CFG7 VCCST_PWRGD_XDP
DNBSWON#
R222 *0_4/S
R231 *0_4
SUSB# [6,11,30]
SLP_S5# [6]
SUSC# [6,30]
SLP_A# [6]
RTC_RST# [7]
DNBSWON# [6,30]
SYS_RESET# [6]
PCH_SLP_S0_N [6,30]
SUSB# [6,11,30]
31
R158 *1K_4
R217 *0_4/S
R620 *0_4/S R619 *0_4
30
31
30
29
323229
28
333328
27
343427
26
353526
25
363625
24
373724
23
383823
22
393922
21
404021
20
414120
19
424219
18
434318
17
444417
16
454516
15
464615
14
474714
13
484813
12
494912
11
505011
10
515110
9
52529
8
53538
7
54547
6
55556
5
56565
4
57574
3
58583
2
59592
1
60601
R208 *0_4
R165 *0_4/S
+3V_DEEP_SUS +3VS5
OBSFN_C0 OBSFN_C1
CFG8 CFG9
CFG10 CFG11
OBSFN_D0 OBSFN_D1
CFG12 CFG13
CFG14 CFG15
XDP_TDO XDP_TDIXDP_TCK1
XDP_TMS
CFG17 [4] CFG16 [4]
CFG8 [4] CFG9 [4]
CFG10 [4] CFG11 [4]
CFG19 [4] CFG18 [4]
CFG12 [4] CFG13 [4]
CFG14 [4] CFG15 [4]
CK_XDP_P [8] CK_XDP_N [8]
JTAG_TDO_PCH[7]
+1.05V
XDP_RST XDP_DBRESET_NH_SYS_PWROK_XDP
R204 *0_4/S
R205 *0_4
C332 *0.1U/10V_4
+V1.05S_VCCST
R201 *51_4
HWPG[4,30,33,34,35]
R214 *1K_4
+3V
R206 *0_4/S
XDP_TRST#
XDP_TDO
XDP_TDI_R
XDP_TMS
R160 *1K_4
C235 *0.1U/10V_4
R223 *0_4/S
+3V
U8 *SN74CBTLV3126RGYR
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
+1.05V[4,7,10,21,27,30,34,37,39] +3V[6,7,8,9,10,12,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +3V_DEEP_SUS[6,7,8,9,10] +3VS5[6,9,10,22,25,28,31,33,34,37,39] +V1.05S_VCCST[2,4,9,36]
PLTRST# [6,14,21,23,24,25,28,30]
JTAG_TDI_PCH [7]
C261 *0.1U/10V_4
1B
2B
3B
4B
DPAD
GND
3
6
8
11
15 7
+1.05V +3V +3V_DEEP_SUS +3VS5 +V1.05S_VCCST
XDP_TDO_CPU [2]
XDP_TDI_CPU [2]
XDP_TMS_CPU [2]
XDP_TRST#_CPU [2,7]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
HSW XDP & APS
HSW XDP & APS
HSW XDP & APS
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
5
4
3
2
Wednesday, October 29, 2014
Sheet :
Sheet :
Sheet :
11 44
11 44
1
11 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
of
of
of
5
4
3
2
1
12
M_A_A[15:0][3]
D D
M_A_BS#0[3] M_A_BS#1[3] M_A_BS#2[3] M_A_CS#0[3] M_A_CS#1[3] M_A_CLKP0[3] M_A_CLKN0[3] M_A_CLKP1[3] M_A_CLKN1[3] M_A_CKE0[3] M_A_CKE1[3] M_A_CAS#[3] M_A_RAS#[3]
R379 10K/F_4 R380 10K/F_4
C C
M_A_WE#[3]
SMB_RUN_CLK[8,11,13,19,29] SMB_RUN_DAT[8,11,13,19,29]
M_A_ODT0[13] M_A_ODT1[13]
M_A_DQSP[7:0][3]
M_A_DQSN[7:0][3]
CPU Bracket
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
DIMM0_SA0 DIMM0_SA1 +SMDDR_VREF_DIMM SMB_RUN_CLK SMB_RUN_DAT
M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7
CN26A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3-DIMM0_H=5.2_STD
DGMK4000406
IC SOCKET DDR3 SODIMM(204P,H5.2,STD)
ddr-ds1sk-20401-std-204p-smt
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
EZIW
5
M_A_DQ5
7
M_A_DQ4
15
M_A_DQ6
17
M_A_DQ2
4
M_A_DQ1
6
M_A_DQ0
16
M_A_DQ7
18
M_A_DQ3
21
M_A_DQ13
23
M_A_DQ12
33
M_A_DQ14
35
M_A_DQ15
22
M_A_DQ9
24
M_A_DQ8
34
M_A_DQ11
36
M_A_DQ10
39
M_A_DQ21
41
M_A_DQ20
51
M_A_DQ19
53
M_A_DQ23
40
M_A_DQ17
42
M_A_DQ16
50
M_A_DQ18
52
M_A_DQ22
57
M_A_DQ24
59
M_A_DQ25
67
M_A_DQ31
69
M_A_DQ27
56
M_A_DQ28
58
M_A_DQ29
68
M_A_DQ30
70
M_A_DQ26
129
M_A_DQ36
131
M_A_DQ33
141
M_A_DQ34
143
M_A_DQ35
130
M_A_DQ32
132
M_A_DQ37
140
M_A_DQ38
142
M_A_DQ39
147
M_A_DQ44
149
M_A_DQ45
157
M_A_DQ46
159
M_A_DQ42
146
M_A_DQ40
148
M_A_DQ41
158
M_A_DQ47
160
M_A_DQ43
163
M_A_DQ49
165
M_A_DQ52
175
M_A_DQ50
177
M_A_DQ51
164
M_A_DQ55
166
M_A_DQ48
174
M_A_DQ54
176
M_A_DQ53
181
M_A_DQ59
183
M_A_DQ56
191
M_A_DQ63
193
M_A_DQ58
180
M_A_DQ57
182
M_A_DQ60
192
M_A_DQ62
194
M_A_DQ61
M_A_DQ[63:0] [3]
VREF DQ0 M1 Solution
SMDDR_VREF_DQ0_M3[3]
+SMDDR_VREF_DIMM[12,13]
DDR_VTTREF[13,35]
SM_VREF[3]
R350 2/F_6
C456
0.022U/25V_4
2 1
R355
24.9/F_4
PM_EXTTS#0[13] DDR3_DRAMRST#[2,13]
SMDDR_VREF_DQ0_M1
R347 *0_6
R397 *0_6
R398 2/F_6
C519
0.022U/25V_4
2 1
R392
24.9/F_4
+3V
+1.35VSUS
R299 10K/F_4
C476 *0.1U/10V_4
R349
1.8K/F_4
R351 *0_6/S
R346
+1.35VSUS
1.8K/F_4
R391
1.8K/F_4
R383
1.8K/F_4
2.48A
+3V
+SMDDR_VREF_DQ0
+1.35VSUS
CN26B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM0_H=5.2_STD
ddr-ds1sk-20401-std-204p-smt
DGMK4000406
IC SOCKET DDR3 SODIMM(204P,H5.2,STD)
VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
VTT1 VTT2
GND GND
44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
203 204
205 206
+0.675V_DDR_VTT
B B
For EMI RESERVE
+1.35VSUS
EC47 120P/50V_4 EC37 120P/50V_4 EC31 120P/50V_4 EC30 120P/50V_4 EC32 120P/50V_4 EC25 120P/50V_4 EC28 120P/50V_4
+0.675V_DDR_VTT
EC51 120P/50V_4 EC42 120P/50V_4
A A
5
4
+1.35VSUS
EC44 120P/50V_4 EC52 120P/50V_4 EC54 120P/50V_4 EC38 0.1U/10V_4 EC34 0.1U/10V_4 EC36 0.1U/10V_4 EC50 0.1U/10V_4
20140821A−EMI request.
Place these Caps near So-Dimm0.
1uF/10uF 4pcs on each side of connector
+1.35VSUS +0.675V_DDR_VTT
C488 1U/6.3V_4 C494 1U/6.3V_4 C489 1U/6.3V_4 C451 1U/6.3V_4 C455 1U/6.3V_4 C452 1U/6.3V_4 C454 1U/6.3V_4 C453 1U/6.3V_4
C493 10U/6.3V_6 C492 10U/6.3V_6 C491 10U/6.3V_6 C457 10U/6.3V_6 C458 10U/6.3V_6 C515 10U/6.3V_6 C490 10U/6.3V_6 C514 10U/6.3V_6
3
C498 1U/6.3V_4 C496 1U/6.3V_4 C504 1U/6.3V_4 C478 1U/6.3V_4 C510 10U/6.3V_6
+SMDDR_VREF_DIMM
C484 *0.1U/10V_4 C477 *2.2U/6.3V_6
+SMDDR_VREF_DQ0
C448 *0.1U/10V_4 C450 *2.2U/6.3V_6
+3V
C381 0.1U/10V_4 C479 2.2U/6.3V_6
+3V[6,7,8,9,10,11,13,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +1.35VSUS[2,4,13,31,35] +0.675V_DDR_VTT[13,35] +SMDDR_VREF_DIMM[12,13] +SMDDR_VREF_DQ0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
DDR3L DIMM0-STD (5.2H)
DDR3L DIMM0-STD (5.2H)
DDR3L DIMM0-STD (5.2H)
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
2
Wednesday, October 29, 2014
1
Sheet :
Sheet :
Sheet :
+3V +1.35VSUS
+0.675V_DDR_VTT +SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
of
of
of
12 44
12 44
12 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
5
4
3
2
1
13
Sheet :
Sheet :
Sheet :
M_B_DQ[63:0] [3]
of
of
of
13 44
13 44
13 44
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
+1.35VSUS
2.48A
D D
PM_EXTTS#0[12] DDR3_DRAMRST#[2,12]
+1.35VSUS
VREF DQ1 M1 Solution
5
R329 *0_6
R328 2/F_6
C420
0.022U/25V_4
2 1
R330
24.9/F_4
DDR_VTTREF[12,35]
SMDDR_VREF_DQ1_M3[3]
C C
B B
Place these Caps near So-Dimm1.
1uF/10uF 4pcs on each side of connector
+1.35VSUS +0.675V_DDR_VTT
C438 1U/6.3V_4 C441 1U/6.3V_4 C517 1U/6.3V_4 C439 1U/6.3V_4 C436 1U/6.3V_4 C435 1U/6.3V_4 C440 1U/6.3V_4 C434 1U/6.3V_4 C419 10U/6.3V_6
C412 10U/6.3V_6
A A
C414 10U/6.3V_6 C413 10U/6.3V_6
C416 10U/6.3V_6 C415 10U/6.3V_6
C411 10U/6.3V_6 C418 10U/6.3V_6
R324
1.8K/F_4
R325
1.8K/F_4
+SMDDR_VREF_DIMM[12]
C383 1U/6.3V_4 C382 1U/6.3V_4 C370 1U/6.3V_4 C369 1U/6.3V_4 C367 10U/6.3V_6
+3V
C368 0.1U/10V_4 C366 2.2U/6.3V_6
PM_EXTTS#0
C459 *0.1U/10V_4
R337 *0_6/S
+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1
+3V
+SMDDR_VREF_DQ1SMDDR_VREF_DQ1_M1
C437 *0.1U/10V_4 C430 *2.2U/6.3V_6
C426 *0.1U/10V_4 C431 *2.2U/6.3V_6
4
CN22B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM1_H=5.15_RVS
DGMK4000425
IC SOCKET DDRIII SO-DIMM(204P,H5.15,RVS)
ddr-ds1rk-20401-tp5b-rvs-204p
DDR_PG_CNTL[2]
PC2100 DDR3 SDRAM SO-DIMM
2
Q23 LTC044
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
203
VTT1 VTT2
GND GND
+5VPCU
R402 100K_4
1 3
+0.675V_DDR_VTT
204 205
206
+1.35VSUS
2
DDR_VTT_PG_CTRL
+5VS5
R406 220K_4
Q21 2N7002K
R405 *0_4
R403 *2M/F_4
3
3
2
C525 0.1U/10V_4
1
3
1
Q22 2N7002K
R296 10K/F_4 R295 10K/F_4
+3V
R377 66.5/F_4
R378 66.5/F_4
51216S3 [35]
M_B_A[15:0][3]
SMB_RUN_CLK[8,11,12,19,29] SMB_RUN_DAT[8,11,12,19,29]
R334 66.5/F_4 R331 66.5/F_4
M_B_DQSP[7:0][3]
M_B_DQSN[7:0][3]
M_B_BS#0[3] M_B_BS#1[3] M_B_BS#2[3] M_B_CS#0[3] M_B_CS#1[3] M_B_CLKP0[3] M_B_CLKN0[3] M_B_CLKP1[3] M_B_CLKN1[3] M_B_CKE0[3] M_B_CKE1[3] M_B_CAS#[3] M_B_RAS#[3] M_B_WE#[3]
+1.35VSUS[2,4,12,31,35] +3V[6,7,8,9,10,11,12,14,16,17,19,20,21,22,23,24,25,26,28,29,30,31,36,37,38] +0.675V_DDR_VTT[12,35] +5VPCU[33] +5VS5[22,27,31,33,35,36,37,38,40]
M_A_ODT0 [12]
M_A_ODT1 [12]
2
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
DIMM1_SA0 DIMM1_SA1
M_B_ODT0 M_B_ODT1
M_B_DQSP2 M_B_DQSP0 M_B_DQSP1 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN2 M_B_DQSN0 M_B_DQSN1 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7
CN22A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3-DIMM1_H=5.15_RVS
DGMK4000425
IC SOCKET DDRIII SO-DIMM(204P,H5.15,RVS)
ddr-ds1rk-20401-tp5b-rvs-204p
+1.35VSUS +3V
+0.675V_DDR_VTT +5VPCU +5VS5
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Date:
Date:
Date:
5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
M_B_DQ22
7
M_B_DQ23
15
M_B_DQ21
17
M_B_DQ18
4
M_B_DQ16
6
M_B_DQ17
16
M_B_DQ20
18
M_B_DQ19
21
M_B_DQ4
23
M_B_DQ5
33
M_B_DQ6
35
M_B_DQ7
22
M_B_DQ2
24
M_B_DQ3
34
M_B_DQ1
36
M_B_DQ0
39
M_B_DQ9
41
M_B_DQ8
51
M_B_DQ11
53
M_B_DQ10
40
M_B_DQ12
42
M_B_DQ13
50
M_B_DQ15
52
M_B_DQ14
57
M_B_DQ26
59
M_B_DQ27
67
M_B_DQ29
69
M_B_DQ28
56
M_B_DQ30
58
M_B_DQ31
68
M_B_DQ24
70
M_B_DQ25
129
M_B_DQ32
131
M_B_DQ33
141
M_B_DQ38
143
M_B_DQ34
130
M_B_DQ36
132
M_B_DQ37
140
M_B_DQ35
142
M_B_DQ39
147
M_B_DQ40
149
M_B_DQ43
157
M_B_DQ47
159
M_B_DQ46
146
M_B_DQ41
148
M_B_DQ42
158
M_B_DQ44
160
M_B_DQ45
163
M_B_DQ52
165
M_B_DQ51
175
M_B_DQ54
177
M_B_DQ48
164
M_B_DQ49
166
M_B_DQ55
174
M_B_DQ50
176
M_B_DQ53
181
M_B_DQ63
183
M_B_DQ62
191
M_B_DQ59
193
M_B_DQ60
180
M_B_DQ56
182
M_B_DQ57
192
M_B_DQ61
194
M_B_DQ58
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
DDR3L DIMM1-RVS (5.2H)
DDR3L DIMM1-RVS (5.2H)
DDR3L DIMM1-RVS (5.2H)
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
1
1
A A
+1.05V_GFX
Near GPU
C134 22U/6.3VS_6_T100 C162 *22U/6.3VS_6_T100 C165 10U/6.3VS_6_T47 C141 *10U/6.3VS_6_T47 C94 4.7U/6.3V_6
C131 1U/6.3V_4 C135 *1U/6.3V_4
PEX_IOVDD + PEX_IOVDDQ = 1.042A
B B
Under GPU
+1.05V_GFX
C154 22U/6.3VS_6_T100 C128 *22U/6.3VS_6_T100 C160 10U/6.3VS_6_T47 C150 *10U/6.3VS_6_T47 C124 4.7U/6.3V_6
Near GPU
Under GPU
C96 1U/6.3V_4 C88 *1U/6.3V_4
PEX_PLL_HVDD + PEX_SVDD_3V3 = 143mA
+3V_AON
C145 0.1U/10V_4 C143 4.7U/6.3V_6 C156 4.7U/6.3V_6
Near GPU
C C
VGPU_CORE_SENSE[38]
VSS_GPU_SENSE[38]
R421 *200/F_4
R73 0_6
+1.05V_GFX
CX300T30001 Change to 0ohm
Near GPU
C84 4.7U/6.3V_6
D D
1
C86 1U/6.3V_4
Under GPU
C123 0.1U/10V_4
PEX_PLLVDD = 130mA
R432 10K/F_4
R420 2.49K/F_4
PLTRST#[6,11,21,23,24,25,28,30] DGPU_HOLD_RST#[8]
PEX_TSTCLK PEX_TSTCLK#
PEX_PLLVDD
TESTMODE
PEX_TERMP
2
AA22 AB23 AC24 AD25 AE26 AE27
AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27
AF22 AE22
AA14 AA15
AF25
2
AA8 AA9
AB8
F2
F1
AD9
C604
0.1U/10V_4
2 1
U20A
PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
PEX_PLL_HVDD PEX_PLL_HVDD
PEX_SVDD_3V3
VDD_SENSE
GND_SENSE
PEX_TSTCLK_OUT PEX_TSTCLK_OUT
PEX_PLLVDD PEX_PLLVDD
TESTMODE
PEX_TERMP
+3V
U24 MC74VHC1G08DFT2G
3 5
3
BOM Default by N16S-GT for Support GC6 2.0.
4
R486 0_4
GC6 2.0
R487 *0_4
N16S-GT support GC6 function
GPU_PEX_RST_HOLD#[17] DGPU_OVT# [30]VGA_OVT#[17]
N16V-GM not support GC6 function
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
1/14 PCI_EXPRESS
PEX_WAKE
PEX_RST
PEX_CLKREQ
PEX_REFCLK PEX_REFCLK
PEX_TX0 PEX_TX0
PEX_RX0 PEX_RX0
PEX_TX1 PEX_TX1
PEX_RX1 PEX_RX1
PEX_TX2 PEX_TX2
PEX_RX2 PEX_RX2
PEX_TX3 PEX_TX3
PEX_RX3 PEX_RX3
PEX_TX4 PEX_TX4
PEX_RX4 PEX_RX4
PEX_TX5 PEX_TX5
PEX_RX5 PEX_RX5
PEX_TX6 PEX_TX6
PEX_RX6 PEX_RX6
PEX_TX7 PEX_TX7
PEX_RX7 PEX_RX7
PEX_TX8 PEX_TX8
PEX_RX8 PEX_RX8
PEX_TX9 PEX_TX9
PEX_RX9 PEX_RX9
PEX_TX10 PEX_TX10
PEX_RX10 PEX_RX10
PEX_TX11 PEX_TX11
PEX_RX11 PEX_RX11
PEX_TX12 PEX_TX12
PEX_RX12 PEX_RX12
PEX_TX13 PEX_TX13
PEX_RX13 PEX_RX13
PEX_TX14 PEX_TX14
PEX_RX14 PEX_RX14
PEX_TX15 PEX_TX15
PEX_RX15 PEX_RX15
GF119GF117
COMMONbga595-nvidia-n13p-gv2-s-a2
3
AB6
AC7 AC6 AE8
AD8 AC9
AB9 AG6
AG7 AB10
AC10 AF7
AE7 AD11
AC11 AE9
AF9 AC12
AB12 AG9
AG10 AB13
AC13 AF10
AE10 AD14
AC14 AE12
AF12 AC15
AB15 AG12
AG13 AB16
AC16 AF13
AE13 AD17
AC17 AE15
AF15 AC18
AB18 AG15
AG16 AB19
AC19 AF16
AE16 AD20
AC20 AE18
AF18 AC21
AB21 AG18
AG19 AD23
AE23 AF19
AE19 AF24
AE24 AE21
AF21 AG24
AG25 AG21
AG22
VGA_RST# PEX_CLKREQ#
PEG_RXP0_C PEG_RXN0_C
PEG_RXP1_C PEG_RXN1_C
PEG_RXP2_C PEG_RXN2_C
PEG_RXP3_C PEG_RXN3_C
+3V
C605 0.1U/10V_4 U22
MC74VHC1G08DFT2G
2 1
3 5
C188 0.22U/10V_4 C189 0.22U/10V_4
C178 0.22U/10V_4 C179 0.22U/10V_4
C177 0.22U/10V_4 C176 0.22U/10V_4
C191 0.22U/10V_4 C190 0.22U/10V_4
NVDD = 32.22 ~ 26.66 A
C104 22U/6.3VS_6_T100 C610 47U/6.3VS_8_T100
C120 4.7U/6.3V_6 C138 4.7U/6.3V_6 C591 4.7U/6.3V_6 C592 4.7U/6.3V_6 C103 4.7U/6.3V_6
4
+3V_AON
GC6 2.0
R473 10K/F_4
GC6 2.0
4
PEGX_RST#
R475 100K/F_4
Under GPU
C127 0.1U/10V_4 C594 0.1U/10V_4 C101 0.1U/10V_4 C588 0.1U/10V_4 C140 4.7U/6.3V_6 C136 4.7U/6.3V_6 C137 4.7U/6.3V_6 C99 4.7U/6.3V_6 C595 4.7U/6.3V_6 C590 4.7U/6.3V_6 C593 4.7U/6.3V_6 C599 4.7U/6.3V_6 C121 4.7U/6.3V_6 C129 4.7U/6.3V_6 C107 4.7U/6.3V_6
+
C117 330U_2.5V_3528
Near GPU
4
5
This GPIO monitors the PCIe reset assertion from the system side during GC6 residency.
C598 *0.1U/10V_4
U20E
11/14 NVVDD
K10
VDD
K12
VDD
K14
VDD
K16
VDD
K18
VDD
L11
VDD
L13
VDD
L15
VDD
L17
VDD
M10
VDD
M12
VDD
M14
VDD
M16
VDD
M18
VDD
N11
VDD
N13
VDD
N15
VDD
N17
VDD
P10
VDD
P12
VDD
P14
VDD
P16
VDD
P18
VDD
R11
VDD
R13
VDD
R15
VDD
R17
VDD
T10
VDD
T12
VDD
T14
VDD
T16
VDD
T18
VDD
U11
VDD
U13
VDD
U15
VDD
U17
VDD
V10
VDD
V12
VDD
V14
VDD
V16
VDD
V18
VDD
bga595-nvidia-n13p-gv2-s-a2 COMMON
SYS_PEX_RST_MON# [17]
+3V_AON
+3V_AON
R444 10K/F_4
2
5
R469 10K/F_4
+3V_GFX
Q29 *2N7002K
1
2
R445
4.7K_4
CLKREQ_C1
Q28 LTC044
1 3
U20C
AD10
AD7
B19
F11
V5 V6
G1 G2 G3 G4 G5 G6 G7
V1 V2
W1 W2 W3 W4
bga595-nvidia-n13p-gv2-s-a2 COMMON
3
2
14/14 XVDD/VDD33
NC NC NC
3V3AUX_NC
FERMI_RSVD1_NC FERMI_RSVD2_NC
CONFIGURABLE POWER CHANNELS * nc on substrate
XPWR_G1 XPWR_G2 XPWR_G3 XPWR_G4 XPWR_G5 XPWR_G6 XPWR_G7
XPWR_V1 XPWR_V2
XPWR_W1 XPWR_W2 XPWR_W3 XPWR_W4
GC6 2.0
CLK_VGA_P [8]
CLK_VGA_N [8]
PEG_RXP0 [8] PEG_RXN0 [8]
PEG_TXP0 [8] PEG_TXN0 [8]
PEG_RXP1 [8] PEG_RXN1 [8]
PEG_TXP1 [8] PEG_TXN1 [8]
PEG_RXP2 [8] PEG_RXN2 [8]
PEG_TXP2 [8] PEG_TXN2 [8]
PEG_RXP3 [8] PEG_RXN3 [8]
PEG_TXP3 [8] PEG_TXN3 [8]
+VGACORE
12
R477 0_4
6
Q27 LTC044
1 3
VDD33 = 56mA
VDD33 VDD33 VDD33 VDD33
6
PCIE_CLKREQ_VGA# [8]
Power down sequence
G10 G12 G8 G9
7
Power up sequence
VDD33 +3.3V_GFX
+VCC_DGFX_CORE
FBVDDQ +1.5V_GFX
PEX_VDD +1.05V_GFX
IFP(CDEF)_IOVDD +1.05V_GFX
C122 0.1U/10V_4
PLACE NEAR BALLS
1 2
C210 1U/10V_6 C209 4.7U/6.3V_6
PLACE NEAR BGA
C147 0.1U/10V_4 C155 0.1U/10V_4
PLACE NEAR BALLS
1 2
C152 1U/10V_6 C158 4.7U/6.3V_6
PLACE NEAR BGA
7
t>0NVVDD
t>0
t>0
BOM Default by N16S-GT for Support GC6 2.0.
N16S-GT support GC6 function
R130 0_4
R83 *0_4
R85 0_4
N16V-GM not support GC6 function
N16S-GT support GC6 function
Quanta Computer Inc.
Quanta Computer Inc.
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Quanta Computer Inc.
Quanta Computer Inc.
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Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
PROJECT : TWB & JWV ( MB )
Document Number
Document Number
Document Number
C
C
C
N16x-PCIe & Power-1
N16x-PCIe & Power-1
N16x-PCIe & Power-1
Date:
Date:
Date:
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Wednesday, October 29, 2014
Sheet :
Sheet :
Sheet :
t>=0
+3V_AON
+3V_GFX
8
14
of
of
of
14 44
14 44
14 44
8
Rev.Size
Rev.Size
Rev.Size
2A
2A
2A
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