Prestigio NOBILE 159W Technical & Service Manual

PRESTIGIO NOBILE 159W

TECHNICAL SERVICE

MANUAL

TECHNICAL SERVICE MANUAL Prestigio Nobile 159W

1.1. Hardware Specification…………………………………………………….

1.2. Software Specification……………………………………………………..

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1.1 Hardware Specification.
A. CPU

The Intel® Pentium® M processor is a high performance, low power mobile processor with

several micro-architectural enhancements over existing Intel mobile processors.

The following list provides some of the key features on this processor:

Supports Intel® Architecture with Dynamic Execution
High performance, low-power core
On-die, primary 32-kbyte instruction cache and 32-kbyte write-back data cache
On-die, 1-MByte second level cache with Advanced Transfer Cache Architecture
Advanced Branch Prediction and Data Prefetch Logic
Streaming SIMD Extensions 2 (SSE2)
400-MHz, Source-Synchronous processor system bus
Advanced Power Management features including Enhanced Intel SpeedStep® technology
Micro-FCPGA and Micro-FCBGA packaging technologies

The Intel Pentium M processor is manufactured on Intel’s advanced 0.13 micron process

technology with copper interconnect. The processor maintains support for MMX™ technology and

Internet Streaming SIMD instructions and full compatibility with IA-32 software. The high

performance core features architectural innovations hlike Micro-op Fusion and Advanced Stack

Management that reduce the number of micro-ops handled by the processor. These results in more

efficient scheduling and better performance at lower power. The on-die 32-kB Level 1 instruction

and data caches and the 1-MB Level 2 cache with Advanced Transfer Cache Architecture enable

significant performance improvement over existing mobile processors. The processor also features a

very advanced branch prediction architecture that significantly reduces the number of mispredicted

branches. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before an

L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance.

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in

multimedia applications including 3-D graphics, video decoding /encoding, and speech recognition.

The new packed double-precision floating-point instructions enhance performance for applications

that require greater range and precision, including scientific and engineering applications and

advanced 3-D geometry techniques, such as ray tracing.

The Intel Pentium M processor’s 400-MHz processor system bus utilizes a split-transaction,

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deferred reply protocol. The 400-MHz processor system bus uses Source-Synchronous Transfer

(SST) of address and data to improve performance by transferring data four times per bus clock (4X

data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses

two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working

together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2

Gbytes/second. The processor system bus uses Advanced Gunning Transceiver Logic (AGTL+)

signal technology, a variant of GTL+ signalling technology with low power enhancements.

Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other

Intel products.

The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic

switching between multiple voltage and frequency points instead of two points supported on

previous versions of Intel SpeedStep technology. This results in optimal performance without

compromising low power. The processor features the Auto Halt, Stop-Grant, Deep Sleep, and

Deeper Sleep low power states.

The Intel Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array

(Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package

technology. The Micro-FCPGA package plugs into a 479-hole,surface-mount, Zero Insertion Force

(ZIF) socket, which is referred to as the mPGA479M socket.

This document includes specifications for the Intel Pentium M processor at Highest Frequency

Mode (HFM) core frequencies of 1.30, 1.40, 1.50, 1.60 and 1.70 GHz, the Low Voltage Intel

Pentium M processor at HFM core frequency of 1.10 and 1.20 GHz and the Ultra Low Voltage Intel

Pentium M processor at HFM core frequency of 900MHz and 1.00 GHz.

B. North Bridge – MCH 855PM

Intel® Centrino™ mobile technology with integrated wireless LAN capabilities was designed

specifically for wireless notebook PCs – delivering outstanding mobile performance and enabling

extended battery life and thinner, lighter designs.

The Intel® 855PM Memory Controller Hub (MCH) is an Intel® Centrino™ mobile technology

component. The MCH manages the flow of information between its four interfaces: the processor

side bus (communication with the Intel® Pentium® M processor), memory interface, AGP interface,

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and hub interface. The MCH arbitrates between the four interfaces when each initiates an operation.

The Intel® 855PM memory controller hub (MCH) is designed for use with the Intel® Pentium® M

processor. The MCH supports data coherency via snooping and must perform address translation for

access to AGP Aperture memory. To increase system performance, the MCH incorporates several

queues.

The Intel® 855PM MCH may contain design defects or errors known as errata, which may cause

the product to deviate from published specifications. This information will be available in

Specification Updates.

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Features

Processor/Host Bus Support

Supports the Intel® Pentium® M processor

2x Address, 4x Data

Supports system bus at 400 MT/s

Supports host bus Dynamic Bus Inversion (DBI)

Supports 32-bit host bus addressing

12 deep In-Order Queue

AGTL+ bus driver technology with integrated GTL termination resistors and low voltage

operation (1.05 V)

Support for DPWR# signal to Intel® Pentium® M processor for PSB power

management

Memory System

Directly supports one DDR channel, 64b wide (72b with ECC)

Supports 200-MHz and 266-MHz DDR devices

Supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb technologies for x16 devices and x8 devices.

All supported devices have four banks

Configurable optional ECC operation (single bit Error Correction and multiple bit Error

Detection)

Supports up to 16 simultaneous open pages

Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every

row.

Thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be

triggered by preset read/write bandwidth limits.

For DDR, Max of two, double-sided SODIMMs (four rows populated) with unbuffered

PC1600/PC2100 DDR (with or without ECC)

By using stacked 512-Mb technology, the largest memory capacity possible is 2.0 GB

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System Interrupts

Supports 8259 and processor system bus interrupt delivery mechanism

Supports interrupts signaled as upstream Memory Writes from AGP/PCI (PCI semantics only)

and hub interface

MSI sent to the CPU through the System Bus

From IOxAPIC in ICH4-M

Supports peer MSI between hub interface and AGP

Provides redirection for upstream interrupts to the System Bus

Accelerated Graphics Port (AGP) Interface

Supports a single AGP device (either through a connector or on the motherboard)

AGP Support

Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol

Supports only 1.5-V AGP electricals

32 deep AGP request queue

PCI semantic (FRAME# initiated) accesses to DRAM are snooped

AGP semantic (PIPE# and SBA) accesses to DRAM are not snooped

High priority access support

Hierarchical PCI configuration mechanism

Delayed transaction support for AGP-to- DRAM FRAME# semantic reads that can not be

serviced immediately

32-bit upstream address support for inbound AGP and PCI cycles

32-bit downstream address support for outbound PCI and Fast Write cycles

AGP Busy/Stop Protocol

AGP Clamping and Sense Amp Control

Hub Interface to ICH4-M

266 MB/s point-to-point hub interface to ICH4-M

66-MHz base clock

Supports the following traffic types to the ICH4-M

1 Hub interface-to-AGP memory writes
2 Hub interface-to-DRAM
3 CPU-to-hub interface
4 Messaging

-MSI Interrupt messages

-Power Management state change

-SMI, SCI, and SERR error indication

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Power Management

SMRAM space remapping to A0000h (128 kB)

Supports extended SMRAM space above 256 MB, additional 128k/256k/512k/1 MB TSEG

from Top of Memory, cacheable (cacheability controlled by CPU)

APM Rev 1.2 compliant power management

Suspend to System Memory

ACPI 1.0b, 2.0 Support

Enhanced Intel SpeedStep® Technology Support

Cache coherency with CPU in sleep mode

Dynamic Memory Power-down

Package

Package options

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593-pin Micro-FCBGA (37.5 x 37.5 mm)

C. South Bridge – ICH4-M

The ICH4 provides extensive I/O support. Functions and capabilities include:

PCI Local Bus Specification, Revision 2.2-compliant with support for 33-MHz PCI operations.
PCI slots (supports up to 6 Req/Gnt pairs)
ACPI Power Management Logic Support
Enhanced DMA Controller, Interrupt Controller, and Timer Functions
Integrated IDE controller supports Ultra ATA100/66/33
USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI high-speed

USB 2.0 Host Controller

Integrated LAN Controller
System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C

devices

Supports Audio Codec ’97, Revision 2.3 specification (a.k.a., AC ’97 Component Specification,

Revision 2.3). Link for Audio and Telephony codecs (up to 7 channels)

Low Pin Count (LPC) interface
Firmware Hub (FWH) interface support
Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)

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The ICH4 incorporates a variety of PCI functions that are divided into three logical devices (29, 30,

and 31) on PCI Bus 0 and one device on Bus 1. Device 30 is the Hub Interface-To-PCI bridge.

Device 31 contains all the other PCI functions, except the USB Controllers and the LAN Controller,

as shown in Table 1-2. The LAN controller is located on Bus 1.

PCI Devices and Functions

Feature

PCI Bus Interface

Ø Supports PCI Revision 2.2 Specification at 33 MHz
Ø 133 MB/sec maximum throughput
Ø Supports up to 6 master devices on PCI
Ø One PCI REQ/GNT pair can be given higher arbitration priority (intended for external

1394 host controller)

Ø Support for 44-bit addressing on PCI using DAC protocol

Integrated LAN Controller

Ø WfM 2.0 and IEEE 802.3 compliant
Ø LAN Connect Interface (LCI)
Ø 10/100 Mbit/sec ethernet support

Integrated IDE Controller

Ø Supports “Native Mode” register and interrupts
Ø Independent timing of up to 4 drives, with separate primary and secondary IDE cable

connections

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Ø Ultra ATA/100/66/33, BMIDE and PIO modes
Ø Tri-state modes to enable swap bay

USB

Ø Includes 3 UHCI host controllers that support 6 external ports
Ø New: Includes 1 EHCI high-speed USB 2.0 Host Controller that supports all six ports
Ø New: Supports a USB 2.0 high-speed debug port
Ø Supports wake-up from sleeping states S1-M–S5
Ø Supports legacy keyboard/mouse software

AC'97 Link for Audio and Telephony CODECs

Ø New: Third AC_SDATA_IN line for three codec support
Ø Supports AC ’97 2.3
Ø New: Independent bus master logic for 7 channels (PCM In/Out, Mic 1 input, Mic 2 input,

modem in/out, S/PDIF out)

Ø Separate independent PCI functions for audio and modem

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Ø Support for up to six channels of PCM audio output (full AC3 decode)
Ø Supports wake-up events

Interrupt Controller

Ø Support up to 8 PCI interrupt pins
Ø Supports PCI 2.2 message signaled interrupts
Ø Two cascaded 82C59 with 15 interrupts
Ø Integrated I/O APIC capability with 24 interrupts
Ø Supports serial interrupt protocol
Ø Supports processor system bus interrupt delivery

New: 1.5 V operation with 3.3 V I/O

Ø 5V tolerant buffers on IDE, PCI, USB over-current and legacy signals

Timers Based on 82C54

Ø System timer, refresh request, speaker tone output

Power Management Logic

Ø ACPI 2.0 compliant
Ø ACPI-defined power states (C1–C4, S1-M, S3–S5)
Ø ACPI power management timer
Ø Support for “Intel® SpeedStepTM technology” processor power control
Ø Support for “Deeper Sleep” power state
Ø PCI CLKRUN# and PME# support
Ø SMI# generation
Ø All registers readable/restorable for proper resume from 0 V suspend states

External Glue Integration

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Ø Integrated pull-up, pull-down and series termination resistors on IDE, processor interface
Ø Integrated Pull-down and Series resistors on USB

Enhanced Hub Interface buffers improve routing flexibility (Not available with all Memory

Controller Hubs)

Firmware Hub (FWH) Interface supports BIOS memory size up to 8 MB
Low Pin Count (LPC) Interface

Ø Supports two Master/DMA devices.

Enhanced DMA Controller

Ø Two cascaded 8237 DMA controllers
Ø PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs
Ø Supports LPC DMA
Ø Supports DMA collection buffer to provide Type-F DMA performance for all DMA

channels

Real-Time Clock

Ø 256-byte battery-backed CMOS RAM

System TCO Reduction Circuits

Ø Timers to generate SMI# and Reset upon detection of system hang
Ø Timers to detect improper processor reset
Ø Supports ability to disable external devices

SMBus

Ø New: Hardware packet error checking
Ø New: Supports SMBus 2.0 Specification
Ø Host interface allows processor to communicate via SMBus
Ø Slave interface allows an external microcontroller to access system resources
Ø Compatible with most 2-wire components that are also I2C compatible

GPIO

Ø TTL, open-drain, inversion

Package 31x31 mm 421 BGA

D. Clock Generator

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The ICS950813 is a single chip clock solution for desktop designs using the

Brookdale/Odem/Montara-GM for P4/Banias processor.

The ICS950813 is part of a whole new line of ICS clock generators and buffers called TCHTM

( Timing Control Hub ). This part incorporates ICS’s newest clock technology with offers more

robust features and functionality. Employing the use of a serially programmable I2C interface, this

device can adjust the output clocks by configuring the frequency setting, the output divider rations,

selecting the ideal spread percentage, the output skew, the output strength, the enabling / disabling

each individual output clock. M/N control can configure output frequency with resolution up to 0.1

MHz increment.

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Output Features

3 Differential CPU Clock Pairs @ 3.3V

7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks

3 PCI_F (3.3V) @ 33.3MHz

1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz

1 REF (3.3V) @ 14.318MHz

5 3V66 (3.3V) @ 66.6MHz

1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

Features / Benefits

Provides standard frequencies and additional 3%, 5% and 10% over-clocked frequencies

Supports spread spectrum modulation: No spread, Center Spread (±0.3%, ±0.55%), or Down Spread

(-0.5%, -0.75%)

Offers adjustable PCI early clock via latch inputs

Selectable 1X or 2X strength for REF via I2C interface

Programmable group to group skew

Linear programmable frequency and spreading %

Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#.

Uses external 14.318MHz crystal

Stop clocks and functional control available through I2C interface.

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Key Specifications

n CPU Output Jitter <150ps
n 3V66 Output Jitter <250ps
n CPU Output Skew <100ps

E. Video Graphics – ATi M11P

The MOBILITY M11 provides one of the fastest and most advanced 2D, 3D, and multimedia

graphics performance for notebooks. Its architecture introduces the latest achievements in the

graphics industry, which enable the use of the progressive new features in upcoming applications,

but without compromising performance. ATI’s support of DirectX® 9 features, highly optimized

OpenGL® support, and flexible memory configurations allow implementations targeted at the

gaming enthusiast, consumer, business and workstation platforms.

SMARTSHADER™ 2.0 — Advanced Shader Technology

Ø Provides complete hardware-accelerated support for the new DirectX® 9 programmable

shader model, enabling more complex and realistic texture and lighting effects than ever

before.

Ø Significant improvement over first-generation shaders introduced in DirectX® 8, with a

much more powerful and intuitive instruction set.

Ø Offers full support for this feature in OpenGL® applications.

SMOOTHVISION™ 2.0 — Flexible Anti-Aliasing and Anisotropic Filtering

Ø 2x/4x/6x full-scene anti-aliasing modes
Ø Adaptive algorithm with programmable sample patterns
Ø 2x/4x/8x/16x anisotropic filtering modes
Ø Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options

High Performance Memory Support

Ø Incorporates support for DDR SDRAM/SGRAM.
Ø Features key items from ATI’s third generation HYPER Z™ III technology that conserves

memory bandwidth for improved performance in demanding applications.

Dual Display Support

Ø Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports

multiple combinations of notebook LCD, traditional CRT monitors, flat panel displays and

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TV.

Ø Features Dual Channel DVI support.
Ø 230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution.
Ø Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA

(1600x1200) resolution.

Ø High performance DAC speeds of 400MHz.

VIDEO Acceleration

Ø M11 allows the integration of industry leading digital video features, including advanced

de-interlacing algorithms for unprecedented video quality and integrated digital TV

decode capability. Includes programmable, independent gamma control for the video

overlay.

Ø New FULLSTREAM™ technology removes blocky artifacts from streaming and Internet

video and provides sharper image quality.

Ø Integrated general purpose xDCT engine (capable of performing both forward and inverse

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discrete cosine transform) and motion compensation (MC) support for the acceleration of

MPEG encoding and decoding as well as DV (digital video) encoding and decoding.

Features In Detail

2D Acceleration Features

Ø A highly optimized 128-bit engine, capable of processing multiple pixels/clock.
Ø Hardware acceleration is provided for Bitblt, line drawing, polygon and rectangle fills, bit

masking, monochrome expansion, panning and scrolling, scissoring, and full ROP support

(including ROP3).

Ø Optimized handling of fonts and text using ATI proprietary techniques.
Ø Game acceleration including support for Microsoft's DirectDraw: Double Buffering,

Virtual Sprites, Transparent Blit, and Masked Blit.

Ø Acceleration in 8/15/16/32 bpp modes.
Ø Support for WIN 2000 & WIN XP GDI extensions: Alpha BLT, Transparent BLT,

Gradient Fill.

Ø Hardware cursor support up to 64x64x32bpp, with alpha channel for direct support of

WIN 2000 & WIN XP alpha cursor standard.

3D Acceleration Features

Ø Four parallel 3D rendering pipelines.
Ø Full DirectX9 Pixel Shader 2.0 support.
Ø Full DX9 conformance, including floating point per component at full speed.
Ø Support for 2xAA, 4xAA and 6xAA subsamples, with little performance loss in most

cases.

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Ø Advanced AA quality algorithms, generating visuals that are superior to other solutions

with an equivalent number of samples.

Ø 2x/4x/8x/16x anisotropic filtering modes. Adaptive algorithm with bi-linear (performance)

and tri-linear (quality) options.

Ø Up to 16 unique textures, sharing 8 texture addresses.
Ø Dedicated geometry acceleration for Direct3D and OpenGL, which incorporates 2 parallel

Vector / Scalar Engines performing HW transformation, clipping and lighting, including:

Texture Coordinate Generation.

Vertex Blending (skinning) with 4 matrices.

6 user defined clip planes.

8 light support.

Directional and Local Lighting.

Ø Fully compliant DirectX 9, Shader Model 2.0, Programmable Vertex Shader (full operand

and operation support) with up to 256 instructions and 256 vectors of constant store. This

includes Vertex Shader Loops, Branches, and Subroutines, which allow for vertex shader

programs of around 64,000 instructions in length.

Motion Video Acceleration Features

Ø Video scaling and fully programmable YCrCb to RGB color space conversion for

full-screen / full-speed video playback and fully adjustable color controls.

Ø Hardware I2C.
Ø VIP 2.0 with multi channel DMA transfer.
Ø 16-bit Zoom Video port.
Ø Front end scaler support for 8, 15, 16, and 32 bpp color depths.
Ø Back end overlay/scaler supports up to 8x4 tap filtering, and always ensures at least 4x2

tap filtering even in extreme cases. 4x4 tap is typical. Back-end scaler also supports

upscaling and downscaling, filtered scaling of all supported YUV formats, RGB32 and

RGB15/16, and filtered display of images up to 1536 pixels wide.

Ø Enhanced MPEG-2 hardware encode/decode acceleration, including support for:

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Integrated general purpose xDCT engine (capable of performing

both forward and inverse discrete cosine transform)

Motion compensation (MC) support for the acceleration of MPEG

encoding and decoding as well as DV (digital video) encoding and

decoding.

Parallel operation of the xDCT and MC and high processing rates

with minimal software overhead

Ø Provides dramatically reduced CPU utilization without incurring the cost of a full

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MPEG-2 decoder.

Ø MPEG-4 simple profile support.

Ø Supports all format DTV/HDTV decode and top quality DVD with lowest CPU usage.

(Note: DTV/HDTV support is through component output, not DVI.)

Ø Adaptive de-interlacing filter eliminates video artifacts caused by displaying interlaced

video on non-interlaced displays, by analyzing image and using optimal de-interlacing

function on a per-pixel basis.

Dual Display Features

General

Ø Hydravision for dual monitor support.
Ø Dual independent displays (LCD/DVI, DVI/CRT, LCD/TV, CRT/TV, etc.)
Ø Two independent CRT controllers to support two asynchronous simultaneous display

paths.

Ø Integrated second DAC for the second CRT (TV) support.
Ø Two triple 10-bit palette DACs with gamma correction for true WYSIWYG color. Pixel

rates up to 400MHz standard.

Ø Resolution, refresh rates and display data can be completely independent.
Ø Primary display path supports VGA and accelerated modes, video overlay, hardware

cursor, and palette gamma correction.

Ø Secondary display path supports accelerated modes, video overlay, hardware cursor, and

palette gamma correction. However, it does not support VGA.

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Ø Single video overlay using back-end scaler is switchable between displays.
Ø Supports two new graphics formats: 16bpp aRGB 4444 and 16bpp alpha and index 88.

Also supports 8/15/16/24/32 bpp graphics formats with gamma correction in all modes.

Ø Support for auxiliary window signal.
Ø Support for up to 4k x 4k resolution display.
Ø Support for DDC1 and DDC2B+ for plug and play monitors, and AppleSense monitor

detection support.

Ø 8-bit alpha blending of graphics and video overlay.
Ø Independent DDC lines for DAC and TMDS connections. Also full AppleSense support

on DAC connection.

Ø Hardware cursor up to 64x64 pixels in 2bpp, full color AND/XOR mix, and full color 8-bit

alpha blend.

Ø Independent h/w icon & h/w cursor on both display paths (simultaneous h/w cursor &

icon).

Ø Virtual desktop support.

TV Out

An integrated TV encoder with on-chip triple DAC allows simultaneous CRT/LCD/TV

output with these outstanding TV-out characteristics:

Ø 10-bit DAC with 8-tap filter producing scaled, flicker removed, artifact suppressed

display on a PAL or NTSC TV with Composite, S-Video, and RGB outputs.

Ø Support for Macrovision 7.02 copy protection standard (required by DVD players) - a

fully programmable timing capability, it will accommodate potential changes in the

Macrovision algorithm without any hardware changes.

Ø YUV Direct/Pass through mode for video/MPEG playback and DVD provides the best

quality movie playback, it also allows titles to be displayed on TV with their original high

quality and without any artifact from the TV-out circuit.

Ø Secondary display support for the RGB mode.
Ø 1024x768 32bpp support. Modes supported include 800x600 and 16:9 modes such as

848x480, with user flexibility for moving and sizing the screen.

Ø Line 21 Closed Caption and Extended Data Service support for encoding in Vertical

Blanking Interval (VBI) of TV signal.

Ø CGMS-A DVD copy management support in VBI through Line-20 and/or Extended Data

Service (Line-21 Field 2).

Ø UV filtering based on color averaging results in a sharper picture as well as reduced

flicker.

Ø ATI's exclusive "Composite Dot Crawl" freeze option for PAL and NTSC to improve

picture quality.

Component output

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Ø Component output (YPbPr) for 480i, 480p, 720p and 1080i (NTSC only).
Ø No support for scaling or flicker removal to component video outputs.
Ø Includes NTSC Macrovision and CGMS.

Digital Display Support

General

Ø Support for fixed resolution displays (e.g. panels) from VGA (640x480) to wide UXGA

(1600x1200) resolution with full ratiometric expansion ability for source modes up to

1280x1024. Higher resolution panels and digital CRTs may be possibly supported -

contact ATI for details.

Ø Improved auto expansion.
Ø Optional auto-centering mode to display desktop at native size without ratiometric

expansion.

Ø Support for VGA text modes in centering panel modes (up to approximately 165 MHz

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pixel frequency).

Ø Support for reduced blanking intervals, as defined by VESA.
Ø HDCP ready.

LVDS

An integrated LVDS transmitter for excellent LCD image quality:

Ø Single and dual pixel per clock, up to 230MHz dual-channel (115MHz per channel)
Ø Supports LCD panels up to QXGA (2048x1536) 60Hz resolution.
Ø General purpose I/O pins that allows support of LCD panel detection.
Ø Conformance with OpenLDI and VESA FPDI specifications.
Ø Common Panel Interface Specification (CPIS) compliant.
Ø Ratiometric expansion with improved sharpness for top image quality when scaling up

from a non-native resolution.

TMDS

Ø Integrated TMDS transmitter running up to 165MHz (supports both coherent and

non-coherent clocking systems) for support up to 1600x1200 at 60Hz. Fully Compliant

with DVI and DFP connection standards. Ratiometric expansion.

Ø Support for external TMDS transmitter via digital output (configurable as a 12 bit or 24 bit

DDR bus) to drive most popular TMDS transmitters up to 165MHz frequency.

Ø Supports DVI, DFP and VESA P&D interfaces with integrated TMDS transmitter.
Ø TMDS transmitter fully supports reduced blanking.

Bus Support Features

Ø Comprehensive AGP support:

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AGP3.0 mode: 4X and 8X operation.

AGP2.0 mode (1.5V signaling only)

Sideband Addressing.

AGP Texturing (Execute mode).

Both AGP reads and writes (with support for the ‘fast write’

capability defined in revision 2.0 of the AGP specification).

Ø PCI 2.3 compliance (using AGP electrical interface).

Memory Support Features

Ø 128/64-bit memory interface using DDR SGRAM, SDRAM or DDRII SDRAM to build

16/32/64/128/256 MB configurations.

Ø Support for SSTL-2, and SSTL-1.8 (1.8V self-terminated) memory interfaces.
Ø Supports Elpida DDR SDRAM, which is similar to the DDR protocol with the following

exceptions:

Lower power through the use of data inversion signals for both

writes and reads

Higher clock speeds with no external termination required

Power Management Features

Ø Single chip solution in 0.13 micron, 1.0V-1.2V CMOS technology
Ø Full ACPI 1.0b, OnNow, and IAPC (Instantly Available PC) power management.
Ø PCI bus power management 1.1 and AGP Busy and Stop signals Rev 1.61 and Solano

2-M.

Ø Static and dynamic Power Management support (APM as well as ACPI) with full VESA

DPM and Energy Star compliance.

Ø AGP_BUSY/STP_AGP power management.
Ø Full POWERPLAYTM, including enhanced POWER ON DEMAND support.
Ø The Chip Power Management Support logic supports four device power states - On,

Standby, Suspend and Off - defined for the OnNow Architecture. Each power state can be

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achieved by software control bits.

Ø Clocks to every major functional block are controlled by a unique dynamic clock

switching technique which is completely transparent to the software. By turning off the

clock to the block that is idle or not used at that point, the power consumption is

significantly reduced during normal operation.

Internal LVDS Spread Spectrum Support

Ø The MOBILITY M11 Spread Spectrum controller is capable of generating a triangular

frequency modulation profile. The amount of spread and the modulation frequency is fully

programmable.

Ø Only the LVDS display is available to be spread (i.e., 1 PLL).

External Spread Spectrum Support

Ø Memory and/or core clock spread spectrum support via the GPIO16 pin.
Ø External spread spectrum supported for TMDS or LVDS transmitters via the

SSIN/SSOUT pin.

PC Design Guide Compliance

MOBILITY M11 complies with all relevant sections of the current PC design guide specifications

from Intel/Microsoft.

Ø Fully compliant with PC99, PC99a, and PC 2001 requirements.
Ø Fully compliant with Mobile PCI rev 1.0.
Ø Bi-endian support for compliance on a variety of processor platforms.

Test Capability Features

The MOBILITY M11 has a variety of test modes and capabilities that provide a very high fault

coverage and low DPM (defect per million) ratio:

Ø Full scan implementation on the digital core logic which provides high fault coverage

through ATPG (Automatic Test Pattern Generation Vectors).

Ø Dedicated test logic for the on-chip custom memory macros to provide complete coverage

on these modules.

Ø A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) for access

to chip-level test functions and for board level connectivity testing.

Ø Integrated hardware diagnostic tests performed automatically upon initialization.

Ø High quality components through at-speed testing, built-in Scan, Iddq, CRC, chip

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diagnostics, and XOR tree.

Ø IEEE 1149.1 Scan path interface.
Ø An XORTREE test mode on all the digital I/O's to allow for proper soldering verification

at the board level.

Ø Improved access to the analog modules and PLLs in the MOBILITY M11 in order to allow

full evaluation and characterization of these modules.

Ø Improved IDDQ mode support to allow chip evaluation through current leakage

measurements.

Other Features

Ø Support for ROM or Flash RAM parallel or serial video BIOS.
Ø Includes patent pending hardware support for the Windows 2000 and Windows XP alpha

cursor, as well as acceleration of new GDI extensions such as Alpha BLTs, Transparent

BLTs, and Gradient Fills.

Compliance with Wassenaar Agreement

Ø 3D vector rate (as defined by the Wassenaar Agreement) is 18 - 23 M 10-pixel

vectors/sec for all of M11-CSP64, M11-CSP128.

F. PCMCIA

OZ711MC1

Feature

Ø Single-Slot CardBus Controller
Ø Integrated Smart Card Reader (SCR) Controllers
Ø Integrated Flash Media Reader (FMR) Controllers
Ø One Optional Dedicated Reader (ODR) Port

PC Card/PCI Features

Ø Pin Compatible with OZ6912, OZ711EC1, and

OZ711M1 Single Socket Controllers

Ø Pin Upgradeable to OZ711MP1, Adding 1394
Ø PC Card Standard Release 8.1 Compliant
Ø Supports USB PC Cards with NewSwitch™ Device

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Ø Compliant with PCI Local Bus Specification Version 2.3
Ø Provides Pipelined PCI/CardBus burst data transfers
Ø Supports Parallel and Serial Interfaces to O2Micro’s

OZ2211, OZ2216, and NewSwitch™ Power Switches

Smart Card Features

Ø Supports Patented SmartCardBus® Operating Mode
Ø Provides Optional Dedicated Smart Card Reader
Ø Supports SmartCardBus® PC Card Passive Adapters
Ø EMV Certified Smart Card Reader Core
Ø Supports Asynchronous and Synchronous Cards
Ø ODR Interface Supports USB Smart Cards
Ø Complies to ISO7816, PC/SC, EMV, and CT-API (B1)

Flash Media Features

Ø Host Controller Supports MultiMediaCard (MMC), and SD Memory Cards

TECHNICAL SERVICE MANUALPrestigio Nobile 159W

Ø MS/MSPro Host Controller Supports 1-bit Memory Stick™ and 4-bit Memory Stick™ PRO

Media Cards

Ø PC Card Socket Supports MMC/SD/MS/MSPro Using O2Micro’s MemoryCardBus™ Passive

Adapters

Ø MultiMediaCard (MMC) Version 2.2 Compliant
Ø Supports SD Memory Card CPRM Security Mode

Power Management Features

Ø Auxiliary Power Supply (VAUX) For D3COLD Standby
Ø ACPI-PCI Bus Power Management Rev 1.1 Compliant
Ø Supports OnNow LAN Wake-up, Ring Indicate,

CardBus Wake Signaling via PME#, and CLKRUN#

OZ2216

The OZ2216 is a dual slot PCMCIA (Personal Computer Memory Card International Association)

PC Card and CardBus power controller. It is used in conjunction with a serial data output, CardBus

controller to control and distribute VCC and VPP voltages to two PC Card slots. When connected to

3.3V, 5V, and 12V system power supplies, the OZ2216 can switch its VCC and VPP outputs between

0V, 3.3V, and 5.0V, in accordance with the control commands from the three-wire serial interface.

The OZ2216 also features low on-resistance MOSFET switches for 5V and 3.3V VCC.

The OZ2216 operation does not require 12V and 5V supplies, making it possible to operate the PC

cards in lowpower 3.3V modes. The internal logic and the MOSFET

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drive circuitry are powered by the 3V supply input. The OZ2216 also features a standby mode that

changes all the output-current limits to 50mA (typical).

The OZ2216 is protected by over temperature shutdown, and it protects itself and the system with

current limiting and cross-conduction lockout.

The OZ2216 is designed for full compatibility with the PCMCIA PC Card Specification,

including the CardBus and Zoomed Video (ZV) options, and is pin-to-pin compatible with

O2Micro’s OZ2206 and Texas Instrument’s

TPS2206/2216.

Feature

Ø Complete VCC and VPP switch for dual-slot PC Card interface
Ø Standard 3-wire serial interface compatible with CardBus Controllers
Ø High-efficiency, low-resistance switches
Ø Meets PC Card standard
Ø Compatible with 3.3V, 5V and 12V PC Cards
Ø Operates in 3.3V low voltage mode when 3.3V is the only available input voltage
Ø Standby Mode: 50-mA Current Limit (Typical)
Ø Current limit and over temperature shutdown
Ø 12V supply can be disabled except during 12V Flash memory programming
Ø Break-before-make switching
Ø Low on-resistance for 5V VCC
Ø Low on-resistance for 3.3V VCC

G. IEEE 1394 – TSB43AB22A

The Texas Instruments TSB43AB22A device is an integrated 1394a-2000 OHCI PHY/link-layer

controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus

Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the

1394 Open Host Controller Interface

Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at

100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB22A device provides two 1394 ports that

have separate cable bias (TPBIAS). The TSB43AB22A device also supports the IEEE Std

1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

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As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std

1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI

configuration header is accessed through configuration cycles specified by PCI, and it provides

plug-and-play (PnP) compatibility. Furthermore, the TSB43AB22A device is compliant with the

PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide

requirements. The TSB43AB22A device supports the D0, D1, D2, and D3 power states.

The TSB43AB22A design provides PCI bus master bursting, and it is capable of transferring a

cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency

can be large, deep FIFOs are provided to buffer the 1394 data. The TSB43AB22A device provides

physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The

TSB43AB22A device also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers.

An advanced CMOS process achieves low power consumption and allows the TSB43AB22A

device to operate at PCI clock rates up to 33 MHz.

The TSB43AB22A PHY-layer provides the digital and analog transceiver functions needed to

implement a two-port node in a cable-based 1394 network. Each cable port incorporates two

differential line transceivers. The transceivers include circuitry to monitor the line conditions as

needed for determining connection status, for initialization and arbitration, and for packet reception

and transmission.

The TSB43AB22A PHY-layer requires only an external 24.576-MHz crystal as a reference for

the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives

an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal.

This reference signal is internally divided to provide the clock signals that control transmission of

the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the

integrated LLC for synchronization and is used for resynchronization of the received data.

Data bits to be transmitted through the cable ports are received from the integrated LLC and are

latched internally in synchronization with the 49.152-MHz system clock. These bits are combined

serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100,

S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During

transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB)

cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A

(TPA) cable pair(s).

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During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled,

and the receivers for that port are enabled. The encoded data information is received on the TPA

cable pair, and the encoded strobe information is received on the TPB cable pair. The received

data-strobe information is decoded to recover the receive clock signal and the serial data bits. The

serial data bits are resynchronized to the local 49.152-MHz system clock and sent to the integrated

LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line

states during initialization and arbitration. The outputs of these comparators are used by the internal

logic to determine the arbitration status. The TPA channel monitors the incoming cable

common-mode voltage. The value of this

common-mode voltage is used during arbitration to set the speed of the next packet transmission. In

addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for

the presence of the remotely supplied twisted-pair bias voltage.

The TSB43AB22A device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port

termination. The PHY layer contains two independent TPBIAS circuits. This bias voltage, when

seen through a cable by a remote receiver, indicates the presence of an active connection. This bias

voltage source must be stabilized by an external filter capacitor of 1.0 μF.

The line drivers in the TSB43AB22A device operate in a high-impedance current mode and are

designed to work with external 112-Ω line-termination resistor networks in order to match the 110-Ω

cable impedance. One network is provided at each end of a twisted-pair cable. Each network is

composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is

directly connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal.

The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to

ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of

the external line-termination resistors are designed to meet the standard specifications when

connected in parallel with the internal receiver circuits. An external resistor connected between the

R0 and R1 terminals sets the driver output current and other internal operating currents. This

current-setting resistor has a value of 6.34 kΩ ±1%.

When the power supply of the TSB43AB22A device is off and the twisted-pair cables are

connected, the TSB43AB22A transmitter and receiver circuitry present a high impedance to the

cable and do not load the TPBIAS voltage at the other end of the cable.

When the device is in a low-power state (for example, D2 or D3) the TSB43AB22A device

automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or

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suspended). In this low-power mode, the TSB43AB22A device disables its internal clock generators

and also disables various voltage and current reference circuits, depending on the state of the ports

(some reference circuitry must remain active in order to detect new cable connections,

disconnections, or incoming TPBIAS, for example). The lowest power consumption (the

ultralow-power sleep mode) is attained when all ports are either disconnected or disabled with the

port interrupt enable bit cleared.

The TSB43AB22A device exits the low-power mode when bit 19 (LPS) in the host controller

control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to

1 or when a port event occurs which requires that the TSB43AB22A device to become active in

order to respond to the event or to notify the LLC of the event (for example, incoming bias is

detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is

detected on a nondisabled port). When the TSB43AB22A device is in the low-power mode, the

internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within

2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section

4.16, Host Controller Control Register) is set to 1.

The TSB43AB22A device supports hardware enhancements to better support digital video (DV)

and MPEG data stream reception and transmission. These enhancements are enabled through the

isochronous receive digital video

enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The

enhancements include automatic timestamp insertion for transmitted DV and MPEG-formatted

streams and common isochronous packet (CIP) header stripping for received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the

isochronous data contexts are implemented as hardware support for the synchronization timestamp

for both DV and MPEG CIP formats. The TSB43AB22A device supports modification of the

synchronization timestamp field to ensure that the value inserted via software is not stale—that is,

the value is less than the current cycle timer when the packet is transmitted.

1.1.1.Features

Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus† and

IEEE Std 1394a-2000

Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394

Compliant with Intel Mobile Power Guideline 2000

Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,

multispeed concatenation, arbitration acceleration, fly-by concatenation, and port

disable/suspend/resume

Power-down features to conserve energy in battery-powered applications include: automatic device

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power down during suspend, PCI power management for link-layer, and inactive ports powered

down

Ultralow-power sleep mode

Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s

Cable ports monitor line conditions for active connection to remote node

Cable power presence monitoring

Separate cable bias (TPBIAS) for each port

1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling

environments

Physical write posting of up to three outstanding transactions

PCI burst transfers and deep FIFOs to tolerate large host latency

PCI_CLKRUN# protocol

External cycle timer control for customized synchronization

Extended resume signaling for compatibility with legacy DV components

PHY-Link logic performs system initialization and arbitration functions

PHY-Link encode and decode functions included for data-strobe bit level encoding

PHY-Link incoming data resynchronized to local clock

Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and

400M bits/s

Node power class information signaling for system power management

Serial ROM interface supports 2-wire serial EEPROM devices

Two general-purpose I/Os

Register bits give software control of contender bit, power class bits, link active control bit, and

IEEE Std 1394a-2000 features

Fabricated in advanced low-power CMOS process

PCI and CardBus register support

Isochronous receive dual-buffer mode

Out-of-order pipelining for asynchronous transmit requests

Register access fail interrupt when the PHY SCLK is not active

H. LAN – Ethernet Controller – RTL8100C

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The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller

that provides 32-bit performance,

PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and

IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power

management Interface (ACPI), PCI power management for modern operating systems that are

capable of Operating System Directed Power Management (OSPM) to achieve the most efficient

power

management possible. The RTL8100C(L) does not support CardBus mode as the RTL8139C does.

In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up (including AMD

Magic Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments.

The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary

power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready

and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin

provides 4 different output signals including active high, active low, positive pulse, and negative

pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with

Wake-On-LAN (WOL) functionality.

The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the

RTL8100C(L) can be shut down temporarily according to user requirements or when the

RTL8100C(L) is in a power down state with the wakeup function disabled.

In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off),

then both the analog and digital parts stop functioning and the power consumption of the

RTL8100C(L) will be negligible. The RTL8100C(L) also

supports an auxiliary power auto-detect function, and will auto-configure related bits of their own

PCI power management registers in PCI configuration space.

The PCI Vital Product Data(VPD) is also supported to provide the information that uniquely

identifies hardware (i.e., the OEM brand name of RTL8100C(L) LAN card). The information may

consist of part number, serial number, and other detailed

information.

To provide cost down support, the RTL8100C(L) is capable of using a 25MHz crystal or OSC as

its internal clock source.

The RTL8100C(L) keeps network maintenance costs low and eliminates usage barriers. It is the

easiest way to upgrade a network

from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at

no additional cost. To improve compatibility with other brands. products, the RTL8100C(L) is also

capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The RTL8100C(L) is

highly integrated and requires no .glue. logic or external memory.

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1.1.2.Feature

Ø 128 pin QFP/LQFP
Ø Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip
Ø 10 Mb/s and 100 Mb/s operation
Ø Supports 10 Mb/s and 100 Mb/s N-way

Auto-negotiation operation

Ø PCI local bus single-chip Fast Ethernet controller
Ø Compliant to PCI Revision 2.2
Ø Supports PCI clock 16.75MHz-40MHz
Ø Supports PCI target fast back-to-back transaction
Ø Provides PCI bus master data transfers and PCI memory space or I/O space mapped data

transfers of RTL8100C(L)’s operational registers

Ø Supports PCI VPD (Vital Product Data)
Ø Supports ACPI, PCI power management
Ø Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation

of either crystal or OSC must be within 50 PPM.

Ø Compliant to PC99/PC2001 standard
Ø Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and

Microsoft® wake-up frame)

Ø Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative

pulse)

Ø Supports auxiliary power-on internal reset, to be readyfor remote wake-up when main power

still remains off

Ø Supports auxiliary power auto-detect, and sets the related capability of power management

registers in PCI configuration space.

Ø Includes a programmable, PCI burst size and early Tx/Rx threshold.
Ø Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate

timer-interrupt

Ø Contains two large (2Kbyte) independent receive and transmit FIFOs
Ø Advanced power saving mode when LAN function or wakeup function is not used
Ø Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD

data.

Ø Supports LED pins for various network activity indications
Ø Supports loop back capability
Ø Half/Full duplex capability
Ø Supports Full Duplex Flow Control (IEEE 802.3x)
Ø 2.5/3.3V power supply with 5V tolerant I/Os.

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Ø 0.25u CMOS process

I. Audio

AC97 Controller – VIA: VT1612A

VIA Technologies’ VT1612ATM 18-bit ∑∆ audio codec conforms to the AC’97 2.2 and the S/PDIF

specification. The VT1612A integrates Sample Rate Converters and can be adjusted in 1Hz

increments. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D

surround sound effect for stereo media.

Furthermore, an integrated headphone amplifier with thermal shutdown adds signal value by

reducing the BOM. This codec is designed with aggressive power management to achieve low

power consumption. When used with 3.3V analog

supply, power consumption is further reduced. The primary applications for this part are desktop and

portable personal computers multimedia subsystems. However, it is suitable for any audio

subsystem requiring stereo audio input/output with S/PDIF digital output at competitive prices.

Feature

Ø AC’97 2.2 S/PDIF extension compliant codec
Ø 18-bit stereo full duplex SD codec
Ø 1Hz resolution VSR (Variable Sampling Rate)
Ø Integrated IEC958 line driver for S/PDIF
Ø S/PDIF compressed digital or LPCM audio out
Ø 3D stereo expansion for simulated surround
Ø 18-bit independent rate stereo ADC/DAC
Ø Hardware VU peak meters for PCM streams
Ø 4 stereo, 2 mono analog line-level inputs
Ø Alt. line-level output with volume control, or
Ø Headphone Amplifier with Thermal Protection
Ø Low Power consumption mode
Ø Exceeds Microsoft® WHQL logo requirements
Ø 3.3V digital, 3.3 or 5V analog power supply

Ø 48-pin LQFP small footprint package.

Amplifier – TI : TPA6011A

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