Prestigio NOBILE 1510 Technical & Service Manual

PRESTIGIO NOBILE 1510

TECHNICAL SERVICE MANUAL

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

Contents

1. Hardware Engineering Specification……………………………………………………………………….

1.1 Introduction ………………………………………………………………………………………………………………..

1.2 System Overview …………………………………………………………………………………………………………..

1.3 System Hardware Parts …………………………………………………………………………………………………...

1.4 Other Functions ……………………………………………………………………………………………………………

1.5 Power Management ………………………………………………………………………………………………………..

1.6 Appendix 1: Intel ICH6-M GPIO Definitions ……………………………………………………………………………

1.7 Appendix 2: W83L950D KBC Pin Definitions …………………………………………………………………………..

1.8 Appendix 3: Nobile 1510 Product Specifications ……………………………………………………………………………

2. System View and Disassembly ……………………………………………………………………………...

2.1 System View ………………………………………………………………………………………………………………..

2.2 System Disassembly ………………………………………………………………………………………………………..

3. Definition & Location of Connectors / Switches …………………………………………………………..

3.1 Mother Board (Side A) ……………………………………………………………………………………………………

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3.2 Mother Board (Side B) ……………………………………………………………………………………………………

3.3 Daughter Board…………………………………………………………………………………………………………….

4. Definition & Location of Major Components ……………………………………………………………..

4.1 Mother Board (Side A) ……………………………………………………………………………………………………

4.2 Mother Board (Side B) ……………………………………………………………………………………………………

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

Contents

5. Pin Description of Major Component …….……………………………………………………………….

5.1 Intel 915GM North Bridge ……………………………………………………………………………………………….

5.2 Intel ICH6-M South Bridge ………………………………………………………………………………………………

6. System Block Diagram ………………………………………………………………………………………

7. Maintenance Diagnostics ……………………………………………………………………………………

7.1 Introduction ………………………………………………………………………………………………………………..

7.2 Maintenance Diagnostics…………………………………………………………………………………………………..

7.3 Error Codes ………………………………………………………………………………………………………………..

8. Trouble Shooting …………………………………………………………………………………………….

8.1 No Power ……………………………………………………………………………………………………………………

8.2 No Display ………………………………………………………………………………………………………………….

8.3 VGA Controller Failure LCD No Display ………………………………………………………………………………..

8.4 External Monitor No Display ……………………………………………………………………………………………..

8.5 Memory Test Error ………………………………………………………………………………………………………..

8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………………

8.7 Hard Driver Test Error ……………………………………………………………………………………………………

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8.8 CD-ROM Driver Test Error ………………………………………………………………………………………………

8.9 USB Port Test Error ……………………………………………………………………………………………………….

8.10 Audio Failure ……………………………………………………………………………………………………………..

8.11 LAN Test Error …………………………………………………………………………………………………………..

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8.12 PC Card Socket Failure …………………………………………………………………………………………………

9. Spare Parts List ……………………………………………………………………………… ……………...

10. System Exploded Views …………………………………………………………………………………….

11. Circuit Diagram …………………………………………………………………………………………….

12. Reference Material …………………………………………………………………………………………

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1. Hardware Engineering Specification

1.1 Introduction

The Prestigio Nobile 1510 model is designed for Intel Mobile Pentium-M Processor and Celeron-M Processor,Dothan
400 and 533 FSB.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface.
It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up
by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such
as Wireless LAN indicator, AC/Battery Power indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK,
CAP LOCK, SCROLL LOCK. It also equipped with GIGA LAN, 56K Fax MODEM, 3 USB port, S-Video, line in,
SPIDIF, and internal/external microphone function.

The memory subsystem supports DDR2 SDRAM channels (64-bits wide).

The 915GM MCH Host Memory Controller integrates a high performance host interface for Intel Dothan processor,
a high performance PCI Express interface, a high performance memory controller, Digital Video port (DVOB &
DVOC) interface, and Direct Media Interface (DMI) connecting with Intel ICH6-M.

The Intel ICH6-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with Azalia interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, the
SATA controller and Direct Media Interface technology.

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Intel Graphics enhancements includes DVMT 3.0, Zone Rendering 2.0, Quad pixel pipe rendering engine, Pixel
Shader 2.0 and 4x Faster Setup Engine.

The Realtek RTL8110SBL is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and
IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface
(ACPI).

The Texas Instruments PCI4510 device is compliant with PC I Local Bus Specification. Function 0 provides the
independent PC Card socket controller compliant with the latest PC Card Standards. Function 1 of the PCI4510
device is an integrated IEEE 1394a-2000 open host controller interface (OHCI)PHY/link-layer controller (LLC)
device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface
Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface
Specification.

The ALC655 is a 16-bit, full duplex AC97 2.3 compatible six channels audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter
technology to meet performance requirements on PC99/2001 systems.

The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded
control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus
interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high performance systems can be implemented easily.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Overview

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

CPU

Core logic
System BIOS
Memory

HDD
ODD

Display

Clock Generator
TV
LAN
PCMCIA +
IEEE1394
Audio System

Intel: Pentium M 735 Dothan 1.7GHz, 400FSB
Intel: Pentium M 770 Dothan 2.13GHz, 533FSB

Thermal spec 27W TDP
Intel 915GM + ICH6-M chipset
W39V040FAP
DDR2 RAM: MT8HTF3264HDY-53EB3 (256Mx2)
Nanya 533,256MB,NT256T64UH4A0FM-37B
Fujitsu:MHT2060AT+ , 60GB
KME: UJ-831BMT-A DVD Dual
KME: UJDA760 DVD Combo
15”: Hydis,HT15X34-110
AU: B150XG01
ICS 954226
Intel 915GM
RTL8110SBL
TI PCI4510

AC’97 CODEC: ALC655
Power Amplifier: TI TPA0212

Modem

Askey 1456VQL4A(INT)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.3 System Hardware Parts

1.3.1 Intel Dothan Processors in Micro-FCBGA package

Intel Dothan Processors with 479 pins Micro-FCBGA package.

It will be manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect. It’s features
include Intel Architecture with Dynamic Execution, On-die primary 32-kB instruction cache and 32-kB write-back
data cache, on-die 2-MB second level cache with advanced Transfer Cache Architecture, Data Prefetch Logic,
Streaming SIMD Extensions 2 (SSE2), 533-MHz FSB.

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock.

Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.

1.3.2 Clock Generator

System frequency synthesizer: ICS954226 is a CK410M Compliant clock synthesizer. It provides a single-chip

solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. It is driven with a

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial
ATA and PCI-Express.

• Supports tight ppm accuracy clocks for Serial-ATA and SRC

• Supports spread spectrum modulation, 0 to –0.5% down spread

• Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning

• Supports undriven differential CPU, SRC pair in PD# for power management

1.3.3 The Mobile Intel 915GM Express Chipset

The Mobile Intel 915GM Express Chipset is a memory controller hub (GMCH) designed for use with the Dothan,
Yonah and Intel Celeron M Processor. It supports Intel Graphics Media Accelerator 900 & PCI Express based
Graphics.

The 915GM GMCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces. Only
Double Data Rate (DDR/DDR2) memory is supported; the buffers support DDR SSTL_2 and DDR2 SSTL_18
signaling interfaces. The memory controller interface is fully configurable through a set of control registers. It
supports a high performance transition interface PCI Express Interface. PCI Express operates at a data rate of 2.5
GB/s. This allows a maximum theoretical bandwidth of 40 GB/s each direction. The 915GM GMCH integrates
Direct media interface (DMI) chip-to-chip interconnect between the GMCH and ICH6-M. DMI supports DMI x2
and DMI x4 configuration.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

 Processor/FSB Support

• Intel

®

Dothan processor

• AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for

reduced power)

• Supports 32-bit AGTL+ host bus addressing

• Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz)

• 2X Address, 4X data

• Host bus dynamic bus inversion HDINV support

• 12 deep, in-order queue

 Memory System

• Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide

• Supports SO-DIMMs of the same type (e.g.,all DDR or all DDR2), not mixed

• Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 rows = 128 MB) using

256-MB technology

• Maximum amount of memory supported is 2 GB using 1-GB technology

• 256-MB, 512-MB and 1-GB technology using x8 and x16 devices

• Three memory channel organizations are supported for DDR / DDR2

--- Single channel

--- dual channel interleaved

--- dual channel asymmetric

• Supports DDR 333 devices and DDR2 400 /533 devices

--- Supports on-die termination (ODT) for DDR2

• Supports Fast Chip Select mode

• Supports partial write to memory using Data Mask signal (DM)

• Supports high-density memory package for DDR or DDR2 type devices

 PCI Express Interface

• One x16 (16 lanes) PCI Express port intended for graphics attach

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an

average of 8 GB/s when x16

• Automatic discovery, negotiation and training of link out of reset

• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)

• Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X relaxed ordering)

• Supports only 1.5-V AGP electricals

• 32 deep AGP request queue

• Hierarchical PCI-compliant configuration mechanism for downstream devices

 Internal Graphics Controller

• Intel Dual-Frequency Graphics Technology support

• 3D Graphics Engine

--- DirectX* 9.0 support

--- OpenGL* 1.5 and 2.0 support

--- Zone rendering 2.0 support

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• Analog CRT DAC Interface Support

--- Supports max DAC frequency up 400 MHz

--- 24-bit RAMDAC support

--- DDC2B compliant

• Analog TV-Out Interface Support

--- Integrated TV-Out device support on display pipes A and B

--- NTSC/PAL encoder standard formats supported

--- 480p/720p/1080i/1080p modes supported

--- Tri-level Sync signal

--- Multiplexed output interface:

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

- Composite video with S-Video

-S-Video

- Component Video

--- Up to 1024 x 768 resolution supported for NTSC/PAL

--- Macrovision, over scan scaling, and flicker filtering support

• Serial digital video out Port (SDVO) interface Support

--- Two SDVO port are muxed with a subset of the external graphics interface using PCI Express*
Architecture signals

--- Each SDVO port support display pixel rates up to 200MP/s

- The two SDVO ports can be combined into a gang mode to support pixel rates up to 400 MP/s

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

--- Supports a variety display devices such as DVI, TV-Out, LVDS, etc.

--- Supports hot plug and display

--- Supports for Macrovision on SDVO TV-Out devices

--- Supports for HDCP SDVO devices

--- External port adds alpha out

• Digital LVDS Interface Support

--- Integrated dual channel LVDS interface supported on display pipe B only

--- Supports 25-MHz to 112-MHz single/dual channel LVDS LCD interface with support for following
format of :

- 1x18 bpp for TFT panels with single channel LVDS

- 2x18 bbp for TFT panels with dual channels LVDS

--- Panel Fitting, Panning, and Center mode supported

--- Spread spectrum clocking (SSC) supported

--- Panel Power Sequencing compliant with SPWG timing specification

--- Integrated PWM interface for LCD backlight inverter control

• Direct Media Interface (DMI)

--- Chip-to-chip interconnect between the GMCH and ICH6-M

--- DMI x2 and DMI x4 configuration supported

--- Bit swapping is supported

--- Lane reversal is not supported

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1.3.4 I/O Controller Hub: Intel ICH6-M

 The ICH6 Provides Extensive I/O Support, Functions and Capabilities Include

• PCI Express Base Specification, Revision 1.0a-compliant

• PCI Local Bus Specification, Revision 2.3-compliant with support for 33 MHz PCI operations(supports up to

seven Req/Gnt pairs).

• ACPI Power Management Logic Support

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controller with independent DMA operation on two ports and AHCI support

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Integrated IDE controller supports Ultra ATA100/66/33

• USB host interface with support for three USB ports; three UHCI host controllers; one EHCI high-speed

USB2.0 Host controller

• Integrated LAN controller

• System Management Bus (SMBus) Specification, Version 2.0 with additional support for I

2

C devices

• Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a.,AC ’97 Component Specification, Revision 2.3)

which provides a link for Audio and Telephony codecs (up to 7 channels)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Supports Intel High Definition Audio

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

1.3.5 CardBus: PCI4510

 The PCI4510 Device Supports the Following Features

• PC Card Standard 8.0 compliant

• PCI Bus Power Management Interface Specification 1.1 compliant

• Advanced Configuration and Power Interface Specification 2.0 compliant

• PCI Local Bus Specification Revision 2.2 compliant

• PC 98/99 and PC2001 compliant

• Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges

• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std

1394a-2000

• Fully compliant with 1394 Open Host Controller Interface Specification 1.1

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Compatible with both TPS2211A and TPS2221 PC Card power switches

• 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core Vcc

• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

• Supports PC Card or CardBus with hot insertion and removal

• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus

• Supports serialized IRQ with PCI interrupts

• Programmable multifunction terminals

• Serial ROM interface for loading subsystem ID and subsystem vendor ID

• ExCA0compatible registers are mapped in memory or I/O space

• Intel 82365SL-DF register compatible

• Supports ring indicate , SUSPEND# , PCI CCLKRUN# protocol , and PCI bus lock (LOCK#)

• Provides VGA/palette memory and I/O , and subtractive decoding options , LED activity terminals

• Fully interoperable with FireWire

TM

and i.LINKTMimplementations of IEEE Std 1394

• Compliant with Intel Mobile Power Guideline 2000

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed

concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume

• Power-down features to conserve energy in battery-powered applications include: automatic device power

down during suspend, PCI power management for link-layer and inactive ports powered down, ultra low­power sleep mode

• Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s

• Cable power presence monitoring

• Separate cable bias (TPBIAS) for each port

• Physical write posting of up to three outstanding transactions

• PCI burst transfers and deep FIFO to tolerate large host latency

• External cycle timer control for customized synchronization

• Extended resume signaling for compatibility with legacy DV components

• PHY-Link logic performs system initialization and arbitration functions

• PHY-Link encode and decode functions included for data-strobe bit level encoding

• PHY-Link incoming data resynchronized to local clock

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Low-cost 24.576MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M

bits/s

• Node power class information signaling for system power management

• Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std

1394a-2000 features

• Isochronously receive dual-buffer mode

• Out-of-order pipelining for asynchronous transmit requests

• Register access fail interrupt when the PHY SCLK is not active

• PCI power-management D0, D1, D2, and D3 power states

• Initial bandwidth available and initial channels available registers

• PME# support per 1394 Open Host Controller Interface Specification

• Advanced sub micron, low-power CMOS technology

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.3.6 AC’97 Audio System: ALC655

The ALC655 is a 16-bit, full duplex AC’97 2.3 compatible six channels audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter
technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of
stereo outputs with 5-bit volume controls, a mono output, and multiple stereo and mono inputs, along with flexible
mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface
circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The
ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in

14.318M24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655 also supports the
S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic produces, such as
AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as
audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers
(WinXP/ME/2000/98/NT), EAX/Direct Sound 3D/I3DL2/A3D compatible sound effect utilities (supporting
Karaoke, 26-kind of environment sound emulation, 10-band equalizer), HRTF 3D positional audio and Sensaura
3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655
includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs can be detected.

 Features

• Meets performance requirements for audio on PC99/2001 systems

• Meets Microsoft WHQL/WLP 2.0 audio requirements

• 16-bit Stereo full-duplex CODEC with 48KHz sampling rate

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TM

• Compliant with AC’97 2.3 specifications

---Front-Out, Surround-Out, MIC-In and LINE-In Jack Sensing

---14.318MHz24.576MHz PLL to save crystal

---12.288MHz BITCLK input can be consumed

---Integrated PCBEEP generator to save buzzer

---Interrupt capability

• Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX

• High quality differential CD input

• Two analog line-level mono input: PCBEEP, PHONE-IN

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Two software selectable MIC inputs

• LINE Input shared with surround output: MIC input shared with Center and LFE output

• Both Front-out and Surround-Out built-in 50mW/20ohm amplifier

• External Amplifier Power Down (EAPD)

• Power management and enhanced power saving features

• Stereo MIC record for AEC/BF application

• Supports Power Off CD function

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Adjustable VREFOUT control

• Supports double sampling rate (96KHz) of DVD audio playback

• Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification

• Support 32K/44.1K/48KHz of S/PDIF input

• Power support: Digital: 3.3V; Analog: 3.3V/5V

• Standard 48-Pin LQFP Package

• EAX

• Direct Sound 3D

TM

1.0 & 2.0 compatible

TM

compatible

• HRTF 3D Positional Audio

• Sensaura

TM

3D Enhancement (optional)

• 10 Bands of Software Equalizer

• Voice Cancellation and Key Shifting in Kara OK mode

• AVRack Media Player

• Configuration Panel to improve Experience of User

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1.3.7 Modem: Askey 1456VQL4A(INT) Data/Fax Modem

 Features

• ITU-T V.90/V.92 data rates 28000 bits/s-56000 bits/s

• High compression throughput due to parallel access directly to the host PC

• ITU-T V.34 extended rates: 33600 bits/s-2400 bits/s V.32terbo, V.32bis, and fallbacks.

• ITU-T V.42 error correction (LAPM and MNP)

• ITU-T V.42bis V.44 and MNP Class 5 data compression

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Supports fax ITU-T V.34, V.17, V.29, V.27ter, and V.21 Ch 2

• ITU-T V.253 Class 1 FAX

• Support Application for Windows 98, Windows 98SE, Windows NT 4.0, Windows 2000, Windows XP

• AC97/MC’97 2.2 compliant

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.3.8 System Flash Memory (BIOS)

 Features

• Single 3.3-volt operations:

---3.3V Read

---3.3V Erase

---3.3V Program

• Fast Program operation:

---Byte-by-Byte programming: 35uS (typ.)

• Fast Erase operation:

---Chip erase 100mS (max.)

---Sector erase 25mS (max.)

---Page erase 25mS (max.)

• Fast Read access time: Tkq 11nS

• Endurance: 10K cycles (typ.)

• 8 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes

• Any individual sector or page can be erased

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• Hardware protection:

---Optional 16K byte or 64K byte Top Boot Block with lockout protection

---#TBL & #WP support the whole chip hardware protection

---Flexible 4K page size can be used as Parameter Blocks

---Low power consumption. Active current: 40mA (typ. For FWH mode)

---Automatic program and erase timing with internal Vpp generation

---End of program or erase detection: Toggle bit; Data polling

---Latched address and data

1.3.9 Memory Syst em

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

 256MB, 512MB, 1GB (x64) 200-Pin DDR2 SDRAM SODIMMs

• JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

• VDD=+1.8V±0.1V, VDDQ=+1.8V±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS,DQS#) option

• Four-bit prefetch architecture

• Differential clock input (CK,CK#)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Command entered on each rising CK edge

• DQS edge-aligned with data for Reads

• DQS center-aligned with data for Writes

• Duplicate output strobe (RDQS) option for x8 configuration

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable CAS Latency (CL) : 2,3,4 and 5

• Posted CAS additive latency (AL) : 0,1,2,3 and 4

• Write latency = Read latency – 1

t

CK

• Programmable burst lengths : 4 or 8

• Read burst interrupt supported by another READ

• Write burst interrupt supported by another WRITE

• Adjustable data – output drive strength

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Concurrent auto precharge option is supported

• Auto Refresh (CBS) and Self Refresh Mode

• 64ms, 8,192-cycle refresh

• Off-chip drive (OCD) impedance calibration

• On-die termination (ODT)

1.3.10 LAN – Integrated Gigabit Ethernet Controller

The Realtek RTL8110SBL (128 LQFP) Gigabit Ethernet controllers combine a triple-speed IEEE 802.3 compliant
Media Access Controller (MAC) with a triple-speed Ethernet transceiver, 32-bit PCI bus controller, and embedded
memory. With state-of-the-art DSP technology and mixed-mode signal technology, they offer high-speed
transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection &
Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing
recovery, and error correction are implemented to provide robust transmission and reception capability at high
speeds.

The devices support the PCI v2.3 bus interface for host communications with power management and are compliant
with the IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps
Ethernet. They also support an auxiliary power auto-detect function, and will auto-configure related bits of the PCI
power management registers in PCI configuration space.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

They support the Advanced Configuration Power management Interface (ACPI) – power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM) – to achieve the most
efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported.

In addition to the ACPI feature, the RTL8110SBL support remote wake-up (including AMD Magic Packet, Re­LinkOk, and Microsoft Wake-up frame) in both ACPI and APM (Advanced Power Management) environments.

The RTL8110SBL is fully compliant with Microsoft NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task­offload features, and supports IEEE 802 IP Layer 2 priority encoding and 802.1Q Virtual bridged Local Area
Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance
when in operation on a network server. Also, the devices boost their PCI performance by supporting PCI Memory
Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To
better qualify for server use, the RTL8110SBL support the PCI Dual Address Cycle (DAC) command when the
assigned buffers reside at a physical memory address higher than 4 Gigabytes.

 Features

• Integrated 10/100/1000 transceiver

• Auto-Negotiation with Next Page capability

• Supports PCI rev 2.3, 32-bit, 33/66MHz

• Supports pair swap/polarity/skew correction

• Crossover Detection & Auto-Correction

28

• Wake-on-LAN and remote wake-up support

• Microsoft NDIS5 Checksum Offload (IP, TCP, UDP) and large send offload support

• Supports Full Duplex flow control (IEEE 802.3x)

• Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab

• Support IEEE 802.1P Layer 2 Priority Encoding

• Support IEEE 802.1Q VLAN tagging

• Serial EEPROM

• 3.3V signaling, 5V PCI I/O tolerant

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Transmit/Receive FIFO (8K/64K) support

• Supports power down/link down power saving

• Supports PCI Message Signaled Interrupt (MSI)

• 128-pin LQFP package

29

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.3.11 Keyboard System: Winbond W83L950D

The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various
registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP­ROM that is divided into four banks, two SMBus interface for master and slave, Support 4 PWM channels, 2 D-A
and 8 A-D converters.

 Features

• 8051 uC based

• Keyboard Controller Embedded Controller

• Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB.

• Support 4 Timer (8 bit) signal with 3 prescalers.

• Support 2 PWM channels, 2 D-A and 8 A-D converters.

• Reduce Firmware burden by Hardware PS/2 decoding

• Support 72 useful GPIOs totally

• Support Flash utility for on board re-flash

• Support ACPI

30

• Hardware fast Gate A20 with software programmable

1.3.12 Hard Disk Drive

Prestigio Nobile 1510 can support SATA or PATA HDD by equipped different HDD transition board.

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

SATA HDD

conditions. In the case of Native IDE enabled operating systems, the ICH6 has separate PCI functions for serial and
parallel ATA (“enhanced mode”). To support legacy operating systems, there is only one PCI function for both the
serial and parallel ATA ports if functionality from both SATA and PATA devices is desired (“combined mode”).
SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate
at the bus’s maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS.

 Features

: The SATA function in the ICH6 has dual modes of operation to support different operating system

• Up-to 150MB/sec bus speed (Serial ATA Generation 1)

• Compliant with Serial ATA 1.0a Specification and Serial ATA 2 Extensions 1.0.

• Supports 48bit-LBA addressing

• Supports Native DMA Queued command (First party DMA queued)

• Also supports Legacy DMA Queued command

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

• Supports Staggered Spin-Up function

• Supports Hot-Plug features

• Supports Serial ATA power management (Host initiated Partial/Slumber)

IDE HDD

low.

 The IDE Interfaces of the ICH6 can Support Several Types of Data Transfers:

: The ICH6 IDE controller features one set of interface signals that can be enabled, tri-stated or driven

• Programmed I/O (PIO): processor is in control of the data transfer.

• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not use the 8237

in the ICH6. This protocol off loads the processor from moving data. This allows higher transfer rate of up to
16MB/s.

• Ultra ATA/33/66/100: DMA protocol that redefines signals on the IDE cable to allow both host and target

throttling of data and transfer rates of up to 33/66/100 MB/s.

32

1.4 Other Functions

1.4.1 Hot Key Function

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Keys

Combin

ation

Fn + F1 Wireless LAN

Fn + F2 Reserve
Fn + F3 Volume Down Decrease speaker volume
Fn + F4 Volume Up Increase speaker volume
Fn + F5 LCD/external

Fn + F6 Brightness down Decreases the LCD brightness
Fn + F7 Brightness up Increases the LCD brightness
Fn + F10 Speaker ON/OFF Toggle speaker on/off
Fn + F11 Panel ON/OFF Toggle Panel on/off
Fn + F12 Suspend to RAM Force the computer into Suspend to DRAM

Feature Meaning

Wireless LAN turn on and turn off

ON/OFF

Rotate display mode in LCD only, CRT only, and

CRT switching

simultaneously display.

mode depending on BIOS Setup.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.4.2 Power On/Off/Suspend/Resume Button

1.4.2.1 APM Mode

At APM mode, power button is on/off system power.

1.4.2.2 ACPI Mode

At ACPI mode, windows power management control panel set power button behavior.

You could set “standby” , “power off” or “hibernate”(must enable hibernate function in power management) to
power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode.

1.4.3 Cover Switch

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover.

At ACPI mode there are four functions to be chosen at windows power management control panel.

1. None

2. Standby

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

3. Off

4. Hibernate (must enable hibernate function in power management)

1.4.4 LED Indicators

System has eight status LED indicators to display system activity, which include three at the lower side of Panel cover,
five in the front-left edge of the notebook.

1.4.4.1 Three LED Indicators on LCD Housing and above Keyboard:

From left to right that indicates WLAN, Power, Battery Status.

AC / Battery Power

This LED lights green when the notebook was powered by AC or battery power line, Flashes (on 1 second,
off 1 second) when entered suspend to RAM state . The LED is off when the notebook is in power off state.

Battery Charge Status (Operate at both system on and off)

With battery operation, this LED stays off. When the battery charge drops to 10% of capacity, the LED
lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if
the battery pack is fully charged or orange (amber) if the battery is being charged.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

Wireless LAN

This LED light green when the wireless LAN is enabled.

1.4.4.2 Five LED Indicators in the Front Side of the Notebook:

From left to right that indicates CD-ROM, HARD DISK, NUM LOCK, CAPS LOCK and SCROLL LOCK.

1.4.5 Battery Status

1.4.5.1 Battery Warning

System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his
data before battery dead. Also, this function protects system from mal-function while battery capacity is low.

Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.

System will suspend to HDD after 2 Minutes to protect users data.

1.4.5.2 Battery Low State

After Battery Warning State, and battery capacity is below 5%, system will generate beep sound for twice per
second.

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

1.4.5.3 Battery Dead State

When the battery voltage level reaches 8.56 volts, system will shut down automatically in order to extend the
battery packs' life.

1.4.6 Fan Power On/Off Management

FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM
control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature will get faster Fan
Speed.

1.4.7 CMOS Battery

CR2032 3V 220mAh lithium battery.When AC in or system main battery inside, CMOS battery will consume no
power.AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.4.8 I/O Port

 One Power Supply Jack

 One External CRT Connector For CRT Display

 Supports three USB port for all USB devices

 One MODEM RJ-11 phone jack for PSTN line

 One RJ-45 for LAN

 One IEEE1394 port

 One S/PDIF Jack

 One Line-In Jack

 One Microphone Input Jack

 One S-Video (PAL/NTSC) connector

1.4.9 Battery Current Limit and Learning

Implanted H/W current limit and battery learning circuit to enhance protection of battery.

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

1.5 Power Management

The Nobile 1510 system has built in several power saving modes to prolong the battery usage for mobile purpose. User
can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing
F2 key). Following are the descriptions of the power management modes supported.

1.5.1 System Management Mode

1.5.1.1 Full On Mode

In this mode, each devices is running with the maximal speed. CPU clock is up to its maximum.

1.5.1.2 Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This
can save battery power without loosing much computing capability.

The CPU power consumption and temperature is lower in this mode.

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.5.1.3 Standby Mode

For more power saving, it turns off the peripheral components. In this mode, the following is the status of each device:

• CPU: Stop grant

• LCD: Backlight off

• HDD: Spin down

1.5.1.4 Suspend to DRAM and HDD

The most chipset of the system is entering power down mode for more power saving. In this mode, the following is
the status of each device:

• Suspend to DRAM

 CPU: off

 Intel 915GM : Partial off

 VGA: Suspend

 PCMCIA: Suspend

 Audio: off

 SDRAM: Self Refresh

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

• Suspend to HDD

 All devices are stopped clock and power-down

 System status is saved in HDD

 All system status will be restored when powered on again

1.5.2 Other Power Management Functions

HDD & Video access: System has the ability to monitor video and hard disk activity. User can enable monitoring

function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter
next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the
system will have some impact

41

M

P

P

P

X

X

X

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.6 Appendix 1: Intel ICH6-M GPIO Definitions -1

Pin name Current Define Power plane

GPIO0 SDIRQ I MAIN
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5 PCI_INTH# I MAIN
GPIO7 SCI# I MAIN
GPIO8 EXTSMI# I RESUME
GPIO9 X I RESUME
GPIO10 X I RESUME
GPIO11 SMBALERT# I RESUME
GPIO12 KBD_US/JP# I MAIN
GPIO13 WAKE_UP# I RESUME
GPIO14 X I RESUME
GPIO15 X I RESUME

INIPCI_ACT# I MAIN
CI_INTE# I MAIN
CI_INTF# I MAIN
CI_INTG# I MAIN

GPIO16
GPIO17
GPIO19

O MAIN
O MAIN
O MAIN

42

1.6 Appendix 1: Intel ICH6-M GPIO Definitions -2

Continue to previous page

Pin name Current Define Power plane

GPIO21 X O MAIN
GPIO23 WIRELESS_PD# O MAIN
GPIO24 SPK_OFF I/O RESUME
GPIO25 I/O RESUME
GPIO26 PANEL_ID0 I MAIN
GPIO27 X I/O RESUME
GPIO28 X I/O RESUME

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

GPIO29 PANEL_ID1 I MAIN
GPIO30 PANEL_ID2 I MAIN
GPIO31 PANEL_ID3 I MAIN
GPIO33 MB_ID0 I/O MAIN
GPIO34 MB_ID1 I/O MAIN
GPIO40 MXM_DETECT# I MAIN
GPIO41 CRT_IN# I MAIN
GPIO48 X O MAIN
GPIO49 HPWRGD OD O MAIN

43

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.7 Appendix 2: W83L950D KBC Pins Definitions -1

Port pin Function Implement

P0 0-7 KO[0..7]
P1 0-7 KO[8..15]
P3 0-7

0 LPC enable H8_THRM#
1 GPIO x1 H8_WAKE_UP#
2 BATT_G#

SMBUS1 or UART

3

P2

4 EXTSMI#
5 CAP#
6 NUM#
7
0 H8_ENABKL

Xcin/cout or PWM 2,3

1
2 LEARING

GPIO x2 (INT1)

3

P4

4 KBRST H8_HRCIN#
5 A20 A20GATE
6 H8_SCI
7

Scan matrix

GPIO x4

GPIO x2

KI[0..7]

BATT_R#

SCROLL#

CHARGING

H8_SUSB

H8_PWRON

44

1.7 Appendix 2: W83L950D KBC Pins Definitions -2

Continue to previous page

Port pin Function Implement

0 GPIO x1 SW_VDD3

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

1 H8_LIDSW#
2 BATT_DEAD#
3

P5

4 BATT_LED#
5
6 BLADJ
7
0 PWRBTN#
1 KBC_RI#
2 AC_ POWER#
3 BATT_V

P6

4 BATT_T
5 H8_I_LIMIT
6 H8_PROCHOT#
7

GPIO x3

(INT20,30,40)

H8_ADEN#

GPIO x2

KBC_PWRON_VDD3S

D/A, PWM 2,3

H8_I_CTR

A/D (INT5-12)

+BC_CPUCORE

45

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.7 Appendix 2: W83L950D KBC Pins Definitions -3

Continue to previous page

Port pin Function Implement

0 T_DATA
1 H8_RSMRST
2 ICH_PWRBTN
3 T_CLK

P7

4 H8_PWRON_SUSB#
5
6 BAT_DATA
7
0 PCICLK_KBC
1 SERIRQ
2 LAD3
3 LAD2

P8

4 LAD1
5 LAD0
6 KBC_PCIRST#
7

PS/2 port x3

SUSC#

SMBUS

BAT_CLK

LPC interface

LFRAME#

46

1.8 Appendix 3: Prestigio Nobile 1510 Product Specifications -1

Prestigio Nobile 1510 Preliminary Specifications R0.6

Model Nobile1510

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

CPU
Chip Set

L2 Cache
System BIOS

Memory

Video Controller
Optical drive

FDD

HDD

Intel Pentium-M Processor Dothan 400 and 533 FSB

-Thermal spec 35W TDP
Intel 915GM+ICH6M
2MB for Dothan
512KB Flash EPROM - include System BIOS, VGA BIOS –
Plug &Play capability -ACPI
0MB DDRII 400/533 SDRAM memory on board

- 2 memory DIMM slots for memory expansion

- 200pin DDRII 400/533 SDRAM SO-DIMM Memory
Module
Support up to 2048MB

- 1.25-inch height memory module supported
SMA

Combo / DVD+RW, DVD-RW, DVD-Dual (12.7mm)
Detected as 2nd Master (by ODD F/W)
External USB I/F Option
Support 2.5" 30GB / 40GB / 60GB / 80GB/100GB/120GB
HDD(9.5mm) 4200rpm or 5400rpm
Ultra DMA(PATA) 100

Display

14.1"/15" XGA TFT

-Resolution: 1024x768

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

1.8 Appendix 3: Prestigio Nobile 1510 Product Specifications -2

Continue to previous page

European keyboard layout

- 19mm key pitch / 3mm stroke

Keyboard

Pointing Device
PC Card Slot

Audio System

I/O Port

- Hot key spec: Fn+F1 : WirelessLAN ON/OFF , Fn+F3/F4 :
Volume down/up, Fn+F5 : LCD/CRT output change
Fn+F6/F7: Brightness up/down, Fn+F11: Display ON/OFF,
Fn+F12: Standby
TouchPad (No scroll button)
TypeII x 1

-PCMCIA Standard Rev.2.1 , CardBus support , w/o ZV port
Built-in Sound system

- AC97 1/F (5.1 CH support)

- AC-3 support

- Built-in stereo speaker, Built-in microphone

- Sound Volume control by Hot-Key (Fn + F3 : Volume
down, Fn + F4 : Volume up)
USB(2.0) x 3
Mic-in x 1(Mono);Line-in x 1
SPDIF x 1 (AC97)
S-Video (PAL/NTSC) x 1
RJ-45 LAN Jack x 1 (with cap) RJ-11Modem Jack x 1 (with
cap)
IEEE 1394 x 1
VGA port x 1
DC-in x 1

48

1.8 Appendix 3: Prestigio Nobile 1510 Product Specifications -3

Continue to previous page

56Kbps(V.90) Fax Modem(MDC(Azalia I/F)) and

Communication

Battery

Indicator

Quick Keys
Power Supply
Safety Lock
Dimension
WEIGHT
OS

10/100/1000 Base-TX LAN
Wireless LAN (Mini PCI Interface IEEE802.11b, g)
Li-ion Battery 2400mAh(6-cell) - Battery Life: 3
hrs( 256+256MB Memory, Dothan 1.7GHz CPU, Backlight:
Mid.)
Power-ON charge available

-RTC backup battery(Lithium) Standard
5 LEDs at parm rest: ODD/HDD/Number Lock/Caps
Lock/Scroll Lock
3 LEDs above keybaord: WLAN/Power/Battery status
3 LEDs on LCD housing: WLAN/Power/Battery status
3 Quick keys: Internet/e-mail/battery low alarm on-off
65W(P) Universal AC Adapter(100-240V)
Kensington Lock x 1
W277 x D329 x H26~33.3mm

2.7kg (P)
Windows XP Pro (With SP2)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Windows Logo

EMI/Safety/
Regulation

Support PC2001 Specification

- Need to get the Log files for WindowsXP Pro, WHQL
Certified
EMI:CE/TUV/CB RF:R&TTE

PTT:CE

49

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2. System View and Disassembly

2.1 System View

2.1.1 Front View



Top Cover Latch



2.1.2 Left-side View

S-Video Port



Line In Connector



S/PDIF Connector



MIC In Connector



Ventilation Openings



IEEE1394 Connector



RJ-11 Connector



RJ-45 Connector



PCMCIA Card Socket



50



















2.1.3 Right-side View

CD/DVD-ROM Drive



USB Port *1



Power Connector







TECHNICAL SERVICE MANUALPrestigio Nobile 1510



2.1.4 Rear View

Lock



USB Ports *2



VGA Port



51







TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.1.5 Bottom View

Hard Disk Drive



CPU



Battery Park



2.1.6 Top-open View

LCD Screen









Stereo Speaker Set



Keyboard



Internal MIC In



Device LED Indicators



Touch Pad



Power Button



Battery Indicator



Power Indicator



Wireless Indicator



52























TECHNICAL SERVICE MANUALPrestigio Nobile 1510

2.2 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.

2.2.1 Battery Pack

2.2.2 Keyboard

2.2.3 CPU

Modular Components

2.2.4 HDD Module

NOTEBOOK

LCD Assembly Components

Base Unit Components

53

2.2.5 CD/DVD-ROM Drive

2.2.6 Modem Card

2.2.7 DDR-SDRAM

2.2.8 LCD Assem bly

2.2.9 LCD Panel

2.2.10 Inverter Board

2.2.11 System Board

2.2.12 Touch Pad

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.1 Battery Pack

Disassembly

1. Carefully put the notebook upside down.

2. Slide the two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of the
compartment (). (Figure 2-1)





Figure 2-1 Remove the battery pack



Reassembly

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.

2. Slide the release lever to the “lock” ( ) position.

54

2.2.2 Keyboard

Disassembly

1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Push the keyboard cover to loose the locks from the battery compartment. (Figure 2-2)

3. Lift the keyboard cover up. (Figure 2-3)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-2 Push the keyboard cover Figure 2-3 Lift the keyboard cover

55

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

4. Slightly lift up the keyboard. (Figure 2-4)

5. Disconnect the cable from the system board, then separate the keyboard. (Figure 2-5)

Figure 2-4 Lift the keyboard Figure 2-5 Disconnect the cable

Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place.

2. Replace the keyboard cover.

3. Replace the battery pack. (Refer to section 2.2.1 Reassembly)

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

2.2.3 CPU

Disassembly

1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove the seven screws fastening the CPU cover. (Figure 2-6)

3. Remove the four spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from
system board. (Figure 2-7)

Figure 2-6 Remove the seven screws

Figure 2-7 Free the heatsink

57

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

4. To remove the existing CPU, loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU.
(Figure 2-8)

Figure 2-8 Remove the CPU

Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into
the holes. Tighten the screw by a flat screwdriver to locking the CPU.

2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with four spring
screws.

3. Replace the CPU cover and secure with seven screws.

4. Replace the battery pack. (Refer to section 2.2.1 Reassembly)

58

2.2.4 HDD Module

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove the two screws fastening the HDD compartment cover. (Figure 2-9)

3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-10)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

cover

Figure 2-10 Remove HDD moduleFigure 2-9 Remove the HDD compartment

59

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

4. Remove the four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-11)

Figure 2-11 Remove hard disk drive

Reassembly

1. Attach the bracket to hard disk drive and secure with four screws.

2. Slide the HDD module into the compartment and secure with one screw.

3. Place the HDD compartment cover and secure with two screws.

4. Replace the battery pack. (Refer to section 2.2.1 Reassembly)

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TECHNICAL SERVICE MANUALPrestigio Nobile 1510

2.2.5 CD/DVD-ROM Drive

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove the one screw fastening the CD/DVD-ROM drive. (Figure 2-12)

3. Insert a small rod, such as a straightened paper clip, into CD/DVD-ROM drive’s manual eject hole () and push
firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out ().
(Figure 2-12)





Figure 2-12 Remove the CD/DVD-ROM drive

Reassembly

1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.

2. Replace the battery pack. (Refer to section 2.2.1 Reassembly)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.6 Modem Card

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove the seven screws fastening the CPU cover. (Refer to step 2 of section 2.2.3 Disassembly)

3. Remove the two screws fastening the modem card. (Figure 2-13)

4. Lift up the modem card and disconnect the cord. (Figure 2-14)

Figure 2-13 Remove the two screws Figure 2-14 Disconnect the cord

Reassembly

1. Reconnect the cord and fit the modem card.

2. Fasten the modem card by two screws.

3. Replace the CPU cover and secure with seven screws. (Refer to step 3 of section 2.2.3 Reassembly)

4. Replace the battery pack. (Refer to section 2.2.1 Reassembly)

62

2.2.7 DDR-SDRAM

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.2.1 Disassembly)

2. Remove the seven screws fastening the CPU cover. (Refer to step 2 of section 2.2.3 Disassembly)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-15 Remove the SO-DIMM

3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-15)

Reassembly

1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into
position.

2. Replace the CPU cover and secure with seven screws. (Refer to step 3 of section 2.2.3 Reassembly)

3. Replace the battery pack. (See section 2.2.1 Reassembly)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.8 LCD ASSY

Disassembly

1. Remove the battery pack and keyboard. (See sections 2.2.1 and 2.2.2 Disassembly)

2. Separate the antenna from the system board. (Figure 2-16)

3. Remove the two hinge covers, then carefully pull the antenna wires out. (Figure 2-17)

Figure 2-16 Separate the antenna Figure 2-17 Remove the two hinge covers

64

4. Disconnect the two cables from the system board. (Figure 2-18)

5. Remove the four screws, then free the LCD assembly. (Figure 2-19)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-18 Disconnect the two cables Figure 2-19 Free the LCD assembly

Reassembly

1. Attach the LCD assembly to the base unit and secure with four screws.

2. Replace the antenna wires back into Mini PCI compartment.

3. Reconnect the two cables to the system board.

4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)

65

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.9 LCD Panel

Disassembly

1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.2.1, 2.2.2 and 2.2.8 Disassembly)

2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-20)

3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process
until the cover is completely separated from the housing.

4. Remove the eight screws and disconnect the cable. (Figure 2-21)

Figure 2-20 Remove LCD cover

Figure 2-21 Remove the eight screws and

disconnect the cable

66

5. Remove the four screws that secure the LCD brackets. (Figure 2-22)

6. Disconnect the cable to free the LCD panel. (Figure 2-23)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-22 Remove the four screws

Figure 2-23 Free the LCD panel

Reassembly

1. Replace the cable to the LCD panel.

2. Attach the LCD panel’s brackets back to LCD panel and secure with four screws.

3. Replace the LCD panel into LCD housing and secure with eight screws.

4. Reconnect one cable to inverter board.

5. Fit the LCD cover and secure with two screws and rubber pads.

6. Replace the LCD assembly, keyboard and battery pack. (See sections 2.2.8, 2.2.2 and 2.2.1 Reassembly)

67

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.10 Inverter Board

Disassembly

1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.2.1, 2.2.2 and 2.2.8 Disassembly)

2. Remove the LCD cover. (Refer to the steps 1-3 of section 2.2.9 Disassembly )

3. Remove the two screws fastening the inverter board and disconnect the cable, then free the inverter board.
(Figure 2-24)

Figure 2-24 Free the inverter board

Reassembly

1. Reconnect the cable. Fit the inverter board back into place and secure with two screws.

2. Replace the LCD cover. (Refer to section 2.2.9 Reassembly)

3. Replace the LCD assembly. (Refer to section 2.2.8 Reassembly)

4. Replace the keyboard and battery pack. (Refer to sections 2.2.2 and 2.2.1 Reassembly)

68

2.2.11 System Board

Disassembly

1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive,modem card, DDR and LCD
assembly. (Refer to sections 2.2.1, 2.2.2, 2 .2.3, 2.2.4, 2.2.5, 2.2.6, 2.2.7 and 2.2.8 Disassembly)

2. Disconnect the touch pad’s cable from the system board. (Figure 2-25)

3. Remove the three screws fastening the housing. (Figure 2-26)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-25 Disconnect the one cable

Figure 2-26 Remove the three screws

69

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

4. Disconnect the left speaker’s cable, then remove the twenty-one screws and free the housing. (Figure 2-27)

5. Disconnect the right speaker’s cable from the system board. (Figure 2-28)

Figure 2-27 Free the housing

Figure 2-28 Lift the system board

70

6. Remove the five screws and lift the system board. (Figure 2-29)

7. Separate the daughter board from the system board and free the system board. (Figure 2-30)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Figure 2-29 Remove the five screws

Figure 2-30 Free the system board

Reassembly

1. Replace the daughter board into the system board.

2. Replace the system board back into the top cover and secure with six screws.

3. Reconnect the right speaker’s cable into the system board.

4. Replace the housing and secure with twenty-four screws.

5. Reconnect the left speaker’s cable into the system board.

6. Turn over the base unit, then reconnect the touch pad’s cable.

7. Replace the LCD assembly, DDR, modem card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery
pack. (Refer to previous section reassembly)

71

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

2.2.12 Touch Pad

Disassembly

1. Remove the battery pack, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, modem card, DDR, LCD
assembly and the system board. (See sections 2.2.1, 2.2.2, 2.2.3, 2.2.4, 2.2.5, 2.2.6, 2.2.7, 2.2.8 and 2.2.11
Disassembly)

2. Remove the four screws and lift the shielding, then free the touch pad. (Figure 2-31)

Figure 2-31 Free the touch pad

Reassembly

1. Replace the touch pad, then fit the shielding and secure with four screws.

2. Replace the battery pack, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, modem card, DDR, LCD
assembly and the system board. (See sections previous section reassembly)

72

3. Definition & Location of Connectors / Switches

3.1 Mother Board (Side A-1)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

J509

J512

J515

J513

J509

J511

J510

J506

J507

504

J508

J505 J502

J501

 J501 : External VGA Connector
 J502 : S-Video Port
 J504 : Battery Connector
 J505 : S/PDIF Connector
 J506,J507 : Daughter Board Connector
 J508 : External MIC Jack
 J509 : Right Audio Channel Co nnector
 J510 : Left Audio Channel Connector
 J511 : CPU Fan Connector
 J512 : CD-ROM Conne ctor
 J513 : RTC Batt ery Connector
 J514 : 1394 Connector
 J515 : MDC Jump Wire Connector

J516

 J516 : RJ45&RJ11 Connector

J514

73

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

3. Definition & Location of Connectors / Switches

3.1 Mother Board (Side A-2)

------ Continued to previous page ------

 J517,J521 : SO DIMM Slot

J519

J526

 J519 : HDD Connector
 J520 : MINI PCI Slot
 J522 : MDC Boar d Connector

J522

J521

J520

J517

J509

 J525 : Line In Connector
 J526 : USB Interface for IR Receiver

J525

74

3. Definition & Location of Connectors / Switches

3.2 Mother Board (Side B)

 J1 : LCD Connecto r
 J2 : Internal Keyboard C onn ector

J5

J509

J1

 J4 : Touch-Pad Connector
 J5 : PCMCIA Card Socket
 J6 : Blue Tooth Connector
 SW1 : Touch-Pad Left Button

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

SW1

SW2

 SW2 : Touch-Pad Right Button

J6

J2J4

75

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

3. Definition & Location of Connectors / Switches

3.3 Daughter Board

 J1 : Power Jack
 J2,J3 : USB Port

J6

J5

J4

SW2

J3

SW1

J1

J2

 J4 : LCD Inverter Board Connector
 J5,J6 : Board to Board Connector
 SW1 : Cover Switch
 SW2 : Power Button

76

4. Definition & Location of Major Components

4.1 Mother Board (Side A)

U510

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

 U501 : ICS954226 Clock Generator
 U506 : Intel Dothan Processor
 U510 : Windbond W83L950D Keyboard BIOS
 U512 : Intel 915GM GMC H North Brid ge

U519

U517

J509

U514

U512

U513

U506

 U513 : Intel ICH6-M South Bridge
 U514 : NS692403
 U517 : PCI4510GHK PCMCIA/CARDBUS
 U519 : RTL8110SBL LAN Connector

U501

77

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

4. Definition & Location of Major Components

4.2 Mother Board (Side B)

 U3 : Audio Codec ALC655
 U5 : Amplifier TPA0 212

J509

U12

U5

U3

 U13 : PCMCIA/CARDBUS Power Matrix

TPS2211A

 U15 : System BIOS SST49CF004A
 U16 : PATA HDD Controller 88SA8040

U15

U13

U16

78

5. Pin Descriptions of Major Components

5.1 Intel 915GM North Bridge(1)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Host Interface Signals

Signal Name Type Description

HADS# I/O

AGTL+

HBNR# I/O

AGTL+

HBPRI# O

AGTL+

HBREQ0# I/O

AGTL+

HCPURST# O

AGTL+

HDBSY# I/O

AGTL+

HDEFER# O

AGTL+

HDINV[3:0]# I/O

AGTL+

Host Address Strobe:

The system bus owner asserts HADS# to indicate the first of two
cycles of a request phase. The GMCH can also assert this signal for
snoop cycles and interrupt messages.

Host Block Next Request:

Used to block the current request bus owner from issuing a new
request. This signal is used to dynamically control the CPU bus
pipeline depth.

Host Bus Priori ty Reque st:

The GMCH is the only Priority Agent on the system bus. It asserts
this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.

Host Bus Request 0#:

The GMCH pulls the processor bus HBREQ0# signal low during
HCPURST#. The signal is sampled by the processor on the
active-to-inactive transition of HCPURST#.
HBREQ0# should be tri-stated after the hold time requirement has
been satisfied.

Host CPU Reset:

The CPURST# pin is an output from the GMCH. The GMCH asserts
HCPURST# while RSTIN# is asserted and for approximately 1 ms
after RSTIN# is deasserted. HCPURST# allows the processor to
begin execution in a known state.

Host Data Bus Busy:

Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.

Host Defer:

Signals that the GMCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.

Host Dynamic Bus Inversio n:

Driven along with the HFD[63:0]# signals. Indicates if the associated
signals are inverted or not. HDINVF[3:0]# are asserted such that the
number of data bits driven electrically low (low voltage) within the
corresponding 16-bit group never exceeds 8.

HDINV# Data Bits

HDINV[3]# HD[63:48]#
HDINV[2]# HD[47:32]#
HDINV[1]# HD[31:16]#
HDINV[0]# HD[15:0]#

Host Interface Signals (Continued)

Signal Name Type Description

HDRDY# I/O

HA[31:3]# I/O

HADSTB[1:0]# I/O

HD[63:0]# I/O

HDSTBP[3:0]#
HDSTBN[3:0]#

HHIT# I/O

HHITM# I/O

79

AGTL+

AGTL+

2X

AGTL+

2X

AGTL+

4X

I/O

AGTL+

4X

AGTL+

AGTL+

Host Da t a Ready:

Asserted for each cycle that data is transferred.

Host Address Bus:

HA[31:3]# connects to the CPU address bus. During processor cycles
the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during
snoop cycles on behalf of DMI.
HA[31:3]# are transferred at 2x rate.
Note that the address is inverted on the CPU bus.

Host Address Strobe:

HA[31:3]# connects to the CPU address bus. During CPU cycles, the
source synchronous strobes are used to transfer HA[31:3]# and
HREQ[4:0]# at the 2x transfer rate.

Strobe Address Bits

HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#

Host Data:

These signals are connected to the CPU data bus. HD[63:0]# are
transferred at 4x rate.
Note that the data signals are inverted on the CPU bus depending on
the HDINV[3:0]# signals.

Host Differential Host Data Strobes:

The differential source synchronous strobes are used to transfer
HD[63:0]# and HDINV[3:0]# at the 4x transfer rate.

Strobe Data Bits

HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, HDINV[3]#
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, HDINV[2]#
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, HDINV[1]#
HDSTBP[0]#, HDSTBN[0]# HD[15:00]#, HDINV[0]#

Host Hit:

Indicates that a caching agent holds an unmodified version of the
requested line.
Also, driven in conjunction with HITM# by the target to extend the
snoop window.

Host Hit Modified:

Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing
the line.
Also, driven in conjunction with HIT# to extend the snoop window.

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.1 Intel 915GM North Bridge(2)

Host Interface Signals (Continued)

Signal Name Type Description

HLOCK# I

AGTL+

HREQ[4:0]# I/O

AGTL+

HTRDY# O

AGTL+

HRS[2:0]# O

AGTL+

HDPWR# O

AGTL+

HCPUSLP# O

CMOS

Host Lock:

All CPU bus cycles sampled with the assertion of HLOCK# and
HADS#, until the negation of HLOCK# must be atomic, i.e. PCI
Express graphics access to System Memory is allowed when
HLOCK# is asserted by the CPU.

Host Request Command:

Defines the attributes of the request. HREQ[4:0]# are transferred at

2X

2x rate.
Asserted by the requesting agent during both halves of the Request
Phase. In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the second half
the signals carry additional information to define the complete
transaction type.

Host Target Ready:

Indicates that the target of the processor transaction is able to enter
the data transfer phase.

Host Response Status:

Indicates the type of response according to the following the table:

HRS[2:0]# Response type

000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response

Host Data Power:

Used by GMCH to indicate that a data return cycle is pending within
2 HCLK cycles or more. CPU use’s this signal during a read-cycle to
activate the data input buffers in preparation for HDRDY# and the
related data.

Host CPU Sleep:

When asserted in the Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked
Loop (PLL) still operating. Processors in this state will not recognize
snoops or interrupts.

Host Interface Reference and Compensation

Signal Name Type Description

HVREF I

HXRCOMP I/O

HXSCOMP I/O A Host X SCOMP:

HXSWING I

HYRCOMP

HYSCOMP I/O

HYSWING I

Host Reference Voltage:

A

Reference voltage input for the Data, Address, and Common clock
signals of the Host AGTL+ interface.

Host X RCOMP:

A

Used to calibrate the Host AGTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VCCP).

Slew Rate Compensation for the Host Interface

Host X Voltage Swing:

A

These signals provide reference voltages used by the HXRCOMP
circuits.

Host Y RCOMP

I/O

A

Used to calibrate the Host AGTL+ I/O buffers.

Host Y SCOMP:

A

Slew Rate Compensation for the Host Interface

Host Y Voltage Swing:

A

These signals provide reference voltages used by the HYRCOMP
circuitry.

:

DMI

Signal Name Type Description

DMI_RXP[1:0]
DMI_RXN[1:0]
DMI_TXP[1:0]
DMI_TXN[1:0]
DMI x2 is supported for Intel 915GMS chipset

I

PCIE

O

PCIE

DMI input from ICH6-M:

Direct Media Interface receive differential pair

DMI output to ICH6-M:

Direct Media Interface transmit differential pair

80

5.1 Intel 915GM North Bridge(3)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

DDR / DDR2 SDRAM Channel A Interface

Signal Name Type Description

SA_DQ[63:0] I/O

SSTL1.8/2

SA_DM[7:0] I/O

SSTL1.8/2

SA_DQS[7:0] I/O

SSTL1.8

SA_DQS[7:0]# I/O

SSTL1.8

SA_MA[13:0] O

SSTL1.8/2

SA_BS[2:0] O

SSTL1.8/2

Data Bus:

DDR / DDR2 Channel A data signal interface to the SDRAM data
bus.

2x

Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A

Data Mask:

These signals are used to mask individual bytes of data in the case of
a partial write, and to interrupt burst writes.

2x

When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SA_DM[7:0] for every data byte
lane.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A

Data Strobes:

DDR: The rising and falling edges of SA_DQS[7:0] are used for
capturing data during read and write transactions.

2x

DDR2: SA_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS[7:0]# during read and write
transactions.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A

Data Strobe Complements

DDR1: No Connect. These signals are not used for DDR devices
DDR2 : These are the complementary DDR2 strobe signals.

2x

Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A

Memory Address:

These signals are used to provide the multiplexed row and column
address to the SDRAM.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_MA13 is for support of 1 Gb devices.
Bank Select:
These signals define which banks are selected within each SDRAM
rank.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_BS2 is for support for DDR2 only for 8 bank devices.

DDR / DDR2 SDRAM Channel A Interface (Continued)

Signal Name Type Description

SA_RAS# O

SA_CAS# O

SA_WE# O

SA_RCVENIN# O

SA_RCVENOUT
#

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

RAS Control signal:
Used with SA_CAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A

CAS Control signal:

Used with SA_RAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A

Write Enable Control signal:

Used with SA_RAS# and SA_CAS# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A

Clock Input:

Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENOUT#.
Leave as No Connect.

O

Clock Output:

Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENIN#.
Leave as No Connect.

PCI Express Based Graphics Interface Signals

Signal Name Type Description

EXP_RXN[15:0]
EXP_RXP[15:0]I PCIE
EXP_TXN[15:0]
EXP_TXP[15:0]O PCIE
EXP_ICOMPO I

EXP_COMPI

PCI Express Based Graphics is supported for Intel 915GM and Intel 915PM chipsets.

PCI Express Receive Differential Pair

PCI Express Transmit Differential Pair

PCI Express Output Current and Resistance Compensation

A

I

PCI Express Input Current Compensation

A

81

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.1 Intel 915GM North Bridge(4)

DDR / DDR2 SDRAM Channel B Interface

Signal Name Type Description

SB_DQ[63:0] I/O

SSTL1.8/2

SB_DM[7:0] O

SSTL1.8/2

SB_DQS[7:0] I/O

SSTL1.8/2

SB_DQS[7:0]# I/O

SSTL1.8

SB_MA[13:0] O

SSTL1.8/2

SB_BS[2:0] O

SSTL1.8/2

Data Lines:
DDR / DDR2 Channel B data signal interface to the SDRAM data
bus.

2x

Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B

NOTE: Signals do not exist in Intel 915GMS.
Data Mask:

When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SB_DM[7:0] for every data byte

2x

lane. These signals are used to mask individual bytes of data in the
case of a partial write, and to interrupt burst writes.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B

NOT

E: Signals do not exist in Intel 915GMS.

Data Strobes:

DDR: The rising and falling edges of SB_DQS[7:0] are used for
capturing data during read and write transactions.

2x

DDR2: SB_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SB_DQS[7:0] and its SB_DQS[7:0]# during read and write
transactions.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B

NOTE: Signals do not exist in Intel 915GMS.
Data Strobe Co mp l e me n ts (DDR2 only):

DDR1: No Connect. These signals are not used for DDR devices
DDR2 : These are the complementary DDR2 strobe signals.

2x

Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B

NOT

E: Signals do not exist in Intel 915GMS.

Memory Address:

These signals are used to provide the multiplexed row and column
address to the SDRAM.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

NOTE: SB_MA13 is for support of 1 Gb devices.
Bank Select:

These signals define which banks are selected within each
SDRAM rank.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

NOTE: SB_BS2 is for DDR2 support only.

DDR / DDR2 SDRAM Channel B Interface (Continued)

Signal Name Type Description

SB_RAS# O

SB_CAS# O

SB_WE# O

SB_RCVENIN# I

SB_RCVENOUT
#

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

SSTL1.8/2

RAS Control signal:
Used with SB_CAS# and SB_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

CAS Control signal:

Used with SB_RAS# and SB_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

Write Enable Control signal:

Used with SB_RAS# and SB_CAS# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

Clock Input:

Used to emulate source-synch clocking for reads.
Leave as No Connect.
NOTE: Signals do not exist in Intel 915GMS.

O

Clock Output:

Used to emulate source-synch clocking for reads.
Leave as No Connect.

NOTE: Signals do not exist in Intel 915GMS.

DMI

Signal Name Type Description

DMI_RXP[3:0]
DMI_RXN[3:0]
DMI_TXP[3:0]
DMI_TXN[3:0]
DMI x2 or x4 is supported for Intel 915GM, Intel 915PM and Intel 910GML chipsets.

82

I

PCIE

O

PCIE

DMI input from ICH6-M:

Direct Media Interface receive differential pair

DMI output to ICH6-M:

Direct Media Interface transmit differential pair

5.1 Intel 915GM North Bridge(5)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

DDR / DDR2 Common Signals

Signal Name Type Description

SM_CK[1:0],
SM_CK[4:3] O SSTL1.8/2

SM_CK[1:0]#,
SM_CK[4:3]# O SSTL1.8/2

SM_CS[3:0]# O

SSTL1.8/2

SM_CKE[3:0] O

SSTL1.8/2

SDRAM Differential Clock:

The crossing of the positive edge of SM_CKx and the negative edge
of its complement SM_CKx# are used to sample the command and
control signals on the SDRAM.
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
SDRAM Inverted Differential Clock:

These are the complementary Differential DDR2 Clock signals.

NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
Chip Select: (1 per Rank):

These signals select particular SDRAM components during the active
state. There is one Chip Select for each SDRAM rank
SM_CS[1:0]# :
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CS[3:2]# :
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
Clock E nable: (1 per Rank):
SM_CKE[3:0] is used:
.To initialize the SDRAMs during power-up
.To power-down SDRAM ranks
. To place all SDRAM ranks into and out of self-refresh during STR.
SM_CKE[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CKE[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B

DDR / DDR2 Common Signals (Continued)

Signal Name Type Description

SM_ODT[3:0]

O

SSTL1.8/2

On Die Termination: Active Termination Contro

SM_ODT[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A

Signal Description

The crossing of the positive edge of SM_CKx and the negative edge
of its
complement SM_CKx# are used to sample the command and control

SM_CK[0:1]

differential

SM_CK[4:3]

differential

E:

NOT

These are the complementary Differential DDR2 Clock signals.

E:

NOT

These signals select particular SDRAM components during the active
To place all SDRAM ranks into and out of self-refresh during STR.

On Die Termination: Active Termination Contro

SM_ODT[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
DDR: Leave as no connects. Not used for DDR devices.
DDR2: On-die termination for DDR2 devices.

and its complement

and its complement

SM_CK2
SM_CK2#

and

SM_CK5

and

are reserved and not supported.

SM_CK5#

l. (DDR2 only)

SM_CK[1:0]#
SM_CK[4:3]#

are reserved and not supported.

signal make a

signal make a

l. (DDR2 only)

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.1 Intel 915GM North Bridge(6)

CRT DAC Signals

Signal Name Type Description

RED O A RED Analog Video Output:

RED# O A RED# Analog Output:

GREEN O

GREEN# O A GREEN# Analog Output:

BLUE O

BLUE# O

REFSET O A Resistor Set:

HSYNC O

HVCMOS

VSYNC O

HVCMOS

This signal is a CRT Analog video output from the internal color
palette DAC.

This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.

GREEN Analog Video Output:

A

This signal is a CRT Analog video output from the internal color
palette DAC.

This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.

BLUE Analog Video Output:

A

This signal is a CRT Analog video output from the internal color
palette DAC.

BLUE# Analog Output:

A

This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.

Set point resistor for the internal color palette DAC. A 256-Ω ± 1%
resistor is required between REFSET and motherboard ground.

CRT Horizontal Synchronizati on:

This signal is used as the horizontal sync (polarity is programmable)
or “sync interval”.
CRT Vertical Synchronization:
This signal is used as the vertical sync (polarity is programmable).

Analog TV-out Signals

Signal Name Type Description

TVDAC_A O

TVDAC_B O

TVDAC_C O

TV_IRTNA O

TV_IRTNB O

TV_IRTNC O

TV_REFSET O

TVDAC Channel A Output:

A

TVDAC_A supports the following:

Composite: CVBS signal
Component: Chrominance (Pb) analog signal
TVDAC Channel B Output:

A

TVDAC_B supports the following:

S-Video: Luminance analog signal
Component: Luminance (Y) analog signal
TVDAC Channel C Output:

A

TVDAC_C supports the following:

S-Video: Chrominance analog signal
Component: Chrominance (Pr) analog signal
Current Return for TVDAC Channel A:

A

Connect to ground on board

Current Return for TVDAC Channel B:

A

Connect to ground on board

Current Return for TVDAC Channel C:

A

Connect to ground on board

TV Resistor set:

A

TV Reference Current uses an external resistor to set internal
reference voltage levels. A 5-k §Ù ± 0.5% resistor is required
between REFSET and motherboard ground.

84

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Display Data Channel (DDC) and GMBUS Support

Signal Name Type Description

LCTLA_CLK I/O

LCTLB_DATA I/O

DDCCLK I/O

DDCDATA I/O

LDDC_CLK I/O

LDDC_DATA

SDVOCTRL_CL
K
SDVOCTRL_DA
TA

COD

COD

COD

COD

COD

COD

COD

COD

I2C Based control signal (Clock) for External SSC clock chip
control –
I2C Based control signal (Data) for External SSC clock chip control –

CRT DDC clock monitor control support

CRT DDC Data monitor control support

EDID support for flat panel display

I/O

EDID support for flat panel display

I/O

I2C Based control signal (Clock) for SDVO device

I/O

I2C Based control signal (Data) for SDVO device

DDR SDRAM Reference and Compensation

Signal Name Type Description

SMRCOMPN I/O A System Memory RCOMP N:

SMRCOMPP I/O A System Memory RCOMP P:

SMXSLEWIN I

SMXSLEWOUT O

SMYSLEWIN

SMYSLEWOUT O

SMVREF[1:0] I

SMOCDCOMP[1
:0]

Buffer compensation
This signal is powered by the System Memory rail (2.5 V for DDR,

1.8 V for DDR2).

Buffer compensation
This signal is powered by the System Memory rail
X Buffer Slew Rate Input control.

A

X Buffer Slew Rate Output control.

A

I

Y Buffer Slew Rate Input control.

A

Y Buffer Slew Rate Output control.

A

SDRAM Reference Voltage:

A

Reference voltage inputs for each DQ, DQS, & RCVENIN#.
Also used during ODT RCOMP.

I

On-Die DRAM OCD driver compensation

A

OCD compensation

LVDS Signals

Signal Name Type Description

LDVS Channel A

LADATAP[2:0] I/O

LADATAN[2:0] I/O

LACLKP

LACLKN I/O

LBDATAP[2:0] I/O

LBDATAN[2:0] I/O

LBCLKP I/O

LBCLKN I/O

LVDD_EN O

LBKLT_EN O

LBKLT_CRTL O

LIBG I/O

LVREFH

LVREFL I

LVBG O A Reserve. - No connect

Note: LVDS Channel B interface is not supported and do not exist for Intel 915GMS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

HVCMOS

HVCMOS

HVCMOS

Ref

Ref

Ref

Channel A differential data output - positive

Channel A differential data output –negative

I/O

Channel A differential clock output – positive

Channel A differential clock output – negative

LDVS Channel B

Channel B differential data output – positive
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential data output –negative
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential clock output – positive
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential clock output – negative

NOTE: Signals do not exist in Intel 915GMS.

LFP Panel power and backlight control

LVDS panel power enable: Panel power control enable control.
This signal is also called VDD_DBL in the CPIS specification and is
used to control the VDC source to the panel logic.
LVDS backlight enable: Panel backlight enable control.
This signal is also called ENA_BL in the CPIS specification and is
used to gate power into the backlight circuitry.
Panel backlight brightness control: Panel brightness control.
This signal is also called VARY_BL in the CPIS specification and is
used as the PWM Clock input signal.

LVDS Reference signals

LVDS Reference Current. –

1.5 kΩ Pull down resistor needed

I

Reserved. - No connect.

Reserved. - No connect.

85

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.1 Intel 915GM North Bridge(8)

Serial DVO Interface.

Signal Name Type Description

SDVOB_CLKP O

SDVOB_CLKN O

SDVOB_RED O

SDVOB_RED#

SDVOB_GREEN O

SDVOB_GREEN
#
SDVOB_BLUE O

SDVOB_BLUE#

SDVOC_RED O

SDVOC_RED# O

SDVOC_GREEN O

SDVOC_GREEN
#

SDVOC_BLUE O

SDVOC_BLUE# O

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

Serial Digital Video B Clock.
Multiplexed with EXP_TXP_3.
Serial Digital Video B Clock Complement.
Multiplexed with EXP_TXN_3.
Serial Digital Video B Red Data.
Multiplexed with EXP_TXP_0.

O

Serial Digital Video B Red Data Complement.
Multiplexed with EXP_TXN_0.
Serial Digital Video B Green Data.
Multiplexed with EXP_TXP_1.

O

Serial Digital Video B Green Data Complement.
Multiplexed with EXP_TXN_1.
Serial Digital Video B Blue Data.
Multiplexed with EXP_TXP_2.

O

Serial Digital Video B Blue Data Complement.
Multiplexed with EXP_TXN_2.

Serial Digital Video C Red Data / SDVO B Alpha.
Multiplexed with EXP_TXP_4.
NOTE: Signals do not exist in Intel 915GMS
Serial Digital Video C Red Complement / Alpha Complement.
Multiplexed with EXP_TXN_4.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Green.
Multiplexed with EXP_TXP_5.
NOTE: Signals do not exist in Intel 915GMS.

O

Serial Digital Video C Green Complement.
Multiplexed with EXP_TXN_5.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video Channel C Blue.
Multiplexed with EXP_TXP_6.

NOT

E: Signals do not exist in Intel 915GMS.
Serial Digital Video C Blue Complement.
Multiplexed with EXP_TXN_6.
NOTE: Signals do not exist in Intel 915GMS.

SDVO B Interface

SDVO C Interfac e

Serial DVO Interface (Continued)

Signal Name Type Description

SDVO C Interface

SDVOC_CLKP O

SDVOC_CLKN O

SDVO_TVCLKI
N
SDVO_TVCLKI
N#
SDVO_FLDSTA
LL
SDVO_FLDSTA
LL#
SDVOB_INT I

SDVOB_INT# I

..

SDVOC_INT I

SDVOC_INT# I

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

PCIE

Serial Digital Video C Clock.
Multiplexed with EXP_TXP_7.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Clock Complement.
Multiplexed with EXP_TXN_7.

NOT

E: Signals do not exist in Intel 915GMS.

SDVO Common Signals

I

Serial Digital Video TVOUT Synchronization Clock.
Multiplexed with EXP_RXP_0.

I

Serial Digital Video TV-out Synchronization Clock Complement.
Multiplexed with EXP_RXN_0.

I

Serial Digital Video Field Stall.
Multiplexed with EXP_RXP_2.

I

Serial Digital Video Field Stall Complement.
Multiplexed with EXP_RXN_2.
Serial Digital Video Input Interrupt.
Multiplexed with EXP_RXP_1.
Serial Digital Video Input Interrupt Complement.
Multiplexed with EXP_RXN_1.
Serial Digital Video Input Interrupt.
Multiplexed with EXP_RXP_5.
Serial Digital Video Input Interrupt Complement.
Multiplexed with EXP_RXN_5.

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5.1 Intel 915GM North Bridge(9)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

Reset and Miscellaneous Signals

Signal Name Type Description

RSTIN# I

PWROK I

H_BSEL [2:0]
(CFG[2:0])

CFG[17:3] I

CFG[20:18]

BM_BUSY# O

THRMTRIP# O

EXT_TS[1:0]# I

HVCMOS

HVCMOS

HVCMOS

AGTL+

HVCMOS

HVCMOS

COD

HVCMOS

Reset In:
When asserted this signal will asynchronously reset the GMCH logic.
This signal is connected to the PLT_RST# output of the ICH6-M.
This input has a Schmitt trigger to avoid spurious resets. This input
buffer is 3.3-V tolerant.
Power OK:
When asserted, PWROK is an indication to the GMCH that core
power has been stable for at least 10 µs.
This input buffer is 3.3-V tolerant.

I

Host Bus Speed Select:

At the deassertion of RSTIN#, the value sampled on these pins
determines the expected frequency of the bus.
External pull-ups are required.

HW straps:

CFG [17:3] has internal pull up.
NOTE: Not all CFG Balls are supported for Intel 915GMS.

I

HW straps:

CFG [20:18] has internal pull down

NOTE: Not all CFG Balls are supported for Intel 915GMS.
GMCH Integrated Graphics Busy:

Indicates to the ICH that the integrated graphics engine within the
MCH is busy and transitions to low power states should not be
attempted until that is no longer the case.
GMCH Thermal Trip:
Assertion of THERMTRIP# (Thermal Trip) indicates the GMCH
junction temperature has reached a level beyond which damage may
occur. Upon assertion of THERMTRIP#, the GMCH will shut off its
internal clocks (thus halting program execution) in an attempt to
reduce the GMCH core junction temperature. To protect GMCH, its
core voltage (Vcc) must be removed following the assertion of
THERMTRIP#. Once activated, THERMTRIP# remains latched
until RSTIN# is asserted. While the assertion of the RSTIN# signal
will deassert THERMTRIP#, if the GMCH’s junction temperature
remains at or above the trip level, THERMTRIP# will again be
asserted.
External Thermal Sensor Input:
If the system temperature reaches a dangerously high value then this
signal can be used to trigger the start of system memory throttling.
NOTE: EXT_TS1# functionality is not supported in 915GMS. A pull
up is required on this pin

PLL Signals

Signal Name Type Description

HCLKP I

HCLKN I

GCLKP I

GCLKN

DREF_CLKP I

DREF_CLKN I

DREF_SSCLKP I

DREF_SSCLKN I

Note: PLL interfaces signal group are supported the Mobile Intel 915GM/PM/GMS and Intel

910GML Express chipsets, unless otherwise noted.

Diff Clk

Diff Clk

Diff Clk

Diff Clk

Diff Clk

Diff Clk

Diff Clk

Diff Clk

Differential Host Clock In:
Differential clock input for the Host PLL. Used for phase cancellation
for FSB transactions. This clock is used by all of the GMCH logic
that is in the Host clock domain. Also used to generate core and
system memory internal clocks. This is a low voltage differential
signal and runs at ¼ the FSB data rate.

Differential Host Clock Input Complement:

Differential PCI Express based Graphics / DMI Clock In:

These pins receive a differential 100 MHz Serial Reference clock
from the external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.

I

Differential PCI Express based Graphics / DMI Clock In
complement
Display PLLA Differential Clock In –

Display PLL Differential Clock In, no SSC support –
Display PLLA Differential Clock In Complement –
Display PLL Differential Clock In Complement - no SSC support
Display PLLB Differential Clock In –
Optional Display PLL Differential Clock In for SSC support –
NOTE: Differential Clock input for optional SSC support for LVDS
display.
Display PLLB Differential Clock In complement –
Optional Display PLL Differential Clock In Complement for SSC
support

NOT

E: Differential Clock input for optional SSC support for LVDS

display.

87

TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.1 Intel 915GM North Bridge(10)

Power and Ground

Interface Ball Name Description

Host VTT (VCCP) FSB power supply (1.05 V) - (VCCP)
DRAM

PCI Express
Based
Graphics /DMI

PLL Analog

High Voltage
Interfaces
CRT DAC

LVDS

VCCA_SM VCCASM is the Analog power supply for SM data buffers used for

VCCSM System memory power supply (DDR=2.5 V; DDR2=1.8 V)

VCC3G PCI Express / DMI Analog power supply (1.5 V)

VCCA_3GBG PCI Express / DMI band gap power supply (2.5 V)

VSSA_3GBG PCI Express / DMI band gap ground
VCCA_HPLL Power supply for the Host VCO in the host/mem/core PLL (1.5 V)
VCCA_MPLL Power supply for the mem VCO in the host/mem/core PLL (1.5 V)

VCCD_HMPLL Power Supply for the digital dividers in the HMPLL (1.5 V)

VCCA_3GPLL Power supply for the 3GIO PLL (1.5 V)

VCCA_DPLLA Display A PLL power supply (1.5 V)

VCCA_DPLLB Display B PLL power supply (1.5 V)

VCCHV Power supply for the HV buffers (2.5 V)

VCCA_CRTD

AC

VSSA_CRTD

AC

VCC_SYNC Power supply for HSYNC/ VSYNC (2.5 V)
VCCD_LVDS Digital power supply (1.5 V)
VCCTX_LVDS Data/Clk Tx power supply (2.5 V)

VCCA_LVDS LVDS analog power supply (2.5 V)

VSSALVDS LVDS analog VSS

DLL & other logic (1.5 V)

Analog power supply for the DAC (2.5 V)

Analog ground for the DAC

Power and Ground (Continued)

Interface Ball Name Description

TVDAC

Core
Ground VSS Ground
NCTF

VCCA_TVBG TV DAC Band Gap Power (3.3 V)

VSSA_TVBG TV DAC Band Gap VSS

VCCD_TVDAC Dedicated Power Supply for TVDAC (1.5 V)

VCCDQ_TVD

AC

VCCA_TVDA

CA

VCCA_TVDA

CB

VCCA_TVDA

CC

VCC Core VCC – (1.05 V or 1.5 V)

Non-Critical To Function power signals:

“NCTF” (Non-Critical To Function) have been designed into the package footprint
to enhance the Solder Joint Reliability of our products by absorbing some of the
stress introduced by the Characteristic Thermal Expansion (CTE) mismatch of the
Die to package interface. It is expected that in some cases, these balls may crack
partially or completely, however, this will have no impact to our product
performance or reliability. Intel has added these balls primarily to serve as sacrificial
stress absorbers.
NOTE: Signals do not exist in Intel 915GMS.

VTT_NCTF NCTF FSB power supply (1.05 V or 1.2 V)

VCC_NCTF NTCF Core VCC – (1.05 V or 1.5 V)

VCCSM_NCTF NTCF System memory power supply (DDR=2.5 V; DDR2=1.8 V)

VSS_NCTF NTCF Ground

Power Supply for Digital Quiet TVDAC (1.5 V)

Power Supply for TV Out Channel A (3.3 V)

Power Supply for TV Out Channel B (3.3 V)

Power Supply for TV Out Channel C (3.3 V)

88

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PCI Interface Signals

Name Type Description

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus.

During the first clock of a transaction, AD[31:0] contain a physical
address (32 bits). During subsequent clocks, AD[31:0] contain data.
The Intel® ICH6 will drive all 0s on AD[31:0] during the address
phase of all PCI Special Cycles.

I/O Bus Command and Byte Enables: The command and byte enable

signals are multiplexed on the same PCI pins. During the address
phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase
C/BE[3:0]# define the Byte Enables.

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge
0001b Special Cycle
0010b I/O Read
0011b I/O Write
0110b Memory Read
0111b Memory Write
1010b Configuration Read
1011b Configuration Write
1100b Memory Read Multiple
1110b Memory Read Line
1111b Memory Write and Invalidate
All command encodings not shown are reserved. The ICH6 does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.

I/O Device Select: The ICH6 asserts DEVSEL# to claim a PCI

transaction. As an output, the ICH6 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH6 address or an
address destined DMI (main memory or graphics). As an input,
DEVSEL# indicates the response to an ICH6-initiated transaction on
the PCI bus. DEVSEL# is tri-stated from the leading edge of
PLTRST#. DEVSEL# remains tri-stated by the ICH6 until driven by
a target device.

I/O Cycle Frame: The current initiator drives FRAME# to indicate the

beginning and duration of a PCI transaction. While the initiator
asserts FRAME#, data transfers continue. When the initiator negates
FRAME#, the transaction is in the final data phase. FRAME# is an
input to the ICH6 when the ICH6 is the target, and FRAME# is an
output from the ICH6 when the ICH6 is the initiator. FRAME#
remains tri-stated by the ICH6 until driven by an initiator.

PCI Interface Signals (Continued)

Name Type Description

IRDY#

TRDY#

STOP#

PAR

I/O Initiator Ready: IRDY# indicates the ICH6's ability, as an initiator,

to complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock
both IRDY# and TRDY# are sampled asserted. During a write,
IRDY# indicates the ICH6 has valid data present on AD[31:0].
During a read, it indicates the ICH6 is prepared to latch data. IRDY#
is an input to the ICH6 when the ICH6 is the target and an output
from the ICH6 when the ICH6 is an initiator. IRDY# remains
tri-stated by the ICH6 until driven by an initiator.

I/O Target Ready: TRDY# indicates the ICH6's ability as a target to

complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH6, as a target, has placed
valid data on AD[31:0]. During a write, TRDY# indicates the ICH6,
as a target is prepared to latch data. TRDY# is an input to the ICH6
when the ICH6 is the initiator and an output from the ICH6 when the
ICH6 is a target. TRDY# is tri-stated from the leading edge of
PLTRST#. TRDY# remains tri-stated by the ICH6 until driven by a
target.

I/O Stop: STOP# indicates that the ICH6, as a target, is requesting the

initiator to stop the current transaction. STOP# causes the ICH6, as an
initiator, to stop the current transaction. STOP# is an output when the
ICH6 is a target and an input when the ICH6 is an initiator.

I/O Cal cula ted/Checked Parity: PAR uses “even” parity calculated on

36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
ICH6 counts the number of one within the 36 bits plus PAR and the
sum is always even. The ICH6 always calculates PAR on 36 bits
regardless of the valid byte enables. The ICH6 generates PAR for
address and data phases and only guarantees PAR to be valid one PCI
clock after the corresponding address or data phase. The ICH6 drives
and tri-states PAR identically to the AD[31:0] lines except that the
ICH6 delays PAR by exactly one PCI clock. PAR is an output during
the address phase (delayed one clock) for all ICH6 initiated
transactions. PAR is an output during the data phase (delayed one
clock) when the ICH6 is the initiator of a PCI write transaction, and
when it is the target of a read transaction. ICH6 checks parity when it
is the target of a PCI write transaction. If a parity error is detected, the
ICH6 will set the appropriate internal status bits, and has the option to
generate an NMI# or SMI#.

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5.2 Intel ICH6-M South Bridge(2)

PCI Interface Signals (Continued)

Name Type Description

PERR#

REQ[0:3]#
REQ[4]# / GPI[40]
REQ[5]# / GPI[1]
REQ[6]# / GPI[0]
GNT[0:3]#
GNT[4]# /

GPO[48]

GNT[5]# /

GPO[17]#

GNT[6]# /
GPO[16]#

PCICLK

PCIRST#

PLOCK#

SERR#

PME#

I/O Parity Error: An external PCI device drives PERR# when it receives

data that has a parity error. The ICH6 drives PERR# when it detects a
parity error. The ICH6 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via the
PERR# signal).

I PCI Requests: The ICH6 supports up to 7 masters on the PCI bus.

The REQ[4]#, REQ[5]#, and REQ[6]# pins can instead be used as a
GPI.

O PCI Grants: The ICH6 supports up to 7 masters on the PCI bus. The

GNT[4]# pin can instead be used as a GPO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT[5]#/GPO[17] and GNT[6]#/GPO[17] both have an internal
pull-up.
NOTE: GNT[6] is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak,
integrated pull-up resistor on the GNT[6] pin.

I PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all

transactions on the PCI Bus.

O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical

OR of the primary interface PLTRST# signal and the state of the
Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh,
bit 6).

NOTE: PCIRST# is in the VccSus3_3 well.
PCI Loc

I/O

require multiple transactions to complete. ICH6 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus.

OD I/O System Error: SERR# can be pulsed active by any PCI device that

detects a system error condition. Upon sampling SERR# active, the
ICH6 has the ability to generate an NMI, SMI#, or interrupt.

OD I PCI Power Management Event: PCI peripherals drive PME# to

wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some cases
the ICH6 may drive PME# active due to an internal wake event. The
ICH6 will not drive PME# high, but it will be pulled up to VccSus3_3
by an internal pull-up resistor.

k: This signal indicates an exclusive bus operation and may

Serial ATA Interface Signals

Name Type Description

SATA[0]TXP
SATA[0]TXN
SATA[0]RXP
SATA[0]RXN
SATA[1]TXP
SATA[1]TXN
SATA[1]RXP
SATA[1]RXN
SATA[2]TXP
SATA[2]TXN
SATA[2]RXP
SATA[2]RXN
SATA[3]TXP
SATA[3]TXN
SATA[3]RXP
SATA[3]RXN
SATARBIAS

SATARBIAS#

SATA[0]GP /
GPI[26]

SATA[1]GP /
GPI[29]

SATA[2]GP /
GPI[30]

O Serial ATA 0 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 0.

I Serial ATA 0 Differential Receive Pair: These are inbound

high-speed differential signals from Port 0.

O Serial ATA 1 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 1.

I Serial ATA 1 Differential Receive Pair: These are inbound

high-speed differential signals from Port 1.

O Serial ATA 2 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 2.

I Serial ATA 2 Differential Receive Pair: These are inbound

high-speed differential signals from Port 2.

O Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3.

I Serial ATA 3 Differential Receive Pair: These are inbound

high-speed differential signals from Port 3.

Serial ATA Resistor Bias:

O

external resistor to ground.

I Serial ATA Resistor Bias Complement: These are analog

connection points for an external resistor to ground.

I Serial ATA 0 General Purpose: This is an input pin which can be

configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal should
be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to
indicate that the switch is open.
If interlock switches are not required, this pin can be configured as
GPI[26].
NOTE: All SATAxGP pins must be configured with the same
function: as either SATAxGP pins or GPI pins.

I Serial ATA 1 General Purpose: Same function as SATA[0]GP,

except for SATA Port 1.
If interlock switches are not required, this pin can be configured as
GPI[29].

I Serial ATA 2 General Purpose: Same function as SATA[0]GP,

except for SATA Port 2.
If interlock switches are not required, this pin can be configured as
GPI[30].

These are analog connection points for an

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Serial ATA Interface Signals (Continued)

Name Type Description

SATA[3]GP /
GPI[31]

SATALED#

I Serial ATA 3 General Purpose: Same function as SATA[0]GP,

except for SATA Port 3.
If interlock switches are not required, this pin can be configured as
GPI[31].

OC O

Serial ATA LED:

SATA command activity. It is to be connected to external circuitry
that can provide the current to drive a platform LED. When active,
the LED is on. When tri-stated, the LED is off. An external pull-up
resistor to Vcc3_3 is required.
NOTE: An internal pull-up is enabled only during PLTRST#
assertion.

This is an open-collector output pin driven during

Interrupt Signals

Name Type Description

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]# /

GPI[5:2]

IDEIRQ

I/O Serial Interrupt Request: This pin implements the serial interrupt

protocol.

OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described
in the Interrupt Steering section. Each PIRQx# line has a separate
Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.

OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can

be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described
in the Interrupt Steering section. Each PIRQx# line has a separate
Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPI.

I IDE Interrupt Request: This interrupt input is connected to the IDE

drive.

LAN Connect Interface Signals

Name Type Description

LAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

I LAN I/F Clock: This signal is driven by the LAN Connect

component. The frequency range is 5 MHz to 50 MHz.

I Received Data: The LAN Connect component uses these signals to

transfer data and control information to the integrated LAN
controller. These signals have integrated weak pull-up resistors.

O Transmit Data: The integrated LAN controller uses these signals to

transfer data and control information to the LAN Connect component.

O LAN Reset/Sync: The LAN Connect component’s Reset and Sync

signals are multiplexed onto this pin.

Other Clocks

Name Type Description

CLK14

CLK48

SATA_CLKP
SATA_CLKN

DMI_CLKP,
DMI_CLKN

I Oscillator Clock: This clock is used for 8254 timers. It runs at

14.31818 MHz. This clock is permitted to stop during S3 (or lower)
states.

I 48 MHz Clock: This clock is used to run the USB controller. IT runs

at 48.000 MHz.
This clock is permitted to stop during S3 (or lower) states.

I 100 MHz Differential Clock: These signals are used to run the

SATA controller. Runs at 100 MHz. This clock is permitted to stop
during S3 (or lower) states.

I 100 MHz Differential Clock: These signals are used to run the

Direct Media Interface. Runs at 100 MHz.

LPC Interface Signals

Name Type Description

LAD[3:0]

FWH[3:0]
LFRAME# /
FWH[4]

LDRQ[0]#
LDRQ[1]# /

GPI[41]

/

LPC Multiplexed Command, Address, Data:

I/O

internal pull-ups are provided.

O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an

abort.

I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to

request DMA or bus master access. These signals are typically
connected to external Super I/O device. An internal pull-up resistor is
provided on these signals.
LDRQ[1]# may optionally be used as GPI.

For LAD[3:0],

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5.2 Intel ICH6-M South Bridge(4)

IDE Interface Signals

Name Type Description

DCS1#

DCS3#

DA[2:0]

DD[15:0]

DDREQ

DDACK#

DIOR# / (DWSTB

/ RDMARDY#)

O IDE Device Chip Selects for 100 Range: For ATA command

register block. This output signal is connected to the corresponding
signal on the IDE connector.

O IDE Device Chip Select for 300 Range: For ATA control register

block. This output signal is connected to the corresponding signal on
the IDE connector.

O IDE Device Address: These output signals are connected to the

corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is
being addressed.

IDE Device Data:

I/O

signals on the IDE connector. There is a weak internal pull-down
resistor on DD7.

I IDE Device DMA Request: This input signal is directly driven from

the DRQ signal on the IDE connector. It is asserted by the IDE device
to request a data transfer, and used in conjunction with the PCI bus
master IDE function and are not associated with any AT compatible
DMA channel. There is a weak internal pull-down resistor on this
signal.

O IDE Device DMA Acknowledge: This signal directly drives the

DAK# signal on the IDE connector. DDACK# is asserted by the Intel
ICH6 to indicate to IDE DMA slave devices that a given data transfer
cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.
This signal is used in conjunction with the PCI bus master IDE
function and are not associated with any AT-compatible DMA
channel.

O

DIOR# /
Disk I/O Re a d (PIO and No n -Ultra DM A ): This is the command to

the IDE device that it may drive data onto the DD lines. Data is
latched by the ICH6 on the de-assertion edge of DIOR#. The IDE
device is selected either by the ATA register file
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA
acknowledge (DDAK#)
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write
strobe for writes to disk. When writing to disk, ICH6 drives valid data
on rising and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA
ready for reads from disk. When reading from disk, ICH6 de-asserts
RDMARDY# to pause burst data transfers.

These signals directly drive the corresponding

IDE Interface Signals (Continued)

Name Type Description

DIOW# / (DSTOP) O Disk I/O Write (PIO and Non-Ultra DMA): This is the command to

IORDY / (DRSTB

/ WDMARDY#)

the IDE device that it may latch data from the DD lines. Data is
latched by the IDE device on the de-assertion edge of DIOW#. The
IDE device is selected either by the ATA register file chip selects
(DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge
(DDAK#).
Disk Stop (Ultra DMA): ICH6 asserts this signal to terminate a burst.

I I/O Channel Ready (PIO): This signal will keep the strobe active

(DIOR# on reads, DIOW# on writes) longer than the minimum width.
It adds wait-states to PIO transfers.
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
disk, ICH6 latches data on rising and falling edges of this signal from
the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
disk, this is de-asserted by the disk to pause burst data transfers.

System Management Interface Signals

Name Type Description

INTRUDER#

SMLINK[1:0]

LINKALERT#

I Intruder Detect: This signal can be set to disable system if box

detected open.
This signal’s status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.

OD I/O System Management Link: SMBus link to optional external system

management ASIC or LAN controller. External pull-ups are required.
Note that SMLINK0 corresponds to an SMBus Clock signal, and
SMLINK1 corresponds to an SMBus Data signal.

OD I/O SMLink Alert: Output of the integrated LAN and input to either the

integrated ASF or an external management controller in order for the
LAN’s SMLINK slave to be serviced.

SM Bus Interface Signals

Name Type Description

SMBDATA
SMBCLK
SMBALERT#/

GPI[11]

OD I/O SMBus Data: External pull-up resistor is required.
OD I/O SMBus Clock: External pull-up resistor is required.

I SMBus Alert: This signal is used to wake the system or generate

SMI#. If not used for SMBALERT#, it can be used as a GPI.

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USB Interface Signals

Name Type Description

USBP[0]P,
USBP[0]N,
USBP[1]P,
USBP[1]N

USBP[2]P,
USBP[2]N,
USBP[3]P,
USBP[3]N

USBP[4]P,
USBP[4]N,
USBP[5]P,
USBP[5]N

USBP[6]P,
USBP[6]N,
USBP[7]P,
USBP[7]N

OC[3:0]#
OC[4]# / GPI[9]
OC[5]# / GPI[10]
OC[6]# / GPI[14]
OC[7]# / GPI[15]
USBRBIAS

USBRBIAS#

I/O Universal Serial Bus Port [1:0] Differential: These differential pairs

are used to transmit Data/Address/Command signals for ports 0 and 1.
These ports can be routed to UHCI controller #1 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K

impedance of 45

I/O Universal Serial Bus Port [3:2] Differential: These differential pairs

are used to transmit data/address/command signals for ports 2 and 3.
These ports can be routed to UHCI controller #2 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K

impedance of 45

Universal Serial Bus Port [5:4] Differentia

I/O

are used to transmit Data/Address/Command signals for ports 4 and 5.
These ports can be routed to UHCI controller #3 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K

impedance of 45

I/O Universal Serial Bus Port [7:6] Differential: These differential pairs

are used to transmit Data/Address/Command signals for ports 6 and 7.
These ports can be routed to UHCI controller #4 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 K

impedance of 45

I Overcurrent Indicators: These signals set corresponding bits in the

USB controllers to indicate that an overcurrent condition has
occurred.
OC[7:4]# may optionally be used as GPIs.
NOTE: OC[7:0]# are not 5 V tolerant.

O USB Resistor Bias: Analog connection point for an external resistor.

Used to set transmit currents and internal load resistors.

I USB Resistor Bias Complement: Analog connection point for an

external resistor. Used to set transmit currents and internal load
resistors.

Ω?pull-downs and provides an output driver

Ωwhich requires no external series resistor

Ω?pull-downs and provides an output driver

Ωwhich requires no external series resistor

l: These differential pairs

Ω?pull-downs and provides an output driver

which requires no external series resistor

Ω

?pull-downs and provides an output driver

Ω

which requires no external series resistor

Ω

EEPROM Interface Signals

Name Type Description

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

O EEPROM Shift Clock: This signal is the serial shift clock output to

the EEPROM.

I EEPROM Data In: This signal transfers data from the EEPROM to

the Intel ® ICH6. This signal has an integrated pull-up resistor.

O EEPROM Data Out: This signal transfers data from the ICH6 to the

EEPROM.

O EEPROM Chip Select: This is the chip select signal to the

EEPROM.

Miscellane ous Signals

Name Type Description

INTVRMEN

SPKR

RTCRST#

TP[0]

TP[1]
TP[2]
TP[3]
TP[4]

I Internal Voltage Regulator Enable: This signal enables the internal

1.5 V Suspend regulator when connected to VccRTC. When
connected to Vss, the internal regulator is disabled

O Speaker: The SPKR signal is the output of counter 2 and is internally

“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device that in turn drives the
system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on SPKR pin.

I RTC Reset: When asserted, this signal resets register bits in the RTC

well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other
RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST# pin.

I Test Point 0: This signal must have an external pull-up to

VccSus3_3.

O Test Point 1: Route signal to a test point.
O Test Point 2: Route signal to a test point.

I Test Point 3: Route signal to a test point.

O Test Point 4: Route signal to a test point.

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5.2 Intel ICH6-M South Bridge(6)

Power Management Interface Signals

Name Type Description

PWRBTN#

RI#

SYS_RESET#

RSMRST#

LAN_RST#

WAKE#

MCH_SYNC#

SUS_STAT# /
LPCPD#

SUSCLK

VRMPWRGD

I Power Button: The Power Button will cause SMI# or SCI to indicate

a system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is
pressed for more than 4 seconds, this will cause an unconditional
transition (power button override) to the S5 state. Override will occur
even if the system is in the S1-S4 states. This signal has an internal
pull-up resistor and has an internal 16 ms de-bounce on the input.

I Ring Indicate: This signal is an input from a modem. It can be

enabled as a wake event, and this is preserved across power failures.

I System Reset: This pin forces an internal reset after being debounced.

The ICH6 will reset immediately if the SMBus is idle; otherwise, it
will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a
reset on the system.

I Resume Well Reset: This signal is used for resetting the resume

power plane logic.

I LAN Reset: When asserted, the internal LAN controller will be put

into reset. This signal must be asserted for at least 10 ms after the
resume well power (VccSus3_3 and VccSus1_5) is valid. When
de-asserted, this signal is an indication that the resume well power is
stable.
NOTE: LAN_RST# must de-assert at some point to complete ICH6
power up sequencing.

I PCI Express* Wake Event: Sideband wake signal on PCI Express

asserted by components requesting wakeup.

I MCH SYNC: This input is internally ANDed with the PWROK

input.
Connected to the ICH_SYNC# output of (G)MCH.

O Suspend Status: This signal is asserted by the ICH6 to indicate that

the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC I/F.

Suspend Clock:

O

to use by other chips for refresh clock.

I VRM Power Good: This should be connected to be the processor’s

VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input.

This clock is an output of the RTC generator circuit

Power Management Interface Signals (Continued)

Name Type Description

PLTRST#

THRM#

THRMTRIP#

SLP_S3#

SLP_S4#

SLP_S5#

PWROK

O Platform Reset: The ICH6 asserts PLTRST# to reset devices on the

platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The
ICH6 asserts PLTRST# during power-up and when S/W initiates a
hard reset sequence through the Reset Control register (I/O Register
CF9h). The ICH6 drives PLTRST# inactive a minimum of 1 ms after
both PWROK and VRMPWRGD are driven high. The ICH6 drives
PLTRST# active a minimum of 1 ms when initiated through the Reset
Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.

I Thermal Alarm: This is an active low signal generated by external

hardware to generate an SMI# or SCI.

I Thermal Trip: When low, this signal indicates that a thermal trip

from the processor occurred, and the ICH6 will immediately
transition to a S5 state. The ICH6 will not wait for the processor stop
grant cycle since the processor has overheated.

O S3 Sleep Control: SLP_S3# is for power plane control. This signal

shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

O S4 Sleep Control: SLP_S4# is for power plane control. This signal

shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.

NOTE:

This pin must be used to control the DRAM power in order

to use the ICH6’s DRAM power-cycling feature. Refer to Chapter

5.14.10.2 for details.

O S5 Sleep Control: SLP_S5# is for

used to shut power off to all non-critical systems when in the S5 (Soft
Off) states.

I Power OK: When asserted, PWROK is an indication to the ICH6

that core power has been stable for at least 99 ms and PCICLK has
been stable for at least 1 mS. An exception to this rule is if the system
is in S3 HOT , in which PWROK may or may notstay asserted even
though PCICLK may be inactive. PWROK can be driven
asynchronously. When PWROK is negated, the ICH6 asserts
PLTRST#.
NOTE: PWROK must de-assert for a minimum of three RTC clock
periods in order for the ICH6 to fully reset the power and properly
generate the PLTRST# output

ower plane control. This signal is

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Processor Interface Signals

Name Type Description

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

INIT3_3V#

INTR

O Mask A20: A20M# will go active based on either setting the

appropriate bit in the Port 92h register, or based on the A20GATE
input being active.

O Processor Sleep: This signal puts the processor into a state that saves

substantial power compared to Stop-Grant state. However, during that
time, no snoops occur.
The Intel® ICH6 can optionally assert the CPUSLP# signal when
going to the S1 state, and will always assert it when going to C3 or
C4.

I Numeric Coprocessor Error: This signal is tied to the coprocessor

error signal on the processor. FERR# is only used if the ICH6
coprocessor error reporting function is enabled in the OIC.CEN
register (Chipset ConfigurationRegisters:Offset 31FFh: bit 1). If
FERR# is asserted, the ICH6 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the OIC register bit setting.

O Ignore Numeric Error: This signal is connected to the ignore error

pin on the processor. IGNNE# is only used if the ICH6 coprocessor
error reporting function is enabled in the OIC.CEN register (Chipset
Configuration Registers:Offset 31FFh: bit 1). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
register (I/O register F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not
asserted when the Coprocessor Error register is written, the IGNNE#
signal is not asserted.

O Initialization: INIT# is asserted by the ICH6 for 16 PCI clocks to

reset the processor.
ICH6 can be configured to support processor Built In Self Test
(BIST).

Initialization 3.3 V:

O

intended for Firmware Hub.

O Processor Interrupt: INTR is asserted by the ICH6 to signal the

processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.

This is the identical 3.3 V copy of INIT#

Processor Interface Signals (Continued)

Name Type Description

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD /

GPO[49]

O Non-Maskable Interrupt: NMI is used to force a non-Maskable

interrupt to the processor. The ICH6 can generate an NMI when
either SERR# is asserted or IOCHK# goes active via the SERIRQ#
stream. The processor detects an NMI when it detects a rising edge on
NMI. NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control register (I/O
Register 61h).

O System Management Interrupt: SMI# is an active low output

synchronous to PCICLK. It is asserted by the ICH6 in response to one
of many enabled hardware or software events.

O Stop Clock Request: STPCLK# is an active low output synchronous

to PCICLK. It is asserted by the ICH6 in response to one of many
hardware or software events.
When the processor samples STPCLK# asserted, it responds by
stopping its internal clock.

I Keyboard Controller Reset CPU: The keyboard controller can

generate INIT# to the processor. This saves the external OR gate with
the ICH6’s other sources of INIT#. When the ICH6 detects the
assertion of this signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH6 will ignore RCIN# assertion during transitions to
the S1, S3, S4, and S5 states.

I A20 Gate: A20GATE is from the keyboard controller. The signal

acts as an alternative method to force the A20M# signal active. It
saves the external OR gate needed with various other chipsets.

OD O Processor Power Good: This signal should be connected to the

processor’s PWRGOOD input to indicate when the processor power
is valid. This is an open- drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH6’s PWROK and
VRMPWRGD signals.
This signal may optionally be configured as a GPO.

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5.2 Intel ICH6-M South Bridge(8)

General Purpose I/O Signals 1,2

Name Type Tolerance Power Well Description

GPO[49]

GPO[48]

GPIO[47:42]
GPI[41]

GPI[40]

GPIO[39:35]
GPIO[34:33]

GPIO[32]
GPI[31]

GPI[30]

GPI[29]

GPIO[28:27]

GPI[26]

GPIO[25]

GPIO[24]

GPO[23]
GPIO[22]
GPO[21]

GPO[20]
GPO[19]

OD O V_CPU_I

O 3.3 V Core This signal is fixed as output only and can

N/A N/A N/A This signal is not implemented.

I 3.3 V Core This signal is fixed as input only and can be used

I 5 V Core This signal is fixed as input only and can be used

N/A N/A N/A This signal is not implemented.

I/O 3.3 V Core This signal can be input or output and is

I/O 3.3 V Core This signal can be input or output.

I 3.3 V Core This signal is fixed as input only and can instead

I 3.3 V Core This signal is fixed as input only and can instead

I 3.3 V Core This signal is fixed as input only and can instead

I/O 3.3 V Resume This signal can be input or output and is

I 3.3 V Core This signal is fixed as input only and can instead

I/O 3.3 V Resume This signal can be input or output and is

I/O 3.3 V Resume This signal can be input or output and is

O 3.3 V Core This signal is fixed as output only.

N/A N/A N/A This signal is not Implemented

O 3.3 V Core This signal is fixed as output only and is

O 3.3 V Core This signal is fixed as output only.
O 3.3 V Core This signal is fixed as output only.

`Core This signal is fixed as output only and can

instead be used as CPUPWRGD.

instead be used as GNT4#.

instead as LDRQ1#.

instead as REQ4#.

unmultiplexed

be used for SATA[3]GP.

be used for SATA[2]GP.

be used for SATA[1]GP.

unmultiplexed.

be used for SATA[0]GP.

unmultiplexed. It is a strap for internal Vcc2_5
regulator. See Section 2.22.1.

unmultiplexed.

unmultiplexed

NOTE: GPO[19] may be programmed to blink
(controllable by GPO_BLINK (D31:F0:Offset
GPIOBASE+18h:bit 19)).

General Purpose I/O Signals 1,2 (Continued)

Name Type Tolerance Power Well Description

GPO[18]

GPO[17]

GPO[16]

GPI[15:14]3

GPI[13]3

GPI[12]3

GPI[11]3

GPI[10:9]3

GPI[8]3

GPI[7]3

GPI[6]3
GPI[5:2]3

GPI[1:0]3

NOTES:

1.All inputs are sticky. The status bit remains set as long as the input was asserted for two
clocks.GPIs are sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.

2.Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some ICH6 GPIOs may be connected to
pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a
loss of core power (PWROK low) or a Power Button Override event will result in the Intel
ICH6 driving a pin to a logic 1 to another device that is powered down.

3.GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either
an SMI# or an SCI, but not both.

O 3.3 V Core This signal is fixed as output only.

NOTE: GPO[18] will blink by default
immediately after reset (controllable by
GPO_BLINK (D31:F0:Offset
GPIOBASE+18h:bit 18)).

O 3.3 V Core This signal is fixed as output only and can be

used instead as PCI GNT[5]#.

O 3.3 V Core This signal is fixed as output only and can be

used instead as PCI GNT[6]#.

I 3.3 V Resume This signal is fixed as input only and can be used

instead as OC[7:6]#

I 3.3 V Resume This signal is fixed as input only and is

unmultiplexed.

I 3.3 V Core This signal is fixed as input only and is

unmultiplexed.

I 3.3 V Resume This signal is fixed as input only and can be used

instead as SMBALERT#.

I 3.3 V Resume This signal is fixed as input only and can be used

instead as OC[5:4]#.

I 3.3 V Resume This signal is fixed as input only and is

unmultiplexed.

I 3.3 V Core This signal is fixed as input only and is

unmultiplexed.

I 3.3 V Core This signal is fixed as input only.
I 5 V Core This signal is fixed as input only and can be used

instead as PIRQ[H:E]#.

I 5 V Core This signal is fixed as input only and can be used

instead as PCI REQ[6:5]#.

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5.2 Intel ICH6-M South Bridge(9)

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

AC ’97/Intel ® High Definition Audio Link Signals

Name Type Description

ACZ_RST#

ACZ_SYNC

ACZ_BIT_CLK

ACZ_SDOUT

ACZ_SDIN[2:0]

NOTES:

1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for
details.

2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This
bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0
AC ’97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit
defaults to 0 (AC ‘97 mode).

O AC ’97/Intel ® High Definition Audio Reset: Master hardware reset

to external codec(s).

O AC ’97/Intel High Definition Audio Sync: 48 kHz fixed rate sample

sync to the codec(s). Also used to encode the stream number.

I/O AC ’97 Bit Clock Input: 12.288 MHz serial data clock generated by

the external codec(s). This signal has an integrated pull-down resistor
(see Note below).
Intel High Definition Audio Bit Clock Output: 24.000 MHz serial
data clock generated by the Intel® High Definition Audio controller
(the Intel ICH6). Thissignal has an integrated pull-down resistor so
that ACZ_BIT_CLK does not float when an
Intel High Definition Audio codec (or no codec) is connected but the
signals are temporarily configured as AC ’97.

O AC ’97/Intel High Definition Audio Serial Data Out: Serial TDM

data output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on the ACZ_SDOUT pin.

I AC ’97/Intel High Definition Audio Serial Data In [2:0]: Serial

TDM data inputs from the three codecs. The serial input is
single-pumped for a bit rate of 24 Mb/s for Intel High Definition
Audio. These signals have integrated pull-down resistors, which are
always enabled.

Firmware Hub Interface Signals

Name Type Description

FWH[3:0] /

LAD[3:0]

FWH[4]

LFRAME#

/

I/O Firmware Hub Signals. These signals are multiplexed with the LPC

address signals.

Firmware Hub Signals.

O

LFRAME# signal.

This signal is multiplexed with the LPC

Power and Ground Signals

Name Description

Vcc3_3

Vcc1_5_A

Vcc1_5_B

Vcc2_5

V5REF

VccSus3_3

VccSus1_5

V5REF_Sus

VccRTC

VccUSBPLL

VccDMIPLL

VccSATAPLL

V_CPU_IO

Vss

3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
S4, S5 or G3 states.

1.5 V supply for core well logic, group A (52 pins). This power may be shut off in
S3, S4, S5 or G3 states.

1.5 V supply for core well logic, group B (45 pins). This power may be shut off in
S3, S4, S5 or G3 states.

2.5V supply for internal logic (2 pins). This power may be shut off in S3, S4, S5 or
G3 states.
NOTE: This voltage may be generated internally (see Section 2.22.1 for strapping
option). If generated internally, these pins should not be connected to an external
supply.
Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
off in S3, S4, S5 or G3 states.

3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to
be shut off unless the system is unplugged.

1.5 V supply for resume well logic (3 pin). This power is not expected to be shut
off unless the system is unplugged.
This voltage may be generated internally (see Section 2.22.1 for strapping option).
If generated internally, these pins should not be connected to an external supply.
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
expected to be shut off unless the system is unplugged.

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by
using a jumper on RTCRST# or GPI.

1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. This signal must be powered
even if USB not used.

1.5 V supply for core well logic (1 pins). This signal is used for the DMI PLL. This
power may be shut off in S3, S4, S5 or G3 states.

1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
This power may be shut off in S3, S4, S5 or G3 states. This signal must be
powered even if SATA not used.
Powered by the same supply as the processor I/O voltage (3 pins). This supply is
used to drive the processor interface signals listed in Table 2-13.
Grounds (172 pins).

97

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TECHNICAL SERVICE MANUAL Prestigio Nobile 1510

5.2 Intel ICH6-M South Bridge(10)

Functional Strap Definitions 1

Signal Usage When Sampled Description

GNT[6]#/
GPO[16]

LINKALERT# Reserved This signal requires an external pull-up resistor.

SPKR No Reboot Rising Edge

INTVRMEN IntegratedVccS

GPIO[25] Integrated

EE_CS Reserved This signal has a weak internal pull-down.

GNT[5]#/
GPO[17]

Top-Block Swa

Override

1_5VRM

Enable/Disabl

Vcc2_5 VRM

Enable/ Disabl

Boot BIOS
Destination

Selection

Rising Edge of

PWROK

ofPWROK

Always This signal enables integrated VccSus1_5 VRM

Rising Edge of

RSMRST#

Rising Edge of

PWROK

The signal has a weak internal pull-up. If the
signal is sampled low, this indicates that the
system is strapped to the “top-block swap” mode
(ICH6 inverts A16 for all cycles targeting FWH
BIOS space). The status of this strap is readable
via the Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until
the system is rebooted without GNT6# being
pulled down.

The signal has a weak internal pull-down. If the
signal is.sampled high, this indicates that the
system is strapped to.the “No Reboot” mode
(ICH6 will disable the TCO Timer. system
reboot feature). The status of this strap is
readable. via the NO REBOOT bit (Chipset
Configuration. Registers:Offset 3410h:bit 5).

when.sampled high.

This signal enables integrated Vcc2_5 VRM
when sampled low. This signal has a weak
internal pull-up during RSMRST# and is
disabled within 100 ms after RSMRST#
de-asserts.

NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up. Allows
for select memory ranges to be forwarded out the
PCI Interface as opposed to the Firmware Hub.
When sampled high, destination is LPC. Also
controllable via Boot BIOS Destination bit
(Chipset Configuration Registers:Offset
3410h:bit 3).
NOTE: This functionality intended for
debug/testing only.

Functional Strap Definitions 1 (Continued)

Signal Usage When Sampled Description

EE_DOUT Reserved This signal has a weak internal pull-up.

ACZ_SDOUT XOR Chain

Entrance / PCI

Express* Port

Configu-ratio

bit 1

ACZ_SYNC PCI Express Po

Configu-ratio

bit 0

TP[1] Reserved This signal has a weak internal pull-down.

SATALED# Reserved This signal has a weak internal pull-up enabled

REQ[4:1]# XOR Chain

Selection

TP[3] XOR Chain

Entrance

Rising Edge of

PWROK

Rising Edge of

PWROK

Rising Edge of

PWROK

Rising Edge of

PWROK

NOTE: This signal should not be pulled low.
Allows entrance to XOR Chain testing when
TP[3] pulled low at rising edge of PWROK. See
Chapter 24 for XOR Chain functionality
information.
When TP[3] not pulled low at rising edge of
PWROK, sets bit 1 of RPC.PC (Chipset
Configuration Registers:Offset 224h). See
Section 7.1.30 for details.
This signal has a weak internal pull-down.
This signal has a weak internal pull-down.
Sets bit 0 of RPC.PC (Chipset Configuration
Registers: Off set 224h). See Section 7.1.30 for
details.

NOTE: This signal should not be pulled high.

only when PLTRST# is asserted.
NOTE: This signal should not be pulled low.
See Chapter 24 for functionality information.

See Chapter 24 for functionality information.
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low
unless using XOR Chain testing.

Real Time Clock Interface

Name Type Description

RTCX1

RTCX2

Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.

Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.

If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.

If no external crystal is used, then RTCX2 should be left floating.

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6. System Block Diagram

TECHNICAL SERVICE MANUALPrestigio Nobile 1510

J514

1394a Port

MINI PCI Slot

CardBus

IEEE1394

PCI4510

200 Pins DDR SO-DIMM Socket * 2

U517

U501

Clock Generator

ICS954226

PCI Bus

USB * 2

CD-ROM

U16

SATA Bridge

IDE

U506

INTEL CPU

DOTHAN

FSB

U512

North Bridge

915GM/PM

DMI

U513

South Bridge

ICH6-M

LVDS Signal

RGB Signal

TV Signal

U503

AC'97 Codec

ALC260

THRMDA/THRMDC

Flat Panel

CRT Connector

TV Connector

U525

Amplifier

TPA0212

J522

M.D.C

Mic-in Connector

Internal Speaker

Headphone

RJ-11 Jack

U13

Power Switch

TPS2211A

PCMCIA

Slot

PATA HDD

LAN Controller

RTL8110SBL

RJ-45 Jack

U519

PCI-E_LAN

FWH BUS

U15

System BIOS

99

LPC BUS

U510

Keyboard BIOS

Winbond

W83L950D

Power Button

SMBUS

Touch Pad

Keyboard

FAN

U507

ADT7460