Prestigio CAVALIERE 141 Technical & Service Manual
PRESTIGIO CAVALIERE 141
TECHNICAL SERVICE
MANUAL
Prestigio Cavaliere 141 Technical Service Manual
Contents
1. Hardware Engineering Specification ----------------------------------------------------------------------------
1.1 Introduction----------------------------------------------------------------------------------------------------------
1.2 System Hardware Parts--------------------------------------------------------------------------------------------
1.3 Other Functions ----------------------------------------------------------------------------------------------------
1.4 Peripheral Components---------------------------------------------------------------------------------------------
1.5 Power Management-------------------------------------------------------------------------------------------------
1.6 Appendix 1:SiS961 GPIO Definitions-------------------------------------------------------------------------------
1.7 Appendix 2:Prestigio Cavaliere 141 product Spec -------------------------------------------------------------------
2. System View and Disassembly-------------------------------------------------------------------------------------
2.1 System View----------------------------------------------------------------------------------------------------------
2.2 System Disassembly--------------------------------------------------------------------------------------------------
3. Definition & Location of Connectors/Switches-----------------------------------------------------------------
3.1 Mother Board-A-----------------------------------------------------------------------------------------------------
3.2 Mother Board-B-----------------------------------------------------------------------------------------------------
3.3 Charge Board--------------------------------------------------------------------------------------------------------
4. Definition & Location of Major Components ------------------------------------------------------------------
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4.1 Mother Board-A -----------------------------------------------------------------------------------------------------
4.2 Mother Board-B ----------------------------------------------------------------------------------------------------
4.3 Charge Board -------------------------------------------------------------------------------------------------------
5. Pin Description of Major Component ---------------------------------------------------------------------------
5.1 Mobil Intel Pentium 4 Processor-M--------------------------------------------------------------------------------
5.2 SiS650 (IGUI HOST Memory Controller)-------------------------------------------------------------------------
5.3 SiS961 (MuTIOL ® Media I/O South Bridge)---------------------------------------------------------------------
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Contents
6. System Block Diagram-----------------------------------------------------------------------------------------------
7. Maintenance Diagnostics--------------------------------------------------------------------------------------------
7.1
Introduction----------------------------------------------------------------------------------------------------------
7.2 Debug Tool-----------------------------------------------------------------------------------------------------------
7.3 Error Codes-----------------------------------------------------------------------------------------------------------
8. Trouble Shooting -----------------------------------------------------------------------------------------------------
8.1 No Power ------------------------------------------------------------------------------------------------------------
8.2 Battery Can not Be Charged ---------------------------------------------------------------------------------------
8.3 No Display -----------------------------------------------------------------------------------------------------------
8.4 VGA Controller Failure LCD No Display--------------------------------------------------------------------------
8.5 External Monitor No Display ------------------------------------------------------------------------------------------
8.6 Memory Test Error -------------------------------------------------------------------------------------------------
8.7 Keyboard (K/B) and Touch-Pad (T/P) Test Error-----------------------------------------------------------------
8.8 Hard Drive Test Error ----------------------------------------------------------------------------------------------
8.9 CD-ROM Drive Test Error-----------------------------------------------------------------------------------------
8.10 USB Port Test Error -----------------------------------------------------------------------------------------------
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8.11 PC-Card Socket Fail -----------------------------------------------------------------------------------------------
8.12 LAN Test Error ----------------------------------------------------------------------------------------------------
8.13 Audio Driver Failure ----------------------------------------------------------------------------------------------
9. Spare Parts List -------------------------------------------------------------------------------------------------------
10. System Exploded Views--------------------------------------------------------------------------------------------
11. Circuit Diagram-----------------------------------------------------------------------------------------------------
12. Reference Material -------------------------------------------------------------------------------------------------
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1. Hardware Engineering Specification
1.1 Introduction
General Description
This document describes the engineering specification for Prestigio Cavaliere 141 portable notebook computer system.
System Overview
The Prestigio Cavaliere 141 model motherboard will accept Intel Mobile Pentium 4 with 400MHz FSB with MicroFCPGA package. It can support Mobile Pentium 4 1.4GHz ~ 2GHz.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 1.0b. It also provides easy configuration through CMOS setup, which is built in system BIOS software and
can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, CD-ROM, HDD, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND
MODE and battery present, capacity & charging status. It also equipped with LAN, 56KMODEM, 4 USB port, 3D
stereo audio functions, TV out and audio line out, line in, external microphone in function.
The memory subsystem supports 128MB on board DDR SDRAM, and with one expansion DDR 128MB/256MB
module.
The SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor,
a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
The SiS961 MuTIOL Media I/O integrates two Universal Serial Bus 1.1 Host Controllers, the Audio Controller with
AC 97 interface, the Ethernet MAC Controller w/ standard MII interface, the IDE Master/Slave controllers, and SiS
MuTIOL technology.
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The ICS 1893 is a low-power, physical-layer device (PHY) that supports the 10Base-T and 100Base-TX Ethernet
standards. This VLSI device is designed for easy implementation of 10/100 Mb/s Fast Ethernet LANs. It interfaces
to a MAC through an MII interface ensuring interoperability between products from different vendors.
The ENE CB1410 CARDBUS controller supports one PCMCIA or CARDBUS interface.
The NS PC87393 Super I/O controller integrates the standard PC I/O functions: LPC bus interface, X-Bus Extension
for read and write operations, floppy disk interface and one EPP/ECP capable parallel port. Like all LPC Super I/O
devices, the PC87393 offers a single-chip solution to the most commonly used PC I/O peripherals to provide for the
increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto the motherboard which
contain 3D audio output.
SiS301LV, which is an accompany chip of SiS VGA chip, integrates: (1) A NTSC/PAL video encoder with
Macrovision Ver.7.1.L1 option for TV display, (2) A LVDS transmitter with bi-linear scaling capability for TFT
LCD panel display. SiS301LV receives digital video signals and control signals from the primary VGA chip then
transforms them into composite, S or component video outputs for TV display, LVDS signals for LCD display.
The H8/3437 is a high performance microcontroller with a fast H8/300 CPU core and a set of on-chip supporting
functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication
interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions
needed in control system configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 Hardware System
System parts
CPU: Using Intel Mobile Pentium 4 microprocessors in Micro-FCPGA package.
Synthesizer: ICS952001.
North Bridge: SiS650.
South Bridge: SiS961.
TV-OUT and display controller: SiS301LV.
LPC to ISA and super I/O controller: NS PC87393
Keyboard System: Hitachi H8/3437 Universal Controller
FAX/MODEM: Askey 56Kbps Fax Modem
LAN PHY: ICS1893
PCMCIA: controller: ENE CB1410 + ENE CP2211
AC’97: Codec: Realtek ALC201
Thermal sensor: ADM1021A
System Flash Memory (BIOS) : Insyde 256KB Flash EPROM
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1.2.1 CPU module
Intel Mobile Pentium 4 Processors with 478 pins Micro-FCPGA package.
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-pipelined
technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution,
advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times
per bus clock.
Support Enhanced n two performance modes.
1.2.2 Synthesizer
System frequency synthesizer:ICS952001
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write operations.
For DDR SDRAM system use the ICS93705 or ICS93722 as the memory buffer.
Use external 14.318MHz crystal.
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1.2.3 SiS650 IGUI HMAC 3D Graphic DDR/SDR Chipset
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a
high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die
termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum
outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and
Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems.
It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from
the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated
GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A
high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL Media
I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link Layer delivering
1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multithreaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder
in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high
performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or
external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by
retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the
Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the
frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
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The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator
with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to
deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge
packaged in 100-pin PQFP is incorporated to expand the SiS 650 functionality to support the secondary display, in
addition to the default primary CRT display. The SiS 301B Video Bridge integrates an NTSL/PAL video encoder
with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT
LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the
extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that
both can generate the display in independent resolutions, color depths, and frame rates.
Two separate buses, Host-t-GUI in the width of 64 bits, and GUI-t-Memory Controller in the width of 128 bits are
devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory
subsystem, the 128 bits GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate,
respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and
the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP
controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of
dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous
downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb
the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data
queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The Mdata/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to
utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data
requests streamlines in the foreground.
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Features
High Performance Host Interface
¾ Support Intel Pentium 4 series CPU with data transfer rate of 400MHz.
¾ Support 12 Outstanding Transactions
¾ Synchronous/Asynchronous Host-t-DRAM Timing
¾ Master deliver System Bus Interrupt support
¾ Smart Prefetch mechanism to boost memory read performance
¾ Support 2M/4M/8M/16M TSEG SMRAM
¾ Support Defer function to maximize bus utilization
¾ Support Dynamic Bus Inversion
¾ AGTL+ & AGTL compliant bus driver auto compensation
64 Bit High Performance DDR266/PC133 Memory Controller
¾ Supports DDR266/200 SDRAM or PC133/100 SDRAM
¾ Support Up to 3 un-buffer Double-sided DIMM DDR266/200
¾ Up to 1 GB per DIMM with max. memory size up to 3 GB
¾ Supports 16Mb, 64Mb, 128Mb, 256Mb, & 512Mb SDRAM technology with page size from 2KB up to 16 KB
¾ Sustains DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
¾ Programmable buffer strength optimizing performance and stability
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¾ Dynamic Clock Enable (CKE) control placing the SDRAM into Suspend to DRAM state
¾ High performance unified memory controller optimizing the DRAM bus utilization
¾ Programmable frame buffer size from 8MB and up to 64MB
¾ 128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
¾ AGP v2.0 Compliant
¾ Supports Graphic Window Size from 4MBytes to 256MBytes
¾ Supports Pipelined Process in CPU-to- A.G.P. Access
¾ Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P. Controller
¾ Read/Write Performance
¾ Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to A.G.P. device
¾ Supports Additional AGP4X/2X interface and Fast Write Transaction
High Throughput SiS MuTIOL connect to SiS961 MuTIOL Media I/O
¾ Bi-directional 16 bit data bus
¾ Perform 533MB/s bandwidth in 66MHz x 4 mode
¾ Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
¾ Packet based, pipelining, and split transaction scheme
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Dedicated Isochroous Response Queue
¾ Serves Isochroous downstream transfers responsive to the memory read requests originated from USB or audio/modem
controllers
¾ Offers privilege service to guarantee minimum latency & timely delivery
High Performance & High Quality 3D Accelerator
¾ Built-in a high performance 256-bit 3D engine
¾ Built-in a high quality 3D engine
High Performance 2D Accelerator
¾ Built-in 128 double-words hardware command queue
¾ Built-in Direct Draw Accelerator
¾ Built-in GDI+ Accelerator
Complete TV-OUT/Digital Flat Panel Solution
¾ Built-in secondary CRT controller for independent secondary CRT, LCD or TV digital output
¾ Cooperates with “SiS301B Video Bridge” to support
¾ Supports Dual 12-bit DDR digital interface to TV encoder and LCD transmitter
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MPEG-2/1 Video Decoder
¾ MPEG-2 ISO/IEC 13818-2 MP@HL and MPEG-1 ISO/IEC 11172-2 standards compliant
¾ Built-in advanced hardware DVD acceleration logic
¾ Support AGP bus master/LFB-mode code fetching
¾ Half pixel resolution in motion compensation
¾ Support VCD, DVD and HDTV (all ATSC modes) decoding
¾ Direct DVD to TV playback
Video Accelerator
¾ Supports single frame buffer architecture
¾ Supports single video windows with overlay function
¾ Supports YUV-to-RGB color space conversion
¾ Supports bi-linear video interpolation with integer increments of 1/2048
¾ Supports graphics and video overlay function
¾ Supports tearing free double buffer flipping
¾ Supports RGB555, RGB565, YUV422, and YUV420 video playback format
¾ Supports filtered horizontal up and down scaling playback
¾ Supports DVD sub-picture playback overlay
¾ Supports DVD playback auto-flipping
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¾ Built-in two 120x128 video playback line buffers to support 1920x1080 video playback
¾ Built-in independent Gamma correction RAM
¾ Supports DCI Drivers
¾ Supports Direct Draw Drivers
High Integration
¾ Built-in 64x128 CRT FIFOs to support ultra high resolution graphics modes and reduce CPU wait-state
¾ Built-in programmable 24-bit true-color RAMDAC up to 333 MHz pixel clock
¾ Built-in two clock generators
¾ Built-in two 120x128 video line buffers for MPEG II video playback
¾ Built-in TV Encoder Interface
Resolution, Color & Frame Rate
¾ Supports 333 MHz pixel clock
¾ Supports VESA standard super high resolution graphics modes
¾ Supports virtual screen up to 4096x4096
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Power Management
¾ Supports VESA Display Power Management Signaling (DPMS) compliant VGA monitor for power
management
¾ Supports direct I/O command to force graphics controller into standby/suspend/off state
¾ Power down internal Gamma/Palette SRAM in direct color mode
¾ Supports PCI power management configuration registers for supporting ACPI power down controller
¾ Power down all internal macro cells such as SRAM, DAC, clock generator when power saving mode
¾ Supports clock stopping for video accelerator, VP, 2D, 3D and MPEG decoder when disabled
¾ Supports auto clock throttling for 2D engine, 3D engine
Multimedia Application
¾ Supports auto clock throttling for 2D engine, 3D engine
¾ Supports RAMDAC snoop for multimedia applications
NAND Tree for Ball Connectivity Testing.
702-Balls BGA Package.
1.8V Core with Mixed 1.2V 1.5V 1.8V, 2.5V and 3.3V I/O CMOS Technology
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1.2.4 SiS961 MuTIOL Media I/O
The SiS961 MuTIOL Media I/O integrates two Universal Serial Bus 1.1 Host Controllers, the Audio Controller with
AC 97 Interface, the Ethernet MAC Controller w/ standard MII interface, the IDE Master/Slave controllers, and SiS
MuTIOL technology. The PCI to LPC Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O
and legacy power management functionalities are integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers
with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally
configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented.
The Integrated AC97 v2.2 compliance Audio Controller that features a 6-channels of audio speaker out and HSP v.90
modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting
multiple audio codecs with one separate modem codec.
The integrated Fast Ethernet MAC Controller features an IEEE 802.3 and IEEE 802.3x compliant MAC with
external LAN physical layer chip supporting full duplex 10 Base-T, 100 Base-T Ethernet, or with external Home
networking physical layer chip supporting 1Mb/s & 10Mb/s Home networking. Additionally, 5 wake-up Frames,
Magic Packet and link status changed wake-up function in G1/G2 states are supported. For storing Mac address, two
schemes are provided: 1. Store in internal APC register or 2. Store in external EEPROM.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4,
and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data
transfer rate in the multitasking environment.
SiS961 supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O
like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired
keyboard controller and PS2 mouse interface, Real Time clock with 512B CMOS SRAM and two 8259A compatible
Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery
modes is supported.
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The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the SiS961 supports Deeper Sleep power state for Intel Mobile processor. For AMD
processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.
A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX and SiS961 MuTIOL
Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Channels Layer
delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to
Multi-threaded I/O Channels layer, the Multi-threaded I/O Packet Layer in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Channels layer to/from SiS645DX, and the Multi-threaded I/O Packet Layer
in SiS645DX to transfer data w/ 533 MB/s from/to memory sub-system to/from the Multi-threaded I/O Packet Layer
in SiS961.
Features
Meet PC2001 Requirements
High performance SiS MuTIOL Technology Interconnecting SiS North Bridge and South Bridge
chips
¾ Bi-directional 16-bit data bus
¾ 533MB/s performance in 4x66 MHz mode
¾ Distributed Arbitration Scheme
¾ Supports Back to Back Transaction
Integrated Multi-threaded I/O link ensures concurrency of upstream/down stream data
transfer
with 1.2GB/s bandwidth
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Multiple DMA Bus Architecture
¾ Concurrent Servicing of all DMA Devices: Dual IDE Controllers, Two USB 1.1 HC, MAC Controller,
Audio/Modem DMA Controller
¾ Separate 32 Bit Input and Output Data Bus Scheme for each DMA Device
¾ Advanced Performance Merits of Split & Pipelined Transaction and Concurrent
¾ Execution among Multi-I/O Devices
Integrated MuTIOL to PCI Bridge
¾ PCI 2.2 Specification Compliance
¾ Supports up to 6 PCI Masters
¾ Two Prefetch cache Buffers support 2 delayed transactions
¾ Fairness Rotating PCI Arbiter Scheme with Option to Place PCI Master 0 as the Highest Priority
Dual IDE Master/Slave Controller
¾ Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming
¾ Dual Independent IDE Channels Each with 16 DW FIFO
¾ Native and Compatibility Mode
¾ PIO Mode 0, 1, 2, 3, 4 and Multiword DMA Mode 0, 1, 2
¾ Ultra DMA 33/66/100
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Universal Serial Bus Host Controller
¾ Integrated Multithreaded IO Link Mastering
¾ Two Independent OHCI USB 1.1 Host Controllers, support up to six ports
¾ Supports wake-up from S1-S3
¾ Legacy Keyboard/Mouse support
Integrated Fast Ethernet MAC Controller
¾ Multithread I/O link Mastering with Read/Write Concurrent transaction
¾ IEEE 802.3 and 802.3x Standard Compatible
¾ Supports Enhanced Software and Automatic Polling schemes to access PHY registers
¾ Supports full duplex 10base-T, 100base-Tx, 1 Mb/s & 10 Mb/s Home Networking
¾ Support ACPI v1.0b and PCI Power Management v1.1 Standard
¾ Support 5 Wake-up Frame, Magic Packet, and Link Status changed wake-up function at G1/G2 state
¾ Integrated 128-bit multicast hash table
¾ Support 2K bytes transmit and receive Data FIFO
¾ MAC address store scheme from external 4-pin EEPROM or Internal APC register
Integrated Audio Controller with AC97 Interface.
¾ AC97 v2.2 compliance
¾ 6 Channels of AC97 speaker outputs and V.90 HSP-Modem
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¾ Supports two Consumer Audio Digital interface: traditional Consumer Digital Audio Out and AC97 V2.2
Compliance Consumer Audio Digital Interface
¾ Supports VRA Mode for both AC97 Audio Link and Consumer Audio Digital Interface
Advanced Power Management
¾ Meets ACPI 1.0b Requirements
¾ Meets APM 1.2 Requirements
¾ ACPI Sleep States Include S1, S3, S4, S5
¾ CPU Power States Include C0, C1, C2 C3, C4
¾ Supports Intel Deeper Sleep Power State for Intel mobile processor.
¾ Reduce AMD processor voltage during S1/C3 state
¾ Power Button with Override only wake up by Power Button
¾ RTC Day-of-Month, Month-of-Year Alarm
¾ 24-bit Power Management Timer
¾ LED Blinking in S0, S1 and S3 States
¾ ACPI System Wake-up Events
¾ Software Watchdog Timer
¾ PCI Bus Power Management Interface Spec. 1.1
¾ Support PCI CLKRUN and STP_PCI function (for Mobile only)
¾ Support RTC32KHz output from GPIO18 (for Mobile only).
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¾ Integrated 32-bit Random Number Generator
¾ Support one GTL-level input signal used to Instantly Power off system
¾ Support one GTL-level input signal used to assert SMI#/SCI#
Integrated DMA Controller
¾ Two 8237A Compatible DMA Controllers
¾ 8/16- bit DMA Data Transfer
¾ Distributed DMA Support
Integrated Interrupt Controller
¾ Two 8259A Compatible Interrupt Controllers for up to 15 interrupts
¾ Programmable Level or Edge Triggered Interrupts
¾ Support Serial Interrupt
¾ Support 8 PCI interrupts for internal device
¾ Support Message Interrupt Delivery Mode
¾ Integrated I/O APIC in Serial Mode or FSB Interrupt Delivery Model for up to 24 Interrupts
Three 8254 Compatible Programmable 16-bit Counters
¾ System Timer Interrupt
¾ Generate Refresh Request
¾ Speaker Tone Output
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Integrated Keyboard Controller
¾ Hardwired Logic Provides Instant Response
¾ Supports PS/2 Mouse Interface
¾ Password Security and Password Power-Up
¾ System Sleep and Power-Up by Hot-Key
¾ KBC and PS2 Mouse Can Be Individually Disabled
Integrated Multimedia Timers
¾ Support three timers operating at 32- or 64-bit mode
Integrated PCI to LPC Bridge
¾ LPC 1.0 Compliance
¾ Support Two Master/DMA devices
NAND Tree for Ball Connectivity Testing
371-Balls BGA Package
1.8V Core with Mixed 1.5V, 1.8V, 2.65V and 3.3V I/O CMOS Technology
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1.2.5 SiS301LV
SiS301LV, which is an accompany chip of SiS VGA chip, integrates
¾ A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display.
¾ A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display.
All the above functions can support dual-display features. It means that the second display device driven by
SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT
monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the primary
VGA chip then transforms them into composite, S or component video output for TV display, LVDS signals for
LCD display. The output display combination can be one of the three : (1) Primary CRT+SiS301LV TV, (2) Primary
CRT+SiS301LV LCD,(3) SiS301LV TV + SiS301LV LCD.
1.2.6 Super I/O_NS PC87393
National Semiconductor’s PC8739x family of LPC Super I/O devices is targeted for a wide range of portable
applications. PC99 and ACPI compliant, the PC8739x family features an X-Bus Extension for read and write
operations over the X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Multiplexer (PPM) for external
Floppy Disk Drive (FDD) support, a Musical Instrument Digital Interface (MIDI) port, and a Game port. Like all
National LPC Super I/O devices, the PC8739x offers a single-chip solution to the most commonly used PC I/O
peripherals.
The PC8739x family also incorporates: a Floppy Disk Controller (FDC), two enhanced Serial Ports (UARTs), one
with Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose Input/Output (GPIO) support for a total of 32 ports,
Interrupt Serializer for Parallel IRQs and an enhanced WATCH DOG timer.
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1.2.7 Keyboard controller Hitachi H8/3437
The H8/3437 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core and a set of onchip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial
communication interface, optional I2C bus interface, host interface, A/D converter, D/A converter, I/O ports, and
other functions needed in control system configurations, so that compact, high-performance systems can be
implemented easily. The series includes the H8/3437 with 60-kbyte ROM and 2-kbyte RAM, the H8/3436 with 48kbyte ROM and 2-kbyte RAM, and the H8/3434 with 32-kbyte ROM and 1-kbyte RAM.
The H8/3437, H8/3436, and H8/3434 are available in mask-ROM versions. The H8/3437 and H8/3434 are also
available in ZTAT™*1 (zero turn-around time) versions, providing a quick and flexible response to conditions from
ramp-up through full-scale volume production, even for applications with frequently-changing specifications. In
addition, the H8/3434 and H8/3437 have F-ZTAT™*2 (flexible-ZTAT) versions with on-board programmability.
Notes: 1. ZTAT™ is a trademark of Hitachi, Ltd.
2. F-ZTAT™ is a trademark of Hitachi, Ltd.
1.2.8 FAX/MODEM module
¾ Made by Billonton Computer corporation
¾ Integrated PCI v2.2 Interface
¾ Host-based ITU V.70 DSVD.
¾ Operation support: Windows 95/NT/ME/2000
¾ K56flex for internet connection rates approaching 56kbits/s.
¾ Data Modes capabilities
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Prestigio Cavaliere 141 Technical Service Manual
¾ ITU-T V.90/K56flex, V.34, V.32bis, V.22bis, V.23, V.22A/B, V.21
¾ Bell 212A and 103
¾ Data Compression V.42bis, MNP Class 5
¾ Error Correction V.42 LAPM and MNP2.4
¾ FAX mode capabilities:
¾ ITU-T V.17, V.29, V.27ter, and V.21 CH 2
¾ TIA/EIA 578 Class 1 FAX
¾ V.80 Host Controlled Communication Protocol Standards
¾ H.324 Interface Support
¾ On Chip PnP Logic
¾ ACPI support “On Now”
¾ Support “Call ID”
¾ PC 97 Compliant – Unimodem/V Compliant
¾ Low Power Consumption
¾ Operation Voltage 3.3V
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Prestigio Cavaliere 141 Technical Service Manual
1.2.9 LAN PHY_ICS1893
The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is
based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. The
ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a
result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from
killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status
information with a Station Management (STA) entity. The ICS1893 Media Dependent Interface (MDI) can be
configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI
configuration can be established manually (with input pins or control register settings) or automatically (using the
Auto-Negotiation features). When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology
capability data with its remote link partner and automatically selects the highest-performance operating mode they
have in common.
1.2.10 PCMCIA controller_ ENE CB1410 + ENE CP2211
CB1410
¾ Ability to wake from D3
¾ 3.3V core logic with universal PCI interface compatible with 3.3V and 5V PCI signaling environment
¾ Mix-to-match 5V/3.3V 16 bit PC Cards and 3.3V CardBus Cards
¾ Single PC Card or CardBus slot with hot insertion and removal
¾ Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
HOT
and D3
COLD
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Prestigio Cavaliere 141 Technical Service Manual
¾ Parallel PCI interrupts, parallel ISA IRQ and Parallel PCI interrupts, Serial ISA IRQ with Parallel PCI interrupts,
and Serial ISA IRQ and PCI interrupts
¾ Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
¾ Pipelined architecture allows greater than 130 Mbps sustained throughput from-CardBus-to-PCI and from-PCI-
to- CardBus
¾ Interface to parallel single-slot PC Card power interface switches
¾ Up to five general-purpose I/Os
¾ Programming output select for CLKRUN#
¾ Five PCI memory windows and two I/O windows available to the 16-bit PC Card Socket
¾ Two I/O windows and two memory windows available to the CardBus Socket
¾ Exchangeable Card Architecture ( ExCA ) compatible registers are mapped in memory I/O space
¾ Distributed DMA ( DDMA ) and PC/PCI DMA
¾ 16-Bit DMA on the PC Card Socket
¾ Ring indicate, SUSPEND#, PCI CLKRUN#, and CardBus CCLKRUN#
¾ Socket activity LED pins
¾ PCI Bus Lock ( LOCK# )
¾ Advanced Submicron, Low-Power CMOS Technology
¾ Internal Ring Qscillator
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Prestigio Cavaliere 141 Technical Service Manual
CP2211 (Power Switch)
¾ Fully integrated VCCand VPPswitching
¾ Low r
DS(ON)
: 90-mΩ 5V and 3.3V VCCSwitches
¾ Compatible with industry standard controllers
¾ 12V supply not required unless the PC Card uses 12V for flash programming or other applications
¾ 3.3V low voltage mode
¾ Short-circuit and thermal protection
¾ Compatible with 3.3V, 5V, and 12V PC Cards
¾ Break-before-make switching
1.2.11 AC’97 Codec _ Realtek ALC201
¾ 20-bit Stereo Digital-to-Analog Converter and 18-bit Stereo Analog to Digital Converter with Sample Rate
Conversion
¾ Four Analog Line-level Stereo Inputs for Connection from LINE IN, CD, VIDEO, and AUX
¾ Two Analog Line-level Mono Inputs for Modem Sub-system and Internal PC Beeper
¾ Mono Microphone Input Switch able from Two External Sources
¾ High Quality Pseudo Differential CD Input
¾ Dual Stereo Line-level Outputs
¾ CrystalClear 3D Stereo Enhancement
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Prestigio Cavaliere 141 Technical Service Manual
1.2.12 Thermal sensor_ ADM1021A
¾ On-Chip and Remote Temperature Sensing
¾ No Calibration Necessary
¾ 1_C Accuracy for On-Chip Sensor
¾ 3_C Accuracy for Remote Sensor
¾ Programmable Over/Under Temperature Limits
¾ Programmable Conversion Rate
¾ 2-Wire SMBus Serial Interface
¾ Supports System Management Bus (SMBus) Alert
¾ 200 _A Max Operating Current
¾ 1 _A Standby Current
¾ 3 V to 5.5 V Supply
¾ Small 16-Lead QSOP Package
1.2.13 System Flash Memory (BIOS)
¾ 2M bit Flash memory
¾ Flashed by 5V only
¾ User can upgrade the system BIOS in the future just running flash program.
¾ See Software BIOS Specification
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Prestigio Cavaliere 141 Technical Service Manual
1.3 Other Functions
1.3.1 Hot Key Function
Keys
Feature Meaning
Combination
Fn + F1 Reserve
Fn + F2 Reserve
Fn + F3 Volume Down
Fn + F4 Volume Up
Rotate display mode in LCD only, CRT only and
Fn + F5 LCD/external CRT switching
simultaneously display.
Fn + F6 Brightness down Decreases the LCD brightness
Fn + F7 Brightness up Increases the LCD brightness
Fn + F8 Brightness MAX Toggle Max Brightness
Fn + F9 Pause
Fn + F10 Break
Fn + F11 Panel Off/On Toggle Panel Off/On
Force the computer into either Suspend to HDD
Fn + F12 Suspend to DRAM/HDD
or Suspend to RAM mode depending on BIOS
Setup.
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