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PRESTIGIO CAVALIERE 141
TECHNICAL SERVICE
MANUAL
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Prestigio Cavaliere 141 Technical Service Manual
Contents
1. Hardware Engineering Specification ----------------------------------------------------------------------------
1.1 Introduction----------------------------------------------------------------------------------------------------------
1.2 System Hardware Parts--------------------------------------------------------------------------------------------
1.3 Other Functions ----------------------------------------------------------------------------------------------------
1.4 Peripheral Components---------------------------------------------------------------------------------------------
1.5 Power Management-------------------------------------------------------------------------------------------------
1.6 Appendix 1:SiS961 GPIO Definitions-------------------------------------------------------------------------------
1.7 Appendix 2:Prestigio Cavaliere 141 product Spec -------------------------------------------------------------------
2. System View and Disassembly-------------------------------------------------------------------------------------
2.1 System View----------------------------------------------------------------------------------------------------------
2.2 System Disassembly--------------------------------------------------------------------------------------------------
3. Definition & Location of Connectors/Switches-----------------------------------------------------------------
3.1 Mother Board-A-----------------------------------------------------------------------------------------------------
3.2 Mother Board-B-----------------------------------------------------------------------------------------------------
3.3 Charge Board--------------------------------------------------------------------------------------------------------
4. Definition & Location of Major Components ------------------------------------------------------------------
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4.1 Mother Board-A -----------------------------------------------------------------------------------------------------
4.2 Mother Board-B ----------------------------------------------------------------------------------------------------
4.3 Charge Board -------------------------------------------------------------------------------------------------------
5. Pin Description of Major Component ---------------------------------------------------------------------------
5.1 Mobil Intel Pentium 4 Processor-M--------------------------------------------------------------------------------
5.2 SiS650 (IGUI HOST Memory Controller)-------------------------------------------------------------------------
5.3 SiS961 (MuTIOL ® Media I/O South Bridge)---------------------------------------------------------------------
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Contents
6. System Block Diagram-----------------------------------------------------------------------------------------------
7. Maintenance Diagnostics--------------------------------------------------------------------------------------------
7.1
Introduction----------------------------------------------------------------------------------------------------------
7.2 Debug Tool-----------------------------------------------------------------------------------------------------------
7.3 Error Codes-----------------------------------------------------------------------------------------------------------
8. Trouble Shooting -----------------------------------------------------------------------------------------------------
8.1 No Power ------------------------------------------------------------------------------------------------------------
8.2 Battery Can not Be Charged ---------------------------------------------------------------------------------------
8.3 No Display -----------------------------------------------------------------------------------------------------------
8.4 VGA Controller Failure LCD No Display--------------------------------------------------------------------------
8.5 External Monitor No Display ------------------------------------------------------------------------------------------
8.6 Memory Test Error -------------------------------------------------------------------------------------------------
8.7 Keyboard (K/B) and Touch-Pad (T/P) Test Error-----------------------------------------------------------------
8.8 Hard Drive Test Error ----------------------------------------------------------------------------------------------
8.9 CD-ROM Drive Test Error-----------------------------------------------------------------------------------------
8.10 USB Port Test Error -----------------------------------------------------------------------------------------------
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8.11 PC-Card Socket Fail -----------------------------------------------------------------------------------------------
8.12 LAN Test Error ----------------------------------------------------------------------------------------------------
8.13 Audio Driver Failure ----------------------------------------------------------------------------------------------
9. Spare Parts List -------------------------------------------------------------------------------------------------------
10. System Exploded Views--------------------------------------------------------------------------------------------
11. Circuit Diagram-----------------------------------------------------------------------------------------------------
12. Reference Material -------------------------------------------------------------------------------------------------
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1. Hardware Engineering Specification
1.1 Introduction
General Description
This document describes the engineering specification for Prestigio Cavaliere 141 portable notebook computer system.
System Overview
The Prestigio Cavaliere 141 model motherboard will accept Intel Mobile Pentium 4 with 400MHz FSB with MicroFCPGA package. It can support Mobile Pentium 4 1.4GHz ~ 2GHz.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 1.0b. It also provides easy configuration through CMOS setup, which is built in system BIOS software and
can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, CD-ROM, HDD, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND
MODE and battery present, capacity & charging status. It also equipped with LAN, 56KMODEM, 4 USB port, 3D
stereo audio functions, TV out and audio line out, line in, external microphone in function.
The memory subsystem supports 128MB on board DDR SDRAM, and with one expansion DDR 128MB/256MB
module.
The SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor,
a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
The SiS961 MuTIOL Media I/O integrates two Universal Serial Bus 1.1 Host Controllers, the Audio Controller with
AC 97 interface, the Ethernet MAC Controller w/ standard MII interface, the IDE Master/Slave controllers, and SiS
MuTIOL technology.
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The ICS 1893 is a low-power, physical-layer device (PHY) that supports the 10Base-T and 100Base-TX Ethernet
standards. This VLSI device is designed for easy implementation of 10/100 Mb/s Fast Ethernet LANs. It interfaces
to a MAC through an MII interface ensuring interoperability between products from different vendors.
The ENE CB1410 CARDBUS controller supports one PCMCIA or CARDBUS interface.
The NS PC87393 Super I/O controller integrates the standard PC I/O functions: LPC bus interface, X-Bus Extension
for read and write operations, floppy disk interface and one EPP/ECP capable parallel port. Like all LPC Super I/O
devices, the PC87393 offers a single-chip solution to the most commonly used PC I/O peripherals to provide for the
increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto the motherboard which
contain 3D audio output.
SiS301LV, which is an accompany chip of SiS VGA chip, integrates: (1) A NTSC/PAL video encoder with
Macrovision Ver.7.1.L1 option for TV display, (2) A LVDS transmitter with bi-linear scaling capability for TFT
LCD panel display. SiS301LV receives digital video signals and control signals from the primary VGA chip then
transforms them into composite, S or component video outputs for TV display, LVDS signals for LCD display.
The H8/3437 is a high performance microcontroller with a fast H8/300 CPU core and a set of on-chip supporting
functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication
interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions
needed in control system configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 Hardware System
System parts
CPU: Using Intel Mobile Pentium 4 microprocessors in Micro-FCPGA package.
Synthesizer: ICS952001.
North Bridge: SiS650.
South Bridge: SiS961.
TV-OUT and display controller: SiS301LV.
LPC to ISA and super I/O controller: NS PC87393
Keyboard System: Hitachi H8/3437 Universal Controller
FAX/MODEM: Askey 56Kbps Fax Modem
LAN PHY: ICS1893
PCMCIA: controller: ENE CB1410 + ENE CP2211
AC’97: Codec: Realtek ALC201
Thermal sensor: ADM1021A
System Flash Memory (BIOS) : Insyde 256KB Flash EPROM
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1.2.1 CPU module
Intel Mobile Pentium 4 Processors with 478 pins Micro-FCPGA package.
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-pipelined
technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution,
advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times
per bus clock.
Support Enhanced n two performance modes.
1.2.2 Synthesizer
System frequency synthesizer:ICS952001
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write operations.
For DDR SDRAM system use the ICS93705 or ICS93722 as the memory buffer.
Use external 14.318MHz crystal.
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1.2.3 SiS650 IGUI HMAC 3D Graphic DDR/SDR Chipset
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a
high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die
termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum
outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and
Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems.
It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from
the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated
GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A
high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL Media
I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link Layer delivering
1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multithreaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder
in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high
performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or
external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by
retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the
Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the
frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
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The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator
with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to
deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge
packaged in 100-pin PQFP is incorporated to expand the SiS 650 functionality to support the secondary display, in
addition to the default primary CRT display. The SiS 301B Video Bridge integrates an NTSL/PAL video encoder
with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT
LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the
extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that
both can generate the display in independent resolutions, color depths, and frame rates.
Two separate buses, Host-t-GUI in the width of 64 bits, and GUI-t-Memory Controller in the width of 128 bits are
devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory
subsystem, the 128 bits GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate,
respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and
the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP
controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of
dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous
downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb
the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data
queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The Mdata/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to
utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data
requests streamlines in the foreground.
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Features
High Performance Host Interface
¾ Support Intel Pentium 4 series CPU with data transfer rate of 400MHz.
¾ Support 12 Outstanding Transactions
¾ Synchronous/Asynchronous Host-t-DRAM Timing
¾ Master deliver System Bus Interrupt support
¾ Smart Prefetch mechanism to boost memory read performance
¾ Support 2M/4M/8M/16M TSEG SMRAM
¾ Support Defer function to maximize bus utilization
¾ Support Dynamic Bus Inversion
¾ AGTL+ & AGTL compliant bus driver auto compensation
64 Bit High Performance DDR266/PC133 Memory Controller
¾ Supports DDR266/200 SDRAM or PC133/100 SDRAM
¾ Support Up to 3 un-buffer Double-sided DIMM DDR266/200
¾ Up to 1 GB per DIMM with max. memory size up to 3 GB
¾ Supports 16Mb, 64Mb, 128Mb, 256Mb, & 512Mb SDRAM technology with page size from 2KB up to 16 KB
¾ Sustains DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
¾ Programmable buffer strength optimizing performance and stability
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¾ Dynamic Clock Enable (CKE) control placing the SDRAM into Suspend to DRAM state
¾ High performance unified memory controller optimizing the DRAM bus utilization
¾ Programmable frame buffer size from 8MB and up to 64MB
¾ 128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
¾ AGP v2.0 Compliant
¾ Supports Graphic Window Size from 4MBytes to 256MBytes
¾ Supports Pipelined Process in CPU-to- A.G.P. Access
¾ Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P. Controller
¾ Read/Write Performance
¾ Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to A.G.P. device
¾ Supports Additional AGP4X/2X interface and Fast Write Transaction
High Throughput SiS MuTIOL connect to SiS961 MuTIOL Media I/O
¾ Bi-directional 16 bit data bus
¾ Perform 533MB/s bandwidth in 66MHz x 4 mode
¾ Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
¾ Packet based, pipelining, and split transaction scheme
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Dedicated Isochroous Response Queue
¾ Serves Isochroous downstream transfers responsive to the memory read requests originated from USB or audio/modem
controllers
¾ Offers privilege service to guarantee minimum latency & timely delivery
High Performance & High Quality 3D Accelerator
¾ Built-in a high performance 256-bit 3D engine
¾ Built-in a high quality 3D engine
High Performance 2D Accelerator
¾ Built-in 128 double-words hardware command queue
¾ Built-in Direct Draw Accelerator
¾ Built-in GDI+ Accelerator
Complete TV-OUT/Digital Flat Panel Solution
¾ Built-in secondary CRT controller for independent secondary CRT, LCD or TV digital output
¾ Cooperates with “SiS301B Video Bridge” to support
¾ Supports Dual 12-bit DDR digital interface to TV encoder and LCD transmitter
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MPEG-2/1 Video Decoder
¾ MPEG-2 ISO/IEC 13818-2 MP@HL and MPEG-1 ISO/IEC 11172-2 standards compliant
¾ Built-in advanced hardware DVD acceleration logic
¾ Support AGP bus master/LFB-mode code fetching
¾ Half pixel resolution in motion compensation
¾ Support VCD, DVD and HDTV (all ATSC modes) decoding
¾ Direct DVD to TV playback
Video Accelerator
¾ Supports single frame buffer architecture
¾ Supports single video windows with overlay function
¾ Supports YUV-to-RGB color space conversion
¾ Supports bi-linear video interpolation with integer increments of 1/2048
¾ Supports graphics and video overlay function
¾ Supports tearing free double buffer flipping
¾ Supports RGB555, RGB565, YUV422, and YUV420 video playback format
¾ Supports filtered horizontal up and down scaling playback
¾ Supports DVD sub-picture playback overlay
¾ Supports DVD playback auto-flipping
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¾ Built-in two 120x128 video playback line buffers to support 1920x1080 video playback
¾ Built-in independent Gamma correction RAM
¾ Supports DCI Drivers
¾ Supports Direct Draw Drivers
High Integration
¾ Built-in 64x128 CRT FIFOs to support ultra high resolution graphics modes and reduce CPU wait-state
¾ Built-in programmable 24-bit true-color RAMDAC up to 333 MHz pixel clock
¾ Built-in two clock generators
¾ Built-in two 120x128 video line buffers for MPEG II video playback
¾ Built-in TV Encoder Interface
Resolution, Color & Frame Rate
¾ Supports 333 MHz pixel clock
¾ Supports VESA standard super high resolution graphics modes
¾ Supports virtual screen up to 4096x4096
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Power Management
¾ Supports VESA Display Power Management Signaling (DPMS) compliant VGA monitor for power
management
¾ Supports direct I/O command to force graphics controller into standby/suspend/off state
¾ Power down internal Gamma/Palette SRAM in direct color mode
¾ Supports PCI power management configuration registers for supporting ACPI power down controller
¾ Power down all internal macro cells such as SRAM, DAC, clock generator when power saving mode
¾ Supports clock stopping for video accelerator, VP, 2D, 3D and MPEG decoder when disabled
¾ Supports auto clock throttling for 2D engine, 3D engine
Multimedia Application
¾ Supports auto clock throttling for 2D engine, 3D engine
¾ Supports RAMDAC snoop for multimedia applications
NAND Tree for Ball Connectivity Testing.
702-Balls BGA Package.
1.8V Core with Mixed 1.2V 1.5V 1.8V, 2.5V and 3.3V I/O CMOS Technology
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1.2.4 SiS961 MuTIOL Media I/O
The SiS961 MuTIOL Media I/O integrates two Universal Serial Bus 1.1 Host Controllers, the Audio Controller with
AC 97 Interface, the Ethernet MAC Controller w/ standard MII interface, the IDE Master/Slave controllers, and SiS
MuTIOL technology. The PCI to LPC Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O
and legacy power management functionalities are integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers
with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally
configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented.
The Integrated AC97 v2.2 compliance Audio Controller that features a 6-channels of audio speaker out and HSP v.90
modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting
multiple audio codecs with one separate modem codec.
The integrated Fast Ethernet MAC Controller features an IEEE 802.3 and IEEE 802.3x compliant MAC with
external LAN physical layer chip supporting full duplex 10 Base-T, 100 Base-T Ethernet, or with external Home
networking physical layer chip supporting 1Mb/s & 10Mb/s Home networking. Additionally, 5 wake-up Frames,
Magic Packet and link status changed wake-up function in G1/G2 states are supported. For storing Mac address, two
schemes are provided: 1. Store in internal APC register or 2. Store in external EEPROM.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4,
and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data
transfer rate in the multitasking environment.
SiS961 supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O
like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired
keyboard controller and PS2 mouse interface, Real Time clock with 512B CMOS SRAM and two 8259A compatible
Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery
modes is supported.
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The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the SiS961 supports Deeper Sleep power state for Intel Mobile processor. For AMD
processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.
A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX and SiS961 MuTIOL
Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Channels Layer
delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to
Multi-threaded I/O Channels layer, the Multi-threaded I/O Packet Layer in SiS961 to transfer data w/ 533 MB/s
bandwidth from/to Multi-threaded I/O Channels layer to/from SiS645DX, and the Multi-threaded I/O Packet Layer
in SiS645DX to transfer data w/ 533 MB/s from/to memory sub-system to/from the Multi-threaded I/O Packet Layer
in SiS961.
Features
Meet PC2001 Requirements
High performance SiS MuTIOL Technology Interconnecting SiS North Bridge and South Bridge
chips
¾ Bi-directional 16-bit data bus
¾ 533MB/s performance in 4x66 MHz mode
¾ Distributed Arbitration Scheme
¾ Supports Back to Back Transaction
Integrated Multi-threaded I/O link ensures concurrency of upstream/down stream data
transfer
with 1.2GB/s bandwidth
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Multiple DMA Bus Architecture
¾ Concurrent Servicing of all DMA Devices: Dual IDE Controllers, Two USB 1.1 HC, MAC Controller,
Audio/Modem DMA Controller
¾ Separate 32 Bit Input and Output Data Bus Scheme for each DMA Device
¾ Advanced Performance Merits of Split & Pipelined Transaction and Concurrent
¾ Execution among Multi-I/O Devices
Integrated MuTIOL to PCI Bridge
¾ PCI 2.2 Specification Compliance
¾ Supports up to 6 PCI Masters
¾ Two Prefetch cache Buffers support 2 delayed transactions
¾ Fairness Rotating PCI Arbiter Scheme with Option to Place PCI Master 0 as the Highest Priority
Dual IDE Master/Slave Controller
¾ Integrated Multithreaded I/O Link Mastering with Read Pipelined Streaming
¾ Dual Independent IDE Channels Each with 16 DW FIFO
¾ Native and Compatibility Mode
¾ PIO Mode 0, 1, 2, 3, 4 and Multiword DMA Mode 0, 1, 2
¾ Ultra DMA 33/66/100
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Universal Serial Bus Host Controller
¾ Integrated Multithreaded IO Link Mastering
¾ Two Independent OHCI USB 1.1 Host Controllers, support up to six ports
¾ Supports wake-up from S1-S3
¾ Legacy Keyboard/Mouse support
Integrated Fast Ethernet MAC Controller
¾ Multithread I/O link Mastering with Read/Write Concurrent transaction
¾ IEEE 802.3 and 802.3x Standard Compatible
¾ Supports Enhanced Software and Automatic Polling schemes to access PHY registers
¾ Supports full duplex 10base-T, 100base-Tx, 1 Mb/s & 10 Mb/s Home Networking
¾ Support ACPI v1.0b and PCI Power Management v1.1 Standard
¾ Support 5 Wake-up Frame, Magic Packet, and Link Status changed wake-up function at G1/G2 state
¾ Integrated 128-bit multicast hash table
¾ Support 2K bytes transmit and receive Data FIFO
¾ MAC address store scheme from external 4-pin EEPROM or Internal APC register
Integrated Audio Controller with AC97 Interface.
¾ AC97 v2.2 compliance
¾ 6 Channels of AC97 speaker outputs and V.90 HSP-Modem
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¾ Supports two Consumer Audio Digital interface: traditional Consumer Digital Audio Out and AC97 V2.2
Compliance Consumer Audio Digital Interface
¾ Supports VRA Mode for both AC97 Audio Link and Consumer Audio Digital Interface
Advanced Power Management
¾ Meets ACPI 1.0b Requirements
¾ Meets APM 1.2 Requirements
¾ ACPI Sleep States Include S1, S3, S4, S5
¾ CPU Power States Include C0, C1, C2 C3, C4
¾ Supports Intel Deeper Sleep Power State for Intel mobile processor.
¾ Reduce AMD processor voltage during S1/C3 state
¾ Power Button with Override only wake up by Power Button
¾ RTC Day-of-Month, Month-of-Year Alarm
¾ 24-bit Power Management Timer
¾ LED Blinking in S0, S1 and S3 States
¾ ACPI System Wake-up Events
¾ Software Watchdog Timer
¾ PCI Bus Power Management Interface Spec. 1.1
¾ Support PCI CLKRUN and STP_PCI function (for Mobile only)
¾ Support RTC32KHz output from GPIO18 (for Mobile only).
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¾ Integrated 32-bit Random Number Generator
¾ Support one GTL-level input signal used to Instantly Power off system
¾ Support one GTL-level input signal used to assert SMI#/SCI#
Integrated DMA Controller
¾ Two 8237A Compatible DMA Controllers
¾ 8/16- bit DMA Data Transfer
¾ Distributed DMA Support
Integrated Interrupt Controller
¾ Two 8259A Compatible Interrupt Controllers for up to 15 interrupts
¾ Programmable Level or Edge Triggered Interrupts
¾ Support Serial Interrupt
¾ Support 8 PCI interrupts for internal device
¾ Support Message Interrupt Delivery Mode
¾ Integrated I/O APIC in Serial Mode or FSB Interrupt Delivery Model for up to 24 Interrupts
Three 8254 Compatible Programmable 16-bit Counters
¾ System Timer Interrupt
¾ Generate Refresh Request
¾ Speaker Tone Output
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Integrated Keyboard Controller
¾ Hardwired Logic Provides Instant Response
¾ Supports PS/2 Mouse Interface
¾ Password Security and Password Power-Up
¾ System Sleep and Power-Up by Hot-Key
¾ KBC and PS2 Mouse Can Be Individually Disabled
Integrated Multimedia Timers
¾ Support three timers operating at 32- or 64-bit mode
Integrated PCI to LPC Bridge
¾ LPC 1.0 Compliance
¾ Support Two Master/DMA devices
NAND Tree for Ball Connectivity Testing
371-Balls BGA Package
1.8V Core with Mixed 1.5V, 1.8V, 2.65V and 3.3V I/O CMOS Technology
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1.2.5 SiS301LV
SiS301LV, which is an accompany chip of SiS VGA chip, integrates
¾ A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display.
¾ A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display.
All the above functions can support dual-display features. It means that the second display device driven by
SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT
monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the primary
VGA chip then transforms them into composite, S or component video output for TV display, LVDS signals for
LCD display. The output display combination can be one of the three : (1) Primary CRT+SiS301LV TV, (2) Primary
CRT+SiS301LV LCD,(3) SiS301LV TV + SiS301LV LCD.
1.2.6 Super I/O_NS PC87393
National Semiconductor’s PC8739x family of LPC Super I/O devices is targeted for a wide range of portable
applications. PC99 and ACPI compliant, the PC8739x family features an X-Bus Extension for read and write
operations over the X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Multiplexer (PPM) for external
Floppy Disk Drive (FDD) support, a Musical Instrument Digital Interface (MIDI) port, and a Game port. Like all
National LPC Super I/O devices, the PC8739x offers a single-chip solution to the most commonly used PC I/O
peripherals.
The PC8739x family also incorporates: a Floppy Disk Controller (FDC), two enhanced Serial Ports (UARTs), one
with Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose Input/Output (GPIO) support for a total of 32 ports,
Interrupt Serializer for Parallel IRQs and an enhanced WATCH DOG timer.
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1.2.7 Keyboard controller Hitachi H8/3437
The H8/3437 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core and a set of onchip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial
communication interface, optional I2C bus interface, host interface, A/D converter, D/A converter, I/O ports, and
other functions needed in control system configurations, so that compact, high-performance systems can be
implemented easily. The series includes the H8/3437 with 60-kbyte ROM and 2-kbyte RAM, the H8/3436 with 48kbyte ROM and 2-kbyte RAM, and the H8/3434 with 32-kbyte ROM and 1-kbyte RAM.
The H8/3437, H8/3436, and H8/3434 are available in mask-ROM versions. The H8/3437 and H8/3434 are also
available in ZTAT™*1 (zero turn-around time) versions, providing a quick and flexible response to conditions from
ramp-up through full-scale volume production, even for applications with frequently-changing specifications. In
addition, the H8/3434 and H8/3437 have F-ZTAT™*2 (flexible-ZTAT) versions with on-board programmability.
Notes: 1. ZTAT™ is a trademark of Hitachi, Ltd.
2. F-ZTAT™ is a trademark of Hitachi, Ltd.
1.2.8 FAX/MODEM module
¾ Made by Billonton Computer corporation
¾ Integrated PCI v2.2 Interface
¾ Host-based ITU V.70 DSVD.
¾ Operation support: Windows 95/NT/ME/2000
¾ K56flex for internet connection rates approaching 56kbits/s.
¾ Data Modes capabilities
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¾ ITU-T V.90/K56flex, V.34, V.32bis, V.22bis, V.23, V.22A/B, V.21
¾ Bell 212A and 103
¾ Data Compression V.42bis, MNP Class 5
¾ Error Correction V.42 LAPM and MNP2.4
¾ FAX mode capabilities:
¾ ITU-T V.17, V.29, V.27ter, and V.21 CH 2
¾ TIA/EIA 578 Class 1 FAX
¾ V.80 Host Controlled Communication Protocol Standards
¾ H.324 Interface Support
¾ On Chip PnP Logic
¾ ACPI support “On Now”
¾ Support “Call ID”
¾ PC 97 Compliant – Unimodem/V Compliant
¾ Low Power Consumption
¾ Operation Voltage 3.3V
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1.2.9 LAN PHY_ICS1893
The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is
based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. The
ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a
result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from
killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status
information with a Station Management (STA) entity. The ICS1893 Media Dependent Interface (MDI) can be
configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI
configuration can be established manually (with input pins or control register settings) or automatically (using the
Auto-Negotiation features). When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology
capability data with its remote link partner and automatically selects the highest-performance operating mode they
have in common.
1.2.10 PCMCIA controller_ ENE CB1410 + ENE CP2211
CB1410
¾ Ability to wake from D3
¾ 3.3V core logic with universal PCI interface compatible with 3.3V and 5V PCI signaling environment
¾ Mix-to-match 5V/3.3V 16 bit PC Cards and 3.3V CardBus Cards
¾ Single PC Card or CardBus slot with hot insertion and removal
¾ Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
HOT
and D3
COLD
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¾ Parallel PCI interrupts, parallel ISA IRQ and Parallel PCI interrupts, Serial ISA IRQ with Parallel PCI interrupts,
and Serial ISA IRQ and PCI interrupts
¾ Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
¾ Pipelined architecture allows greater than 130 Mbps sustained throughput from-CardBus-to-PCI and from-PCI-
to- CardBus
¾ Interface to parallel single-slot PC Card power interface switches
¾ Up to five general-purpose I/Os
¾ Programming output select for CLKRUN#
¾ Five PCI memory windows and two I/O windows available to the 16-bit PC Card Socket
¾ Two I/O windows and two memory windows available to the CardBus Socket
¾ Exchangeable Card Architecture ( ExCA ) compatible registers are mapped in memory I/O space
¾ Distributed DMA ( DDMA ) and PC/PCI DMA
¾ 16-Bit DMA on the PC Card Socket
¾ Ring indicate, SUSPEND#, PCI CLKRUN#, and CardBus CCLKRUN#
¾ Socket activity LED pins
¾ PCI Bus Lock ( LOCK# )
¾ Advanced Submicron, Low-Power CMOS Technology
¾ Internal Ring Qscillator
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CP2211 (Power Switch)
¾ Fully integrated VCCand VPPswitching
¾ Low r
DS(ON)
: 90-mΩ 5V and 3.3V VCCSwitches
¾ Compatible with industry standard controllers
¾ 12V supply not required unless the PC Card uses 12V for flash programming or other applications
¾ 3.3V low voltage mode
¾ Short-circuit and thermal protection
¾ Compatible with 3.3V, 5V, and 12V PC Cards
¾ Break-before-make switching
1.2.11 AC’97 Codec _ Realtek ALC201
¾ 20-bit Stereo Digital-to-Analog Converter and 18-bit Stereo Analog to Digital Converter with Sample Rate
Conversion
¾ Four Analog Line-level Stereo Inputs for Connection from LINE IN, CD, VIDEO, and AUX
¾ Two Analog Line-level Mono Inputs for Modem Sub-system and Internal PC Beeper
¾ Mono Microphone Input Switch able from Two External Sources
¾ High Quality Pseudo Differential CD Input
¾ Dual Stereo Line-level Outputs
¾ CrystalClear 3D Stereo Enhancement
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1.2.12 Thermal sensor_ ADM1021A
¾ On-Chip and Remote Temperature Sensing
¾ No Calibration Necessary
¾ 1_C Accuracy for On-Chip Sensor
¾ 3_C Accuracy for Remote Sensor
¾ Programmable Over/Under Temperature Limits
¾ Programmable Conversion Rate
¾ 2-Wire SMBus Serial Interface
¾ Supports System Management Bus (SMBus) Alert
¾ 200 _A Max Operating Current
¾ 1 _A Standby Current
¾ 3 V to 5.5 V Supply
¾ Small 16-Lead QSOP Package
1.2.13 System Flash Memory (BIOS)
¾ 2M bit Flash memory
¾ Flashed by 5V only
¾ User can upgrade the system BIOS in the future just running flash program.
¾ See Software BIOS Specification
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1.3 Other Functions
1.3.1 Hot Key Function
Keys
Feature Meaning
Combination
Fn + F1 Reserve
Fn + F2 Reserve
Fn + F3 Volume Down
Fn + F4 Volume Up
Rotate display mode in LCD only, CRT only and
Fn + F5 LCD/external CRT switching
simultaneously display.
Fn + F6 Brightness down Decreases the LCD brightness
Fn + F7 Brightness up Increases the LCD brightness
Fn + F8 Brightness MAX Toggle Max Brightness
Fn + F9 Pause
Fn + F10 Break
Fn + F11 Panel Off/On Toggle Panel Off/On
Force the computer into either Suspend to HDD
Fn + F12 Suspend to DRAM/HDD
or Suspend to RAM mode depending on BIOS
Setup.
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1.3.2 Power on/off/suspend/resume button
1.3.2.1 APM mode
At APM mode, Power button is on/off system power.
1.3.2.2 ACPI mode
At ACPI mode. Power button behavior was set by windows power management control panel.
You could set “standby” , “power off” or “hibernate”(must enable hibernate function in power
management) to power button function.
Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.3.3 Cover Switch
System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover.
At ACPI mode there are four functions to be chosen at windows power management control panel.
1. None
2. Standby
3. Off
4. Hibernate (must enable hibernate function in power management)
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1.3.4 LED Indicators
System has eight status LED indicators to display system activity, which include three at front side and five above
keyboard.
1.3.4.1 Three LED indicators at front side:
From left to right that indicate, AC POWER, BATTERY POWER and BATTERY STATUS
AC POWER: This LED lights green when the notebook is being powered by AC, and flash (on 1 second, off 1
second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by
batteries.
BATTERY POWER: This LED lights green when the notebook is being powered by Battery , and flash (on 1
second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the notebook is
off or powered by batteries, or when Suspend to Disk.
BATTERY STATUS: During normal operation, this LED stays off as long as the battery is charged. When the
battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC
is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being
charged.
1.3.4.2 Five LED indicators above keyboard:
From left to right that indicates LAN, CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK and SCROLL
LOCK.
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1.3.5 Battery status
1.3.5.1 Battery Warning
System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his
data before battery dead. Also, this function protects system from mal-function while battery capacity is low.
Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.
System will Suspend to HDD after 2 Minutes to protect users data.
1.3.5.2 Battery Low State
After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second.
1.3.5.3 Battery Dead State
When the battery voltage level reaches 7.6 volts, system will shut down automatically in order to extend the battery
packs' life.
1.3.6 Fan power on/off management
FAN is controlled by H8 embedded controller using AD2201 to sense CPU temperature and PWM control fan speed.
Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.
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1.3.7 CMOS Battery
¾ CR2032 3V 220mAh lithium battery
¾ When AC in or system main battery inside, CMOS battery will consume no power.
¾ AC or main battery not exist, CMOS battery life at less (220mAh/5.8uA) 4 years.
¾ Battery was put in battery holder, can be replaced
1.3.8 I/O Port
¾ One Power Supply Jack.
¾ One External CRT Connector For CRT Display
¾ One S-Video TV Output Connector
¾ Supports four USB port for all USB devices.
¾ One MODEM RJ-11 phone jack for PSTN line
¾ One RJ-45 for LAN.
¾ Headphone Out Jack.
¾ Microphone Input Jack.
¾ Line in Jack
¾ Line out Jack
¾ One CardBus Sockets for one type II PC card extension
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1.3.9 Battery current limit and learning.
Implanted H/Wcurrent limit and battery learning circuit to enhance protection of battery.
1.4 Peripheral Components
1.4.1 LCD PANEL
1stSource QDI 14.1” TFT: QD141X1LH03-MP01
nd
2
Source: Chi-Mei 14.1 TFT : N141X6-L0
Please reference the spec. for detail.
1.4.2 Ext. Floppy Disk Drive
External USB 3.5” 1.44MB /1.2 MB/720KB FDD (Option)
st
Source :Mitsumi D353FUE
1
nd
2
Source :NEC UF0002
1.4.3 HDD
Fujitsu 20GB: MHR2020AT / 30GB: MHR2030AT/ 40GB : MHR2040AT
Hitachi 20 GB: DK23DA-20F / 30GB DK23DA-30F/ 40GB DK23DA-40F
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1.4.4 DVD ROM Drive
1stsource :TEAC DV-28E-B93
nd
source: QSI SDR-083
2
1.4.5 COMBO Drive
1stsource : KME UJDA730-MT-A
nd
2
source : QSI SBW-161(16X Combo)
rd
3
source : NEC CB2100A
1.4.6 Keyboard
JME 19mm pitch/3.0mm stroke
1.4.7 Track Pad : Synaptics TM41PUM311-2
¾ Accurate positioning
¾ Low fatigue pointing action
¾ Low profile
¾ No moving part, high reliability
¾ Low power consumption
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¾ Environmentally sealed
¾ Compact size.
¾ Software configurable
¾ Low weight
¾ Operating temperature: 0 to 60 degree C
¾ Operating humidity : 5%-95% relative humidity, non condensing
¾ Storage temperature: -40 to +65 degree C
¾ ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01
¾ Power supply voltage : 5.0Voltage ± 10%
¾ Power supply current : 4.0mA max operating.
1.4.8 Fan
HY45J05-001
1.5 Power management
The Prestigio Cavaliere 141 system has built in several power saving modes to prolong the battery usage for mobile
purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup
(booting by pressing F2 key). Following are the descriptions of the power management modes supported.
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1.5.1 System Management Mode
1.5.1.1 Full on mode
In this mode, each devices is running with the maximal speed. CPU clock is up to its maximum.
1.5.1.2 Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can
save battery power without loosing much computing capability.
The CPU power consumption and temperature is lower in this mode.
1.5.1.3 Standby mode
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device:
--CPU: Stop grant
--LCD: backlight off
--HDD: spin down
1.5.1.4 Suspend to DRAM
The most chipset of the system is entering power down mode for more power saving. In this mode, the following is
the status of each device:
Suspend to DRAM
--CPU: off
--NB: Partial off
--VGA: Suspend
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--PCMCIA: Suspend
--Audio: off
--SDRAM: self Refresh
Suspend to HDD
--all devices are stopped clock and power-down
--System status is saved in HDD
--All system status will be restored when powered on again
1.5.2 Other power management functions
1.5.2.1 HDD & Video access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state
depending on the application. When the VGA activity monitoring is enabled, the performance of the system will
have some impact.
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1.6 Appendix 1: SiS961 GPIO Definitions
Pin name MUX Function GPIO Function Power plane
GPIO0 SPDIF GPIO MAIN
GPIO1 LDRQ1# GPIO MAIN
GPIO2 THERM# GPIO MAIN
GPIO3 EXTSMI# GPIO MAIN
GPIO4 CLKRUN# GPIO MAIN
GPIO5 PREQ5# GPIO MAIN
GPIO6 PGNT5# GPIO MAIN
GPIO7 GPWAK# GPIO AUX
GPIO8 RING GPIO AUX
GPIO9 AC_SDIN2 GPIO AUX
GPIO10 AC_SDIN3 GPIO AUX
GPIO11 STP_PCI#/CLK25
GPIO AUX
M
GPIO12 CPUSTP# GPIO AUX
GPIO13 DPRSLPVR GPIO AUX
GPIO14 AGPSTOP# GPIO AUX
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GPIO15 KBDAT/VGATEM GPIO AUX
GPIO16 KBCLK/LOHI# GPO AUX
GPIO17 PMDAT/VGATEM GPO AUX
GPIO18 PMCLK/RTC32KH
GPO AUX
Z
GPIO19 Reserved for CLK GPIO AUX
GPIO20 Reserved for Data GPIO AUX
GPIO21 EESK GPI AUX
GPIO22 EEDI GPI AUX
GPIO23 DDEO GPI AUX
GPIO24 EECS GPI AUX
APICD0 THERM2# MAIN
(GTL LEVEL)
APICD1 GPIOFF# MAIN
(GTL LEVEL)
APICCLK Reserved MAIN
OC5 GPI GPI AUX
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1.7 Appendix 2: Prestigio Cavaliere 141 product spec.
Model
CPU
Core L ogi c
L2 Cache
Sy st em B I OS
Memory
VGA Controller
Vi deo M emor y
CD- ROM/ DV D/ Combo
FDD
HDD
8677
Intel Pentium 4 Processor-M: 1.6GHz/1.7GHz/1.8GHz/1.9GHz/2.0GHz/2.2GHz/2.4GHz/2.6GHz
Intel Mobile Celeron Northwood: 1.4GHz/1.5GHz/1.7GHz/1.8GHz/2.0GHz/2.2GHz
FSB 400MHz
Nort h Bri dge: SiS650
Sout h Bri dge: SiS961
512KB on di e
Insyde 256KB Flash EPROM
-Includes System BIOS, VGA BIOS, and Plug & Play capability, ACPI
128 MB DDR SDRAM on board wi th one expansi on DDR 128M B/256MB modul e
-Support PC-266
SiS650 i ntegrated
8/16/32MB UMA
Internal 24X CD-ROM or DVD ROM, CD-RW, DVD Combo Drive
-Hei ght: 12.7mm I DE I /F
Ext ernal USB 3.5" 1.44MB/1.2MB/720KB FDD ( Opti on)
2.5" 20 GB /30GB /40GB HDD (9.5mm hei ght)
Suppor t A TA33/66/100
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Model
Display
Keyboard
Pointing Device
PCM C I A
Audio
I/O ports
8677
14.1" XGA TFT LCD
Windows 98 keyboard, multi languages support US and Europe
Gl i de pad wi t h 2 butt ons and scr oll butt on ( 4 di r ecti onal scr ol l)
1 Type I I sl ot, Card Bus por t suppor t
Two speak er (1W out put)
Build-in microphone
Build-in AC-Link Audio controller
Digital volume control
-VGA out
-USB 1.1 x 4
-DC input
-M icr ophone j ack x1
-Line in x1
-L i ne out x1
-TV out x1
-RJ-11 modem port x1
-RJ-45 LAN port x1
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Model
Communi cat i on
Battery
AC adapter
Dimensi ons
Wei ght
Sof t w ar e
Indicater
Col or cart on box
Friendly User’s I n t er f ac e
8677
56K MD C Fax modem
10/100 based- T L AN
8-cell Li-ON (4S2P) Battery
I nput:100-240V , 50/60 Hz A C,CPO
310x277x29mm(f ront si de) /33mm(back si de)
3.0Kg
Wi ndows 2000/M E/ XP/X P Pro
3 LEDs for Power/Battery status (on Inverter module)
5 LEDs f or CD-ROM, HDD, Num lock, Cap l ock and Scroll l ock (i n K eyboard Cover)
TBD
TBD
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2. System Assembly & Disassembly
2.1 System View
q
2.1.1 Front View
n Microphone Connector
o Audio Input Connector
n
p Audio Output Connector
q Top Cover Latch
p
o
2.1.2 Left-Side View
n VGA Port
o S-Video Output Connector
p RJ-45 Connector
q RJ-11 Connector
r PC Card Slot
44
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2.1.3 Right-Side View
n CD-ROM/DVD-ROM Drive
o USB Ports
p Power Connector
q Kensington Lock
2.1.4 Rear View
n Battery Charge Indicator
o Battery Power Indicator
p AC Power Indicator
q Battery Pack
n
q
nop
o
p
q
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2.1.5 Bottom View
n SO-DIMM cover
o CPU cover
p Hard Disk Drive cover
q Battery Pack
2.1.6 Top-Open View
n LCD Screen
o Stereo Speaker
p Keyboard
q Touch Pad
r Device LED Indicators
n
n
p
o
q
v
u
t
s
o
r
s Power Button
t Battery Charge Indicator
u Battery Power Indicator
v AC Power Indicator
o
p
q
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2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.2.1 Battery Pack
2.2.2 Keyboard
NOTEBOOK
Modular Components
LCD Assembly Components
Base Unit Components
47
2.2.3 CPU
2.2.4 HDD Module
2.2.5 CD/DVD-ROM Drive
2.2.6 SO-DIMM
2.2.7 LCD Assembly
2.2.8 LCD Panel
2.2.9 Inverter Board
2.2.10 System Board
2.2.11 Touch pad
2.2.12 Modem Card
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2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Pull the battery pack out of the compartment (o) while sliding and holding the release lever outwards to the “unlock”
( ) position (n). (Figure 2-1)
n
o
Figure 2-1 Remove the battery pack
n
Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a click-
ing sound.
2. Slide the release lever to the “lock” ( ) position.
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2.2.2 Keyboard
Disassembly
1. Remove the battery pack. (See section 2.2.1 disassembly)
2. Remove one screw fastening the LED cover on the bottom of the notebook. (Figure 2-2)
Figure 2-2 Remove one screw Figure 2-3 Remove the LED panel
3. Open the top cover. Slide and hold the LED panel to rightward. Feel the LED panel loose, then take it away.
(Figure 2-3)
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4. Slightly lift up the keyboard. Then disconnect the cable from system board to detach the keyboard. (Figure 2-4)
Figure 2-4 Disconnect the cable
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Fit the LED panel and secure by one screw.
3. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.3 CPU
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove two screws fastening the CPU compartment cover. (Figure 2-5)
Figure 2-5 Remove the CPU compartment cover Figure 2-6 Remove the heat sink
3. Remove four screws fastening the heat sink and disconnect the fan’s power cord to detach the heat sink from the CPU
compartment. (Figure 2-6)
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4. Push the lever to the right .Then lift up the lever to the vertical position .Finally remove the existing CPU.(Figure 2-7)
2
1
Figure 2-7 Remove the P4 CPU
Reassembly
1. Align the arrowhead corner of the CPU with the beveled corner of the socket, and insert the CPU pins into the holes.
Place the lever back to the horizontal position and push the lever to the left.
2. Reconnect the fan’s power cord to the system board, fit the heat sink onto the top of the CPU and secure with four
screws.
3. Replace the CPU compartment cover and secure with two screws.
4. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.4 HDD Module
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove two screws fastening the HDD compartment cover, and lift the cover up. (Figure 2-8)
Figure 2-8 Remove the HDD cover Figure 2-9 Remove the HDD drive
3. Slide the hard disk drive outwards to unplug the drive. (Figure 2-9)
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4. Remove four screws to separate the hard disk drive from the bracket. (Figure 2-10)
Figure 2-10 Free the HDD drive
Reassembly
1. To install the hard disk drive, place it in the bracket and secure with four screws.
2. Put the hard disk drive in the compartment and slide it inwards to plug.
3. Replace the HDD compartment cover and secure with two screws.
4. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.5 CD/DVD-ROM Drive
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove one screw that secures the CD/DVD-ROM drive. (Figure 2-11)
Figure 2-11 Remove one screw Figure 2-12 Remove CD/DVD-ROM
3. Put the notebook back to the upright position. Then insert a small rod, such as a straightened paper clip, into the
drive’s manual eject hole and push firmly to release the tray. Pull the tray out until fully extended, then carefully pull
harder to remove the CD/DVD-ROM drive. (Figure 2-12)
Reassembly
1. To replace the CD/DVD-ROM drive, slide and push it all the way into the compartment to plug.
2. Secure the CD/DVD-ROM drive with one screw.
3. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.6 SO-DIMM
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove one screw fastening the memory compartment cover to access the SO-DIMM socket. (Figure 2-13)
Figure 2-13 Remove the cover Figure 2-14 Remove the SO-DIMM
3. Pull the retaining clips outwards (n) and remove the SO-DIMM (o). (Figure 2-14)
Reassembly
1. To install the SO-DIMM, match the SO-DIMM's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the SO-DIMM into
position.
2. Replace one screws to fasten the memory compartment cover.
3. Replace the battery pack. (See section 2.2.1 reassembly)
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2.2.7 LCD Assembly
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Remove the LED cover. (See the step 1—3 of section 2.2.2 disassembly)
3. Open the top cover. Then remove the two hinge covers. (See Figure 2-15.)
Figure 2-15 Remove two hinge covers Figure 2-16 Separate the LCD assembly
2. Disconnect the two LCD cables from the system board, and remove four screws of the hinges. Now you can separate
the LCD assembly from the base unit. (Figure 2-16)
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws of the hinges.
2. Reconnect the LCD cables to the system board. And replace two hinge covers
3. Replace the LED panel and battery pack. (See section 2.2.1 and 2.2.2 reassembly)
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2.2.8 LCD Panel
Disassembly
1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)
2. Upturn the notebook, remove the LCD assembly. (See section 2.2.7 Disassembly.)
3. Remove the four rubber pads and four screws on the corners of the panel. (Figure 2-17)
Figure 2-17 Remove LCD frame Figure 2-18 Remove LCD panel
4. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out. Repeat the process until the
frame is completely separated from the housing.
5. Remove the four screws on two sides of LCD panel, and disconnect the cable from the inverter board. (Figure 2-18)
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6. Remove the four screws fastening the LCD bracket on side of the LCD panel. (Figure 2-19)
Figure 2-19 Remove the LCD bracket
Reassembly
1. Attach the LCD bracket on the LCD panel and secure with four screws.
2. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board.
3. Fit the LCD frame back into the LCD housing and replace the four screws and four rubber pads.
4. Replace the LCD assembly and battery pack. (See section 2.2.1and 2.2.7 reassembly.)
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2.2.9 Inverter Board
Disassembly
1. Remove the LCD assembly and detach the LCD frame (see instructions in previous two sections).
2. To remove the inverter board on the bottom of the LCD assembly, disconnect the cable and remove two screw.
(Figure 2-20)
Figure 2-20 Remove the inverter board
Reassembly
1. Fit the inverter board back into place and secure with two screw.
2. Reconnect the cable.
3. Replace the LCD frame. (See section 2.2.8 Reassembly.)
4. Replace the LCD assembly. (See section 2.2.7 Reassembly.)
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2.2.10 System Board
Disassembly
1. Remove the battery pack, LED panel, heat sink, HDD module, CD/DVD-ROM drive and LCD assembly.
(See the Disassembly parts in previous sections.)
2. Remove the keyboard (See section 2.2.2 disassembly) and disconnect the touch pad cable from system board.
(Figure 2-21)
Figure 2-21 Remove the touch pad cable Figure 2-22 Remove the sixteen screws
4. Remove sixteen screws on the bottom of the notebook. (Figure 2-22)
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5. Remove seven screws on the battery pack compartment of the notebook. Then remove the bottom housing.
(Figure 2-23)
o
n
Figure 2-23 Remove seven screws Figure 2-24 Loose the system board
6. Remove one screw fastening the charge board and disconnect the right speaker cable( ) , then disconnect the
connector from system board slot( ). (Figure 2-24)
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7. Remove six screws and two nuts fastening the system board on the cover assembly .Then disconnect the left speaker
cable from the system board. (Figure 2-25)
Figure 2-25 Remove the system board Figure 2-26 detach the LED board
8. Disconnect the LED board connector from system board slot. (Figure 2-26)
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Reassembly
1. Reconnect the LED board to system board.
2. Fit the system board back into cover assembly and secure with six screws and two nuts. Then reconnect the left
speaker cable.
3. Replace the charge board and secure with one screw. Then reconnect the right speaker cable.
4. Fit the bottom housing and secure with twenty three screws.
5. Reconnect the touch pad and keyboard cable.
6. Replace the heat sink, HDD module, CD/DVD-ROM drive LCD assembly , keyboard and battery pack.
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2.2.11 Touch pad
Disassembly
1. Remove the system board. (See section 2.2.10disassembly)
2. Remove the four screws to lift up the touchpad holder and touchpad panel. (Figure 2-27)
Figure 2-27 Remove the touch pad holder Figure 2-28 Remove the touch pad shield
3. To tack the touch pad out, remove the ten screws fastening the touch pad shield. (Figure 2-28)
Reassembly
1. Replace the touch pad and fit the touch pad shield on it.
2. Fasten the touch pad shield by ten screws.
3. Replace the touchpad holder and secure with four screws.
4. Assemble the notebook. (See section 2.2.10 Reassembly.)
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2.2.12 Modem Card
Disassembly
1. Remove the battery pack, LED panel, heat sink, HDD module, CD/DVD-ROM drive and LCD assembly.
(See the Disassembly parts in previous sections.)
2. Disassembly the notebook to access the system board . (See section 2.2.10disassembly)
3. Remove the two screws fastening the modem card, and then disconnect the cable from system board . (Figure 2-29)
Figure 2-29 Remove the modem card
Reassembly
1. Reconnect the cable to modem card and secure the modem card with two screws.
2. Assemble the notebook. (See section 2.2.10disassembly)
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3. Definition & Location of Connectors / Switches
3.1 Mother Board-A
J502
J504
J506
J508
J509
J510
J511
J515
J514
J513
J509
J502 : LED Board Connector
J504 : VGA Connector
J505 : Primary IDE Connector
J506 : TV Out Connector
J508 : LAN Connector(RJ45)
J509 : DDR Socket
J510 : RJ11
J511 : PCMCIA Socket
J512 : Secondary IDE Connector
J513 : Line In
J514 : Line Out
J515 : MIC In
J505
J512
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3. Definition & Location of Connectors / Switches
3.2 Mother Board-B
J1 : LCD Connector
SW7
SW5
SW6
SW2
SW3
SW4
J7
J5
J4
J3
J2
J1
J2 : LCD Inverter Board Connector
J3 : Charge Board Connector
J4 : Internal KB Connector
J5 : Touch Pad Connector
J7 : Transform Board Connector(MDC)
SW2 : SW_LEFT
SW3 : SCRL_UP
SW4 : SW_RIGHT
SW5 : SCRL_LEFT
SW6 : SCRL_RIGHT
SW7 : SCRL_DOWN
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3. Definition & Location of Connectors / Switches
3.3 Charge Board
Side A
J1 : Charge Board to MB Connector
J1
Side B
J501
J504
J503
PJ501
J501 : Battery Connector
J503,J504 : USB Connector
PJ50 : Power Jack
Right Side View
PJ501
J503
J504
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4. Definition & Location of Major Components
4.1 Mother Board-A
U503
U506
U505
U50
5
U507
U509
U504
U505
U506
U507
U508
U510
U514
U513
U512
U511
U516
U517
J509
U503 : SiS301LV(LVDS Interface)
U505 : SiS650(North Bridge)
U506 : P4 478 CPU Socket(Mobile P4)
U507 : ES824(DATA Buffer)
U508 : ICS952001(Clock Generator)
U509 : ICS1893(LAN PHY)
U510 :ICS93722(DDR Clock Buffer)
U511 : On Board DDR RAM
U512 : On Board DDR RAM
U513 : On Board DDR RAM
U514 : On Board DDR RAM
U516 : SiS961 ( South Bridge)
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4. Definition & Location of Major Components
4.2 Mother Board-B
U11 : CP2211(Card Bus Power Controller)
U13 : F3437(H8)
U11
U19 : PC87393(Super I/O)
U13
U19
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4. Definition & Location of Major Components
4.3 Charge Board
Side A
PU9
PU9 :TL594C Pulse-Width-Modulation Controller
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5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
The Coordinates of the
Processor Pins as Viewed
From the Top of the Package
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5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Signal Description
Pin Name Type/No. Descr iption
A[35:3]#
A20M#
ADS# Input/ Output ADS# (Address Strobe) is asserted to indicate the validity of the
ADSTB[1:0]# Input/
AP[1:0]#
Input/
Output
Input
Output
Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address
space. In subphase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of all agents on the Mobile Intel Pentium 4
Processor-M system bus. A[35:3]# are protected by parity signals
AP[1:0]#. A[35:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples
a subset of the A[35:3]# pins to determine power-on configuration.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.Asserting
A20M# emulates the 8086 processor's address wrap-around at the
1-Mbyte boundary. Assertion of A20M# is only supported in real
mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
transaction
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
Signals
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]# ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along
with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A
correct parity signal is high if an even number of covered signals are
low and low if an odd number of covered signals are low. This allows
parity to be high when all the covered signals are high.
AP[1:0]# should connect the appropriate pins of all Mobile Intel
Pentium 4 Processor-M system bus agents. The following table
defines the coverage model of these signals.
Request Signals
A[35:24]# AP0# AP1#
A[23:3]# AP1# AP0#
REQ[4:0]# AP1# AP0#
Associated Strobe
subphase 1
subphase 2
Pin Name Type/No.
BCLK[1:0] Input
BINIT#
BNR#
BPM[5:0]#
74
Input/
Output
Input/
Output
Input/
Output
Description
The differential pair BCLK (Bus Clock) determines the system
bus frequency. All processor system bus agents must receive
these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing V
BINIT# (Bus Initialization) may be observed and driven by all
processor system bus agents and if used, must connect the appropriate
pins of all such agents. If the BINIT# driver is enabled during
power-on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and
BINIT# is sampled asserted, symmetric agents reset their bus LOCK#
activity and bus request arbitration state machines. The bus agents do
not reset their IOQ and transaction tracking state machines upon
observation of BINIT# activation. Once the BINIT# assertion has
been observed, the bus agents will re-arbitrate for the system bus and
attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a
central agent may handle an assertion of BINIT# as appropriate to the
error handling architecture of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals.
They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring
processor performance. BPM[5:0]# should connect the appropriate
pins of all Mobile Intel Pentium 4 Processor-M system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of the
processor.
Please refer to the Mobile Intel. Pentium. 4 Processor-M and Intel.
845MP/845MZ Chipset Platform Design Guide and ITP700 Debug
Port Design Guide for more detailed information.
These signals do not have on-die termination and must be
ter minated on the system boar d.
CROSS
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5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name Type/No.
BPRI#
BR0#
BSEL[1:0]
D[63:0]#
Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
Input/
Output
Output BSEL[1:0] (Bus Select) are used to select the processor input clock
Input/
Output
Description
processor system bus. It must connect the appropriate pins of all
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this pin
is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
frequency. associated with each combination. The required frequency
is determined by the processor, chipset, and clock synthesizer. All
agents must operate at the same frequency. The Mobile Intel Pentium
4 Processor-M operates at a 400-MHz system bus frequency (100
MHz BCLK[1:0] frequency). For more information about these pins,
including termination recommendations refer to the appropriate
platform design guidelines.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data pathbetween the processor system bus agents, and must connect
the appropriate pins on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times
in a common clock period. D[63:0]# are latched off the falling edge
of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data
signals correspond to a pair of one DSTBP# and one DSTBN#. The
following table shows the grouping of data signals to data strobes and
DBI#.
Quad-Pumped Signal Groups
Furthermore, the DBI# pins determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DBI# signal. When
the DBI# signal is active, the corresponding data group is inverted
and therefore sampled active high.
Dat a Gr oup
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
DSTBN#/
DSTBP #
DBI#
Pin Name Type/No. Descr iption
DBI[3:0]# Input/
DBR# Output DBR# (Data Bus Reset) is used only in processor systems where no
DBSY# Input/
DEFER#
DP[3:0]#
DPSLP#
DSTBN[3:0]# Input/
75
Output
Output
Input DEFER# is asserted by an agent to indicate that a transaction cannot
Input/
Output
Input DPSLP# when asserted on the platform causes the processor to
Output
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate
the polarity of the D[63:0]# signals. The DBI[3:0]# signals are
activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within the
covered group, would change level in the next cycle.
DBI[3:0] Assignment To Data Bus
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor system bus to indicate that the data bus
is in use. The data bus is released after DBSY# is deasserted. This
signal must connect the appropriate pins on all processor system bus
agents.
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of all processor system
bus agents.
DP[3:0]# (Data parity) provide parity protection for the D[63:0]#
signals. They are driven by the agent responsible for driving
D[63:0]#, and must connect the appropriate pins of all Mobile Intel
Pentium 4 Processor-M system bus agents.
transition from the Sleep State to the Deep Sleep state. In order to
return to the Sleep State, DPSLP# must be deasserted and BCLK[1:0]
must be running.
Data strobe used to latch in D[63:0]#.
Bus Signa l Da ta Bu s Signals
DBI3#
DBI2#
DBI1#
DBI0#
Signa ls
D[15:0]#, DBI0# DSTBN0#
D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Associated Str obe
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5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name Type/No. Descr iption
DSTBP[3:0]# Input/
DRDY#
FERR#/PBE# Output FERR#/PBE# (floating point error/pending break event) is a
GHI#
Output
Input/
Output
Input The GHI# signal controls the selection of the operating mode bus
Data strobe used to latch in D[63:0]#.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of all processor system
bus agents.
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/ PBE#
is similar to the ERROR# signal on the INTEL 387 coprocessor, and
is included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will
remain asserted until STPCLK# is deasserted. For additional
information on the pending break event functionality, including the
identification of support of the feature and enable/disable information,
refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID
Instruction application
note.
ratio and voltage in the Mobile Intel Pentium 4 Processor-M. On the
Mobile Intel Pentium 4 Processor-M featuring Enhanced Intel
SpeedStep technology, this signal is latched on entry to Sleep state
and is observed during the Deep Sleep state. GHI# determines which
of two performance states is selected for operation. This signal is
ignored when the processor is not in the Deep Sleep state. This signal
should be driven with an Open-drain driver. For connection and
termination guidelines refer to the Mobile Intel.Pentium.4
Processor-M and Intel.845MP/845MZ Chipset Platform Design
Guide.
Signa ls Associa ted Str obe
D[15:0]#, DBI0# DSTBP0#
D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#
Pin Name Type/No. Descr iption
GTLREF
COMP[1:0]
HIT#
HITM#
IERR#
IGNNE#
INIT#
Input GTLREF determines the signal reference level for AGTL+ input pins.
Analog COMP[1:0] must be terminated on the system board using precision
Input/
Output
Input/
Output
Output IERR# (Internal Error) is asserted by a processor as the result of an
Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to
Input INIT# (Initialization), when asserted, resets integer registers inside
GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1. Refer to
the Mobile Intel. Pentium. 4 Processor-M and Intel. 845MP/845MZ
Chipset Platform Design Guide for more information.
resistors.Refer to the Mobile Intel. Pentium. 4 Processor-M and Intel.
845MP/845MZ Chipset Platform Design Guide for details on
implementation.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any system bus agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall, which
can be continued by reasserting HIT# and HITM# together.
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This
transaction may optionally be converted to an external error signal
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
This signal does not have on-die termination and must be
terminated on the system boar d.
ignore a numeric error and continue to execute noncontrol
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a noncontrol floating-point instruction if a
previous floating-point instruction caused an error. IGNNE# has no
effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding
Input/Output Write bus transaction.
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on Reset
vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal and must connect the appropriate pins of all
processor system bus agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
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5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name Type/No. Descr iption
ITPCLKOUT
1:0]
ITP_CLK[1:0] Input ITP_CLK[1:0] are copies of BCLK that are used only in processor
LINT[1:0]
LOCK#
REQ[4:0]# Input/
Output ITPCLKOUT[1:0] is an uncompensated differential clock output that
Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
Input/
Output
Output
is a delayed copy of the BCLK[1:0], which is an input to the
processor. This clock output can be used as the differential clock into
the ITP port that is designed onto the motherboard. If
ITPCLKOUT[1:0] outputs are not used, they must be terminated
properly. Refer to the ITP700 Debug Port Design Guide for details on
implementing a debug port.
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of all
processor system bus agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor system bus, it will wait until it observes LOCK#
deasserted. This enables symmetric agents to retain ownership of the
processor system bus throughout the bus locked operation and ensure
the atomicity of lock.
REQ[4:0]# (Request Command) must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals
are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal
description for details on parity checking of these signals.
Pin Name Type/No. Descr iption
MCERR# Input/
Output
PROCHOT# Output The assertion of PROCHOT# (Processor Hot) indicates that the
PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor
RESET# Input Asserting the RESET# signal resets the processor to a known state
MCERR# (Machine Check Error) is asserted to indicate an
unrecoverable error without a bus protocol violation. It may be driven
by all processor system bus agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus
transaction after it observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, please refer to
the IA-32
Software Developer’s Manual, Volume 3: System Programming
Guide.
processor die temperature has reached its thermal limit. See Section 6
for more details.
requires this signal to be a clean indication that the clocks and power
supplies are stable and within their specifications. ‘Clean’ implies that
the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on
until they come within specification. The signal must then transition
monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all system bus agents
will deassert their outputs within two clocks. RESET# must not be
kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration.
This signal does not have on-die termination and must be
ter min ated on the system boa r d.
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b
5. Pin Descriptions of Major Components
5.1 Mobile Intel Pentium 4 Processor-M
Pin Name Type/No. Description
VCCSENSE
VCCVID
VID[4:0]
SSA
V
SSSENSE
V
Output VCCSENSE is an isolated low impedance connection to processor
Input Independent 1.2-V supply must be routed to VCCVID pin for the
Output VID[4:0] (Voltage ID) pins are used to support automatic selection of
Input V
Output V
core power (VCC). It can be used to sense or measure power near the
silicon with little noise.
Mobile Intel Pentium 4 Processor-M’s Voltage Identification circuit.
power supply voltages (Vcc). Unlike some previous generations of
processors, these are open drain signals that are driven by the Mobile
Intel Pentium 4 Processor-M and must
e pulled up to 3.3V (max.) with 1Kohm resistors. The voltage supply
for these pins must be valid before the VR can supply Vcc to the
processor. Conversely, the VR output must be disabled until the
voltage supply for the VID pins becomes valid. The VID pins are
needed to support the processor voltage specification variations.The
VR must supply the voltage that is requested by the pins, or disable
itself.
SSA
is the isolated ground for internal PLLs.
SSSENSE
is an isolated low impedance connection to processor core
SS
. It can be used to sense or measure ground near the silicon with
V
little noise.
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5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
Host BUS Interface
Name Pin Attr Signal Description
RS[2:0]#
HTRDY#
DRDY#
DBSY#
HD[63:0]#
DBI[3:0]#
HDSTBP[3:0]# I/O
HDSTBN[3:0]# I/O
HNCOMP
O
1.2~1.85V – M
O
1.2~1.85V – M
I/O
1.2~1.85V – M
I/O
1.2~1.85V – M
I/O
1.2~1.85V – M
I/O
1.2~1.85V – M
1.2~1.85V – M
1.2~1.85V– M
I
M
Response Status:
RS[2:0]# are driven by the response agent to indicate the
transaction response type. The following shows the response
type.
RS[2:0] Response
000 Idle State
001 Retry
010 Defer
011 Reserved
100 Reserved
101 No data
110 Implicit Write-back
111 Normal Data
Target Ready:
During write cycles, response agent will drive TRDY# to
indicate it is ready to accept data.
Data Ready:
DRDY# is driven by the bus owner whenever the data is valid
on the bus.
Data Bus Busy:
Whenever the data is not valid on the bus with DRDY# is
deserted, DBSY# deasserted to hold the bus.
Data Bus Busy:
Whenever the data is not valid on the bus with DRDY# is
deserted, DBSY# deasserted to hold the bus.
Dynamic Bus Inversion: An active DBI# will invert
it’s corresponding data group signals.
DBI0# is referenced by HD[15:0],
DBI1# is referenced by HD[31:16]
DBI2# is referenced by HD[47:32]
DBI3# is referenced by HD[63:48]
Source synchronous data strobe used to latch data at falling edge
HD[15:0], DBI0# are latched by HDSTBP0#
HD[31:16], DBI1# are latched by HDSTBP1#
HD[47:32], DBI2# are latched by HDSTBP2#
HD[63:48], DBI3# are latched by HDSTBP3#
Source synchronous data strobe used to latch data at falling edge
HD[15:0], DBI0# are latched by HDSTBN0#
HD[31:16], DBI1# are latched by HDSTBN1#
HD[47:32], DBI2# are latched by HDSTBN2#
HD[63:48], DBI3# are latched by HDSTBN3#
GTL N-MOS Compensation Input
Host BUS Interface Continue
Name Pin Attr Signal Description
CPUCLK
CPUCLK#
CPURST#
CPUPWRGD#
ADS#
HADSTB[1:0]#
1.2~1.85V – M
HREQ[4:0]# I/O
HA[31:3]#
BREQ0#
BPRI#
BNR#
HLOCK#
HIT#
HITM #
DEFER#
I
0.71V – M
O
1.2~1.85V – M
I/O
O
1.2~1.85V – M
1.2~1.85V – M
1.2~1.85V – M
I/O
1.2~1.85V – M
O
1.2~1.85V – M
O
1.2~1.85V – M
I/O
1.2~1.85V – M
I
1.2~1.85V – M
I/O
1.2~1.85V – M
I/O
1.2~1.85V – M
O
1.2~1.85V – M
Host differential clock input.
Host Bus Reset:
CPUR ST# is used to keep all the bus agents in
the same initial state before valid cycles issued.
CPUPWRGD# is used to inform CPU that main power is stable
Address Strobe :
Address Strobe is driven by CPU or SiS650 to indicate the start
of a CPU bus cycle.
Source synchronous address strobe used to latch
HREQ[4:0]# & HA[31:3]# at both falling and rising edge.
HREQ[4:0]# & HA[16:3]# are latched by
HASTB0#
HA[31:17] are latched by HASTB1#
Request Command:
HREQ[4:0]# are used to define each transaction type during the
clock when ADS# is asserted and the clock after ADS# is
asserted.
Host Address Bus
Symmetric Agent Bus Request:
BREQ0# is d riven by the sym metric agen t to request for the
bus.
Priority Agent Bus Request:
BPRI# is driven by the priority agent that wants to request the
bus.
BPRI# has higher priority than BREQ0# to access a bus.
Block Next Request:
This signal can be driven asserted by any bus agent to block
further requests being pipelined.
Host Lock :
CPU asserts HLOCK# to indicate the current bus cycle is
locked.
Keeping a Non-Modified Cache Line
Hits a Modified Cache Line:
Hit Modified indicates the snoop cycle hits a modified line in
the L1/L2 cache of C PU.
Defer Transaction Com pletion:
defer response to host bus.
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5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
Host BUS Inter face Continue
Name Pin Attr Signal Description
HPCOMP
HVREF[4:0]
HNCOMPVREFI M
I
M
GT L P-MOS Compensation Input
AGTL+ I/O reference voltage
DRAM Contr oller
Name Pin Attr Signal Description
SD CL K
SD RCL KI
FWDSDCLKO O
MA[14:0]
SRA S#
SCA S#
SW E #
CS[5:0]#
CSB[5:0]#
DQM[7:0]# O
DQS[7:0]
MD[63:0]
CKE[5:0]
S3AUXSW#
(CKE6)
DDRVREF[A:B] I
I
3.3V - M
I
2.5V/3.3V - M
2.5V/3.3V – M
O
2.5V/3.3V - M
O
2.5V/3.3V - M
O
2.5V/3.3V - M
O
2.5V/3.3V - M
O
2.5V/3.3V - M
2.5V/3.3V - M
I/O
2.5V/3.3V - M
I/O
2.5V/3.3V - M
O (open-drain)
2.5V/3.3V –
AUX
O (open-drain)
2.5V/3.3V AUX
M
SDRAM Clock Input
SDRAM Read Clock Input
SDRAM Forward Clock Out put
Syst em Mem o ry Address Bus
SDRAM Ro w Address Stro be
SDRA M Co lum n A ddress St ro be
SDRAM W rite En able
SDRAM Ch ip Select
CSB[5:0] multiplexed with DQS[5:0]
SDRAM Input/Output Data Mask
DDR Data Strobe
Syst em Me m o ry D at a Bus
SDRAM Clo ck Enable
Aux power switch for ACPI-S3 state, low active.
DDR I/O Reference Voltage
Power and Ground Signals
Nam e T oler an ce Power Pla ne Type Attr ibu te
C4XAVDD 3.3V MAIN Analog
C4XAVSS 0V GROUND Analog
DACAVDD1 1.8V MAIN Analog
DACAVDD2 1.8V MAIN Analog
DACAVSS1 0V GROUND Analog
DACAVSS2 0V GROUND Digital
DCLKAVDD 3.3V MAIN Digital
DCLKAVSS 0V GROUND Analog
DDRAVDD 3.3V MAIN Analog
DDRAVSS 0V GROUND Analog
ECLKAVDD 3.3 MAIN Analog
ECLKAVSS 0V GROUND Analog
IVDD
OVDD 3.3V MAIN Digital
PVDD 3.3V MAIN Digital
PVDDM
PVDDP
PVDDZ 1.8V MAIN Digital
SDAVDD
SDAVSS
VDDM
VDDQ
VDDZ
VDDMCMP 1.8V MAIN Analog
VTT
Z1XAVDD 3.3V MAIN Analog
Z1XAVSS 0V GROUND Analog
Z4XAVDD 3.3V MAIN Analog
Z4XAVSS 0V GROUND Analog
1.8V MAIN Digital
3.3V AUX Digital
1.8V MAIN Digital
3.3V MAIN Analog
0V GROUND Analog
2.5/3.3V MAIN(AUX) Digital
1.5/1.8/3.3V MAIN Digitalv
1.8V MAIN Digital
1.2~1.85V MAIN Digital
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5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
Power and Ground Signals Continue
Nam e Toleran ce Power P lane Typ e Attr ibu te
A1XAVDD 3.3V MAIN Analog
A1XAVSS 0V GROUND Analog
A4XAVDD 3.3V MAIN Analog
A4XAVSS 0V GROUND Analog
AGPVSSREF 0V GROUND Analog
AUX1.8
AUX3.3
C1XAVDD 3.3V MAIN Analog
C1XAVSS 0V GROUND Analog
1.8V AUX Digital
3.3V AUX Digital
VGA Interface
Name Pin Attr Signal Descr iption
VOSCI
HSYNC
VSYNC
INTA#
VGPIO[1:0] I/O
VCOMP
VRSET
VVBWN
ROUT
GOUT
BOUT
I
3.3V - M
O
3.3V - M
O
3.3V - M
O
3.3V - M
3.3V - M
AI
Analog - M
AI
Analog - M
AI
Analog - M
AO
Analog - M
AO
Analog - M
AO
Analog - M
14.318 Reference Clock Input
Horizontal Sync
Vertical Sync
Internal VGA Interrupt Pin
Internal VGA GPIO pins
Compensation Pin
Reference Resistor
Voltage Reference
Red Signal Output
Green Signal Output
Blue Signal Output
SiS MuT IOL Inter face
Signal Name Pin Attr Signal Description
ZCLK I
3.3V-M
ZUREQ/ZQREQ I/O
1.8-M
ZSTB[1:0] I/O
1.8-M
ZSTB[1:0]# I/O
1.8-M
ZAD[15:0] I/O
1.8-M
ZVREF I
M
ZCMP_N I
M
ZCMP_N I
M
AGPCLK I
3.3V – M
AFRAME# I/O
1.5V/3.3V - M
AIRDY# I/O
1.5V/3.3V - M
ATRDY# I/O
1.5V/3.3V - M
ASTOP# I/O
1.5V/3.3V - M
ADEVSEL# I/O
1.5V/3.3V - M
ASERR# I/O
1.5V/3.3V - M
AREQ# I/O
1.5V/3.3V - M
AGNT# I/O
1.5V/3.3V - M
AAD[31:0] I/O
1.5V/3.3V - M
AC/BE[3:0 I/O
1.5V/3.3V - M
APAR I/O
1.5V/3.3V - M
ST[2:0] O
1.5V/3.3V - M
SiS MuTIOL Connect
SiS MuTIOL Connect Control pins
SiS MuTIOL Connect Strobe
Strobe Compliment
I/O
1.8V - M
SiS MuTIOL Connect Reference Voltage
N-MOS Compensation Input
P-MOS Compensation Input
AGP Clock
AGP Frame#
AGP Initiator Ready
AGP Target Ready
AGP Stop#
AGP Device Select
AGP System Error
AGP Bus Request
AGP Bus Grant
AGP Address/Data Bus
AGP Command/Byte Enable
AGP Parity
AGP Status Bus
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p
5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
SiS MuTIOL Inter face
Name P in Att r Signa l Descr ip tion
PIPE#
SBA[7:0]
RBF#
WBF#
AD_STB[1:
0]
AD_STB[1:
0]#
SB_STB
SB_STB#
I
1.5V/3.3V - M
I/O
1.5V/3.3V - M
I
1.5V/3.3V - M
I
1.5V/3.3V - M
I/O
1.5V/3.3V - M
I/O
1.5V/3.3V - M
I
1.5V/3.3V - M
I
1.5V/3.3V - M
AGP Pipeline Request
Side Band Address
Read Buffer Full
Write Buffer Full
AD Bus Strobe
AD Bus Strobe Compliment
Side Band Strobe
Side Band Strobe Compliment
Ster eo Glasses Interface
Name Pin Attr Signal Description
CSYNC
RSYNC
LSYNC
O
3.3V - M
O
3.3V - M
O
3.3V - M
Stereo Clock
St er e o Righ t
St er e o Le f t
Test Mode/Hardwar e Trap/Power Management
Name Pin Attr Signal Description
DLLEN#
DRAM_SEL I
TRAP [1:0]
ENTEST
TESTMOD
E[2:0]
AUXOK
PCIRST#
PW ROK
I/O
3.3V/5V - M
3.3V/5V - AUX
I
3.3V/5V - M
I
3.3V/5V - M
I
3.3V/5V - M
I
3.3V - AUXI
I
3.3V - AUXI
I
3.3V - AUXI
Hardware T rap pin (refer to section 5)
Hardware T rap pin (refer to section 5)
Hardware T rap pins (refer to sect ion 5)
Test Mode enable pin
T est Mo de select pin
Nand Tree Test: 100
Auxiliary Power OK :
This signal is supplied from the power source of resume well. It
is also used t o reset the logic in resume power well. If there is
no auxiliary power source on the system, this pin should be tie
together with PWROK.
PCI Bus Reset :
PCIRST # is supplied from SiS MuTIOL Media IO SiS961.
Main Power OK :
A high-level input to this signal indicates the power being
supp lied to t he syst em is in st able o p er at ing st a t e. During the
er io d o f P W ROK being low, CP URST and P CI RST # will all
be assert ed unt il aft er P WROK goes h igh fo r 2 4 ms.
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5. Pin Descriptions of Major Components
5.2 SiS650 (IGUI Host Memory Controller )
VB Inter face
Name Pin Attr Signal Description
VBC LK
VBH CL K
VBCAD
VBCTL[1:0] O
VGPIO[3:2] I/O
VBHSYNC
VBVSY N C
VBD E
VBGC LK
VBD[11:0]
VAHSYNC
VAVSYNC
VADE
VA GCL K
VA GCL K#
VAD[11:0] I/O
I
1.8V/3.3V - M
O
1.8V/3.3V – M
I/O
1.8V/3.3V – M
1.8V/3.3V - M
3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
I/O
1.8V/3.3V - M
1.8V/3.3V - M
Channel B/A Clock Input
VBCLK multiplexed with SBA0
VB Programming Int erface Clock
VBHCLK multiplexed with RBF#
VB Programming Int erface Dat a
VBCAD multiplexed wit h AREQ#
VB Data Control
VBCTL[1:0] multiplexed with AAD[29:28]
VB GPIO pins
VGPIO[3:2] multiplexed with PIPE#/WBF#
Channel B H-Sync
VBHSYNC multiplexed with AAD30
Channel B V-Sync
VBVSYNC multiplexed with AAD31
Channel B Dat a Valid
VBDE multiplexed with AAD27
Channel B Clock Output.
This clock is used to trigger dual edge data transfer.
Perfect dut y cycle is required.
VBGCLK mult iplexed wit h AD_STB1
Channel B Dat a
VBD[11:0] multiplexed wit h AAD
Channel A H-Sync
VAHSYNC multiplexed wit h AAD18
Channel A V-Sync
VAVSYNC multiplex ed wit h AAD17
Channel A Data Valid
VADE multiplexed with AAD16
Channel A Clock Output.
This clock is used to trigger dual edge data transfer.
Perfect dut y cycle is required.
VAGCLK multiplexed wit h AD_STB0
Channel A Differential Clock Output. (To support
Chrontel).
VAGCLK# multiplexed with AD_STB0#
Channel A Data
VAD[11:0] multiplexed with AAD
VGA Interface
Name Pin Attr Signal Description
VO SC I
HSYNC
VSYNC
INTA#
VGPIO[1:0] I/O
VCO MP
VRSE T
VVBW N
ROUT
GOUT
BOUT
I
3.3V - M
O
3.3V - M
O
3.3V - M
O
3.3V - M
3.3V - M
AI
Analog - M
AI
Analog - M
AI
Analog - M
AO
Analog - M
AO
Analog - M
AO
Analog - M
14.318 Reference Clock Input
Horizontal Sync
Vertical Sync
Internal VGA Interrupt Pin
Internal VGA GPIO pins
Com p ensat ion Pin
Reference Resistor
Voltage Reference
Red Sign a l Out put
Green Signal Out put
Blue Signa l O ut p ut
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5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
MuTIOL Connect In ter face
Name Pin Attr Signal Description
ZCLK I
ZUREQ
ZDREQ
ZSTB[1:0]
ZST B[1:0]#
ZAD[15:0]
ZVRE
ZCMP_N I -M N-MOS Compensation Input
ZCMP_P I -M
3.3V - M
I/O
1.8V - M
I/O
1.8V - M
I/O
1.8V - M
I/O
1.8V - M
I/O
1.8V - M
I -M Megaband I/O Connect I/O reference voltage
Megaband I/O Connect Clock
Megaband I/O Conect Controll pins
Megaband I/O Conect Controll pins
Megaband I/O Connect Strobe
Strobe Compliment
Address/Data pins
P-MOS Compensation input
General Purpose I/O
Signal Name Pin Attr Signal Description
GPIO[6:0]
GPIO14,[12:7] I/O
GPIO13
GPIO[18:15]
GPIO[20:19]
I/O
3.3V/5V -M
3.3V/5V -AUX
O
3.3V/5V - AUX
O
3.3V/5V - AUX
I/O
3.3V/5V - AUX
GPIO:
Can be a general purpose input or output.
GPIO :
Can be a general purpose input or output.
GPO:
Can be a general purpose output.
GPO:
Can be a general purpose output.
GPIO:
Can be a general purpose input or output.
Host Bus Inter fa ce
Name Pin Attr Signal Description
FERR#
IG NNE#
NMI
INTR
API CD[1:0]
CPUSLP#/
CPUSTP#
STP CLK#
INIT#
APICCK
A20M#
I
1.1V/2.65V -M
OD
1.1V/2.65V -M
OD
1.1V/2.65V -M
OD
1.1V/2.65V -M
I/OD
1.1V/2.65V -M
OD
1.1V/2.65V -M
OD
1.1V/2.65V -M
OD
1.1V/2.65V -M
I
2.5V - M
OD
1.1V/2.65V- M
Floating Point Error:
CPU will assert this signal upon a floating point error occurring.
Ignore Numeric Error:
IGNNE# is asserted to inform CPU to ignore a numeric error.
Non-Maskable Interrupt:
A rising edge on NMI will trigger a non-maskable interrupt to
CPU.
Interrupt Request:
High-level voltage of this signal conveys to CPU that there is
outstanding interrupt(s) needed to be serviced.
API C Da ta:
These two signals are used to send and receive APIC data.
CPU Sleep:
The CPUSLP# can be used to force CPU enter the Sleep state.
CPU Clock STOP:
For Intel Mobile processor, this signal can be used to stop the
clock to the processor. If the processor is in Quick Start state
and the processor clock is stopped, the processor will enter the
Deep Sleep state.
For AMD processor, this signal can be to reduce processor
voltage during C3/S1 state.
Stop C lock:
STPCLK# will be asserted to inhibit or throttle CPU activities
upon a pre-defined power management event occurs
Initialization:
INIT is used to re-start the CPU without flushing its internal
caches and registers. In Pentium III platform it is active high.
This signal requires an external pull-up resistor tied to 3.3V.
API C C lock:
This signal is used to determine when valid data is being sent
over the APCI bus.
Address 20 Mask:
When A20M# is asserted, the CPU A20 signal will be
forced to “0”
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5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
PCI Interface
Name Pin Attr Signal Description
AD[31:0]
PAR
FRAME#
IRDY#
TR DY#
STO P #
I/O
3.3V/5V -M
I/O
3.3V/5V -M
I/O
3.3V/5V -M
I/O
3.3V/5V -M
I/O
3.3V/5V -M
I/O
3.3V/5V -M
PC I Ad dr ess /Data B us:
In address phase:
1.When the SiS961 is a PCI bus master, AD[31:0] are output
signals.
2.When the SiS961 is a PCI target, AD[31:0] are input signals.
In data phase:
1.When the SiS961 is a target of a memory read/write cycle,
AD[31:0] are floating.
2.When the SiS961 is a target of a configuration or an I/O cycle,
AD[31:0] are output signals in a read cycle, and input signals in
a write cycle.
Par ity:
SiS961 drives out Even Parity covering AD[31:0] and
C/BE[3:0]#. It does not check the input parity signal.
Frame#:
FRAME# is an output when the SiS961 is a PCI bus master.
The SiS961 drives FRAME# to indicate the beginning and
duration of an access. When the SiS961 is a PCI slave device,
FRAME# is an input signal.
In itia tor R ea dy:
IRDY# is an output when the SiS961 is a PCI bus master. The
assertion of IRDY# indicates the current PCI bus master's
ability to complete the current data phase of the transaction. For
a read cycle, IRDY# indicates that the PCI bus master is
prepared to accept the read data on the following rising edge of
the PCI clock. For a write cycle, IRDY# indicates that the bus
master has driven valid data on the PCI bus. When the SiS961 is
a PCI slave, IRDY# is an input pin.
Target Ready:
TRDY# is an output when the SiS961 is a PCI slave. The
assertion of TRDY# indicates the target agent's ability to
complete the current data phase of the transaction. For a read
cycle, TRDY# indicates that the target has driven valid data
onto the PC I bus. For a write cycle, TRDY# indicates that the
target is prepared to accept data from the PCI bus. When the
SiS961 is a PCI master, it is an input pin.
Stop#:
STOP# indicates th at the bus master must start terminating its
current PCI bus cycle at the next clock edge and release control
of the PCI bus. STOP# is used for disconnection, retry, and
target-abortion sequences on the PCI bus.
PCI Interface Continue
Name Pin Attr Signal Description
DEVSEL#
PR E Q [4:0]#
PG NT[4:0]#
PR EQ 5# /
GPIO5
PG NT5# /
GPIO6
INT[A:D]#
PCIRST#
SERR#
I/O
3.3V/5V -M
I
3.3V/5V -M
O
3.3V –M
I
I/O
3.3V/5V- M
O
I/O
3.3V- M
I
3.3V/5V –M
O
3.3V –M
I
3.3V/5V –M
Device Select:
As a PCI target, SiS961 asserts DEVSEL# by doing positive or
subtractive decoding. SiS961 positively asserts DEVSEL# when
the DRAM address is being accessed by a PCI master, PCI
configuration registers or embedded controllers’ registers are
being addressed, or the BIOS memory space is being accessed.
The low 16K I/O space and low 16M memory space are
responded subtractively. The DEVESEL# is an input pin when
SiS96 1 is acting as a PCI master. It is asserted by the ad dressed
agent to claim the current transaction.
PCI Bus Request:
PCI Bus M aster Request Signals
PCI Bus Gra nt:
PCI Bus M aster Grant Signals
PCI Bus Request:
PCI Bus M aster Requ est Signal
PCI Bus Gra nt:
PCI Bus M aster Grant Signal
PCI interrupt A,B,C,D:
The PCI interrupts will be connected to the inputs of the internal
Interrupt controller throu gh the rerouting logic associated w ith
each PC I interrupt.
PC I Bu s Reset:
PCIRST# will be asserted during the period when PWROK is
low, and will be kept on asserting until about 24ms after
PWROK goes high.
System Error:
When sampled active low, a non-m askable interrupt (NM I) can
be generated to CPU if enabled.
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5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
IED Interface
Name Pin Attr Signal Description
IDA[15:0]
IDB[15:0]
IDECSA[1:0]#
IDECSB[1:0]#
IIOR[A:B]#
IIOW[A:B]#
IC HR DY[A:B]
IDREQ[A:B]
IDAC K[A: B]#
IIRQ[A:B]
IDSAA[2:0]
IDSAB[2:0]
CBL ID[A:B]
I/O
3.3V/5V -M
I/O
3.3V/5V -M
O
3.3V -M
O
3.3V -M
O
3.3V -M
O
3.3V -M
I
3.3V/5V -M
I
3.3V/5V -M
O
3.3V -M
I
3.3V/5V -M
O
3.3V -M
O
3.3V -M
I
3.3V/5V -M
Primary Channel Data Bus
Secondary Channel Data Bus
Primary Channel CS[1:0]
Secondary Channel CS[1:0]
Primary/Secondary Channel IOR# Signals
Primary/Secondary Channel IOW# Signals
Primary/Secondary Channel ICHRDY# Signals
Primary/Secondary Channel DMA Request Signals
Primary/Secondary Channel DMACK# Signals
Primary/Secondary Channel Interrupt Signals
Primary Channel Address [2:0]
Secondary Channel Address [2:0]
Primary/Secondary Ultra-66 Cable ID
Legacy I/O and M iscellaneous Signals
Signal Name Pin Attr Signal Description
SPK O
ENTEST I
OSCI I
3.3V -M
3.3V/5V -M
3.3V -M
Speaker output:
The SPK is connected to the system speaker.
SiS961 Test Mode Enable Pin
SiS961 Test Mode Enable Pin
Power Management Interface
Name Pin Attr Signal Description
ACPILED
EXTSMI# /
GPIO3
PME#
PSON#
AUXOK
PWRBTN#
RING /
GPIO8
BCLK_STP#
GPIO12
DPRSLP VR
GPIO13
OD
<=5V -AUX
I
I/O
3.3V/5V -M
I
3.3V/5V -AUX
OD
<=5V -AUX
I
3.3V -AUX
I
3.3V/5V -AUX
I
I/O
3.3V/5V -AUX
O
I/O
3.3V/5V -AUX
O
O
3.3V/5V -AUX
ACPILED :
ACPILED can be used to control the blinking of an LED at the
frequency of 1Hz to indicate the system is at power saving
mode.
Exter nal SMI#:
EXTSMI# can be used to generate wakeup event, sleep event, or
SCI/SMI# event to the ACPI compatible power management
unit.
PME# :
When the system is in power-down mode, an active low event
on PME# will cause the PSON# to go low and hence turn on the
power supply. When the system is in suspend mode, an active
PME# event will cause the system wakeup and generate an
SCI/SMI#.
ATX Power ON/OFF control:
PSON# is used to control the on/off state of the ATX power
supply. When the ATX power supply is in the OFF state, an
activated power-on event will force the power supply to ON
state.
Auxiliar y Power OK:
This signal is supplied from the AUX power source. It is also
used to reset the logic in AUX power well. If there is no
auxiliary power source on the system, this pin should be tied
together with PWROK.
Power Button:
This signal is from the power button switch and will be
monitored by the ACPI-compatible power management unit to
switch the system between working and sleeping states.
Ring Indication:
An active RING pulse and lasting for more than 4ms will cause
a wakeup event for system to wake from S1~S5.
Stop C PU clock:
Output to the external clock generator for it to turn off the CPU
clock during C3/Sx.
Deeper Sleep:
DPRSLP# can be used to lower the Intel processor voltage
during C3/S1 state.
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5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
AC’97 Inter face
Name Pin Attr Signal Description
AC_BIT _CL K I
AC_RESET#
AC_SDI N0
AC_SDI N1
AC_SDI N[3:2]/
GPIO[10:9]
AC_SDO UT
AC_SYNC
3.3V/5V -M
O
3.3V -AUX
I
3.3V/5V -AUX
I
3.3V/5V -AUX
I
I/O
3.3V/5V -AUX
O
3.3V -M
O
3.3V -M
AC’97 Bit Clock:
This signal is a 12.288MHz serial data clock, which is generated
by primary Codec.
AC’97 Reset:
Hardware reset signal for external Codecs.
AC’97 Serial Data Input :
Serial data input from primary Codec.
AC’97 Serial Data Input:
Serial data input from secondary Codec. When Modem Codec is
used, this pin dedicate to Modem Serial data input.
AC’97 Serial Data Input:
Serial data input from third and forth Audio Codec.
AC’97 Serial Data Output:
Serial data output to Codecs.
AC’97 Synchronization:
This is a 48KHz signal, which is used to synchronize the Codecs
USB Inter face
Name Pin Attr Signal Description
USBCL K48M
OC[0:5]#
UV[2:0]+,
UV[2:0]-
UV[5:3]+,
UV[5:3]-
I
3.3V/5V -M
I/O
3.3V/5V - AUX
I/O
3.3V - AUX
I/O
3.3V - AUX
USB 48 MHz clock in pu t:
This signal provides the fundamental clock for the USB
Controller.
USB Por t 0-5 Over cur rent Detect ion:
OC[0:5]# are used to detect the overcurrent condition of USB
Ports 0-5.
USB Por t [2:0] Differen tia l
These differential pairs are used to transmit Data/Address
/Command signals for ports 0-2. (USB controller 1)
USB Por t [5:3] Differ en tial
These differential pairs are used to transmit Data/Address/
Command signals for ports 3-5. (USB controller 2)
:
:
LPC Inter face
Name Pin Attr Signal Descr iption
LAD[3:0]
LDRQ#
LDRQ1# /
GPIO1
LFRAME#
SIRQ
I/O
3.3V/5V-M
I
3.3V/5V-M
I
I/O
3.3V/5V-M
O
3.3V -M
I/O
3.3V/5V -M
LP C Ad dress/Data Bus:
LPC controller drives these four pins to transmit LPC command,
address, and data to LPC device.
LP C DM A Requ est 0:
This pin is used by LPC device to request DMA cycle.
LP C DM A Requ est 1:
This pin is used by LPC device to request DMA cycle.
LPC Frame:
This pin is used to notify LPC device that a start or a abort LPC
cycle will occur.
I/O
3.3V/5V -M
TRC Inter face
Name Pin Attr Signal Description
I
3.3V -RTC
I
3.3V-RTC
O
<3.3V -RTC
I
3.3V-RTC
Battery Power OK:
When the internal RTC is enabled, this signal is used to indicate
that the power of RTC well is stable. It is also used to reset the
logic in RTC well. If the internal RTC is disabled, this pin
should be tied low.
RTC 32.768 KHz Input:
When internal RTC is enabled, this pin provides the 32.768
KHz clock signal from external crystal or oscillator.
RTC 32.768 KHz Outp ut :
When internal RTC is enabled, this pin should be connected
with the other end of the 32.768 KHz crystal or left unconnected
if an external oscillator is used.
Main Power OK
A high-level input to this signal indicates the power being
supplied to the system is in stable operating state. During the
period of PWROK being low, PCIRST# will all be asserted
until after PWROK goes high for 12 ms.
:
BATOK
OSC32KHI
OSC32KHO
PWROK
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Prestigio Cavaliere 141 Technical Service Manual
5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
Keyboard Control Interface
Name Pin Attr Signal Description
KBDAT /
GPIO15
KBCLK /
GPIO16
PM DAT /
GPIO17
PMCLK /
GPIO18
I/OD
O/OD
3.3V/5V -AUX
I/OD
O/OD
3.3V/5V -AUX
I/OD
O/OD
3.3V/5V -AUX
I/OD
O/OD
3.3V/5V -AUX
Keyboar d Dada:
When the internal keyboard controller is enabled, this pin is
used as the keyboard data signal.
Keyboar d Clock:
When the internal keyboard controller is enabled, this pin is
used as the keyboard clock signal.
PS2 Mouse Data:
When the internal keyboard and PS2 mouse controllers are
enabled, this pin is used as PS2 mouse data signal.
PS2 Mouse Clock:
When the internal keyboard and PS2 mouse controllers are
enabled, this pin is used as the PS2 mouse clock signal.
MAC Inter face
Name Pin Attr Signa l Descr iption
RXER
MIICLK25M
MDC O
TXD[0:3]
TXEN
RXD[0:3]
I
3.3V/5V -AUX
I
3.3V/5V -AUX
3.3V -AUX
I
3.3V/5V -AUX
O
3.3V -AUX
I
3.3V/5V -AUX
RX Pa cket Er ror
This event is signaled after the last received descriptor in a
failed packet reception that has been updated with valid status.
PHY 25MHz Clock Input:
This pin provides the 25MHz clock signal input to the built-in
oscillator.
Management Data Clock:
Clock signal with a maximum rate of 2.5MHz used to transfer
management data for the external physical unit on the
MIIMDIO pin.
Receive Data:
This is a group of 4 data signals aligned on nibble boundaries
which are driven synchronous to the RXCLK by the external
physical unit.
Transmit Data:
This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external physical unit.
Receive Data:
This is a group of 4 data signals aligned on nibble boundaries
which are driven synchronous to the RXCLK by the external
physical unit.
MAC Interface Continue
Name Pin Attr Signal Description
TXEN
MDIO
RXDV
COL
CRS
RXCLK
TXCLK
O
3.3V -AUX
I/O
3.3V/5V -AUX
I
3.3V/5V -AUX
I
3.3V/5V -AUX
I
3.3V/5V -AUX
I
3.3V/5V -AUX
I
3.3V/5V -AUX
Transmit Enable:
When set to a 1, and the transmit state machine is idle, then the
transmit state machine becomes active. This bit will read back
as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has
completely reset before setting this bit
Management Data I/O:
Bi-direction signal used to transfer management information for
the external physical unit. Requires external pull-up resistor.
Receive Dat a Valid
This indicates that the external physical unit is presenting
recovered and decoded nibbles on the RXD[3:0] and that
RXCLK is synchronous to the recovered data. This signal will
encompass the frame, starting with the Start-Of-Frame delimiter
and excluding the End-Of-Frame delimiter.
Collision Detect:
This signal is asserted high asynchronous by the external
physical unit upon detection of a collision on the medium. It’ll
remain asserted as long as the collision condition persists.
Carrier Sense:
This signal is asserted high asynchronously by the physical unit
upon detection of a non-idle medium.
Receive Clock
A continuous clock that is recovered from the incoming data.
During 100Mb/s operation RXCLK is 25MHz and during
10Mb/s this is 2.5MHz.
Transmit Clock
A continuous clock that is sourced by the physical unit. During
100Mb/s operation RXCLK is 25MHz and during 10Mb/s this
is 2.5MHz.
.
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5. Pin Descriptions of Major Components
5.3 SiS961(MuTIOL® Media I/O South Bridge )
Power and Gr ound Signals
Name Toler ance Power Pla ne T ype Attribute
VSS 0V GROUND
VSSZ 0V GROUND Digital
IVDD 1.8V MAIN Digital
PVDDZ 1.8V MAIN Digital
VDDZ 1.8V MAIN Digital
VDDZC MP 1.8V MAIN Analog
VSSZCMP 0V GROUND Analog
ZVSSREF 0V GROUND Analog
PVDD 3.3V MAIN Digital
OVDD 3.3V MAIN Digital
VTT 1.1V-2.65V MAIN Digital
IVDD_AUX 1.8V AUX Digital
PVDD_AUX 3.3V AUX Digital
OVDD_AUX 3.3V AUX Digital
MI IAVDD 3.3V AUX Analog
MI IAVSS 0V GROUND Analog
USBVDD 3.3V AUX Analog
USBVSS 0V GROUND Analog
RT CVDD 3.3V RTC Analog
RT CVSS 0V GROUND Analog
Z1XAVDD 3.3V MAIN Analog
Z1XAVSS 0V GROUND Analog
Z4XAVDD 3.3V MAIN Analog
Z4XAVSS 0V GROUND Analog
IDE AVDD 1.8V MAIN Analog
IDE AVSS 0V GROUND Analog
Digital
General Purpose I/O
Signal Name Pin Attr Signal Description
GPIO[6:0]
GPIO14,[12:7]
GPIO13
GPIO[18:15]
GPIO[20:19]
I/O
3.3V/5V -M
I/O
3.3V/5V -AUX
O
3.3V/5V - AUX
O
3.3V/5V - AUX
I/O
3.3V/5V - AUX
GPIO:
Can be a general purpose input or output.
GPIO :
Can be a general purpose input or output.
GPO:
Can be a general purpose output.
GPO:
Can be a general purpose output.
GPIO:
Can be a general purpose input or output.
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6. System Block Diagram
J511
PC Card
Socket
External KB
Touch Pad
Power Button
TV
D
D
C
C
L
L
PCI BUS
U515
PCI1410
U11
Power Switch
CP2211
S-Video
LVDS
U13
H8
H8
CD-ROM
FAN
SMBUS
HDD
USB
Thermal
Sensor
U503
LVDS
Interface
ISA Bus
U6
CRT
R,G,B
VB Bus
U517
BIOS
U506
Mobile Intel Pentium 4
Processor
U505
North Bridge
SiS650
Hyper ZIP Bus
U516
South Bridge
SiS961
LPC Bus
U19
Super I/O
PC87393
PIO
90
EIGHT
LED
378 Port
For Debug
MII
AC Link
U522
AC97
CODEC
J7
MDC
U7-U10
U511-U514
On Board
DDRRAM
J509
DDRRAM Slot
U509
LANPHY
MIC
Amplifier
MDC
Daughter
BD
U521
J508
RJ45
Line Out
J501
RJ11
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Prestigio Cavaliere 141 Technical Service Manual
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal
checks on the hardware. This power-on self test (POST) allows the computer to
detect problems as early as the power-on stage. Error messages of post can alert
you to the problems of your computer.
If an error is detected during these tests, you will see an error message
displayed on the screen. If the error occurs before the display is initialized,then
the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port (378H) is written at the beginning of the test.
Therefore, if the test failed, the user can determine where the problem occurred
by reading the last value written to port 378H by the eight LEDs on board.
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7. Maintenance Diagnostics
7.2 Debug Tool
Cavaliere 141 MB would not support Parallel Port, then we could not plug the Debug Card to PIO
Port to get the Port 378 error code. For the cause, Cavaliere 141 MB have reserved eight LEDs
that are parallel connection with PIO output lines(Figure 1),when the system BIOS write the error
code to Port 378, the LEDs can show the messages.
Maybe the LEDs have not been mount on the mother board, you must place the LEDs for
getting error code.(Figure 2)
U19
Super
I/O
+3V
RP36
RP531
4.7K*8
Figure1 : Circuit Figure2 : 378 Port LEDs Location
+3V
RP36
RP531
4.7K*8
D506 – D513
CL-190G
PIO[D0:D8]
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D3-D10
CL-190G
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Prestigio Cavaliere 141 Technical Service Manual
7. Maintenance Diagnostics
7.3 Error Codes : Following is a list of error codes in sequent display on the PIO debug board. System
Soft BIOS:
Code Descr iption
10H Some Type Of Long Reset
11H Tur n off FASTA20 for POST
12H Signal Power On Reset
13H Initialize the Chipset
14H Se a r ch F or I S A Bu s VG A Ad a p t er
15H Reset Cou nter /Timer
16H User register config through CMOS
17H Size Memor y
18H Dispatch To RAM Test
19H Checksum the ROM
1AH Reset PIC's
1BH Initialize Video Adapter(s)
1CH Initialize Video (6845 Regs)
1DH Initialize Color Adapter
1EH Initialize Monochrome Adapter
1FH Test 8237A Page Register s
20H Test Keyboard
21H Test Keyboard Controller
22H Check If CMOS Ram Valid
23H Test Batter y Fail & CMOS X-SUM
24H Test the DMA controller s
25H Initialize 8237A Controller
26H Initialize Int Vector s
Code Description
27H RAM Quick Sizing
28H Pr otected mode en ter ed safely
29H RAM test completed
2AH Protected mode exit successful
2BH Setup Sha dow
2CH Going To Initialize Video
2DH Sear ch For Monochr ome Ada pter
2EH Search For Color Adapter
2FH Signon messages displayed
30H Special init of keyboar d ctlr
31H Test If Keyboar d Present
32H Test Keyboard Interrupt
33H Test Keyboard Command Byte
34H TEST, Blank and count all RAM
35H Pr otected mode enter ed safely (2).
36H RAM test complete
37H Pr ot ected mode exit successful
38H Update OUTPUT port
39H Setup Cache Controller
3AH Test If 18.2Hz Per iodic Wor king
3BH Test for RTC ticking
3CH Initialize the har dwar e vector s
3DH Sear ch an d Init the Mouse
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7. Maintenance Diagnostics
7.3 Error Codes : Following is a list of error codes in sequent display on the PIO debug board. System
Soft BIOS:
Code Descr iption
3EH Update NUMLOCK status
3FH Special init of COMM and LPT ports
40H Configure the COMM and LPT ports
41H Initialize the floppies
42H Initialize the har d disk
43H Initialize option ROMs
44H OEM's init of power management
45H Update NUMLOCK status
46H Test For Copr ocessor Insta lled
47H OEM functions before boot
48H Dispatch To Op. Sys. Boot
49H J ump Into Bootstr ap Code
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Prestigio Cavaliere 141 Technical Service Manual
8. Trouble Shooting
8.1 No Power 8.8 Hard Disk Drive Test Error
8.2 Battery Can not Be Charged 8.9 CD-ROM Driver Test Error
8.3 No Display 8.10 USB Port Test Error
8.4 LCD No Display or Picture Abnormal
8.5 External Monitor No Display or Color Abnormal
8.11 PC Card Socket Test Error
8.12 LAN Test Error
8.6 Memory Test Error 8.13 Audio Driver Failure
8.7 Keyboard and Touch Pad Test Error
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Prestigio Cavaliere 141 Technical Service Manual
8.1 No Power:
When the power button is pressed, nothing happens ,power indicator does not light up.
P1
Power In
PJ501
PF2,PL3,PL4
PR19
PD12
P3
PWR_VDDIN
PQ8,PQ9
F4,U15
P1
ADINP
J1
J3
PD10,PL5,PQ2
PL501,PU2,PU8
(Charge)
PD13,PD14,PD15
PD16
(Discharge)
H8_AVREF
U15 Q21
P1
Battery
P1
D/VMAIN
8677 DD BOARD
P28
L30
L28
P28
VDD5
J501
PQ13-PQ16
(Discharge)
P26
H8_VDDA
Q18
Main Voltage Map
J1 J3
PL1,PL2,PU501,PU1~PU10
PU502,PU13,PU14
PU502,PU11
PU12
PU9,PU4,PU6
PU9,PU3,PU5
P28
VDD5S
P30
+1.8V_P
P4
+3V_P
P4
+5V_P
P31
+CPU_CORE
+2.5V_P
JO6
P32
+1.8V
PGDN
PGDN
P30
JO8,JO9
R79
R80
L13
L9
R647
R648
L27
L539
Note:
P12
PU502
+2.5V_DDR
P7
ZVREF
P7
VDDZCMP
P7
DACAVDD1
P15
SZVREF
P15
SVDDZCMP
P15
IDEAVDD
: Page 12 on circuit diagram.
: Through by part PU502.
P32
L526
P9
+VCLK_DDR
L525
P9
+VCLK_DDRA
R94
R97
R95
R96
R132
R130
R125
R120
P6
DDRVREFA
P6
DDRVREFB
P11
+VREF_DDR
P12
+VREF_DIMM
+S5V
Q23
U18
P28
VDD3
PU9,PU3,PU5
PU1,PT501
96
P4
+12V_P
JO1
P32
+S12V
Q4
P29
+12V
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Prestigio Cavaliere 141 Technical Service Manual
8.1 No Power:
When the power button is pressed, nothing happens ,power indicator does not light up.
PGUP
Note:
P32
PU501
P4
+5V_P
P4
+3V_P
PGUP
: Page 32 on circuit diagram.
: Through by part PU501.
JO2
P32
JO3
PU15
+1.25V_P
U501,L505
U501,L504
+S5V
U1
P32
JO508
P3
+VCC_USB_0
P3
+5V
+VCC_USB_1
U502,L513
P3
+VCC_USB_2
U502,L512
P3
+VCC_USB_3
P29
+1.25V
JO4,JO5
P32
+S3V
U502
JS503
JS504
R727
L540
L540
P32
L538
L29
U14
DAC_VDD
+5V_HDD
+5V_CDROM
RVDD/LVDD
CARD_VCC
U5
P10
P18
P18
P20
VA
P29
+3V
P16
MII_AVDD
P17
USBVDD
P29
+S1.8V
L31
P17
IVDD_AUX
P21
P22
97
U504
L528
L532
L523
L529
L521
L22
L527
L21
L519
L520
L512
L513
L517
L518
L516
+CPU_VCCVID
+VCLK_REF
+VCLK_Z
+VCLK_48
P9
P9
+VCLK_PCI
+VCLK_AGP
+VCLK_CPU
+VCLK_SDRAM
+VCLK_VDDA
C1XAVDD
C4XAVDD
A4XAVDD
A1XAVDD
SDAVDD
DDRAVDD
Z1XAVDD
P5
P5
P5
P5
P6
P6
P7
P9
P9
P9
P9
P3
P9
P9
L515
L514
L511
L508
L509
L5
L510
L506
L503
L505
L507
Q1
L535
L534
Z4XAVDD
DCLKAVDD
ECLKAVDD
TVPLL_VCC
TVPLL_VCC
VDDT
P10
+VCH_DVDD
+LVDD4/5
+LVDD2
+LVDD0/1
+LPLL_VDD
+3V_LCDVCC
SZ1XAVDD
SZ4XAVDD
P7
P7
P7
P10
P10
P10
P10
P10
P10
P10
P14
P15
P15
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Prestigio Cavaliere 141 Technical Service Manual
PJ501
Power In
I_LIMIT
To H8
PWR_VDDIN
F5
3216FF-1
Mother Board
8.1 No Power:
When the power button is pressed, nothing happens ,power indicator does not light up.
ADINP
PL3
PF2
PC9
0.1u
PR21
10
PR21
10
8
2
U15
7
LP2951-02BM
RLZ5.6B
SW_VDD5
From H8
D8
PU17
MAX4173
6
OUT
6
1
PL4
PC10
0.1u
H8_AVREF
PD5
RLZ24D
VCC
RS+
RS-
SI2301DS
C202
10U
3
4
5
Q21
C196
4.7U
PR19
PR19
0.01
0.01
VDD5
PD12
BAV70LT1
PWR_VDDIN
PD16
BAV70LT1
D/VMAIN
PD13
PQ16
SI4835DY
1
2
3
S
D
5
678
1
5
3
7
J1 J3
JS1
1
JS3
5
JS2
3
JS7
7
4
I_LIMIT
LEARNING#
BATT_DEAD
1.25V
PL1
PL2
PD14
PD15
EC31QS04
VDD5
5
PU10B
LMV393M
6
PQ14
2N7002
8
PR49
33k
G
PR41
100k
PR5
301k
PR4
100k
D
S
7
PR50
100k
4
G
D/ADEN#
D/LEARNING#
D/BATT_DEAD
BATT
D/BATT_V
PC1
0.1U
D
S
PR23
470k
PR30
100k
G
PQ7
2N7002
3
2
1
S
PQ9
SI4835DY
3
2
1
S
4
4
G
G
PR34
8
7
6
5
D
PC47
0.1U
PQ8
SI4835DY
8
7
6
5
D
PC47
0.1U
PR42
324k
2
PR44
4.7k
PR45
4.7k
ADEN#
3
DTC144WK
1
PQ13
1M
D/VMAIN
PR38
3.3k
PR47
Q23
787k
SI2301DS
+S5V
R144
SW_VDD5#
100k
2
From H8
3
Q22
J501
1
PF1
TR/SFT-10A
Battery In
PR48
100k
PC2
0.1U
PQ12
SCK431
DTC144WK
1
PQ15
SI4835DY
231
S
G
D
678
5
ADEN#
BATT_DEAD#
Q26
DTC144TKA
2
VDD5
BATT_V
Mother Board
47
U13
39
81
H8
30
38
3
1
D501
3
1
R670
2.2k
98
Page 100
Prestigio Cavaliere 141 Technical Service Manual
8.1 No Power:
When the power button is pressed, nothing happens ,power indicator does not light up.
No power
Is the
Notebook connected
to power (Either AC adaptor
or battery)?
Yes
Yes
Try another known good battery,charge BD
or AC adapter.
No
No
Connect
AC adaptor
or battery
Board-level
Troubleshooting
Where
From Power Source
Problem(First use
AC to power it)
AC
Check following parts and signals:
PARTS: SIGNAL:
Charge BD
PJ501
PL3
PL4
PD5
PD6
PF2
PU10
PQ7~9
PQ13~16
PR30
PR23
PR44
PR45
M/B
U13
U15
Q26
D501
R670
F5
D8
Q21~23
ADINP
D/VMAIN
VDD5S
D/ADEN#
D/LEARNING
PWR_VDDIN
H8_AVREF
SW_VDD5
SW_VDD5#
Power
OK?
No
Replace
Motherboard
Yes
Replace the faulty
AC adaptor ,
charge BD or
Battery.
99
Battery
Check following parts and signals:
PARTS: SIGNAL:
Charge BD
PF1
PR47
PC2
PR48
PL1
PR41
PL2
PR38
PR5
PQ12
PR4
PC52
PC1
PC50
PU10
PC60
M/B
U13
Q26
D501
R670
D/VMAIN
D/BATT_V
D/BATT_T
D/BATT_DEAD
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