Philips XSA5224CU, XNE5224CK Datasheet
SA5224
FDDI fiber optic postamplifier
Product specification
Replaces datasheet NE/SA5224 of 1995 Apr 26
IC19 Data Handbook
1998 Oct 07
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
SA5224FDDI fiber optic postamplifier
2
1998 Oct 07 853-1594 20141
DESCRIPTION
The SA5224 is a high-gain limiting amplifier that is designed to
process signals from fiber optic preamplifiers. Capable of operating
at 125Mb/s, the chip is FDDI compatible and has input signal
level-detection with a user-adjustable threshold. The DATA and
LEVEL-DETECT outputs are differential for optimum noise margin
and ease of use. Also available is the SA5225 which is an ECL 10K
version of the SA5224.
FEA TURES
•Wideband operation: 1.0kHz to 120MHz typical
•Applicable in 155Mb/s OC3/SONET receivers
•Operation with single +5V or –5.2V supply
•Differential 100k ECL outputs
•Programmable input signal level-detection
•Fully differential for excellent PSRR to 1GHz
PIN DESCRIPTION
D Package
CAZN
CAZP
GND
A
D
IN
D
OUT
D
OUT
V
REF
V
SET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
D
IN
CF
JAM
V
CCA
V
CCE
GND
E
ST
ST
SD00374
Figure 1. Pin Configuration
APPLICATIONS
•FDDI
•Data communication in noisy industrial environments
•LANs
ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
16-Pin Plastic Small Outline (SO) package
–40 to +85°C
SA5224D SOT109-1
BLOCK DIAGRAM
(6) (2) (1) (16)
(13)
(12)
(8)
(9)
(10)
(11)(7)(3)
(16)
(15)
(5)
(4)
LIMITING
AMPLIFIER
ECL
BUFFER
JAM
BUFFER
SD
BUFFER
LEVEL
DETECTOR
REFERENCE
D
IN
D
IN
V
REF
V
SET
GND
A
C
F
GND
E
D
OUT
D
OUT
JAM
ST
V
CCE
C
AZN
C
AZP
V
CCA
ST
SD00375
Figure 2. Block Diagram
Philips Semiconductors Product specification
SA5224FDDI fiber optic postamplifier
1998 Oct 07
3
PIN DESCRIPTIONS
PIN NO. NAME FUNCTION
1 C
AZN
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZP
will cancel the offset voltage of the
limiting amplifier.
2 C
AZP
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZN
will cancel the offset voltage of the
limiting amplifier.
3 GNDAAnalog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL
operation. Must be at same potential as GNDE (Pin 11).
4 D
IN
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 5).
5 D
IN
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 4).
6 V
CCA
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as V
CCE
(Pin 14).
7 C
F
Filter capacitor for level detector. Capacitor should be connected between this pin and V
CCA
.
8 JAM This ECL-compatible input controls the output buffers D
OUT
and D
OUT
(Pins 12 and 13). When an ECL LOW signal
is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the D
OUT
and D
OUT
pins
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).
9
ST
Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable
threshold level.
10 ST ECL compliment of ST (Pin 9).
11 GNDEDigital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL
operation. Must be at the same potential as GNDA (Pin 3).
12
D
OUT
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH
condition. Complimentary to D
OUT
(Pin 13).
13 D
OUT
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW
condition. Complimentary to D
OUT
(Pin 12).
14 V
CCE
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as V
CCA
(Pin 6).
15 V
REF
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
16 V
SET
Input threshold level setting circuit. This input can come from a voltage divider between V
REF
and GNDA.
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNITS
V
CC
Power supply (VCC - GND) 6 V
T
A
Operating ambient –45 to +85
°C
T
J
Operating junction –55 to +150
°C
T
STG
Storage –65 to +150
°C
P
D
Power dissipation, TA = 25°C (still air)
1
16-pin Plastic SO
1100 mW
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
θ
JA
: 16-pin SO: θJA = 110°C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER RATING UNITS
V
CC
Supply voltage 4.5 to 5.5 V
T
A
Ambient temperature ranges –40 to +85
°C
T
J
Junction temperature ranges –40 to +110
°C
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