Philips VES1.1E Schematic

Colour Television Chassis

VES1.1E

LA

See table of contents on page 3

Published by MB/SC 1363 Quality Printed in the Netherlands Subject to modification EN 3122 785 19393

2013-Mar-29

2013 ©

TP Vision Netherlands B.V.

All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change pr oducts at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.

EN 2 VES1.1E LA1.

Revision List

1. Revision List

Manual xxxx xxx xxxx.0

• First release.

Manual xxxx xxx xxxx.1

• Added the Service Mode menu

.

Manual xxxx xxx xxxx.2

• Added several new sets to this chassis, see table 2-1

Described

model numbers.

• Added the section Hotel Mode setup menu

.

Manual xxxx xxx xxxx.3

• Added several schematics of the SSB

• Added the schematics of the PSU

.

.

2. Technical Specifications and Connections

Index of this chapter:

Technical specifications
Directions for Use

Notes:

• Figures can deviate due to the different set executions.

• Specifications are indicative (subject to change).

Technical Specifications

For on-line product support please use the links in Table 2-1. Here is
product information available, as well as getting started, user manuals,
frequently asked questions and software & drivers.

Table 2-1 Described model numbers

CTN Styling Published in:

19PFL2908H/12 2900 3122 785 19392
22PFL2807H/12 2800 3122 785 19390
22PFL2908H/12 2900 3122 785 19392
24HFL2808D/12
24PFL2908H/12
26HFL2808D/12 2800 3122 785 19392
26PFL2908H/12
32PFL2807H/12

2800 3122 785 19392
2900 3122 785 19392

2900 3122 785 19392
2800 3122 785 19390

Directions for Use

You can download this information from the following websites:

http://www.philips.com/support
http://www.p4c.philips.com

2013-Mar-29

back to

div. table

Contents

1 Introduction ............................................................................................................................................. 6

1.1

1.2 SSB Placement of Blocks .................................................................................................................. 8

2 Tuner (TU3) .............................................................................................................................................. 9

2.1 General description of the Sony RE216 tuner .................................................................................. 9

3 Audio amplifier stage with AZAD2102 (U163, U164) ............................................................................. 11

3.1 General description ........................................................................................................................ 11

3.2 Features .......................................................................................................................................... 12

3.3 Absolute

3.4 Pinning ............................................................................................................................................ 15

4 Audio amplifier stage with TPA3113 (U168) .......................................................................................... 15

4.1 General Description ....................................................................................................................... 15

4.2 Absolute Ratings ............................................................................................................................. 16

General

3.3.1 Electrical

3.3.2 Operating

4.2.1 Electrical Characteristics ........................................................................................................ 16

Block

Diagram

Ratings

Characteristics

specifications

................................................................................................................... 7

........................................................................................................................... 13

....................................................................................................... 13

....................................................................................................... 14

4.2.2 Operating

4.3

5 Power stage ............................................................................................................................................ 18

5.1 Power management ....................................................................................................................... 21

6 Microcontroller – MSTAR (U5) ............................................................................................................... 23

6.1 Description ..................................................................................................................................... 23

6.2 MSTAR block diagram .................................................................................................................... 27

6.3 Reset circuit .................................................................................................................................... 28

7 CI interface ............................................................................................................................................. 28

8 USB interface .......................................................................................................................................... 29

9 DDR2 SDRAM K4T1G164QF (U155) ....................................................................................................... 30

9.1 Description ..................................................................................................................................... 30

9.2 Features .......................................................................................................................................... 30

Pinning ........................................................................................................................................................ 31

10 Scaler and LVDS sockets ..................................................................................................................... 32

Pinning

........................................................................................................................................... 17

Specifications

...................................................................................................... 17

10.1 LVDS sockets block diagram .......................................................................................................... 32

10.2 Panel supply switch circuit ............................................................................................................. 32

11 SPI flash memory - MX25L1005 (U158) ............................................................................................. 33

11.1 General Description ....................................................................................................................... 33

11.2 Features.......................................................................................................................................... 33

11.3 Absolute maximum ratings ............................................................................................................ 34

11.4 Pinning ............................................................................................................................................ 34

12 NAND Flash memory – NAND512XXA2C (U162) ................................................................................ 35

12.1 General Description ....................................................................................................................... 35

12.2 Features .......................................................................................................................................... 35

12.3 Pinning ............................................................................................................................................ 36

13 LNBH23L (U6) ..................................................................................................................................... 37

13.1 Description ..................................................................................................................................... 37

13.2 Features.......................................................................................................................................... 37

13.3 Block diagram ................................................................................................................................. 38

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3) ....................................................................... 38

14.1 Description ..................................................................................................................................... 38

14.2 Features.......................................................................................................................................... 38

14.3 Pin Assignment .............................................................................................................................. 40

15 LM1117 (U175, U180, U181) .............................................................................................................. 41

15.1 General description ........................................................................................................................ 41

15.2 Features .......................................................................................................................................... 41

15.3 Applications .................................................................................................................................... 41

15.4 Absolute maximum ratings ............................................................................................................ 41

15.5 Pinning ............................................................................................................................................ 42

16 MP2012 (U176) .................................................................................................................................. 42

17 General description ............................................................................................................................ 42

17.1 Features .......................................................................................................................................... 42

17.2 Pinning ............................................................................................................................................ 43

18 RTA8283A (U23, U173) ....................................................................................................................... 43

18.1 General description ........................................................................................................................ 43

18.2 Features .......................................................................................................................................... 43

18.3 Pinning ............................................................................................................................................ 45

19 MP1583 (U174) .................................................................................................................................. 46

19.1 General description ........................................................................................................................ 46

19.2 Features .......................................................................................................................................... 46

19.3 Pinning ............................................................................................................................................ 46

20 FDC642 ............................................................................................................................................... 47

20.1 General description ........................................................................................................................ 47

20.2 Features .......................................................................................................................................... 47

20.3 Pinning ............................................................................................................................................ 47

21 FDC604P ............................................................................................................................................. 48

21.1 General description ........................................................................................................................ 48

21.2 Features .......................................................................................................................................... 48

21.3 Pinning ............................................................................................................................................ 48

22 Connectors ......................................................................................................................................... 49

22.1 SCART (SC1) .................................................................................................................................... 49

22.2 HDMI (CN707, CN708) ................................................................................................................... 49

22.3

VGA (CN711)

................................................................................................................................. 50

23 Service menu mode ............................................................................................................................ 51

23.1 Main service menu ......................................................................................................................... 51

23.2 Video Settings ................................................................................................................................. 52

23.3 Audio Settings ................................................................................................................................ 52

23.4 Options 1 ........................................................................................................................................ 53

23.5 Options 2 ........................................................................................................................................ 53

23.6 Tuning Settings ............................................................................................................................... 54

23.7 Source Settings ............................................................................................................................... 54

23.8 Diagnostic ....................................................................................................................................... 54

23.9 USB operations ............................................................................................................................... 54

23.10 Profile Operations ...................................................................................................................... 57

23.10.1 Upload profile Data from USB ............................................................................................ 57

23.10.2 PQ Files Operations ............................................................................................................ 57

23.10.3 Upload PQ files from USB ................................................................................................... 57

23.10.4 Ci+ credentials key update ................................................................................................. 57

23.10.5 HDCP keys update .............................................................................................................. 57

23.10.6 Edid update ....................................................................................................................... 58

23.10.7 DDR settings update ........................................................................................................... 58

23.10.8 MAC address update .......................................................................................................... 58

23.11 Hotel Mode setup menu ............................................................................................................ 58

23.11.1 Hotel TV welcome image update (only available in Hotel TVs) ......................................... 58

24 Software update ................................................................................................................................. 59

25 Troubleshooting ................................................................................................................................. 59

25.1 No backlight problem ..................................................................................................................... 59

25.2 CI module problem ......................................................................................................................... 61

25.3 LED blinking problem ..................................................................................................................... 63

25.4 IR problem ...................................................................................................................................... 63

25.5 Keypad touchpad problems ........................................................................................................... 64

25.6 USB problems ................................................................................................................................. 65

25.7 No sound problem.......................................................................................................................... 65

25.8 No sound problem at headphone .................................................................................................. 66

25.9 Standby On/Off problem................................................................................................................ 66

25.10 DVD problems ............................................................................................................................ 67

25.11 No signal problem ...................................................................................................................... 67

26 Styling sheet ....................................................................................................................................... 69

27 Schematics .......................................................................................................................................... 70

27.1 SSB .................................................................................................................................................. 70

27.2 PSU ................................................................................................................................................. 79

1 Introduction

The SSB is driven by a MStar SOC. This IC is capable of handling Video and audio
processing, Scaling-Display processing, 3D comb filter, OSD and text processing, LVDS
transmitting, channel and MPEG2/4 decoding, integrated DVB-T/C demodulator and
media center functionality.

The TV supports PAL, SECAM, NTSC colour standards and multiple transmission
standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Also DVB T,
DVB-C are supported internal demodulators of Mstar IC and DVB-S/S2 is supported with
external demodulator.

Sound system output is supplying max. 2 × 2.5 W (less 10% THD at maximum output)
with 4

Ω

speakers or 2 × 6 W for stereo 8 Ω

speakers.

Supported peripherals are:

1 RF input VHF I, VHF III, UHF @ 75 Ω (Common)
1 Side AV (CVBS, R/L_Audio)
1 SCART socket (Common)
1 YPbPr (Optional)
1 PC input (Common)
2 HDMI 1.3 input (1 HDMI input is common, 1 input is optional)
1 S/PDIF output (Optional)
1 Headphone (Optional)
1 Common interface (Common)
1 USB (Common)
1 DVD (Optional)
1 On-board Keypad (Optional)
1 External Keypad (Optional)
1 External TouchPad (Optional)

1.1

GPIO

General

Block

Diagram

D3K

••

HDIJI1

!

i

Mstar

VGA

-HPOEre

cr-.

2XIi'H

.O.UDIO AU'

Block Diagram

V1.1

Drawn

By Ulas

03.01.2011

Dere i

1.2 SSB Placement of Blocks

Sat
Demod

Tuner(T3
)

External
Keyboard
Touchboard

DVD
Connector

Power Connector

CI Connector

Nand
Flash
(U162)

LVDS

Connectors

USB

Main IC

(U5)

DDR2
RAM
(U155)

YPbPr SAV HP

Satellite Tuner

SPI
Flash

HDMI
Connectors

Adapter DC
Input

VGA

SPDIF
Out

Keypad

SCART
Connec
tor

Speaker
Con.

Led
Con

Inv.
Con

2 Tuner (TU3)

A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands (From 48 MHz to 862 MHz for COFDM, from 45.25 MHz to 863.25 MHz for CCIR
channels). The tuning is available through the digitally controlled I2C bus (PLL).

In the active antenna option, the following circuits are used. ANT_CTRL pin is controlled by
microcontroller. If ANT_CTRL is low, ANT_PWR will be low. If ANT_CTRL is high,
ANT_PWR will be high.

OVER_CUR_DETECT pin is a monitor for short circuit in antenna. OVER_CUR_DETECT
is low, ANT_CTRL will be low, so ANT_PWR will be low. Finally, short circuit protection is
done by circuits and microcontroller.

2.1 General description of the Sony RE216 tuner

The SUT-RE216 is designed for terrestrial TV (digital & analog) and digital cable
reception. It includes a full band tuner and a channel filtering for digital signals. It provides
a low IF output after channel filtering to drive a channel demodulator. Tuning, band
switching and initialization are made via an I
interface. The module is built on a low-loss printed
circuit board carrying all the components in a metal
housing frame with top and rear covers. The single
aerial connector is mounted on one frame side and all
other connections are made via pins at the bottom.

Features:

 Full frequency range from 47 to 870 Mhz

• Digital Platform (DVB-T/T2, DVB-C, ISDB-T & ATSC)

 Analog platforms (PAL B/G/I/D/K, NTSC M & SECAM L/L’)
 Low IF tuner concept

2

C bus

./

Programmable channel Filter

./

Fully

I2C

bus

controlled

./

For Hybrid TV

AGC:

applications

I

:

---------------------------------------•

bandwidth

-

----{)-------w.

---

---o

..-----'M'h\--{®f-----....-!-'N\\-OIAocI

1000

1KO

3.3V pull up

-

1uF

---Pinning Table

and Application Block Diagram of Tuner---

3 Audio amplifier stage with AZAD2102 (U163, U164)

3.1 General description

This chassis uses two 2.5 W Class D Mono Audio Amplifers for from 16" to 24"
TVs.

AZAD2102B
AVdd = DVdd = 5.5 Volt) with high efficiency filter-free class-D audio power amplifier
in a 1613 mm x 1613 mm wafer chip scale package (W CSP). AZAD2102B uses
Current- switch technology to achieve high performance class-d amplifier that
features 0.03% THD, 85% efficiency, –70 dB PSRR, to improve RF-rectification immunity.

AZAD2102B provide a Vibration-Spectrum modulation clock for PWM Output. This
vibration frequency is around 10 kHz shift (+/- 5 kHz of Fpwm).

The advantage of the small size package (WCSP) makes AZAD2102B very suitable for
mobile phone and PDA device application. And the Class-D amplifier structure let
AZAD2102B to have highly efficiency power consumption than Class-AB amplifier.
AZAD2102B can shrink the application board, reduce system cost, and external
components.

ESD level protection I/O embedded in AZAD2102B. For general applications, there is
no need to add extra ESD protection devices (like Varistors) in application systems for
AZAD2102B’s I/O.

is a 2.9 Watts (max. can offer 3.0 Watts @ Load = 3 Ω,THD = 10%,

3.2 Features

• CMOS Technology

• High Efficiency 85%

• High PSRR 70 dB at 217 Hz

• Differential OP-amp Input

• AZAD2102B provides Vibration-Spectrum Modulation clock for reduce EMI

• Provide Mute function (set Mute_B to GND will go into Mute status)

• For the input stage AZAD2102B built-in a 10Kohm resistors (Gain

setting = 29.5 dB)

• Maximum Battery Life and Minimum Heat

• Efficiency With an 8 Ω

• 3.5 mA Quiescent Current

• Output Power at 10% THD

• 2.85 Watts at AVdd = DVdd = 5.0 Volt, Rload = 4 Ω

• 1.45 Watts at AVdd = DVdd = 3.6 Volt, Rload = 4Ω

• 0.30 Watts at AVdd = DVdd = 3.0 Volt, Rload = 4Ω

• 1.75 Watts at AVdd = DVdd = 5.5 Volt, Rload = 8Ω

• 0.87 Watts at AVdd = DVdd = 3.6 Volt, Rload = 8Ω

• 0.41 Watts at AVdd = DVdd = 3.0 Volt, Rload = 8Ω

• Eliminate Power on and Power-off “Pop” noise

• A fewer external components

• Optimized PWM output stage eliminates LC output filter

• Internally generate 290 kHz switching frequency to eliminate capacitor and resistor

• Improve PSRR (–70 dB) and wide supply voltage (3.0 V to 5.5 V)

•

Fully differential design reduces RF rectification

• This chip has been built-in a very strong ESD protection.

• System level ESD 4 KV (IEC 61000-4-2 ESD Contact Level)

• Wafer chip scale package (WCSP)

•

TSSOP package with exposed pad

Speaker:

.

Operating Votl

age

Vop AVdd-DVdd

to

AVss-DVss

3.0 5

5.5

v

RL=80 f=

217Hz

Common mode

rejectio

n

High level nput

current

Under

Voltage

I

I

3.3 Absolute

Ratings

3.3.1 Electrical

VDD = AVdd = DVdd, VSS = AVss = DVss = Ground

TA =

25˚C, Filter

P

ARAMETER

Output offset vol

Power supply
ra

tio

ra

tio

Low level

current

Input

Operation cur

Characteristics

Bandwidth =

tage

rejection

rent

20 Hz -20 kHz

Symbo

l

vos

PSRR

Cf':lRR

I

IIHII

I

IlLI

lop

VDD = 5.5

VDD = 3.0

VDD

=

3.0 V

i

nput ac grounded with

Ci=2.2uF,Vripple=

= 3.0 V to 5.5 V,Vic =

VDD

0.5 V,Vi c = VDD/2

VDD=

5.5V,Vi=5.8V

VDD=

5.5V,Vi=-0.3V

=

5.5 V,no load

VDD

VDD = 3.6 V,no load

TEST COND TIONS

V,VI=

0 V,AV = 6 V/V

V,VI=

0 V,AV = 6 V/V

V,VI=

0 V,AV = 6 V/V 1.2

to

5.5 V, AV = 2 V/V

200mVpp,

to

0.5 VDD

3.0

VDD/2 to

-0.8 V,

MNI

TYP

4.5

MAX

6.5

UNIT

mV

2.1

4.0

3.0

-68

-65

25

1

3.6

5.0

4.2

VDD = 3.6

dB

dB

uA

uA

mA

Output

switchin

frequency

Vibration-Spectrum

Modulation

Protect

Mute_B

Gain

g

clock Ranqe

ion

pin Impedance

VDD = 3.0 V,no load

F

pwm

Fvs

UVP

RMuB

Gain

VDD = 5.5 V,no load

VDD = 3.6 V,no load

VDD = 3.0 V,no load

VDD = 5.0

Vin+

Mute_B

VDD=5.0V,Ri=5K0+10K

(Av=20V/V)

O

and

V,no load

Vin-

to

Ground

connect

to

GND,no load

2.5

3.5

290

300

315

+/-5 +/-10

18

2.0

270

20

22

2.5

KHz

KHz

v

KQ

V/V

VDD = 3.0 V

0.60

No

weighting

45

3.3.2 Operating

TA = 25°C,Gain = 20

Pw

THD+N

PSRR

SNR

Vnoise

CMRR

ZI

ZF

P

ARAMETER TEST COND

Output

power

Total ha

distortion

Supply

rejection ratio

Signal-to-noise r

Output noise

Common

rejecti

Input impedance

Feedback res

rmonic

ripple

on

specifications

V/V,

THO+ N = 10%,

= 4Q

THO + N

RL = 4 Q

THO+ N =

= 8Q

THO + N

RL

VDD

plus

noise

VDD = 3.0 V,PO = 200

VDD
Av=20V/V,Inputs
grounded with

atio

VDD

VDD

kHz, nputs ac-grounded wi

Ci = l.OJJF

VDD = 3.6

level

mode

ratio

istor

TIONS

f = 1

kHz,RL

= 1%, f = 1

10%, f = 1kHz,RL

= 1%, f = 1 kH

= 8 Q

=

5.0 V,PO = 1W,RL = 8 Q,f = 1

=

3.6 V,PO = 0.5 W,RL = 8 Q, f = 1

=

3.6

V,

connect

Ci = l.OJ,JF

=

5 V,PO = 1W,RL = 8 Q

=

3.6 V,f = 20 Hz

V,Vin = 100mVpp f

kHz,

z,

mW,

RL = 8 Q, f = 1

to

to

20

th

= 5.0V

VDD

VDD = 3.6

VDD = 3.0 V

=

5.0 V

VDD

VDD = 3.6

VDD = 5.0

VDD = 3.6 V

VDD = 3.0

VDD

=

5.0 V

VDD = 3.6

VDD = 3.0 V

kHz

kHz

kHz

=

217 H.

F

VRipple
mVpp

A wei

= 217Hz

z,

= 200

ghting

V

V

V

V

V

MIN

TYP MAX

2.85

1

.45

0.77

2.25

1.15

1.75

0.87

0.47

1.39

0.70

0.36

0.15

0.12

0,09

-67

95

dB

120

8

40

-72

10 12

150 180

UNIT

w

w

w

w

%

VDD

dB

J,JVRMS

dB

kQ

kQ

3.4 Pinning

4 Audio amplifier stage with TPA3113 (U168)

4.1 General Description

This chassis uses a 6 W Class D Mono Audio Amplifier for from 26” to 32” TVs.
The TPA3113D2 is a 6 W (per channel) efficient, Class-D audio power amplifier for driving
bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of
inexpensive ferrite bead filters at the outputs while meeting EMC requirements.
SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a
DC detection circuit. The adjustable power limiter allows the user to set a "virtual" voltage
rail lower than the chip supply to limit the amount of current through the speaker. The DC
detect circuit measures the frequency and amplitude of the PWM signal and shuts off the
output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3113D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the
TPA3113D2, 87%, eliminates the need for an external heat sink when
playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output.
The short-circuit protection and thermal protection includes an auto-recovery feature.

3.2. Features

• 6 W/ch into an 8-Ω Loads at 10% THD+N From a 10-V Supply

• 12-W into a 4-Ω Mono Load at 10% THD+N From a 10-V Supply

• 87% Efficient Class-D Operation Eliminates Need for Heat Sinks

• Wide Supply Voltage Range Allows Operation from 8 V to 26 V

• Filter-Free Operation

• SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC

Protection

• Flow Through Pin Out Facilitates Easy Board Layout

• Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto

Recovery Option

• Excellent THD+N / Pop-Free Performance

• Four Selectable, Fixed Gain Settings

• Differential inputs

4.2 Absolute Ratings

4.2.1 Electrical Characteristics

65

IJV

·

c

·c

p

4.2.2 Operating

AC

CHARACTERISTICS

TA

= 25•c, Vee =

KsvR

THO+N Total

Vn

SNR Signa-l

fosc

12

V, RL

PARAMETER TEST CONDITIONS

Supply

ripple rejection

harmonic

Output integrated nois

Crosstalk

to-noise ratoi

Oscillator frequency

T

hermal trip

The

point

rmal hysteresis

4.3

NAME

so

FAULT

LI

LINN

GAlNO

GAIN1

AVCC

AGNO

GVOO

PLIMIT

RINN

RINP

NC

PBTL

PVCCR

PVCCR

BSPR

OUTPR

PGNO

OUTNR

BSNR

BSNL

OUTNL

PGNO

OUTPL

BSPL

PVCCL

PVCCL

Pinning

PIN

NP

Specifications

= 8 0

(unless

distortion +noise RL = 8

e

Pin

Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

otherwise noted

200 mVpp
Gain

20 Hz to 22 kHz,A-weighted fi

P0 = 1 W,Gain

Maxi

Gain

110/P

I

0

I

I

I

Gani select

I

Gani seel ct most

0

I

I

I

I

p

p

I

Bootstrap 110

0

0

I

Bootstrap 1/0 for right channel,

I

Bootstrap 1/0

0

0

I

Bootstrap 1/0 for left c

p

p

)

ripple

from 20

= 20 dB,Inputs ac-coupled to AGNO

0, f = 1kHz, Po = 3 W (half-p

= 20 dB, f = 1 kHz

mum output at
= 20 dB, A-weighted

Shutdown
enabled).TTL l

Open
compilant to

FAULT pin

be reset by cycling PVCC.

Postiive

Negative audio input for left channeL

Analog supply

Analog signalgrou

High-side

as

Power
powerlimit. Connect di

Negative

Positive

Not connected

ParallelBTL

Power supply for right channel H-bridge. Right c

supply inputs

Power supply for right channel H-bri
channel

Class-0

Power ground for the H-bri

Class-0

Class-0 H-bridge ne

Power

Class-0

Power supply for left
supply

Power supply for left
supply

logic input for audio amp (LOW =

drain output

audio

FET gate drive suppl

supply for PLIMIT function

limti leveladjust

audio input for right ch

audio

power

H-bridge

H-bridge

ground

H-bridge

inputs are

i

nputs

Hz-1kHz,

lter, Gani = 20 dB

THO+N

<

1%, f = 1 kHz

ogic l

evels with

used to display short cir

AVCC.Short circuit

to

SO pin. Otherwise,

input

for left channeL

least sign

ifi

cant bit. TTL

significant bit TTL logic l

nd.

Connect to the thermal pad.

Connect a resistor divi

rectly to

input

for right

channeL Bi

mode switch

are connect internally.

supply inputs

for

right channel, positive

positive output

negative

for left c

for the H-bri

positive output

connect internally.

are connect internally.

are connect internally.

dges.

output for right c

hanne,l n

egative high-side FET.

gative output

dges.

hanne,l positive

channelH-bridge.

channelH-bri

ower)

,

DESCRIPTION

compli

ance to AVCC.

faults can be set

y.Nominalvol

GVOO for no power limit.

anne.l Biased at

negative

cuit

both

short circuit

Biased at

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5 Power stage

The DC voltages required at various parts of the chassis and panel are provided by a
main power supply unit. This chassis can operate with the different supplies: IPS60,
IPS16, IPS17, PW26, PW27 as main power supply and also with 12V adaptor.

CN706 is used for IPS60, IPS16 and IPS17 and CN1 is used for PW26 and PW27.

JK9 is used for the adapter option and also CN705 inverter socket or DB32 chassis with
CN706 is used to supply backlight.

The power supplies generate 18V, 12V, 5V, 3,3V and 12V, 5V, stand- by mode DC
voltages. Power stage which is on-chassis generates 5V, 3V3 stand by voltage and 12V,
8V, 5V, 3V3, 2.5V, 1,8V and 1,2V supplies for other different parts of the chassis. Chassis
block diagram is indicated below.

The blocks on power block diagram is using dependent to main supply. For PW26 and
PW27 just common blocks are enough for proper operation.

For IPS16, IPS17, IPS60 below blocks must work properly.

For adapter case also below blocks are necessary.

Short CCT Protection Circuit

Short circuit protection is necessary for protecting chassis and main IC against damages
when any Vcc supply shorts to ground. Protect pin should be logic high while normal
operation. W hen there is a short circuit protect pin shold be logic low. After any short
detection, SW forces LEDs on LED card to blink.

5.1 Power management

--- Power Management with Adaptor---

--- Power Management with PW25/ PW26---

--- Power Management with IPS16/IPS17/IPS60/PW05---

--- Power Management with PW03/PW04/PW07---

6 Microcontroller – MSTAR (U5)

6.1 Description

MSD9WB9PT-2 (Main IC) (U5)

The MSD9WB9PT-2 is MStar’s most up-to-date system-on-chip solution for flat panel
integrated digital television products. Building on the success of MStar’s preceding SOC
series, the MSD9WB9PT-2 provides most cost-effective solution for DTV application with
creative and attractive features exclusively presented by MStar.
The MSD9WB9PT-2 integrates DTV/multi-media all-purpose AV decoder, DVB-T
demodulator, VIF demodulator, and Sound/Video processor into a single device. This
allows the overall BOM to be reduced significantly making the MSD9WB9PT-2 a very
competitive multi-media DTV solution. For ATV users, the MSD9WB9PT-2 provides multi­standard analog TV support with adaptive 3D video decoding and VBI data extraction.
The build-in audio decoder is capable of decoding FM, AM, NICAM, A2, BTSC and EIA-J
sound standards. The MSD9WB9PT-2 supplies all the necessary A/V inputs and outputs
to complete a receiver design including a multi-port HDMI receiver and component video
ADC. All input selection multiplexed for video and audio are integrated, including full
SCART support with CVBS output. The equipped MStar MACE-5 color engine is the
latest masterpiece from
MStar famous color engine series providing excellent video and picture quality in Full-HD
and large-scale displaying system.
To meet the increasingly popular energy legislative requirements without the use of
additional hardware, the MSD9WB9PT-2 has an ultra low power standby mode during
which an embedded MCU can act upon standby events and wake up the system as
required.

The MSD9WB9PT-2 is composed of several modules:

• High Performance Micro-processor

o Ultra high speed/performance 32-bit RISC CPU
o One full duplex UARTs
o Supports USB and ISP programming
o DMA Engine

• Transport Stream De-multiplexer

o Supports parallel and serial TS interface, with or without sync signal
o Supports TS input and output for external CI module
o Maximum TS data rate is 104 Mb/sec for serial or 16 MB/sec for parallel
o 32 general purpose PID filters and section filters for each transport stream

de-multiplexer

o Supports additional audio/video/PCR filters
o Supports TS DMA channel for time-shift
o Supports 3DES/DES and AES encryption/decryption

• MPEG-2 Video Decoder

o ISO/IEC 13818-2 MPEG-2 video MP@HL
o Automatic frame rate conversion
o Supports resolution up to HDTV (1080i, 720p) and SDTV

•

MPEG-4

•

Hardware

•

NTSC/PAL/SECAM

•

Multi-Standard TV Sound Processor

•

Audio Interface

Video Decoder

o ISO/IEC 14496-2 MPEG-4 ASP video decoding
o Supports resolutions up to HDTV (1080p@30fps)
o

Supports DivX1 Home Theater & HD profilesOptional

o Supports VC-1Optional, FLV video format decoding

JPEG

o Supports sequential mode, single scan
o

Supports both color and grayscale pictures

o Following the file header scan the hardware decoder fully handles the

decode process

o Supports programmable Region of Interest (ROI)
o Supports formats: 422/411/420/444/422T
o Supports scaling down ratios: 1/2, 1/4, 1/8
o Supports picture rotation

o Supports NTSC-M, NTSC-J, NTSC-4.43, PAL (B,D, G, H, M, N, I, Nc),

and SECAM standards

o Automatic standard detection
o Motion adaptive 3D comb filter
o Five configurable CVBS & Y/C S-video inputs
o

Supports Teletext, Closed Caption (analog CC 608/ analog CC 708/digital

608/digital CC708), V-chip and SCTE

CC

o SIF audio decoding
o Supports BTSC/A2/EIA-J demodulation
o Supports NICAM/FM/AM demodulation
o Supports MTS Mode Mono/Stereo/SAP in BTSC/ EIA-J mode
o Supports Mono/Stereo/Dual in A2/NICAM mode
o Built-in audio sampling rate conversion (SRC)
o Audio processing for loudspeaker channel, including volume, balance,

mute, tone, EQ,virtual stereo/surround and treble/bass controls

o Advanced sound processing options available,for example: SRS1, BBE2,

QSound3, Audyssey4

o Supports digital audio format decoding:

MPEG-1,


 Supports Optional Dolby Digital Plus, Dolby mPulse, and MS10

multistream decoder, including Dolby Digital Encoder for
transcoding streams to Dolby Digital 5.1 (DDCO)

 Supports MPEG Audio, Dolby Digital, Dolby Digital Plus format AD

(Audio Description)

o Supports PVR and time-shifting

o One SIF audio input interface with minimal external saw filters
o Four L/R audio line-inputs
o Two L/R outputs for main speakers and additional line-outputs
o Supports stereo headphone driver

2

o I

S digital audio input & output

o S/PDIF digital audio output
o HDMI audio channel processing
o Programmable delay for audio/video synchronization

Video

Decoder

MPEG-2 (Layer I/II), MP3, Dolby Digital (AC-3), AAC-LC

o

Analog RGB Compliant

Input

Port

o Three analog ports support up to 1080P
o

Supports PC RGB input up to SXGA@75Hz

o Supports HDTV RGB/YPbPr/YCbCr
o Supports Composite Sync and SOG Sync-on-Green
o Automatic color calibration
o

AV-link support

o Analogue RGB Auto-Configuration & Detection
o Auto input signal format and mode detection
o Auto-tuning function including phasing, positioning, offset, gain, and jitter

detection

o Sync Detection for H/V Sync

•

DVI/HDCP/HDMI

Compliant

Input

Port

o Two HDMI/DVI Input ports
o HDMI 1.3 Compliant
o HDCP 1.1 Compliant
o 225 MHz @ 1080P 60 Hz input with 12-bit Deep-color support
o CEC support
o Single link DVI 1.0 compliant
o Robust receiver with excellent long-cable support

• MStar Advanced Color Engine

(MStarACE

-5)

• 10/12-bit internal data processing

• Fully programmable multi-function scaling engine

o

Nonlinear video scaling supports various modes including

o

Supports dynamic scaling for

VC

-1

• High-Quality DTV video processor
o

3D motion video deinterlacer with motion object st

o

Edge-oriented deinterlacer with edge and artifact smoother

o Automatic

3:2/2:2/M:N

pull-down detection and recovery

o 3D multi-purpose noise reduction for DTV or lousy air/cable input
o

MPEG
reduction

o

Arbitrary frame rate

artifact removal including de-blocking and mosquito noise

conversion

• MStar Professional Picture Enhancement:
o

Dynamic brilliant and fresh

o

Dynamic Blue Stretch

o

Intensified contrast and

o

Dynamic Vivid

o

Dynamic sharpened Luma/Chroma

o

Global and local dynamic depth of field perception

o

Accurate and independent color control

o

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o

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details

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• Programmable 12-bit RGB gamma CLUT

• Output Interface

o Single/dual link 8/10-bit LVDS output
o Supports panel resolution up to Full-HD (1920x1080) @ 60Hz
o Supports TH/TI format
o Supports dithering options to 6/8-bit output
o Spread spectrum output for EMI suppression

•

CVBS

Video

Encoder

o Supports all NTSC/PAL TV Standard
o Stand-alone scaling engine
o Programmable Hue, Contract, Brightness
o Supports TTX/CC/WSS output

o

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abilizer

Pa

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o Allows CVBS output of all source inputs

•

2D Graphics

Engine

o Hardware Graphics Engine for responsive
o Interactive applications
o Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid

draw

o BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt
o Raster Operation (ROP)
o Support Porter-Duff

•

VIF Demodulator

o Compliant with NTSC M/N, PAL B, G/H, I, D/K, SECAM L/L' standards
o Audio/Video dual-path processor
o Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution
o

Maximum IF gain of 37 dB

o Programmable TOP to accommodate different tuner gain and SAW filter

insertion loss to optimize noise and linearity performance

o Multi-standard processing with single SAW
o Supports silicon tuner low IF output architecture

•

DVB-T Demodulator

o Digital carrier frequency offset correction: ±500KHz
o Optimised for SFN channels with pre/post-cursive echoes inside/outside

the guard

o Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset
o Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test

requirement

o ±400kHz internal carrier offset recovery range
o 6.8 usecs echo cancellation at 7 Msym/s
o Supports IF, low-IF, zero-IF inputs
o

Ultra-fast automatic blind UHF/VHF channel scan (constellations and
symbol rate)

•

Co

nnectivity

o Two USB 2.0 host ports
o USB architecture designed for efficient support of external storage

devices in conjunction with off air broadcasting

•

Miscellaneous

o DRAM interface supporting one 16-bit DDR2 @1066MHz
o Supports PVR
o Supports Common Interface for conditional access support
o Bootable SPI interface with serial flash support
o Parallel interface for external NAND flash support
o Power control module with ultra low power MCU available in standby

mode

o 380-ball LFBGA package
o Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and

analog)

6.2 MSTAR block diagram

6.3 Reset circuit

Reset circuit using for initiliazing main Mstar IC. Reset condition is high and nomal
working condition is low for RESET pin.

7 CI interface

CI Interface Power Switch:

It is used for CI module supply, when Module is inserted (it means CI detect is low) This
circuit is opened or closed by CI_POWER_CTRL port of main uController

8 USB interface

Main Concept IC has integrated 2 USB 2.0 interface. One of them is used for ethernet
function, the other one is used for USB connectivity for last user. Last user can play video,
picture and audio files. Also digital channels can be record to external storage device by
this interface. All SW files can be updated with interface.

USB circuit has 3 main parts

• Integrated USB 2.0 Host interface of D3K (U5)

• Protection IC (U145)

• Over current protection IC (U8)

9 DDR2 SDRAM K4T1G164QF (U155)

9.1 Description

The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-rate transfer
rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed
to comply with the following key DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip Driver (OCD) impedance adjustment and
On Die Termination. All of the control and address inputs are synchronized with a pair of
externally supplied differential clocks. Inputs are latched at the crosspoint of differential
clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional
strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to
convey row, column, and bank address information in a RAS/CAS multiplexing style. For
example, 1Gb (x8) device receive 14/10/3 addressing. The 1Gb DDR2 device operates
with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1 Gb DDR2 device is
available in 60 ball FBGA(x8) and 84ball FBGA(x16).

9.2 Features

• JEDEC standard VDD = 1.8V ± 0.1V Power Supply

• VDDQ = 1.8V ± 0.1V

• 533MHz fCK for 1066Mb/sec/pin

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 4, 5, 6, 7

• Programmable Additive Latency: 3, 4, 5. 6

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional

feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High

• Temperature Self-Refresh rate enable

• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <

95°C

• All of products are Lead-free, Halogen-free, and RoHS compliant

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10 Scaler and LVDS sockets

10.1 LVDS sockets block diagram

10.2 Panel supply switch circuit

This switch is used to open and close panel supply of TCON. It is controlled by port of
main ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel
supplys are connected to this circuit. All of them are optional according to panels.

11 SPI flash memory - MX25L1005 (U158)

11.1 General Description

MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as
131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L1005 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user
with ease of interface, a status register is included to indicate the status of the chip. The
status read command can be issued to detect completion status of a program or erase
operation via WIP bit. W hen the device is not in operation and CS# is high, it is put in
standby mode and draws less than 10uA DC current. The MX25L1005 utilize MXIC's
proprietary memory cell, which reliably stores memory contents even after 100,000
program and erase cycles.

11.2 Features

• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3

• 1,048,576 x 1 bit structure

• 32 Equal Sectors with 4K byte each, Any Sector can be erased individually

• 2 Equal Blocks with 64K byte each, Any Block can be erased individually

• Single Power Supply Operation

• 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

11.3 Absolute maximum ratings

RATING VALUE
Ambient Operating

Temperature

0°C to 70°C

Storage Temperature -55°C to 125°C
Applied Input Voltage -0.5v to 4.6v
Applied Output Voltage -0.5v to 4.6v

VCC to Ground Potential -0.5v to 4.6v

11.4 Pinning

8-PIN SOP (150mil)

SYMBOL DESCRIPTION
CS# Chip select
SI Serial Data Input
SO Serial Data Output
SCLK Clock Input
HOLD# Hold, to pause the device without

deselecting the device

VCC +3.3v Power Supply

GND Ground

12 NAND Flash memory – NAND512XXA2C (U162)

12.1 General Description

The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page
family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512
Mbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either
528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8
or x16 input/output bus. This interface reduces the pin count and makes it possible to
migrate to other densities without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an
error correction code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.

12.2 Features

• High density NAND flash memories

o 512-Mbit memory array
o Cost effective solutions for mass storage applications

• NAND interface

o x8 or x16 bus width
o Multiplexed address/ data

• Supply voltage: 1.8 V, 3 V

• Page size

o x8 device: (512 + 16 spare) bytes
o x16 device: (256 + 8 spare) words

• Block size

o x8 device: (16K + 512 spare) bytes
o x16 device: (8K + 256 spare) words

• Page read/program

o Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
o Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
o Page program time: 200 μs (typ)

• Copy back program mode

• Fast block erase: 2 ms (typ)

• Status register

• Electronic signature

• Chip Enable ‘don’t care’

• Security features

o OTP area

• Serial number (unique ID) option

• Hardware data protection

o Program/erase locked during power transitions

• Data integrity

o 100,000 program/erase cycles (with ECC)
o 10 years data retention

• RoHS compliant packages

• Development tools

o Error correction code models
o Bad blocks management and wear leveling algorithms

12.3 Pinning

13 LNBH23L (U6)

13.1 Description

Intended for analog and digital satellite receivers,the LNBH23L is a monolithic voltage
regulator
and interface IC, assembled in QFN32 5 x 5 specifically designed to provide the 13 / 18 V
power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna
dish or to
the multi-switch box. In this application field, it offers a complete solution with extremely
low
component count, low power dissipation together with simple design and I²C standard
interfacing.

13.2 Features

• Complete interface between LNB and I²C bus

• Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ.

93% @ 0.5 A)

• Selectable output current limit by external resistor

• Compliant with main satellite receivers output voltage specification

• Auxiliary modulation input (EXTM pin) facilitates DiSEqC™ 1.X encoding

• Accurate built-in 22 kHz tone generator suits widely accepted standards

• Low-drop post regulator and high efficiency step-up PWM with integrated power

NMOS allow low power losses

• Overload and over-temperature internal protections with I²C diagnostic bits

• LNB short circuit dynamic protection

• +/- 4 kV ESD tolerant on output power pins

13.3 Block diagram

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3)

14.1 Description

The M88DS3002 is an advanced single-chip demodulator for digital satellite television
broadcasting. It is fully compliant with the DVB-S/S2 standard and can support QPSK,
8PSK, 16APSK and 32APSK demodulation schemes. The chip provides a fast, easy-to­apply and cost-effective front-end solution for digital satellite receiver. The M88DS3002
accepts baseband differential or single ended I and Q signals from a tuner, then
digitizes, demodulates and decodes the signals, and finally outputs an MPEG transport
stream. The M88DS3002 supports symbol rate from 1 Msps up to 45 Msps, and code
rate from 1/4 to 9/10. Its features cover blind scan, fade detection, timing and carrier
recovery, performance monitoring, co-channel interference cancellation, command
interface, and DiSEqC™ 2.X interface, etc. The device is controlled via a 2-wire serial
bus. The M88DS3002 works properly with 1.25 V and 3.3 V voltage supplies. Typically,
the power consumption is around 390 mW. The chip is available in a 64-pin QFN
package and is RoHS compliant.

14.2 Features

• Multi-standard demodulation

• Compliant with DVB-S/S2 specification

• QPSK, 8PSK, 16APSK and 32APSK demodulation schemes

• Maximum channel bit rate is 130 Mbps

• Maximum symbol rates are: 45 Msps for QPSK and 8PSK; 36 Msps for 16APSK

and 28 Msps for 32APSK

• DSP features

• Symbol rate sweeping

• I/Q impairment cancellation

• Automatic spectrum inversion

• Adaptive equalizer for RF reflection removal

• Roll-off factor automatic identification

• Blind scan for programming search

• High performance on-chip micro-controller

• Multi-error monitor

• Accurate SNR estimation

• Multi-lock indicators

• Clipping rate reporter

• DC removal

• Automatic frequency correction (AFC)

• Fast timing loop acquisition

• Robust frame synchronization scheme

• Phase noise indicator

• Fast system recovery from fading or other abnormal conditions

• Co-channel interference cancellation

• Constellation monitor

• Interface

• DVB-S/S2 common, parallel and serial MPEG output interface compliant

• 2-wire serial bus to configure the device

• 2-wire bus repeater for tuner configuration

• DiSEqC™ 2.X compliant interface

• General purpose output (GPO)

• Dedicated reference clocks (13.5MHz / 27MHz) generation

• System

o On-chip 8-bit ADC
o On-chip PLL for master clock from a 27 MHz external clock or quartz

crystal

o Sleep mode supported

14.3 Pin

Assignment

---Block Diagram of M88DS3002---

15 LM1117 (U175, U180, U181)

15.1 General description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA
of load current. It has the same pin-out as National Semiconductor’s industry standard
LM317. The LM1117 is available in an adjustable version, which can set the output
voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of
tantalum capacitor is required at the output to improve the transient response and
stability.

15.2 Features

• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

• Space Saving SOT-223 Package

• Current Limiting and Thermal Protection

• Output Current 800mA

• Line Regulation 0.2% (Max)

• Load Regulation 0.4% (Max)

• Temperature Range

• LM1117 0°C to 125°C

• LM1117I -40°C to 125°C

10μF

15.3 Applications

• 2.85V Model for SCSI-2 Active Termination

• Post Regulator for Switching DC/DC Converter

• High Efficiency Linear Regulators 15

• 32” TFT TV Service Manual 10/01/2005

• Battery Charger

• Battery Powered Instrumentation

15.4 Absolute maximum ratings

15.5 Pinning

16 MP2012 (U176)

17 General description

The MP2012 is a fully integrated, internally compensated 1.2MHz fixed frequency PWM
step-down converter. It is ideal for powering portable equipment that runs from a single
cell Lithium-Ion (Li+) Battery, with an input range from 2.7V to 6V. The MP2012 can
provide up to 1.5A of load current with output voltage as low as 0.8V. It can also operate
at 100% duty cycle for low dropout applications. With peak current mode control and
internal compensation, the MP2012 is stable with ceramic capacitors and small inductors.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.

17.1 Features

• 2.7-6V Input Operation Range

• Output Adjustable from 0.8V to VIN

• 1 μA Max Shutdown Current.

• Up to 95% Efficiency

• 100% Duty Cycle for Low Dropout

• Applications

• 1.2MHz Fixed Switching Frequency

• Stable with Low ESR Output Ceramic

• Capacitors

• Thermal Shutdown

• Cycle-by-Cycle Over Current Protection

• Short Circuit Protection

• Available in 6-pin 3x3mm QFN

17.2 Pinning

Pin # Name

Description

1

FB

Feedback input. An external resistor divider from

output voltage.

2

GND,

Pad

Ground pin. Connect exposed pad to ground

3

SW

Switch node to the inductor.

4

PVIN

Input supply pin for power FET.

5

VIN

Input Supply pin for controller. Put small
decoupling ceramic near this pin.

6

EN

Enable input, “High” enables MP2012. EN is
pulled to GND with 1Meg internal resistor.

Exposed

18 RTA8283A (U23, U173)

the output to GND, tapped to the FB pin sets the

plane for proper thermal performance.

18.1 General description

The RT8283A is a high-efficiency, monolithic synchronous step-down DC/DC converter
that can deliver up to 3A output current from a 4.5V to 23V input supply. The RT8283A's
current mode architecture and external compensation allow the transient response to be
optimized over a wide range of loads and output capacitors. Cycle-by-cycle current limit
provides protection against shorted outputs and soft-start eliminates input current surge
during start-up. The RT8283A also provides output under voltage protection and thermal
shutdown protection. The low current (<3μA) shutdown mode provides output

disconnect,
enabling easy power management in batterypowered systems. The RT8283A is available
in a SOP-8 package.

18.2 Features

• ±1.5% High Accuracy Feedback Voltage

• Integrated N-MOSFET Switches

• Current Mode Control

• Fixed Frequency Operation : 340kHz

• Output Adjustable from 0.8V to 20V

• Up to 95% Efficiency

• Thermal Shutdown Protection

18.3 Pinning

Pin No.

Pin

Name

Description

1

BOOT

greater ceramic capacitor from BOOT to SW pins.

2

large ceramic capacitor.

3

4, 9 (Exposed

Pad)

5

FB

Feedback Input pin is connected to the converter output.

6

COMP

Compensation Node. COMP is used to compensate the

7

EN

Enable Input Pin. Logic high enables the converter; a

automatic startup.

8

SS

Soft-Start Control Input. SS controls the soft-start period.

Bootstrap for high-side gate driver. Connect a 0.1μF or

VIN

SW Phase Node--Connect to external L-C filter..

GND Ground.

Input Supply 4.5V to 23V. Must bypass with a suitably

It is used to set the output of the converter to regulate to
the desired value via an internal res divider. For an
adjustable output, an external res divider is connected to
this pin.

regulation Control loop. Connect a series RC network
from COMP to GND. In some cases, an additional
capacitor from COMP to GND is required.

logic low forces the RT8253A into shutdown mode.
Attach this pin to VIN with a 100kΩ pull up resistor for

Connect a capacitor from SS to GND to set the soft-start
period. A 0.1μF capacitor sets the soft-start period to

13.5ms.

19 MP1583 (U174)

Pin
No.

Pin

Name

Description

High-Side Gate Drive Bootstrap Input. BS supplies the drive for the

2

IN

Power Input. Drive IN with a 4.75V to 23V power source.

3

SW

Power Switching Out is the switching node that supplies power to the
output

4

GND

Ground.

5

FB

Feedback Input. FB senses the output voltage and regulates it. Drive

threshold is 1.222V.

6

COMP

Compensation Node is used to compensate the regulation control
loop.

19.1 General description

The MP1583 is a step-down regulator with a built-in internal Power MOSFET. It
achieves
3A of continuous output current over a wide input supply range with excellent load and
line regulation. Current mode operation provides fast transient response and eases
loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and
thermal shutdown. An adjustable soft-start reduces the stress on the input source at start­up. The MP1583 requires a minimum number of external components, providing a
compact solution.

19.2 Features

• 3A Output Current

• Programmable Soft-Start

• 100mΩ

Internal

• Stable with Low ESR Output Ceramic Capacitors

• Up to 95% Efficiency

• 20μA Shutdown

• Fixed 385KHz Frequency

• Thermal Shutdown

• Cycle-by-Cycle Over Current Protection

• Wide 4.75V to 23V Operating Input Range

• Output Adjustable from 1.22V to 21V

• Under-Voltage Lockout

Power

Mode

MOSFET Switch

19.3 Pinning

1 BOOT

high-side N-Channel MOSFET switch.

FB with a resistive voltage divider from the output voltage. FB

7

EN

Enable/UVLO. A voltage greater than 2.71V enables operation. For

complete low current shutdown the EN pin voltage needs to be at less

reaches 2.71V.

8

SS

Soft-Start Control Input. SS controls the soft-start period.

than 900mV. When the voltage on EN exceeds 1.2V, the internal
regulator will be enabled and the soft-start capacitor will begin to
charge. The MP1583 will start switching after the EN pin voltage

20 FDC642

20.1 General description

This P-Channel 2.5V specified MOSFET is produced using Fairchild’s advanced
PowerTrench® process that has been especially tailored to minimize on-state resistance
and yet maintain low gate charge for superior switching performance.

These devices have been designed to offer exceptional power dissipation in a very small
footprint for applications where the larger packages are impractical.

20.2 Features

• Max rDS(on) = 65 mΩ at VGS = -4.5 V, ID = -4.0 A

• Max rDS(on)

• Fast switching speed

• Low gate charge (11nC typical)

• High performance trench technology for extremely low rDS(on)

• SuperSOTTM-6 package: small footprint (72% smaller than standard

• Termination is Lead-free and RoHS Compliant

20.3 Pinning

=

100 mΩ at VGS = -2.5 V, ID = -3.2 A

SO-8); low profile (1 mm thick)

21 FDC604P

21.1 General description

This P-Channel 1.8V specified MOSFET uses Fairchild’s low voltage PowerTrench
process. It has been optimized for battery power management applications.

21.2 Features

• –5.5 A, –20 V. RDS(ON) = 33 mΩ @ VGS = –4.5 V

• RDS(ON) = 43 mΩ @ VGS = –2.5 V

=

• RDS(ON)

• Fast switching speed.

• High performance trench technology for extremely low RDS(ON)(S)

21.3 Pinning

60 mΩ @ VGS = –1.8 V

22 Connectors

22.1 SCART (SC1)

22.2 HDMI (CN707, CN708)

-

.

22.3

VGA

(CN711)

14.

VERTICAL

15. DOC CLOCK

SYNC

_.

15

.

23 Service menu mode

To enter the service menu, press MENU-4-7-2-5 keys consecutively, on the remote control. The top-level
service menu will appear. All submenus can be selected via Up/Down keys and displayed by pressing OK
key. When a submenu is displayed, top-level service menu disappears. Pressing RETURN key, returns to
the one level higher menu. Pressing the MENU key will exit service menu.

Some items are changeable at service menu, the values of which are stored in the NVM when the menu is
closed. Some items are read-only, which can only be changed by Profile Manager and displayed in service
menu for convenience.

23.1 Main service menu

Service menu or a sub-menu is displayed on the screen when the TV is in one of the TV/AV/PC modes. It
shows what the items are set in Profile Manager. It is a read-only screen, not writable.

It shows the following items:

 TV Life Time: The number of minutes the set is in the “On” mode.

 Standby SW Version: The version number of the Stand-by software.

 Mboot Version: The version number of the Mboot software.

 PANEL: The LCD panel identification including the software version information.

 PQ: Picture quality tool version information.

 PROFILE: TV specific option profile

 PIX FILES: Not applicable

 HW Profile Version: The version number of the hardware profile.

 SW Profile Version: The version number of the software profile.

 Lan Profile Version: The version number of the Lan profile.

 Customer: Philips

Items exist in the main screen of service menu. Also, software version number and DCF id are written in
the header of service menu.

The main items in Service Menu:

23.2 Video Settings

RF AGC adjustments for neighbour and image channels exist or don't. Also, ADC Calibration gain

and offset values for RGB separately due to selected sources

23.3 Audio Settings

Surround type and surround mode text items are displayed.

23.4 Options 1

Profile options such as AUTO TV off time, Power up mode, EPG type, etc. are displayed in options 1.

23.5 Options 2

Profile options such as APS sorting, Dynamic Menu, Auto zoom mode etc. are displayed in Options 2.

23.6 Tuning Settings

Tuner type is displayed.

23.7 Source Settings

Enable and disabled sources are displayed.

When TV is disabled, Items which are connected to Tuner are picked off from menu. (Install and Retune

Menu, Channel List Menu...).

23.8 Diagnostic

The result of various diagnostic tests are displayed here.

23.9 USB operations

USB operations are performed by pressing that button.

See Service Menu Design Idea for Menu structure, look and feel, position, etc…

Video Settings

• RF AGC SECAM

Options 2

RF AGC NEIGHBOUR NO IMAGE NO

•

RF AGC NEIGHBOUR NO IMAGE YES

•

RF AGC NEIGHBOUR YES IMAGE NO

•

RF AGC NEIGHBOUR YES IMAGE YES

•

RF AGC

•

ADC Calibration Source

•

ADC Calibration R Gain

•

ADC Calibration G Gain

•

ADC Calibration B Gain

•

ADC Calibration R Offset

•

ADC Calibration G Offset

•

• ADC Calibration B Offset

Audio Settings

Options 1

• Surround Type

• Surround Mode Text

• Auto TV OFF

Power Up mode

•

Backlight Trick Mode

•

Cable Support

•

EPG Type

•

Hotel Mode

•

LCN

•

PC Standby

•

Stby Search

•

Test Tool

•

Local Key

•

• Volume Level

• Aps Sorting

Dynamic Menu

•

EPG Menus

•

Transparent Text

•

• HDMI Number

Source Settings

Remote control type

•

• DCF ID

Tuning Settings

• Tuner Type

• TV

•

EXT1

EXT2

•

EXT2-S

•

FAV

•

S-VIDEO

•

HDMI 1

•

HDMI 2

•

HDMI 3

•

HDMI 4

•

YPBPR

•

VGA/PC

•

Diagnostic

• Blu-ray

• Remote control test

UHF test

•

VHF test

•

Factory reset

•

Tuner I2C

•

IF I2C

•

HDMI I2C

•

Ethernet

•

EDID Status

•

HDCP Status

•

DDR Settings

•

CI+ Credentials

•

• MAC Address

USB Operations Press this button to perform USB operations.

USB stick should be connected before this operation.

23.10 Profile Operations

VES1.1E LA profile data are kept in the flash file system as separate files. So they can be downloaded to
USB memory stick or uploaded to TV from a memory stick individually.

23.10.1 Upload profile Data from USB

1. Create a folder named profile in the USB stick.

2. Copy mb62_swprofile.bin and mb62_hwprofile.bin into the USB profile folder.

3. Plug the USB stick into the TV.

4. Open service menu and select “USB Operations”.

The files will be automatically copied to the TV flash file system.

After a reboot, App/Mw will start to use new profiles. It is possible to upload hardware or software profiles

separately.

23.10.2 PQ Files Operations

It is also possible to download/upload PQ files from/into the SSB when USB Operations button in service

menu is pressed.

Whenever a USB stick is connected to TV set and USB Operations button in service menu is pressed, /pq

folder is checked.

If it exists and if they include some files, necessary copy/delete operations are performed.

23.10.3 Upload PQ files from USB

1. Create a folder named “pq” in the USB stick.

2. Copy VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin and Titania2_Main_Text.bin into USB “pq”

folder.

3. Connect USB stick to TV.

4. Open service menu, select “USB Operations”.

The files named VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin, Titania2_Main_Ex.bin and
Titania2_Main_Text.bin

will be copied from USB to TV.

23.10.4 Ci+ credentials key update

1. Create a “spi” folder in root of the memory stick

2. Copy mb62_credentials.bin to “spi” folder

3. Connect the USB stick to the TV.

4. Perform USB Operations in the service menu.

23.10.5 HDCP keys update

1. Create a “spi” folder in root of the memory stick.

2. Copy “mb62_hdcp.bin” to “spi” folder.

3. Connect the USB stick to the TV.

4. Perform USB operations in the service menu.

23.10.6 Edid update

1. Create a “spi” folder in root of the memory stick.

2. Copy “edid.edid” to the “spi” folder.

3. Connect the USB stick to the TV.

4. Perform USB operations in the service menu.

23.10.7 DDR settings update

1. Create a “spi” folder in root of the memory stick.

2. Rename the ddr binary file to be used which resides in the config_mb62 folder as mb62_ddr.bin.

3. Copy the file “mb62_ddr.bin” to the “spi” folder.

4. Connect the USB stick to the TV.

5. Perform USB operations in the service menu.

23.10.8 MAC address update

1. Create “spi” folder in root of the memory stick.

2. Copy the file “mb62_mac.bin” to the “spi” folder.

3. Connect the USB stick to the TV.

4. Perform USB operations in the service menu.

23.11 Hotel Mode setup menu

The hotel mode setup menu has a normal and a high security mode.

To enter the hotel mode setup menu of a set in the normal security mode, press “MENU 7935” on the
remote control belonging to this set.

To enter the hotel mode setup menu of a set in the high security mode, the yellow service remote control
is needed. To navigate through the menu, the remote control that belongs to the set is needed.
To enter the hotel mode setup menu on a set with high security mode, first put the yellow remote in RC5
mode and then press the “Home/Menu” button.

•

Note: To order a yellow remote, use order code: 22AV8573/00 or 12NC 8670 000 67389.

23.11.1 Hotel TV welcome image update (only available in Hotel TVs)

In the VES1.1E LA the welcome image can be updated

Copy To USB

There are two steps and both are independent of each other.

Copy the updated welcome image to USB as “hotel_wel.png”. Copy NVRAM data (service list,
preferences, etc.) to the USB device. In this chassis all nvram data is stored in 8 × 32KB Flash
files named as Flash0.bin, Flash1.bin ... Flash7.bin. When a Copy to USB is called, those files
are copied from TV to USB. Then they can be used for various purposes testing on another TV
or testing/debugging on observatory etc. Note that USB should be plugged before this
operation.

Copy From USB

There are two steps and both are independent of each other.

If there is file named “hotel_wel.png” in directory “welcome_image”. It is copied to the tv to use
as welcome image.

Copy from USB device data to NVRAM. Just the reverse operation is done by a copy to USB
call. Previously copied nvram files (Flashx.bin) are copied into TV. If there is no flash file or
some of them are available on USB, the available ones are copied. If no USB is connected,
nothing happens.

• Note: For the clone function a USB stick (Copy to USB – Copy from USB) must be formatted to FAT32. If the

USB stick is not formatted to FAT32 the other TVs will not accept cloned data and cause performance issues.

:

24 Software update

In the VES1.1E LA there is only one software package. From following steps software update
procedure can be seen:

1. MB62_en.bin, mboot.bin and usb_auto_update_T4.txt documents should copy

flash memory(not in a

2. Put flash memory to the tv when tv is powered

3. Power on the and wait when the tv is

4. If first time installation screen is displayed, it means the software update procedure

folder).

off.

opened.

directly i

nside of a

is successful.

25 Troubleshooting

25.1 No backlight problem

Problem: If TV is working, led is normal and there is no picture and backlight on the panel.

Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin

Backlight pin should be high in open position. If it is low, please check Q181 and panel
cables.

Dimming pin should be high or square wave in open position. If it is low, please check
S16 for Mstar side and panel or power cables, connectors.

Backlight power supply should be in panel specs. Please check CN705 for the SSB,
related connectors for power supply cards.

STBY_ON/OFF should be low for standby on condition, please check R1677.

25.2 CI module problem

Problem: CI is not working when CI module inserted.

Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins
CI supply shoul be 5V when CI module inserted. If it is not 5V please check
CI_POWER_CTRL, this pin should be low.

PCM D7

".

Please check mechanical positions

Detect ports should be low. If
pins

and 3V3_VCC on

the SSB.

Cl Detect

Cl Detect

it

R1632

'A

of the CI module.

is not low please check the Cl connector pins, Cl module

4

7

8

10

11

12

13

14

21
22

23
24

25

27
28
29

30
31

PCM D3
PCM D4

PCM

PCM OB_

PCM A9
PCM AS

DS

PCM D6

PCM CB N
PCM AlO

N

PCM All

PCM A13
PCM A14

12p

sov

3V3_VCC

25.3 LED blinking problem

Problem: LED blinking, no other operation

This problem indicates a short on Vcc voltages. Protect pin should be logic high while
normal operation. When there is a short circuit protect pin will be logic low. If you detect
logic low on protect pin, unplug the TV set and control voltage points with a multimeter to
find the shorted voltage to ground.

25.4 IR problem

Problem: LED or IR not working
Check LED card supply on the SSB.

Ql70

Ql7l

LED

SOCKET

L--<J

+----·2--

C949 600R

·

H

SV

STBY

F259

- -·[>IR

N

@

.-<

BC949B

IN

25.5 Keypad touchpad problems

Problem Keypad or Touchpad is not

Check keypad supply and keyboard pin on

working.

the SSB.

25.6 USB problems

Problem: USB is not working or no USB Detection.

Check USB Supply, It should be nearly 5V.

25.7 No sound problem

Problem: No audio at main TV speaker outputs.

Check supply voltages of VDD_AUDIO, 5V_VCC and 3V3_VCC with a voltage-meter.
There may be a problem in headphone connector or headphone detect circuit (when
headphone is connected, speakers are automatically muted). Measure voltage at
HP_DETECT pin, it should be 3.3v.

25.8 No sound problem at headphone

Problem: No audio at headphone output.

Check HP detect pin, when headphone is. Check 5V_VCC and 3V3_VCC with a voltage­meter.

25.9 Standby On/Off problem

Problem:
Device cannot boot, TV hangs in standby mode.

There may be a problem about power supply. Check 12V_VCC, 5V_VCC and 3V3_VCC with a voltage-meter. Also there
may be a problem about SW. Try to update TV with latest SW. Additionally it is goood to check SW printouts via
hyper-terminal (or Teraterm). These printouts may give a clue about the problem.

25.10 DVD problems

Problem: DVD is not working.

Check that DVD source is selected in Service menu. Check supply voltage of DVD
namely 12V_VCC.

25.11 No signal problem

Problem: No signal in TV mode.

Check tuner supply voltage; 3V3_TUN. Check tuner options are correctly set in Service menu. Check AGC voltage at
IF_AGC pin of tuner.

26 Styling sheet

1

1

DISPLAYASM32" LED

8

METAL FRAME 32"LED

SCREWP C ZN YFMB3 x 9.5

1

IR

17LD98

1

1

1

3

5

6

7

11

9

10

2

1

COVER FOOT

2

ASM

BACKCOVER32130 LED DVD

1

4

8

BACKCOVERMETAL32130

SCREWP C ZN Y

10

11

1

2

27 Schematics

4k7

R16

1

2

5V_VCC

BC848B

Q172

ANT_CTRL

FDN336P

Q175

10k

R1590

3V3_S2_TUN

R1581

1k

10k

R1595

16V

C29 10n

S2_AGC

12V_VCC

1k

R31

10n

16V

C25

R22

10k

R1593

10k

F1

60R

TSMISYNC

TSMICLK

3V3_S2_VDDD

SUT-RE216 TU3

5

4

3

2

1

6

7

8

9

IF_AGC

IF_P

IF_N

RESET

ANT-DC

+3V3

SCL

SDA

GND

R32

1k

C26

16V

10n

3V3_S2_TUN

S2_QP

S2_QN

S2_IN

S2_IP

3V3_S2_TUN

C24

50V

27p

M88DS3002

U3

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

323130292827262524232221201918

17

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

495051525354555657585960616263

64

NC5

GPO

VCC_10

NC4

NC3

VDDD_4

NC2

NC1

NC9

NC8

LOCK

VCC_9

LNB_EN

CKXTAL_13

OLF

GNDD

M_CKOUT

M_SYNC

VCC_8

M_VAL

M_ERR

M_DATA7

M_DATA6

VDDD_3

M_DATA5

M_DATA4

VCC_7

M_DATA3

M_DATA2

M_DATA1

M_DATA0

VCC_6

AAGC

SCLT

SDAT

VCC_3

SDA

SCL

VDDD_2

ADDR_SEL1

ADDR_SEL0

VCC_4

VSEL

DISEQC_IN

DISEQC

VCC_5

CKXTAL_27

RESET

GNDA_1

XTAL_IN

XTAL_OUT

VDDA_1

GNDA_2

IP

IN

VDDA_2

GNDA_3

QN

QP

NC6

VDDD_1

VCC_1

VCC_2

NC7

LNB_OUT

1n

C16

50V 50V

C17

1n

50V

C18

1n

1V25_S2_VDDI

3V3_S2_TUN

R1594

10k

27MHz

X1

3

1 4
2

50V

C23

27p

OVER_CUR_DETECT

3V3_S2_VDDA

3V3_S2_TUN

3k3

R39

C27

16V

10n

S5

12

S11

12

C965

16V

100n

47R

R27

R28
47R

S12

1

2

1V2_VCC

F2

60R

S20

1 2

3V3_VCC

F3

60R

3V3_VCC

10n

16V

C28

100n 10V

C44

10V

C45

100n

SDA_S2_TUN

R35
33R

33R

R36

SCL_S2_TUN

S2_IP

20k

R1586

C21

50V

27p

27p

50V

C22

3V3_S2_TUN

3V3_S2_TUN

M88TS2022

U4

28272625242322

21

20

19

18

17

16

15

8

9

1011121314

1

2

3

4

5

6

7

VDDA2

CK_OUT

IP

IN

VDDA1

QN

QP

VDDA4

TEST1

TEST2

TEST3

VDDA3

XTALN

XTALP

RES

CAP

CKDIV_OPT

RFBYPASS

RESET

LNA_IN

TEST

VDAA5

VDD_DIG

SDA

SCL

VDD_REG

AGC

VDDA6

S138

12

2R1

TH1

CN17

S25

1

2

50V

C62

2p2

C63

2p2
50V

33p

C35

50V

50V

1n

C19

10k

R4

L1

4n7

IF_AGC_TUNER

47R

R1583

1

2

3456

7

8

R4

R1

R3

R2

TS_MDI3

TS_MDI2

TS_MDI1

TS_MDI4

TS_MDI5

TS_MDI6

TS_MDI7

3V3_S2_VDDA

10p

C8

10p

C9

S2_IN

C30

16V

10n

10nC31

16V

C32 10n

16V

S2_QN

10p

C10

C11

10p

S2_QP

3V3_S2_VDDD

10V

C38

100n

1V25_S2_VDDI

1V25_S2_VDDI

3V3_S2_VDDA

10V

C36

100n

100n

C37

10V

SDA_S2_TUN

SCL_S2_TUN

R13

4k7

1

2

4k7

R14

1

2

3V3_S2_VDDD

C910

10V

100n

1

2

TS_MDI0

100n

C912

10V

1

2

R1584

47R

1

2

3456

7

8

R4

R1

R3

R2

10k

R1597

IF_AGC_MST

C20

50V

1n

Ulas Dereli

TUNER&S2_TUNER&DEMOD

8

17mb62-1

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:

A3

PROJECT NAME :

SCH NAME :

DRAWN BY :

SHEET:

14-03-2011_17:04

S41

S40

TP47

1

TP48

1

TUN_SCL

R29

47R

TUN_SDA

TUN_SDA

33p

C34

50V

TUN_SCL

ACTIVE_ANT_SUPPLY

C904

100n

10V

1

2

TUN_SCL_MST

10V100n

C52

C53

100n 10V

C54

10V100n

10V

C55

100n

100n 10V

C56

10V100n

C57

47R
R30

60R

F4

3V3_VCC

1k

F304

D206

C5V6

TUN_SDA_MST

3V3_S2_TUN

16V

22u

C60

3V3_S2_VDDD

FK1601 TU1

5

4

3

2

1

6

7

8

9

IF_AGC

IF_P

IF_N

CLK_OUT

ANT-DC

VCC

SCL

SDA

GND

ACTIVE_ANT_SUPPLY

C61

6V3

22u

C58
22u
6V3

22u
6V3

C59

3V3_TUNER

DIGITAL_IF_N

DIGITAL_IF_P

IF_AGC_TUNER

27MHz

X3

3

1 4

2

100R

R1963

1 2

10n

C33

16V

18p

C72

50V

S2_AGC

R44

2k

R15

4k7

1

2

3V3_TUNER

IF_AGC_TUNER

3V3_S2_VDDD

TSMIVALID

DIGITAL_IF_P

DIGITAL_IF_N

SDA_SYS

SCL_SYS

50V

18p

C73

33R

R37

33R

R38

100n 10V

C39

C40

10V100n

3V3_S2_VDDD

C46

10V100n

10V

C47

100n

1V25_S2_VDDI

DISEQC_OUT

10V

C48

100n

100n 10V

C49

1V25_S2_VDDI

ACTIVE_ANT_SUPPLY

RESET_S2

C50

100n 10V

1V25_S2_VDDI

1V25_S2_VDDI

1V25_S2_VDDI

3V3_S2_VDDD

47R

R26

1V25_S2_VDDI

50V

12p

C71

1V25_S2_VDDI

3V3_S2_VDDD

1V25_S2_VDDI

10V

C41

100n

10V

C42

100n

100n 10V

C43

RESET_TUNER

SONY TUNER

NC

NUTUNE/SEMCO/LG

NC

NC

0.5pF

3.3pF

27 MHZ KULLANILACA K

NC

NCNCNCNC

00 SEÇILDI WRITE:D0H READ:D1H

KONTROL EDILECEK

NC

NC

27.1 SSB

NUP4004M5

D5

543

2

1

CN711

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R1505

470R

75R

R1479

12

F179

1k

DVD_IR

DVD_IR_ON/OFF

3V3_VCC

4k7

R694

12

47k

R498

1 2

Q157

BC848B

123

IR_IN

TP245

1

CDA4C16GTH

D4

123

4 5

678

12V_VCC

DVD_CVBS_IN

R1650

180R

75R

R1652

S80

1 2

DVD_WAKEUP

FS1

4A/24VDC

1 2

TP250

1

R1974

33R

R1975

33R

50V

27p

C828

1 2

CN704

1 2

3 4

5 6

7 8

9 10

R1616

4k7

12

DVD_SPDIF

100R

R1624

1 2

10V

100n

C628

1 2

DVD_SENSE

50V

27p

C650

1 2

TP247

1

DVD_IR

C972

50V

220p

R1623

100R

R1976

33R

TP49

1

2k7

R1209

TP50

1

U5

MSD9WB9PT-2

K2

K3

J2

J3

H1

H3

H2

L6

L5

L3

K1

M3

L2

N3

M2

L1

M5

N4

R2

R3

P2

P1

N1

N2

P3

T1

U2

U3

V2

T3

T2

U1

VCOM

CVBSOUT0

CVBS4

CVBS3

CVBS2

CVBS1

CVBS0

SOGIN2

BIN2P

BIN2M

GIN2P

GIN2M

RIN2P

RIN2M

VSYNC1

HSYNC1

SOGIN1

BIN1P

BIN1M

GIN1P

GIN1M

RIN1P

RIN1M

VSYNC0

HSYNC0

SOGIN0

BIN0P

BIN0M

GIN0P

GIN0M

RIN0P

RIN0M

5

SCART_AUD_R_IN

RCA_Y

220R

R124

C884

47n

16V

Ulas Dereli

PERIPHERALs

8

17mb62-1

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:

A3

PROJECT NAME :

SCH NAME :

DRAWN BY :

SHEET:

14-03-2011_17:05

50V

C823

27p

1 2

27p

C829

50V

1 2

RCA_PR

RCA_PB

JK1

7

6

5

4

3

2

1

TP242

1

TP2

1

TP3

1

TP13

1

R1619

75R

12

S9

1 2

47n

C882

16V

JK3

7

6

5

4

3

2

1

R1621

75R

1

2

S42

1 2

JK4

1

2

3

4

5

6

YEL

WHT

RED

VGA_VSNC

VGA_HSNC

5V_VCC

2k7

R1206

D3

CDA4C16GTH

123

45

678

R1265

10k

1

2

R1310

10k

1 2

10V

C663
100n

1

2

VGA_B

VGA_R

VGA_G

10k

R1311

1 2

75R

R1620

1

2

16V

C807

47n

16V

47n

C806

C802

16V

47n

C881

16V

47n

1n

C859

50V

C810

16V
47n

R104

33k

100R

R1243

68k

R103

SC_CVBS_OUT

Q119

BC848B

1

2

3

390R

R102

SCART_CVBS_OUT

12V_VCC

BC858B

Q146

1

2

3

10V

10u

C378

16V

C120

100n

C5V6

D171

3n3

C856

50V

F202

600R

1 2

CDA4C16GTH

D2

123

45

678

4n7

50V

C858

SC_AUD_R_OUT

D1

CDA4C16GTH

123

45

678

C853

50V

3n3

C835

50V

220p

1 2

C833

50V

220p

12

3n3

C854

50V

SC_AUD_R_IN

600R

F206

1 2

C831

220p

50V

12

100R

R1245

1 2

F201

600R

1 2

SCART_AUD_R_IN

SCART_AUD_L_IN

RX/SCL_SC

TX/SDA_SC

C836

220p

50V

12

75R

R1482

12

SC_CVBS_OUT

C832

50V

220p

12

R1182

4k7

1 2

SC_PIN8

220R

R1233

R221

100R

SC_CVBS_IN

SC_G

SC_R

SC_B

SC_FB

R1483

75R

12

10V
C664

100n

12

D178

C15V

12

22k

R1187

1 2

C857

4n7

50V

SC_AUD_L_OUT

F205

600R

1 2

SC_AUD_L_IN

600R

F200

1 2

100R

R1244

1 2

SC1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

SCART LT1

R1486

75R

2

600R

F203

1 2

C830

220p

50V

1

2

SAV_CVBS_IN

SAV_L_IN

SAV_R_IN

3n3

C855

50V

S39

1 2

47n

C809

16V

SAV_R

SAV_L

SAV_CVBS_IN

R1420

33R

47n
16V

C808

C862

1n 50V

R1409

33R

16V

C885

47n

SAV_L

VGA_R

VGA_G

VGA_B

VGA_HSNC

VGA_VSNC

1n50V

C861

470R

R1423

VGA_G

SC_R

SC_G

SC_B

SC_CVBS_IN

SC_FB

R1415

33R

SC_CVBS_IN

SAV_CVBS_IN

C800

16V

47n

16V

C803

47n

47n

16V

C804

100R

R1949

47n

16V

C805

DVD_CVBS_IN

R1516

75R

1

2

R1422

33R

RCA_Y

RCA_Y

RCA_PB

R1481

75R

12

RCA_PR

470R

R1494

16V

C886

47n

16V

47n

C883

R1408

33R

33R

R1421

R1419

33R

16V

47n

C798

C796

16V

47n

C79747n
16V

R11

300R

SC_R

SCART_CVBS_OUT

75R

R1480

12

75R

R1489

12

16V
47n

C795

33R

R1413

47n

C799

16V

33R

R1412

R1411

33R

16V

C794

47n

75R

R1485

1

2

75R

R1515

12

47R

R1249

R1517

75R

1

2

10u

C973

16V

SCART_AUD_L_IN

SC_CVBS_IN

JK7

1

2

3

4

YEL

WHT

RED

TP38

1

TP44

1

TP42

1

TP4

1

R1587

75R

TP43

1

TP1

1

TP5

1

16V

47n

C959

33R

R1530

47p

C860

50V

R620
100R

SAV_R

SCART

DVD INTERFACE (for 26" to 32")

!

YPbPr Slim INPUT

INDIA OPTION

SCART VIDEO OUTPUT AMPLIFIER

SAV Slim INPUT

SAV RCA INPUT

PC INPUT

1UF

62R

62R

62R

SC SVHS opt

62R

30064869

NC

30062423

30062840

Ulas Dereli

17mb62-1

8

RAM&NAND&CI

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:

A3

PROJECT NAME :

SCH NAME :

DRAWN BY :

SHEET:

14-03-2011_17:06

R1950

10k

4k7

R8

R9

4k7

3V3_VCC

4k7

R1971

R1663

4k7

12

R1618

4k7

1 2

TUN_SCL_MST
TUN_SDA_MST

1V8_VCC

DDR18V

R10

4k7

16V

100n

C913

330R

F8

12

3V3_TUNER

IF_AGC_MST

R12

4k7

22R

R1313

22R

R1986

R1987

22R

22R

R1984

R1985

22R

22R

R1603

F181

60R

R1613

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

OVER_CUR_DETECT

R1610

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

50V4p7

C967

3V3_VCC

R1172

4k7

33R

R1425

R1427

33R

100R

R5

C905

10V

100n

R33
33R

C712

10V

100n

1

2

C709

10V

100n

1

2

C710
100n
10V

1

2

R6

100R

VCC_PCMCIA

10V

220n

C1214

DDR18V

AVDD_DDR

R1356

1k

22R

R1367

1
2
3
4 5

6

7

8

R1
R2
R3
R4

1k

R1365

DDR18V

1k

R1355

220n

10V

C683

1k

R1364

C715

220n

10V

220n

10V

C714

10V

220n

C716

C711

220n

10V

C713

10V

220n

DDR18V

C5V6

D205

22R

R1982

R1380

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

R1370

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

R1366

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

R1609

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

22R

R1369

1
2
3
4 5

6

7

8

R1
R2
R3
R4

U155

HY5PS121621C

J1R1M9J9E1A1G9G7G3G1E9C9C7C3C1

A9

J2J7H8H2F8F2E7D8D2B8B2

A7

P9

N1

J3

E3

A3

K9

K8

J8

K2

L8

K3

L7

K7

L3

L2

R2

P7

M2

P3

P8

P2

N7

N3

N8

N2

M7

M3

M8

R8

R7

R3

L1

E2

A2

B3

A8

B7

B9

B1

D9

D1

D3

D7

C2

C8

F9

F3

E8

F7

F1

H9

H1

H3

H7

G2

G8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

LQDS

LQDS_P

LDM

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQS

UDQS_P

UDM

NC1

NC2

NC3

NC4

NC5

NC6

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

BA0

BA1

RAS_P

CAS_P

WE_P

CS_P

CKE

CK

CK_P

ODT

VSS1

VSS2

VSS3

VSS4

VSS5

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSDL

VREF

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDD1

VDD2

VDD3

VDD4

VDD5

VDDL

3V3_VCC

R1513

33R

C906

10V

100n

U5

MSD9WB9PT-2

C10
D21

A9

E20

B9

E19

C9

F20

B8
F19
D20

C8
F21

C13
A19
A12
B19
A20
B12
C19
A13
B14
C18
C14
A18
B18
B13
B17
C15

A16
C16
A15
B15

B16
C17

C12
B11
C20

B20
B10
A10
C21
B21
D19
C11

F18

MVREF

A_ODT

A_BADR[2]

A_BADR[1]

A_BADR[0]

A_CASZ

A_RASZ

A_WEZ

A_MCLKE

A_MCLKZ

A_MCLK

A_DQM[1]

A_DQM[0]

A_DQSB[1]

A_DQS[1]

A_DQSB[0]

A_DQS[0]

A_MDATA[15]

A_MDATA[14]

A_MDATA[13]

A_MDATA[12]

A_MDATA[11]

A_MDATA[10]

A_MDATA[9]

A_MDATA[8]

A_MDATA[7]

A_MDATA[6]

A_MDATA[5]

A_MDATA[4]

A_MDATA[3]

A_MDATA[2]

A_MDATA[1]

A_MDATA[0]

A_MADR[12]

A_MADR[11]

A_MADR[10]

A_MADR[9]

A_MADR[8]

A_MADR[7]

A_MADR[6]

A_MADR[5]

A_MADR[4]

A_MADR[3]

A_MADR[2]

A_MADR[1]

A_MADR[0]1

BSH103

Q209

R1385

33R

1

2

3456
7
8

R1

R2

R3

R4

R1171

4k7

R1514

33R

33R

R1402

R1983

22R

U5

MSD9WB9PT-2

K21
L19
M19
T12
U13
V14
V12
V18

R19
P19
N21
N19
V20
U20
T20
T19
P17
N18
U17
V16
R20
R17
T16
V19

W21
U16
V17
T17
V21
T14
M21
P16
N20

G21
G20
G19

U10
T9
V11
U11
U9
T10
V9

P18
R18
T18
W19
Y21
Y19
R21
T21
Y20
W20
R16

K20
L20
M20
T13
U14
U12
T11
U18
U19
P20
K19

W1
Y1

AA2
Y2

Y3
AA3

W5
W4

AA4
Y4
W6
Y5

GPIO69

GPIO68

GPIO67

GPIO66

RF_AGC

IF_AGC

SIFM

SIFP

VIFM

VIFP

IM

IP

TS0SYNC

TS0VALID

TS0CLK

TS0DATA[7]

TS0DATA[6]

TS0DATA[5]

TS0DATA[4]

TS0DATA[3]

TS0DATA[2]

TS0DATA[1]

TS0DATA[0]

TS1SYNC

TS1VALID

TS1CLK

TS1DATA[7]

TS1DATA[6]

TS1DATA[5]

TS1DATA[4]

TS1DATA[3]

TS1DATA[2]

TS1DATA[1]

TS1DATA[0]

F_RBZ/GPIO136

PF_WEZ/GPIO134

PF_OEZ/GPIO 133

PF_CE1Z/GPIO 132

PF_CE0Z/GPIO 131

PF_AD[15]/GPI O130

PF_ALE/GPIO 135

GPIO127

GPIO128

GPIO125

PCMREG/CI_CLK

PCMIOW/CI_WR

PCMWAIT/CI_WACK

CI_CD

PCMWEN

PCMCEN/CI_CS

PCMIOR/CI_RD

PCMOEN

PCM_IRQ/CI_INT

CI_RST

PCMADR[14]/CI_A [14]

PCMADR[13]/CI_A [13]

PCMADR[12]/CI_A [12]

PCMADR[11]/CI_A [11]

PCMADR[10]/CI_A [10]

PCMADR[9]/CI_A[9]

PCMADR[8]/CI_A[8]

PCMADR[7]/CI_A[7]

PCMADR[6]/CI_A[6]

PCMADR[5]/CI_A[5]

PCMADR[4]/CI_A[4]

PCMADR[3]/CI_A[3]

PCMADR[2]/CI_A[2]

PCMADR[1]/CI_A[1]

PCMADR[0]/CI_A[0]

PCMDATA[7]/CI_DATA[7]

PCMDATA[6]/CI_DATA[6]

PCMDATA[5]/CI_DATA[5]

PCMDATA[4]/CI_DATA[4]

PCMDATA[3]/CI_DATA[3]

PCMDATA[2]/CI_DATA[2]

PCMDATA[1]/CI_DATA[1]

PCMDATA[0]/CI_DATA[0]

2

DIGITAL_IF_N

180R

R1977

VCC_PCMCIA

DIGITAL_IF_P

12V_VCC

33R

R1395

1

2

3456
7
8

R1

R2

R3

R4

VCC_PCMCIA

R1177

4k7

R1951

4k7

CN141

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

BC848B

Q208

1

2

3

VCC_PCMCIA

C966

50V

12p

33R

R1398

1

2

3456

7

8

R4

R1

R3

R2

R1642

10k

3V3_VCC

3V3_VCC

10k

R1632

PCM_CD1_N

C968
12p
50V

33R

R1394

1

2

3456
7
8

R1

R2

R3

R4

33R

R1399

1

2

3456
7
8

R1

R2

R3

R4

R1396

33R

1

2

3456
7
8

R1

R2

R3

R4

R1397

33R

1

2

3456
7
8

R1

R2

R3

R4

33R

R1392

1

2

3456

7
8

R1

R2

R3

R4

R1401

33R

5V_VCC

33R

R1424

R1393

33R

1

2

3456
7
8

R1

R2

R3

R4

33R

R1384

1

2

3

4 5

6
7
8

R1

R2

R3

R4

R1390

33R

1

2

3456
7
8

R1

R2

R3

R4

R1512

33R

10V

C653
100n

1

2

10V

C654
100n

1

2

R1953

4k7

3V3_VCC

CI_POWER_CTRL

50V

C969
12p

C687

10V

220n

R1496

4k7

3V3_VCC

R1660

4k7

1

2

33R

R1942

6V3

22u

C970

BACKLIGHT_ON/OFF

R344
1k2

33k

R1605

R1604

33k

R160718k

18k

R1606

HDMI1_5V

HDMI0_5V

BC848B

Q181

1

2

3

R1661

4k7

1 2

R1662

1k2

3V3_VCC

S81

U162

NAND512-A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

NC29

NC28

NC27

NC26

I/O7

I/O6

I/O5

I/O4

NC25

NC24

NC23

VDD2

VSS2

NC22

NC21

NC20

I/O3

I/O2

I/O1

I/O0

NC19

NC18

NC17

NC16NC15

NC14

NC13

NC12

NC11

WP

W

AL

CL

NC10

NC9

VSS1

VDD1

NC8

NC7

E

R

RB

NC6

NC5

NC4

NC3

NC2

NC1

PANEL_VCC_ON/OFF

100n

C1220

10V

1

2

FLH_3.3V

F_RBZ

FLH_3.3V

R1495

3k9

3V3_VCC

60R

F187

100n
10V

C656

1

2

100n
10V

C657

1

2

6V3

C868
22u

FLH_3.3V

FLH_3.3V

FLH_3.3V

R1388

33R

1
2
3456

7

8

R1
R2
R3
R4

R1382

33R

1

2

3456
7
8

R1

R2

R3

R4

33R

R1383

1

2

3456
7
8

R1

R2

R3

R4

R1389

33R

1

2

3456

7

8

R4

R1

R3

R2

R34
33R

4k7

R47

4k7

R48

R49

4k7

22u

C782

6V3

22R

R1332

220n

C718

10V

R1368

22R

1
2
3
4 5

6

7

8

R1
R2
R3
R4

R50

4k7

FLH_3.3V

AA_DDR2_DQSB0

AA_DDR2_DQSB0

AA_BADR_BA2

AA_BADR_BA2

AA_MCLK

AA_MCLK

AA_MCLKZ

AA_MCLKZ

AA_DDR2_DQSB1

AA_DDR2_DQSB1

AA_DDR2_DQS1

AA_DDR2_DQS1

AA_DDR2_DQS0

AA_DDR2_DQS0

AA_DDR2_DQM0

AA_DDR2_DQM0

AA_DDR2_DQM1

AA_DDR2_DQM1

AA_BADR_BA0

AA_BADR_BA0

AA_BADR_BA1

AA_BADR_BA1

AA_ODT

AA_ODT

AA_WEZ

AA_WEZ

AA_RASZ

AA_RASZ

AA_CASZ

AA_CASZ

AA_MDATA15

AA_MDATA15

AA_MDATA14

AA_MDATA14

AA_MDATA13

AA_MDATA13

AA_MDATA12

AA_MDATA12

AA_MDATA11

AA_MDATA11

AA_MDATA10

AA_MDATA10

AA_MDATA9

AA_MDATA9

AA_MDATA8

AA_MDATA8

AA_MDATA5

AA_MDATA5

AA_MDATA2

AA_MDATA2

AA_MDATA0

AA_MDATA0

AA_MADR12

AA_MADR12

AA_MADR11

AA_MADR11

AA_MADR10

AA_MADR10

AA_MADR9

AA_MADR9

AA_MADR8

AA_MADR8

AA_MADR7

AA_MADR7

AA_MADR6

AA_MADR6

AA_MADR5

AA_MADR5

AA_MADR4

AA_MADR4

AA_MADR3

AA_MADR3

AA_MADR2

AA_MADR2

AA_MADR1

AA_MADR1

AA_MADR0

AA_MADR0

A_MADR12

A_MADR12

A_MADR11

A_MADR11

A_MADR10

A_MADR10

A_MADR9

A_MADR9

A_MADR8

A_MADR8

A_MADR7

A_MADR7

A_MADR6

A_MADR6

A_MADR5

A_MADR5

A_MADR4

A_MADR4

A_MADR3

A_MADR3

A_MADR2

A_MADR2

A_MADR1

A_MADR1

A_MADR0

A_MADR0

A_MDATA0

A_MDATA0

MVREF

MVREF

A_BADR_BA2

A_BADR_BA2

A_DDR2_DQSB1

A_DDR2_DQSB1

A_DDR2_DQS1

A_DDR2_DQS1

A_DDR2_DQSB0

A_DDR2_DQSB0

A_DDR2_DQS0

A_DDR2_DQS0

A_DDR2_DQM0

A_DDR2_DQM0

A_DDR2_DQM1

A_DDR2_DQM1

A_BADR_BA0

A_BADR_BA0

A_BADR_BA1

A_BADR_BA1

A_ODT

A_ODT

A_MCLKE

A_MCLKE

A_WEZ

A_WEZ

A_RASZ

A_RASZ

A_CASZ

A_CASZ

TS_MDI1

TS_MDI1

TS_MDI2

TS_MDI2

TS_MDI3

TS_MDI3

TS_MDI4

TS_MDI4

TS_MDI5

TS_MDI5

TSMICLK

TSMICLK

TSMIVALID

TSMIVALID

TS_MDI0

TS_MDI0

A_MDATA9

A_MDATA9

A_MDATA2

A_MDATA2

A_MDATA5

A_MDATA5

A_MDATA7

A_MDATA7

A_MDATA8

A_MDATA8

A_MDATA10

A_MDATA10

A_MDATA11

A_MDATA11

A_MDATA12

A_MDATA12

A_MDATA13

A_MDATA13

A_MDATA14

A_MDATA14

A_MDATA15

A_MDATA15

A_MCLKZ

A_MCLKZ

A_MCLK

A_MCLK

PCM_CD2_N

PCM_CD2_N

TSMOSTART

TSMOSTART

TSMOCLK

TSMOCLK

TSMOVALID

TSMOVALID

TS_MDO7

TS_MDO7

TS_MDO6

TS_MDO6

TS_MDO5

TS_MDO5

TS_MDO4

TS_MDO4

TS_MDO3

TS_MDO3

TS_MDO0

TS_MDO0

PCM_WE_N

PCM_WE_N

PCM_IORD_N

PCM_IORD_N

PCM_IOWR_N

PCM_IOWR_N

PCM_IRQA_N

PCM_IRQA_N

PCM_OE_N

PCM_OE_N

PCM_CE_N

PCM_CE_N

PCM_WAIT_N

PCM_WAIT_N

PCM_RST

PCM_RST

PCM_D0

PCM_D0

PCM_D1

PCM_D1

PCM_D2

PCM_D2

PCM_D3

PCM_D3

PCM_D6

PCM_D6

PCM_D7

PCM_D7

PCM_D5

PCM_D5

PCM_A8

PCM_A8

PCM_A9

PCM_A9

PCM_A11

PCM_A11

PCM_A12

PCM_A12

PCM_A10

PCM_A10

PCM_A14

PCM_A14

PCM_A13

PCM_A13

PCM_A7

PCM_A7

PCM_A7

PCM_A6

PCM_A6

PCM_A6

PCM_A5

PCM_A5

PCM_A5

PCM_A4

PCM_A4

PCM_A4

PCM_A3

PCM_A3

PCM_A3

PCM_A2

PCM_A2

PCM_A2

PCM_A1

PCM_A1

PCM_A1

PCM_A0

PCM_A0

PCM_A0

TS0_CLK

TS0_CLK

TS0_SYNC

TS0_SYNC

TS0_VALID

TS0_VALID

TS0_D7

TS0_D7

TS0_D6

TS0_D6

TS0_D5

TS0_D5

TS0_D4

TS0_D4

TS0_D3

TS0_D3

TS0_D2

TS0_D2

P_D0

P_D0

P_D1

P_D1

P_D2

P_D2

P_D3

P_D3

P_D5

P_D5

P_D6

P_D6

P_D7

P_D7

P_A0

P_A0

P_A3

P_A3

P_A4

P_A4

P_A5

P_A5

P_A6

P_A6

P_A7

P_A7

P_A8

P_A8

P_A9

P_A9

P_A10

P_A10

P_A11

P_A11

P_A12

P_A12

P_A13

P_A13

P_A14

P_A14

P_WAIT_N

P_WAIT_N

P_IOWR_N

P_IOWR_N

P_RESET

P_RESET

P_IRQA_N

P_IRQA_N

P_OE_N

P_OE_N

P_IORD_N

P_IORD_N

P_CE_N

P_CE_N

P_WE_N

P_WE_N

F_RBZ

PF_AD15

PF_AD15

PF_CE1Z

PF_CE1Z

PF_CE0Z

PF_CE0Z

PF_ALE

PF_ALE

PF_OEZ

PF_OEZ

PF_WEZ

PF_WEZ

TS1_D0

TS1_D0

TS1_D1

TS1_D1

TS1_D2

TS1_D2

TS1_D3

TS1_D3

TS1_D4

TS1_D4

TS1_D5

TS1_D5

TS1_D6

TS1_D6

TS1_D7

TS1_D7

TS1_CLK

TS1_CLK

TS1_VALID

TS1_VALID

TS1_SYNC

TS1_SYNC

TSMISYNC

TSMISYNC

TS_MDI6

TS_MDI6

TS_MDI7

TS_MDI7

AA_MCLKE

AA_MCLKE

A_MDATA6

A_MDATA6

AA_MDATA6

AA_MDATA6

A_MDATA1

A_MDATA1

AA_MDATA1

AA_MDATA1

A_MDATA3

A_MDATA3

AA_MDATA3

AA_MDATA3

A_MDATA4

A_MDATA4

AA_MDATA4

AA_MDATA4

AA_MDATA7

AA_MDATA7

P_REG_N

P_REG_N

PCM_REG_N

PCM_REG_N

P_A1

P_A1

P_A2

P_A2

TS_MDO2

TS_MDO2

TS0_D0

TS0_D0

TS_MDO1

TS_MDO1

TS0_D1

TS0_D1

PCM_D4

PCM_D4

P_D4

P_D4

NAND_ALE

NAND_ALE

NAND_CEz

NAND_CEz

NAND_CLE

NAND_CLE

NAND_WPz

NAND_WPz

NAND_WPz

9k1

NC

NC

30022165 KULLANILDI

CI INTERFACE

NC

1k

0R

NAND FLASH

128 MEGABYTE

TS IN& OUT

1 2 3 4 5 6 7 8

AUDIO OUTPUTs

A

B

SC_L_OUT

C

SC_R_OUT

D

SC_AUD_R_IN

SC_AUD_L_IN

E

SAV_R_IN

SAV_L_IN

F

220k

R1899

MAIN_R

220k

R1898

C1168

12

HP_L DSP_HP_L

100u

16V

C1169

12

HP_R

100u

16V

22k

R1924

1 2

22k

R1925

1 2

AUDIO INPUTs

R1902

10k

12k

R1921

R1901

10k

12k

R1920

R1903

10k

12k

R1918

R1904

10k

12k

R1919

R1858

R1859

R1900

100R

DSP_MAIN_LMAIN_L

50V

4n7

C1183

R1897

100R

DSP_MAIN_R

50V

4n7

C1184

L119

4u7

220R

C1170
10u
10V

L120

DSP_HP_R

4u7

220R

C1171
10u
10V

R223

12

DSP_SCART_L

100R

50V

C1185

100p

R222

12

DSP_SCART_R

100R

50V

100p

C1186

AMP_MUTE

PROTECT

RESET_TUNER

DVD_IR_ON/OFF

ANT_CTRL

4k7

R1601

1 2

3V3_STBY

SCART_AUDIO_IN_L
SCART_AUDIO_IN_R

SAV_AUDIO_IN_L
SAV_AUDIO_IN_R

16V

100n

NC

10k

10k

R1839

R1838

3V3_STBY

C1174

10V

C119910u

10k

4k7

4k7

R17

R1840

1 2

1 2

3V3_VCC

3V3_VCC

SC_AUD_R_OUT

SCART_AUDIO_IN_R

50V

470p

C1187

SC_R_OUT

SCART_AUDIO_IN_L

50V

470p

C1188

C1198

10u

C1195

DSP_MAIN_L

DSP_MAIN_R
DSP_SCART_L
DSP_SCART_R

DSP_HP_L
DSP_HP_R

1u

C1201

6V3

MODE SELECTION
MODE SELECTION

MODE SELECTION

RESET_S2

4k7

10k

R1892

R1656

R1836

1 2

3V3_STBY

C1203

1u
6V3

C1197

10V10u

10u 10V

10V

C1200

4u7

10V

12

4k7

R1614

SPDIF_OUT

C1196

10V10u

N5

AUL0

L4

AUR0

R5

AUL1

T6

AUR1

P6

AUL2

P5

AUR2

T4

AUL3

T5

AUR3

N6

AUOUTL0

R6

AUOUTR0

W9

AUOUTL1

AA9

AUOUTR1

Y7

EAR_OUTL

AA7

EAR_OUTR

MSD9WB9PT-2

U5

AUVRP

U6

AUVAG

U4

AUVRM

D4

I2S_OUT_MCK

D6

I2S_OUT_SD

F4

I2S_OUT_WS

F5

I2S_OUT_BCK

E4

I2S_IN_BCK

C4

I2S_IN_SD

D3

I2S_IN_WS

P4

SPDIFO

U5

3

RXA0N
RXA0P
RXA1N
RXA1P
RXA2N

RXA2P
RXACKN
RXACKP

DDCDA_CK
DDCDA_DA
HOTPLUGA

RXB0N

RXB0P

RXB1N

RXB1P

RXB2N

RXB2P
RXBCKN
RXBCKP

DDCDB_CK
DDCDB_DA
HOTPLUGB

E2

HDMI_1_RX0N

F3

HDMI_1_RX0P

F2

HDMI_1_RX1N

G3

HDMI_1_RX1P

G2

HDMI_1_RX2N

G1

HDMI_1_RX2P

E3

HDMI_1_CLKN

E1

HDMI_1_CLKP

H5

HDMI_1_SCL

H6

HDMI_1_SDA

J6

B2

HDMI_0_RX0N

B1

HDMI_0_RX0P

C2

HDMI_0_RX1N

C1

HDMI_0_RX1P

D2

HDMI_0_RX2N

D1

HDMI_0_RX2P

A2

HDMI_0_CLKN

C3

HDMI_0_CLKP

J5

HDMI_0_SCL

K4

HDMI_0_SDA

K5

R1917

H4

CEC

12

10R

HDMI1_5V

4k7

R1896

1 2

R1912

4k7

1 2

U9

LM809

12

10R

R74

3V3_STBY

3V3_STBY

PRE-AMP for SCART AUDIO

R1916

C1182
10u

220k

10V

R1914

12

33k

1

OUT1

U178

2

OUT2

IN1-

TL062

3

IN2-

IN1+

4 5

IN2+VSS

C1177

100n

VDD

R1915

16V

220k

12V_VCC

F301

12

12V_VCC

600R

R1913

1 2

C1180

33k

C1205

10u

10V

47p

8

50V

R1926

1 2

7

82k

R1928

6

1 2

V+

C1181

R1929

1 2

20k

V+

C1206

10u

10V

47p

50V

R1927

1 2

82k

V+

1k

HDMI0_5VR1895

R1911

RST

R1909

1k

12

R1910

1k

VCC

GND

C1202

1u
6V3

12

3

2

1

12

1k

2

12

132

SC_AUD_L_OUT

SC_L_OUT20k

Q204
BC848B

3

1

HDMI1_HPD

HDMI0_HPD

Q203
BC848B

6V3C11u

R76

12

12V_VCCSTBY_INFO

1k

12

10R

R75

COAX SPDIF OUT

F5

12

5V_VCC

600R

C15

16V

100n

4k7

1 2

C1175

1 2

100n

4k7

1 2

R1907

1 2

SPDIF_OUT

100R

12

10V

50V

220p

C1178

NC

C1189

C1190

50V

470p

50V

470p

SAV_AUDIO_IN_R

SAV_AUDIO_IN_L

50V

220p

NC

1 2

C1179

TP251

1

C1176
2
3

JK10

1

C5V6

1 2

1 2

100n

10V

1k

D199

R1908

1 2

1 2

NC

Q202

BC848B

S92

R1889

3

2

1

R1890

HDMI_0_RX2P

HDMI_0_RX2N
HDMI_0_RX1P

HDMI_0_RX1N
HDMI_0_RX0P

HDMI_0_RX0N
HDMI_0_CLKP

HDMI_0_CLKN

HDMI_0_SCL
HDMI_0_SDA

HDMI0_5V

HDMI0_HPD

HDMI_1_RX2P

HDMI_1_RX2N
HDMI_1_RX1P

HDMI_1_RX1N

HDMI_1_RX0P

HDMI_1_RX0N
HDMI_1_CLKP

HDMI_1_CLKN

HDMI_1_SCL
HDMI_1_SDA

HDMI1_5V

HDMI1_HPD

HDMI2

2

2

1

2

CEC

HDMI1

CEC

R1877

1

10R

R1869

12

10R

10R

1

R1868

R1887

12

10R

10R

2

R1867

R1886

12

10R

10R

1

R1879

R1880

12

10R

R1888

12

10R

2

10R

1

R1885

10R

12

R1878

47k

1 2

R1874

1

10R

R1870

12

10R

10R

1

R1884

R1871

12

10R

10R

2

R1872

R1882

12

10R

10R

1

R1876

R1883

12

10R

R1873

12

10R

2

10R

1

R1875

10R

12

R1881

47k

1 2

PL1

PL2

PL3

PL4

PROJECT NAME :

SCH NAME :

AUDIO_IO&HDMI_INPUTs

DRAWN BY :

Ulas Dereli

R1864

R1863

47k

1 2

47k

1 2

R1865

R1862

17mb62S

CN708

21
20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

CN707

21
20

1

2

3

4

5

6

7

8

9
10
11
12
13
14
15
16
17
18
19

26-10-2011_15:43

87654321

A

B

COMMON OPTIONAL

C

D

E

F

A3

T. SHT:

8

AX M

1 2 3 4 5 6 7 8

AUDIO AMP for 16" to 24"

A

MAIN_L

VDD_AUDIO

Q160
BC848B

R817

100R

L_AUDIO_N_OUT

R623

C612

220n

10V

B

VDD_AUDIO

3

BC848B

2

MAIN_R

C

R_AUDIO_P

R_AUDIO_N

L_AUDIO_P

L_AUDIO_N

1

100R

R818

Q133

C602

220n

10V

R_AUDIO_N_OUT

R613

CN710

D

4k7

4k7

1

2

3

4

5

6

INP

GNDA

VDD_AUDIO

INP

GNDA

VDD_AUDIO

VDD_AUDIO_PWR

U163 PT2333

OUTN

VDDA

VDD1

C665

2

100n

1

10V

PT2333U164

OUTN

VDDA

VDD1

C666

2

10V

1

100n

12V_VCC

5V_VCC

GNDB

INN

SDB

OUTP

C3C2C1B3B2B1A3A2A1

L_AUDIO_P_OUT

AMP_EN

4k7

R624

10V

C617

220n

GNDB

INN

SDB

OUTP

C3C2C1B3B2B1A3A2A1

R_AUDIO_P_OUT

AMP_EN

4k7

R614

10V

C608

220n

30001734 KULLANILDI

F283

60R

NC 30049510 KULLANILDI

F285

D192

60R

SK24

F294

60R

220u

10V

10V

220u

C870

C615

VDD_AUDIO

AMP_MUTE

AMP_EN

R1684

1 2

10k

POP NOISE CIRCUIT

S87

1 2

BC848B

3

1

NC

S86

1 2

16V

10u

C1032

BC858B

Q186

R1702

2

12

10k

2

NC

R1712

VDD_AUDIO

15k

R616

1 2

NC

3

BC848B
Q185

1

3V3_STBY

NC

10k

3k9

R1711

1 2

R1309

3V3_VCC10k

C1058
100n
16V

12V_VCC

5V_VCC

R1941

R1701

A

1k

100k

B

12

D191

1N4148

47k

R1699

1

Q195

2

3

100k

R1718

1 2

C

D

Ü.A. DEGISTIRILECEK

AUDIO AMP for 26" to 32"

F282

C1121

220n
25V

25V

220n

25V

220n

F281

60R

VDD_AUDIO

60R

L_AUDIO_P_OUT

16V

10u

L_AUDIO_N_OUT

R_AUDIO_N_OUT

R_AUDIO_P_OUT

25V

VDD_AUDIO

16V

10u

AMP_EN

1

SD

S85

30022132 KULLANILDI

30050557 KULLANILDI

100k

R1715

NC

10k

100k

R1717

1

2

3

4 5

R1741

100k

R1714

NC

100R

8

R1

7

R2

6

R3

R4

CONNECT TO DSP_M_R GND

MAIN_L

30050557 KULLANILDI

CONNECT TO DSP_M_L GND

C1123

1u
50V

C1074

1u
25V

R1687

10k

C1073

1u
25V

MAIN_R

E

VDD_AUDIO

VDD_AUDIO

R1716

VDD_AUDIO

F

C1077

1u
6V3

1uC1075
6V3

ANALOG VCC

R1696

10k

30050557 KULLANILDI

C1076

6V3

30050557 KULLANILDI

6V3
1u

C1078

2

FAULT

3

LINP

4

LINN

5

GAIN0

6

GAIN1

7

AVCC

TPA3110D2

8

AGND

9

GVDD

10

PLIMIT

1u

11

RINN

12

RINP

13

NC

14

PBTL

U168

PVCCL2

PVCCL1

OUTPL

PGND1

OUTNL

OUTNR

PGND2

OUTPR

PVCCR1

PVCCR2

28

27

C1045

26

BSPL

25

24

23

C1046

22

BSNL

C1044

21

BSNR

20

19

18

C1043220n

17

BSPR

16

15

C1122

L124

10u

F296

60R

C1226

25V

C1227

C1228

1u

1u

C1229

1u

25V

25V

25V

1u

L125

10u

F299

60R

F298

60R
L126

10u

L127

10u

F297

60R

L_AUDIO_P

50V

1n

C942

L_AUDIO_N

1n

50V

C943

R_AUDIO_N

1n

50V

C944

R_AUDIO_P

50V

1n

C945

HP_L

HP_R

2N7002

Q192

2N7002

Q210

SLIM HEADPHONE OUTPUT

1

1

TP51

2

6

3

4

5

7

1

TP52

4k7

1

R1149

3V6 lik zener kullanilmali

D203

C5V6

17mb62S

87654321

R1704

R1960

1

TP230

1

TP229

R1854

680R

680R

10k

1 2

HP_MUTE

R1855

C1172

C729
10n

10n

16V

16V

10k

1 2

HP_DETECT

PROJECT NAME :

SCH NAME :

AUDIO_AMP&HP_AMP

DRAWN BY :

Ulas Dereli

JK6

3V3_VCC

A3

T. SHT:

8

26-10-2011_15:43

E

F

AX M

A

B

C

D

E

F

3V3_VCC

SCL_SYS
SDA_SYS

PCM_CD1_N

3V3_VCC

BACKLIGHT_DIM

3V3_STBY

KEYBOARD

DVD_SENSE

SC_PIN8

3V3_STBY

DVD_WAKEUP

R1524

50V

33p

C952

1M

R1533

RESET

50V

C951

33p

10k

R1567

LED2

3V3_STBY

1 2 3 4 5 6 7 8

10k

R1835

10k

R1615

NC

12

12

4k7

4k7

R1527

IR_IN

24MHz

USB_DP
USB_DM

TP54
TP53

TP55

Q170
BC848B

3

2

1

RESET

R1668

1k

C1016

D189

1N4148

12

4k7

4k7

R1528

1 2

R1

4k7

12

SPI_CSN_1

SPI_SCK

SPI_SDI_1

SPI_SDO

FLASH_WPN

RX/SCL_SC
TX/SDA_SC

R1543

1 2

100R

X2

S38

100R

12

R1666

10n

C1215

LED SOCKET

12345

CN703

1

1

150R

R1940

1

10k

220R

R1571

R1563

1 2

3

Q174

2

1

BC858B

220R

R1569

1 2

PANEL VCC = 5V/12V

16V

100n

6V3

22u

C1031

C1015

2

100n

1

10k

10V

R1667

16V

R1833

J21
J20
J19

B4
C5
V3

B6
C7
B5
C6
A6
A7

K6
M6

H19
H20

A4

Y6

AA6

E5

B3
A3
W8
Y8
J9
H9

Q173

TP57

1

C949

1 2

27p

50V

220R

1 2

3

1

220R

1 2

TP61

1

PWM0
PWM1
PWM2

SAR0
SAR1
SAR2

GPIO12
SCZ
SCK
SDI
SDO
GPIO14

DDCA_CK/UART0_RX
DDCA_DA/UART0_TX

U5

MSD9WB9PT-2

4

DDCR_CK
DDCR_DA

SPDIFI/GPIO139

IRIN

XIN
XOUT

HWRESET

USB0_DP
USB0_DM
USB1_DP
USB1_DM
GND0
GND1

1

TP56

5V_STBY

F259

1 2

600R

10k

Q171

R1562

BC848B

R1572

2

BC858B

R1570

5V_STBY

RESET

3V3_VCC

3

1

IR_IN

LVB0P
LVB0M
LVB1P
LVB1M
LVB2P

LVB2M
LVBCKP
LVBCKM

LVB3P

LVB3M

LVB4P

LVB4M

LVA0P

LVA0M

LVA1P

LVA1M

LVA2P

LVA2M
LVACKP
LVACKM

LVA3P

LVA3M

LVA4P

LVA4M

GPIO137

GPIO141
GPIO143

GPIO10
GPIO11

GPIO7

2

5V_VCC

AA19

TX_B_0_P

AA20

TX_B_0_N

AA18

TX_B_1_P

W18

TX_B_1_N

W17

TX_B_2_P

Y18

TX_B_2_N

W16

TX_B_CLK_P

Y17

TX_B_CLK_N

AA16

TX_B_3_P

Y16

TX_B_3_N

AA15

TX_B_4_P

W15

TX_B_4_N

W14

TX_A_0_P

Y15

TX_A_0_N

W13

TX_A_1_P

Y14

TX_A_1_N

AA13

TX_A_2_P

Y13

TX_A_2_N

AA12

TX_A_CLK_P

W12

TX_A_CLK_N

W11

TX_A_3_P

Y12

TX_A_3_N

W10

TX_A_4_P

Y11

TX_A_4_N

R1959

1 2

Y9
W7

AA10

100R

Y10

R1954
R1952

1 2

4k7

B7
E6
F6

12

4k7

R1672

R1617

3V3_STBY

10k

R1568

LED1

USB INTERFACE

4

3

2

1

CN1

4k7

R1198

1

IN

2

GND

3

EN

C610
10u

U8

TPS2553-1

FAULT

10V

ILIM

3V3_STBY

4k7

HP_MUTE
DVD_SPDIF
HP_DETECT

CI_POWER_CTRL

3V3_VCC

STBY_ON/OFF_NOT
LED1
LED2

12

12

4k7

4k7

R1671

3V3_STBY

3V3_STBY

ONBOARD KEYBOARD

TP10

1

2k

R7

R45

R23

10k

+ -

470R

4

SW5

E2

G1G2G3

G4

3 BUTTONS KEYBOARD OPTION

TP6

1

6

IO4

IO1

U145

5

VDD

GND

AZ099-04S

4

IO3 IO2

1

TP7

6

OUT

R77

5

560R

R46

4

560R

3V3_STBY

SPI_CSN_1

SPI_SDO

FLASH_WPN

TOUCH_PAD_OPTION

MECH_SWITCH

D204

B5V1

12TC3

KEYBOARD_ONBOARD

E1

R844

1 2

1

10R

2

R845

1 2

3

10R

SERIAL FLASH

4k7

4k7

R1357

R1358

R1967

1 2

100R

1 2

100R

1 2

100R

R1969

S76

1

R1968

KEYBOARD_ONBOARD

R793

1 2

47R

12345

CN709

EXT KEYPAD

123456789

CN138

USB_DP

USB

USB_DM

TP14

D165

TP111TP151TP40

U158

MX25L512

1

CS#

2

SO

3

WP#

4 5

HOLD#

1

C658

2

100n

1

10V

4k7

R1183

8

VCC

TP12

7

R1248

1 2

6

1

SCLK

R1970

100R

1 2

1

SIGND

100R

1N5819

SPI_SCK

SPI_SDI_1

3V3_STBY

TP41

C630

2

100n

1

10V

F248

1 2

KEYBOARD

600R

F249

1 2

3V3_STBY

600R

R1937

1 2

SCL_SYS

47R

R1936

1 2

SDA_SYS47R

6

SINGLE LVDS FFC OPTIONS

PANEL_VCC

OP_PIN11

1 2

PANEL_VCC

5150494847464544434241403938373635343332313029282726252423222120191817161514131211

OP_PIN45

5150494847464544434241403938373635343332313029282726252423222120191817161514131211

OP_PIN9

OP_PIN8

S3

S13

S14

1 2

1 2

TX_A_3_P

TX_A_3_N

TX_A_CLK_P

TX_A_CLK_N

101112131415161718192021222324252627282930

123456789

CN137

OP_PIN42

OP_PIN43

TX_B_CLK_P

TX_B_CLK_N

TX_B_2_P

TX_B_4_N

TX_B_4_P

TX_B_3_N

TX_B_3_P

1

TP60

1

OP_PIN42

OP_PIN43

TP59

101112131415161718192021222324252627282930

OP_PIN27

TX_B_2_N

TX_B_1_N

TX_B_1_P

TX_B_0_P

TX_B_0_N

TX_A_4_N

TX_A_4_P

1

TP35

1

TP58

15.6" LVDS OPTION

TX_A_0_N

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_N

TX_A_2_P

TX_A_CLK_N

TX_A_CLK_P

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_P

TX_A_2_N

OP_PIN10

OP_PIN11

OP_PIN9

TX_A_0_N

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_N

TX_A_2_P

TX_A_CLK_N

TX_A_CLK_P

TX_A_3_N

TX_A_3_P

987654321

10

LG BASED 30070519

987654321

10

SAM BASED 30070519

TX_A_0_N

OP_PIN6

OP_PIN8

OP_PIN7

11 12

13 14

15 16

17 18

19 20

OP_PIN27

OP_PIN5

PANEL_VCC

CN3

1 2

3 4

5 6

7 8

9 10

OP_PIN42

CN4

OP_PIN43

MEGA_DCR_IN

CN2

MEGA_DCR_OUT

PANEL_VCC

DIMMING

PANEL_VCC

PANEL_VCC

SCH NAME :

DRAWN BY :

R73
33k

R2

33k

12V_VCC

R71
33k
R60

1 2

10k

R70
33k
R59

1 2

10k

R69
33k
R58

1 2

10k

S4

R67
33k
R56

1 2

10k

S2

R72
33k
R61

1 2

10k

GPIOs&USB&LVDS_OUT

Ulas Dereli

PANEL_VCC

BACKLIGHT_ON/OFF

PANEL_VCC

PANEL_VCC = 5V/12V

OP_PIN5PANEL_VCC

OP_PIN6PANEL_VCC

OP_PIN7PANEL_VCC

OP_PIN8

OP_PIN9

PROJECT NAME :

PANEL_VCC

TX_B_0_N

TX_B_0_P

TX_B_1_N

TX_B_1_P

TX_B_2_N

TX_B_2_P

TX_B_CLK_N

TX_B_CLK_P

TX_B_3_N

TX_B_3_P

TX_A_0_N

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_N

TX_A_2_P

TX_A_CLK_N

TX_A_CLK_P

TX_A_3_N

TX_A_3_P

OP_PIN9

PANEL_VCC

PANEL_VCC

PANEL_VCC

1

TP34

1

TP33

1

TP32

1

TP31

1

TP30

1

TP29

1

TP28

1

TP27

1

TP26

1

TP25

1

TP24

1

TP23

1

TP22

1

TP21

1

TP20

1

TP19

1

TP18

1

TP17

1

TP16

1

TP9

S15

12

1

TP8

1 2

1 2

1 2

1 2

1 2

1 2

17mb62S

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

CN139

9

8

7

6

5

4

3

2

1

A

B

C

19" TO 22" DOUBLE LVDS FFC OPTIONS

D

R68

OP_PIN10PANEL_VCC

33k
R57
10k

R66

OP_PIN11PANEL_VCC

33k
R55
10k

R65
33k
R54
10k

R62
33k
R51
10k

R63
33k
R52
10k

R64
33k
R53
10k

OP_PIN27

OP_PIN42

OP_PIN43

OP_PIN45PANEL_VCC

E

F

A3

T. SHT:

8

16-11-2011_10:11

87654321

AX M

1V2_VCC

ADAPTOR OVER VOLTAGE PROTECTION

3V3_STBY

A

1V8_VCC

B

C

D

E

F

3V3_VCC

3V3_VCC

12V_VCC/STBY

5V_VCC

12V_VCC/STBY

16V

3V3_STBY

12V_VCC/STBY

12V_VCC/STBY

1 2 3 4 5 6 7 8

F277

60R

C1081

C997

10u

100n

6V3

16V

F271

60R

C1024

C1025

C1030

100n

100n

10u

16V

16V

6V3

F272

60R

C990

100n

100n

22u

16V

16V

6V3

C1004

C1001

F270

60R

C1029
10u
6V3

C1014
100n
16V

VDD_3V3

C1005
100n
16V

AVDD_DDR

C1022
100n
16V

C1070
100n
16V

AVDD_3V3

VDDC_1V2

2V5_VCC

POWER SOCKET

C7

22u

CN706

1920

1718

1516

1314

1112

910

78

56

34

12

S10

S19

S21

S22

3V3_VCC

VDD_AUDIO_PWR

12V_VCC/STBY

5V_STBY

DIMMING

BACKLIGHT_ON/OFF

STBY_ON/OFF

S7

S8

12V_VCC

12V_STBY

12V_VCC

12V_STBY

5V_VCC

C6

16V

22u

VDD_AUDIO_PWR

2V5_VCC

C1028
10u
6V3

F274

60R

C1007
100n
16V

1k

F295

60R 402 ferrite secilecek

F305

1k

C1009
100n
16V

F306

1k

C1008
100n
16V

F307

1k

C1221
100n
16V

F308

1k

C1222
100n
16V

BACKLIGHT_DIM

MEGA_DCR_IN

S18

NC

PANEL_VCC_ON/OFF

AVDD_2V5_PGA

AVSS_PGA

C1223
100n
16V

C1224
100n
16V

C1225
100n
16V

MEGA_DCR_OUT

3V3_VCC

5V_VCC

12V_VCC

AVDD2V5_ADC

AVDD2V5_REF

AVDD2V5_AUD

AVDD2V5_MOD

NC

S16

L9M9N9P9R9

D10

E10

F10

G10

H10

J10

K10

L10

M10

N10

P10

R10

D11

E11

F11

G11

H11

J11

K11

L11

M11

N11

P11

R11

D12

E12

F12

G12

H12

J12

K12

L12

M12

N12

P12

R12

D13

E13

F13

G13

H13

J13

K13

L13

M13

N13

P13

R13

D14

E14

L14

M14

N14

P14

R14

D15

K15

L15

M15

N15

P15

R15

D16

K16

L16

M16

D17

K17

L17

M17

K18

L18

M18

GND9

GND8

GND7

GND6

GND5

GND4

GND3

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND20

GND21

GND22

GND23

GND24

GND25

GND26

GND27

GND28

GND29

GND30

GND31

GND32

GND33

GND34

GND35

GND36

GND37

GND38

GND39

GND40

GND41

GND42

GND43

GND44

GND45

GND46

GND47

GND48

GND49

GND50

GND51

GND52

GND53

GND54

GND55

GND56

GND57

GND58

GND59

GND60

GND61

GND62

GND63

GND64

GND65

GND66

GND67

GND68

GND69

GND70

GND71

GND72

GND73

GND74

GND75

GND76

GND77

GND78

GND79

GND80

6

U5

AVDD_DDR_4

AVDD_DDR_3

AVDD_DDR_2

AVDD_DDR_1

VDDC0

H15

H16

H17

J14

J15

J16

J17

VDDC_1V2

PW04 LOW POWER Option

5V_STBY

DIMMING CIRCUIT

3V3_VCC

R1158

1 2

4k7

1k

R1221

1 2

C839

S17

R1165

2

1 2

4k7

C838

1 2

220p

50V

F302

1 2

60R

F289

1 2

60R

F288

1 2

60R

F290

1 2

60R

3V3_VCC

4k7

1 2

NC

S82

1 2

3

R1685

2

12

10k

1

1 2

220p

3

50V

Q189
BC848B

1

R1166

1 2

4k7

C840

1 2

220p

50V

PANEL SUPPLY SWITCH

33k

1u

25V

1 2

C1128

22k

R1749

R1678

3

R1693

2

12

C1042
100n

Q190
BC848B

2

1

1

10V

10k

Q194
BC848B

LM1117

IN

ADJ

1234

R1734

R1725

1 2

47R

H14

U1

OUT

VOUT

2

2

N7N8P7P8T8R7R8U8V8

K14

AVDD2V5_REF

AVDD2V5_ADC

AP211H

3V3_STBY

1

Q193
BC858B

R1761

3

100R

1

8

R1

2

7

R2

3456

R3

R4

3

Q188
BC848B

1

5

6

Q199

FDC642P

1

3 4

2

AVDD2V5_AUD

AVDD2V5_MOD

R1679
100R

C774
10u
10V

TP213

1

PANEL_VCC

STBY_ON/OFF_NOT

AVSS_PGA

AVDD_2V5_PGA

DIMMING

E8F8G8

R1748

1 2

4k7

MSD9WB9PT-2

G9E9F9J8H8

AVDD_3V3

3V3_STBY

4k7

R1676

R1677

1 2

1 2

4k7

3

2

Q191
BC848B

1

G16

G17

G15

SHORT CCT PROTECTION

PROTECT

TP202

1

3

C971

2

100n

1

10V

1

BC848B

L2

12V_VCC

220n

C13

25V

10u

SDA_SYS
SCL_SYS

12V_VCC

STBY_ON/OFF

VDD_3V3

Q178

2

R19

AVDD_LPLL

VDDP1

VDDP0

AVDD_EAR33

AVDD_AU33

AVDD_CVBS33_1

AVDD_CVBS33_0

AVDD_DMPLL

AVDD_ALIVE_2

AVDD_ALIVE_1

AVDD_ALIVE_0

PGA_VCOM

AVDD_PGA25

AVDD_MOD25_1

AVDD_MOD25_0

AVDD_AU25

AVDD_REF25_1

AVDD_REF25_0

AVDD_ADC25_1

AVDD_ADC25_0

AVDD_126

DVDD_DDR

VDDC6

VDDC5

VDDC4

VDDC3

VDDC2

VDDC1

AVDD_DDR_0

E15

E16

E17

F16

F17

AVDD_DDR

3

3V3_STBY

R1635

12

3

10k

1

R1636

Q180

1 2

3

2

10k

BC858B

3

R1638

1 2

10k

10k

R1639

1 2

LNB CIRCUIT

10V

220u

C65

27

V_UP

4

LX

19

VCC

18

VCC_L

6

SDA

9

SCL

14

TTX

29

RSV_1

30

RSV_2

3V3_VCC

220n

POWER_1&LNBP

Ulas Dereli

C69
1u
50V

LNBH23L

ADDR

101528520

C14

25V

PROJECT NAME :

C70
470n
25V

D8

SK24

10k

R18

10k

3V3_VCC

SCH NAME :

DRAWN BY :

1 2

1 2

1 2

3

1

BC848B

U6

BYP

Q211

I_SEL

15k

K9

R1649

33k

10k

1 2

R1631

D185

BAW56

R1727

33k

R1750

22k

3V3_VCC

D186

BAW56

5V_VCC

3V3_TUNER

D184

BAW56

R20

1 2

10k

2

R1973

100R

1N4001

D7

VO_TX

EXTM

VO_RX

PDC

DSQIN

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13

P_GND

A_GND

R43

W2W3V4V5V6

BYPASS

1u
6V3

C974

12

12

3V3_STBY

LM809

22
13
21
11
12

1
2
3
7

8
16
17
23
24
25
26
31
32

17mb62S

GND84

GND83

GND82

GND81

VDD_AUDIO_PWR

12V_VCC

U7

VCC

RST

4k7

2k2

R42

DISEQC_OUT

D9

D18

GND86

GND85

GND87

R40
20k
R21
10k

GND

132

C68

R41

15n

C12

220n

25V

26-10-2011_15:44

87654321

50V

D6

12V_STBY

LNB_OUT

1N5819

T. SHT:

A

B

C

D

E

F

A3

8

AX M

ADAPTER SOCKET

W_ADAPTER

5

4

3

JK9

A

2

1

1

TP36

CCFL INVERTER SOCKET

CN705

B

12V_INV

1

1

TP37

2

3

1

TP39

4

S1

5

S6

6

1

1

TP45

TP46

C

1 2 3 4 5 6 7 8

D

MOSFET_CONTROL

FS3

1 2

12V_STBY

7A/32VDC

NC

FS2

1 2

7A/32VDC

!

12V_INV

TP239

1

5

6

Q1

FDC604P

1

3 4

2

5

6

Q2

FDC642P

1

3 4

2

INVERTER SOCKET W/ADAPTER

DIMMING

BACKLIGHT_ON/OFF

SW1

12V_STBY

R1692

12

25V

33k

1 2

220n

C1049

R1732

12

33k

R1733

3

2

12

10k

1

R1724

1 2

47R

Q182
BC848B

5

6

FDC642P

1

3 4

2

POWER BLOCK DIAGRAM

SW1

12V_STBY 12V_VCC

DC-DC1

DC

5V_STBY

DC

DC-DC2

DC

3V3_STBY

DC

12V_VCC

12V_STBY

DC/DC1

F9

1 2

60R

0R

F287

1 2

60R

C1091

22u

16V

C1092
22u
16V

C1112

10n

W/ADAPTOR

TP243

C1038
100n

U174

2

MP1583

1

1

16V

BS

2

IN

3

SW

C1037

4

GND

100n
16V

L118

1 2

15u

D197

SS33

1 2

16V

8

SS

R1972

12

7

EN

6

COMP

5

FB

R1737

C1102

C1103
22u

22u

16V

16V

33k

10k

R1690

1 2

10k

F7

1 2

60R

F6

1 2

60R

12V_STBY

1 2

5n6

50V

C1130

R1709

1 2

3k9

5V_VCC

5V_STBY

MOSFET_CONTROL

5V_STBY

SW2

1 2

C1047

R1698

10k

12

25V

33k

R1729

220n

R1722

1 2

47R

1k

R1728

3

2

12

Q184
BC848B

1

1

6

1

Q198

FDC604P

5V_VCC

5

3 4

2

W/ADAPTOR & W/IPS16&17&60&PW25&PW06

FS5

1 2

12V_VCC

7A/32VDC

4A

Q200

12V_VCC

12V_STBY

F10

1 2

60R

F286

1 2

60R

C1089
22u
16V

TP238

1

C1114

10n

16V

DC/DC2

2

1

1

2

C1090

3

22u
16V

4 5

for 3v3 Panel Sup.

L123

1 2

15u
L16

10u

30068939

BS

U23

IN

MP1484

SW

NC

C1096

22u

6V3

10V

C1036

100n

1

2

8

SS

R1689

12

7

EN

6

COMP

FBGND

R1735

C1129

1 2

5n6

12V_STBY

10k

R1708

5k6

3N3

R3

6k8

50V

F12

22k

1 2

60R

F11

1 2

60R

3V3_VCC

3V3_STBY
C1097
22u
6V3

1

TP244

3V3_STBY

MOSFET_CONTROL

C1048

R1697

SW3

R1723

1 2

Q183
BC848B

5

3 4

2

47R

12

25V

33k

1 2

220n

R1731

10k

R1730

3

2

12

10k

1

6

1

Q197

FDC604P

FS4

1 2

7A/32VDC

2A

DC-DC4

DC

1V2_VCC

DC

SW2

5V_VCC

LDO2

LDO

SW3

3V3_VCC

DC-DC3

1V8_VCC

DC

DC

LDO1

2V5_VCC

LDO

A

3V3_TUN

B

C

3V3_VCC

D

E

1 2

5V_VCC

F

LDO1

U175

F303

60R

LM1117

IN OUT

12

GND

VOUT

6V3

1234

C1080

100u

STBY_ON/OFF

STBY_ON/OFF_NOT MOSFET_CONTROL

R1721

1 2

100R

S89

S83

100R

1 2

R1720

NC

C1033
22u
6V3

2V5_VCC

3V3_STBY

F291

1 2

60R

C1093

C1107

1u
6V3

22u

6V3

DC/DC3

6

EN

U176

5

VIN

GND

MP2012

PVIN SW

C1094
22u
6V3

R1738

FB

COMMON

DC/DC4

T. SHT:

E

F

A3

8

AX M

R1769

20k

100k

R1770

1

2

34

150k
150K

C1098
22u
6V3

TP241

1

1V8_VCC3V3_VCC

10UH
L116

10u

C1101

22u

6V3

12V_VCC

F273

1 2

60R

R1979

123

100R

R2

C1217

C1085
22u
16V

678

10n

C1113

50V

10n

45

16V

R4R1R3

C1084
22u
16V

2

1

30068939

1

BS

U173

2

IN

MP1484

3

COMP

SW

4 5

L117

10u

SS

EN

FBGND

C1087
22u
6V3

F300

1 2

330R

LDO2

6V3

22u

C1079

PROJECT NAME :

POWER_2

Ulas Dereli

U2

LM1117

IN OUT

ADJ

VOUT

1234

1 2

12

R24

100R

AP211H

C1212

22u

6V3

100R

R25

3V3_TUNER

C1034

2

100n

1

10V

17mb62S

26-10-2011_15:44

87654321

C1035

100n

10V

1

2

8

R1691

7

12

12V_VCC

10k

C1131

R1710

1 2

6

3k9

1 2

R1686

5n6

39k

50V

R1768

1k

TP231

22k

R1736

1

1V2_VCC
C1086
22u
6V3

5V_VCC

SCH NAME :

DRAWN BY :

27.2 PSU