TV signal processor-Teletextdecoder
with embedded µ-Controller
GENERAL DESCRIPTION
The various versions of the TDA955X/6X/8X H/N1 series
combine thefunctions of a video processor together with a
µ-Controller and US Closed Caption decoder. Most
versions have a Teletext decoder on board. The Teletext
decoderhas aninternal RAM memoryfor 1or10 page text.
The ICs are intended to be used in economy television
receivers with 90° and 110° picture tubes.
The ICs have supply voltages of 8 V and 3.3 V and they
are mounted in a QFP 80 envelope.
The features are given in the following feature list. The
differences between thevarious ICs are given in the table
on page 4.
FEATURES
TV-signal processor
• Multi-standard vision IF circuit with alignment-free PLL
demodulator
• The QSS and mono FM functionality are both available
so that an FM/AM TV receiver can be built without the
use of additional ICs
• The mono intercarrier sound circuit has a selective
FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
The quality of this system is such that the external
band-pass filters can be omitted.
• The FM-PLL demodulator can be set to centre
frequencies of 4.74/5.74 MHz so that a second sound
channel can be demodulated. In such an application it is
necessary that an external bandpass filter is inserted.
• The visionIF and mono intercarrier soundcircuit can be
used for the demodulation of FM radio signals
• Video switch with 2 external CVBS inputs and a CVBS
output. One of the CVBS inputs can be used as Y/C
input.
• 2 external audio inputs. The selection of the various
inputs is coupled to the selection of the CVBS signals
• Integrated chrominance trap circuit
• Integrated luminance delay line with adjustable delay
time
• Switchable group delay correction in the CVBS path
• Picture improvement features with peaking (with
switchable centre frequency, depeaking, variable
positive/negative overshoot ratio and video dependent
coring), dynamic skin tone control and blue-, black- and
white stretching
TDA955X/6X/8X H/N1 series
• Integrated chroma band-pass filter with switchable
centre frequency
• Switchable DC transfer ratio for the luminance signal
• Only one reference (12 MHz) crystal required for the
µ-Controller, Teletext- and the colour decoder
• PAL/NTSC or multi-standard colour decoder with
automatic search system
• Internal base-band delay line
• Indication of the Signal-to-Noise ratio of the incoming
CVBS signal
• A linear RGB/YUV/YP
external RGB/YUVsources. The synchronisation circuit
can be connected to the incoming Y signal. The
Text/OSD signals are internally supplied from the
µ-Controller/Teletext decoder.
• RGB control circuit with ‘Continuous Cathode
Calibration’, white point and black level off-set
adjustment so that the colour temperature of the dark
and the light parts of the screen can be chosen
independently.
• Contrast reduction possibility during mixed-mode of
OSD and Text signals
• Adjustable ‘wide blanking’ of the RGB outputs
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output
stages
• Horizontal and vertical geometry processing
• Horizontal and vertical zoom function for 16 : 9
applications
• Horizontal parallelogram and bow correction for large
screen picture tubes
• Low-power start-up of the horizontal drive circuit
P3.1/ADC11port 3.1 or ADC1 input
P3.2/ADC22port 3.2 or ADC2 input
P3.3/ADC33port 3.3 or ADC3 input
VSSC/P4digital ground for µ-Controller core and periphery
P0.55port 0.5 (8 mA current sinking capability for direct drive of LEDs)
P0.6/CVBSTD6port 0.6 (8 mA current sinking capability for direct drive of LEDs)
or
Composite video input. A positive-going 1V(peak-to-peak) input is required
VSSA7analog ground of Teletext decoder and digital ground of TV-processor
SECPLL8SECAM PLL decoupling
VP292nd supply voltage TV-processor (+8 V)
DECDIG10supply voltage decoupling of digital circuit of TV-processor
PH2LF11phase-2 filter
PH1LF12phase-1 filter
GND313ground 3 for TV-processor
DECBG14bandgap decoupling
GND43ground for TV-processor
CVBS3/Y44CVBS3/Y input
C45chroma input
WHSTR46white stretch capacitor
CVBSO47CVBS output
AUDOUT /AMOUT
IFVO2492nd IF video output signal (with or without group delay correction)
INSSW2502nd RGB / YUV insertion input
R2/VIN512nd R input / V (R-Y) input / PR input
G2/YIN522nd G input / Y input
B2/UIN532nd B input / U (B-Y) input / PB input
BCLIN54beam current limiter input
BLKIN55black current input / V-guard input
RO56Red output
GO57Green output
BO58Blue output
VDDA59analog supply of Teletext decoder and digital supply of TV-processor (3.3 V)
VPE60OTP Programming Voltage
VDDC61digital supply to core (3.3 V)
OSCGND62oscillator ground supply
XTALIN63crystal oscillator input
XTALOUT64crystal oscillator output
RESET65reset
VDDP66digital supply to periphery (+3.3 V)
P1.0/INT167port 1.0 or external interrupt 1 input
P1.1/T068port 1.1 or Counter/Timer 0 input
P1.2/INT069port 1.2 or external interrupt 0 input
P1.3/T170port 1.3 or Counter/Timer 1 input
P1.6/SCL71port 1.6 or I2C-bus clock line
P1.7/SDA72port 1.7 or I2C-bus data line
P2.0/TPWM73port 2.0 or Tuning PWM output
P2.1/PWM074port 2.1
P2.2/PWM175port 2.2
P2.3/PWM276port 2.3
P2.4/PWM377port 2.4
P2.5/PWM478port 2.5
SYNC_FILTER79CVBS (i.e. P0.6/CVBS) Sync filter input: This pin should be connected to V
1. The function of pin 15, 27, 33 and 48 is dependent on the mode of operation (mono intercarrier mode / QSS IF
amplifier and East-West output or not) and is controlled by some software control bits. The valid combinations are
given in table 1.
2000 Jun 228
2000 Jun 229
Table 1 Pin functions for various modes of operation
IC MODEFM-PLL MODE (QSS = 0)QSS MODE (QSS = 1)
Function
FMI bit-01
East-West Y/NNYNYNY
CMB1/CMB0 bits00
AM bit−−−−−01−01−0/1−0/1
Pin 15AVLEWDAVLEWDAVLEWD
Pin 27
1. When additional (external) selectivity is required for FM-PLL system pin 27 can be used as sound IF input. This function is selected by means of
SIF bit in subaddress 28H.
FM DEMODULATIONQSS/AM DEMODULATIONFM RADIO / FM DEMODULATION
TV signal processor-Teletext decoder with
embedded µ-Controller
FUNCTIONAL DESCRIPTION OF THE 80C51
The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
• 3K (1 page teletext version) Auxiliary RAM,
maximum of 2K required for Display
• 12K (10 page teletext version) Auxiliary RAM,
maximum of 10K required for Display
• 8-Level InterruptController for individual enable/disable
with two level priority.
• Two 16-bit Timer/Counters.
• Additional 16-bit Timer with 8-bit Pre-scaler.
• WatchDog Timer.
• Auxiliary RAM Page Pointer.
• 16-bit Data pointer
• Idle, Stand-by and Power-Down modes.
• 18 General I/O.
• Five 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analogue signals.
• One 14-bit PWM for Voltage Synthesis tuner control.
• 8-bit ADC with 4 multiplexed inputs.
• 2 high current outputs for directly driving LED’s etc.
• I2C Byte Level bus interface.
TDA955X/6X/8X H/N1 series
the 32K banks iscommon andis alwaysaddressable. The
other three banks (Bank0, Bank1, Bank2) can be
accessed byselecting the right bankvia the SFR ROMBK
bits 1/0.
FFFFH
Bank0
32K
8000H
Fig.3 ROM Bank Switching memory map
RAM Organisation
The Internal Data RAM is organised into two areas, Data
Memory and Special FunctionRegisters (SFRs)as shown
in Fig.4.
FFH
Upper
128
80H
7FH
Lower
128
FFFFH
Bank1
8000H
7FFFH
Common
0000H
Accessible
by Indirect
Addressing
only
Accessible
by Direct
and Indirect
Addressing
32K
32K
FFFFH
Bank2
32K
8000H
Accessible
by Direct
Addressing
only
Memory Organisation
Thedevice hasthe capabilityof amaximum of128K Bytes
of PROGRAM ROM and 12K Bytes of DATA RAM. The
OSD (& Closed Caption) only version has a 2K RAM and
a maximum of 64K ROM, the 1 page teletext version has
a 3KRAM and also amaximum of 64K ROM whilst the 10
page teletext version has a 12K RAM and a maximum of
128K ROM.
ROM Organisation
The 64Kdevice hasa continuous address space from0 to
64K. The 128K is arranged in four banks of 32K. One of
2000 Jun 2211
00H
Data MemorySpecial Function Registers
Fig.4 Internal Data Memory
DATA MEMORY
TheData memoryis256 x8-bitsand occupiestheaddress
range00 toFF Hexwhen using Indirectaddressing and00
to7F Hexwhen usingdirect addressing. TheSFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Directaddressing only.The lower 128 Bytes ofData
memory are mapped as shown in Fig.5. The lowest 32
bytes aregrouped into 4 banks of 8 registers,the next 16bytes above the register banks form ablock of bit addressable
memory space. The upper 128 bytes are not allocated for any special area or functions.
7FH
Bank Select
Bits in PSW
11 = BANK3
10 = BANK2
01 = BANK1
00 = BANK0
Fig.5 Lower 128 Bytes of Internal RAM
2FH
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
(Bit Addresses 0-7F)
Bit Addressable Space
R0 - R7
4 Banks of 8 Registers
SFR MEMORY
TheSpecial FunctionRegister (SFR)space isused forport latches,counters/timers, peripheralcontrol, data capture and
display. Theseregisters can only be accessed by direct addressing.Sixteen of theaddresses in theSFR space are both
bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summaryof the SFR
map in address order is shown in Table 2.
STASTART flag. Whenthis bitis set in slave mode, thehardware checks theI2C busand generates a STARTcondition if thebus is freeor after thebus
becomes free. If the device operates in master mode it will generate a repeated START condition.
STOSTOP flag. Ifthis bit isset in a master modea STOP condition isgenerated. ASTOP condition detected onthe I2C busclears this bit.This bit may
also be set in slavemode in order to recoverfrom an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware
releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.
SISerial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1.
-The general call address has been received while S1ADR.GC and AA=1.
-A data byte has been received or transmitted in master mode (even if arbitration is lost).
-A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
AAAssert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1).
-A data byte is received, while the device is programmed to be a master receiver.
-A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.
M1,M0 = 01, 16 bit time interval or event counter.
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1.
M1,M0 = 11, stopped.
GATEGating control Timer/Counter 0.
C/TCounter/Timer 0 selector.
M1,M0Mode Control bits Timer/Counter 0.
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.
M1,M0 = 01, 16 bit time interval or event counter.
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0.
M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter.
ROM VER<4:0>Mask programmable identification for character set
Rom Version <4> :
0 - Spanish Flicker Stopper Disabled.
1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).
1Reserved
VIDEO SIGNAL
QUALITY
TXT13VPS
VPS RECEIVED0 -
CLEARING
525 DISPLAY0 - 625 Line synchronisation for Display.
525 TEXT0 - 525 Line WST not being received
0 - Acquisition can not be synchronised to CVBS input.
1 - Acquisition can be synchronised to CVBS
PAGE
RECEIVED
1 - VPS data
PAGE
0 - No page clearing active
1 - Software or Power On page clear in progress
1 - 525 Line synchronisation for Display.
1 - 525 line WST being received
CLEARING
525
DISPLAY
525 TEXT625 TEXTPKT 8/30FASTEXT0xxxxxxx0B
625 TEXT0 - 625 Line WST not being received
1 - 625 line WST being received
PKT 8/300 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected
1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected
FASTEXT0 - No Packet x/27 data detected
1 - Packet x/27 data detected
0Reserved
TXT14000DISPLAY
DISPLAY BANK0 - Select lower bank for Display
1 - Select upper bank for Display
PAGE<3:0>Current Display page
TXT15000MICRO
MICRO BANK0 - Select lower bank for Micro
1 - Select upper bank for Micro
BLOCK<3:0>Current Micro block to be accessed by TXT9, TXT10 and TXT11
TXT170FORCE
FORCE
ACQ<1:0>
00 - Automatic Selection
01 - Force 525 timing, Force 525 Teletext Standard
10 - Force 625 timing, Force 625 Teletext Standard
11 - Force 625 timing, Force 525 Teletext Standard
NOT<3:0>National Option table selection, maximum of 32 when used with East/West bit
BS<1:0>Basic Character set selection
TXT19TENTC<2>TC<1>TC<0>00TS<1>TS<0>00H
00 - Automatic Selection
01 - Force Display to 525 mode (9 lines per row)
10 - Force Display to 625 mode (10 lines per row)
11 - Not Valid (default to 625)
Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011- CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110- CLUT entry 14
111 - CLUT entry 15
TEN0 - Disable Twist function
1- Enable Twist character set
TC<2:0>Language control bits (C12/C13/C14) that has Twisted character set
TS<1:0>Twist Character set selection
TXT20DRCS
DRCS ENABLE0 - Normal OSD characters used
OSD PLANES0 - Character code columns 8 and 9 defined as single plane characters
OSD LANG
ENABLE
OSD LAN<2:0>Alternative C12/C13/C14 bits for use with OSD menus
TXT21DISP
LINES<1:0>
CHAR
SIZE<1:0>
ENABLE
1 - Re-map column 9 to DRCS (TXT and CC modes),
1- Character code columns 8 and 9 defined as double plane characters
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
LINES<1>
DISP
The number of display lines per character row.
00 - 10 lines per character (defaults to 9 lines in 525 mode)
01 - 13 lines per character
10 - 16 lines per character
11 - reserved
Character matrix size.
00 - 10 lines per character (matrix 12x10)
01 - 13 lines per character (matrix 12x13)
10 - 16lines per character (matrix 12x16)
11 - reserved
TV signal processor-Teletext decoder with
embedded µ-Controller
External (Auxiliary + Display) Memory
The normal 80C51 external memory area has been
mappedinternally tothe device,this means thatthe MOVX
instruction accesses data memory internal to the device.
The movx memory map is shown in Fig.6.
7FFFH
4800H
47FFH
Display RAM
for
Data RAM
(2)
(1)
TEXT PAGES
0200H
01FFH
0000H
Lower 32K bytes
(1) Amount of Data RAM depends on device, PainterOSD 64K has 0.75K,
Painter1.1 has 1K and Painter1.10 has 2K
(2) Amount of Display RAM depends on the device, PainterOSD 64K has
1.25K, Painter1.1 has 2K and Painter1.10 has 10K
(3) Display RAM for Closed Caption and Text is shared
Fig.6 Movx Address Map
Auxiliary RAM Page Selection
The Auxiliary RAM page pointer is used to select one of
the 256 pages within the auxiliary RAM, not all pages are
allocated, refer to Fig.7. A page consists of 256
FFFFH
8C00H
8BFFH
Dynamically
Re-definable
Characters
8800H
87FFH
Display Registers
87F0H
871FH
8700H
845FH
Display RAM
Closed Caption
8000H
Upper 32K bytes
CLUT
for
(3)
TDA955X/6X/8X H/N1 series
consecutive bytes. XRAMP only works on internal MOVX
memory.
FFH
(XRAMP)=FFH
00H
FFH
(XRAMP)=FEH
MOVX @Ri, A
MOVX A, @Ri
00H
FFH
00H
FFH
00H
(XRAMP)=01H
(XRAMP)=00H
Fig.7 Indirect addressing
(Movx address space)
Power-on Reset
Power on reset is generated internally to the
TDA955x/6x/8x device, hence no externalreset circuitryis
required. The TV processor die shall generate the master
reset in the system, which in turn will reset the
microcontroller die
A external reset pin is still present and is logically ORed
with theinternal Power on reset. This pin willonly be used
fortest modesand OTP/ISPprogramming.The activehigh
reset pinincorporates an internalpull-down, thus it can be
left unconnected in application.
Power Saving modes of Operation
There are three Power Saving modes, Idle, Stand-by and
Power Down, incorporated into the Painter1_Plus die.
When utilizing either mode, the 3.3v power to the device
(Vddp, Vddc & Vdda) should be maintained, since Power
Saving isachieved by clockgating on asection by section
basis.
STAND-BY MODE
During Stand-by mode, the Acquisition and Display
sections of the device are disabled. The following
functions remain active:-
• 80c51 CPU Core
• Memory Interface
• I2C
• Timer/Counters
• WatchDog Timer
• SAD and PWMs
FFFFH
FF00H
FEFFH
FE00H
01FFH
0100H
00FFH
0000H
MOVX @DPTR,A
MOVX A,@DPTR
2000 Jun 2230
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