Philips UMA1021M-C2, UMA1021M-C1 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of 1996 Aug 28 File under Integrated Circuits, IC17

1999 Jun 17

INTEGRATED CIRCUITS

UMA1021M

Low-voltage frequency synthesizer for radio telephones

1999 Jun 17 2

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1021M

FEATURES

• Low phase noise

• Low current from 3 V supply

• Fully programmable main divider

• 3-line serial interface bus

• Independent fully programmable reference divider,

driven from external crystal oscillator

• Dual charge pump outputs

• Hard and soft power-down control.

APPLICATIONS

• 900 MHz and 2 GHz mobile telephones

• Portable battery-powered radio equipment.

GENERAL DESCRIPTION

The UMA1021M BICMOS device integrates a prescaler, programmable dividers, and a phase comparator to implement a phase-locked loop.

The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at RF input frequencies up to

2.2 GHz, with a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus.

Separate power and ground pins are provided to the analog (charge-pump) and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. V

DD1

and V

DD2

must also be at the same potential (VDD). VCC must be equal to or greater than VDD(e.g. VDD=3V and VCC= 5 V for wider VCO control voltage range).

The phase detector has two charge-pump outputs, CP and CPF, the latter of which is enabled directly at pin FAST. This permits the design of adaptive loops. The charge pump currents (phase detector gain) are fixed by an external resistance at pin I

SET

and via the serial interface. Only a passive loop filter is necessary; the charge pumps function within a wide voltage compliance range to improve the overall system performance.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

digital supply voltage V

DD1=VDD2

;

VCC≥ V

2.7 − 5.5 V

charge-pump supply voltage VCC≥ V

2.7 − 5.5 V

DD+ICC

supply current − 10 − mA

CC(pd)+IDD(pd)

total supply current in power-down mode − 5 −µA

RF input frequency 300 − 2200 MHz

xtal

crystal reference input frequency 3 − 35 MHz

phase comparator frequency − 200 − kHz

amb

operating ambient temperature −30 − +85 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UMA1021M SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1999 Jun 17 3

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1021M

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MBG366

FAST CHARGE

PUMP

CHARGE PUMP

PHASE COMPARATOR

MAIN DIVIDER

WITH

PRESCALER

REFERENCE

DIVIDER

SERIAL INTERFACE

BAND GAP

8 9

10 7 5 17

13 12

UMA1021M

14 4 18

FAST

CPF

DD1

SS3

RFI

SS2

POL

PON

SS1

LOCK

SET

GND(CP)

XTALA XTALB

DD2

E DATA CLK

1999 Jun 17 4

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1021M

PINNING

SYMBOL PIN DESCRIPTION

FAST 1 enable input for fast charge-pump

output CPF CPF 2 fast charge-pump output CP 3 normal charge-pump output V

DD2

4 power supply 2

SS3

5 ground 3 RFI 6 2 GHz main divider input V

SS2

7 ground 2 POL 8 digital input to select polarity of

power-on inputs (PON and sPON): POL = 0 for active LOW and

POL = 1 for active HIGH PON 9 power-on input V

SS1

10 ground 1 CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input V

DD1

14 power supply 1 XTALB 15 complementary crystal frequency

input from TCXO; if not used should be decoupled to ground

XTALA 16 crystal frequency input from TCXO;

if not used should be decoupled to

ground GND(CP) 17 ground for charge-pump V

18 supply for charge-pump

SET

19 external resistor from this pin to

ground sets the charge-pump

currents LOCK 20 out-of-lock detector output

Fig.2 Pin configuration.

handbook, halfpage

UMA1021M

MBG365

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12 11

FAST

CPF

DD2

SS3

RFI

SS2

POL

PON

SS1

LOCK I

SET

CC GND(CP) XTALA

XTALB V

DD1 E

DATA CLK

FUNCTIONAL DESCRIPTION Main divider

The main divider is clocked at pin RFI by the RF signal which is AC-coupled from an external VCO. The divider operates with signal levels from 50 to 225 mV (RMS), and at frequencies from 300 MHz to 2.2 GHz. It consists of a fully programmable bipolar prescaler followed by a CMOS counter. Any divide ratios from 512 to 131071 inclusive can be programmed.

Reference divider

The reference divider is clocked by the differential signal between pins XTALA and XTALB. If only one of these inputs is used, the other should be decoupled to ground. The applied input signal(s) should be AC-coupled. The circuit operates with levels from 50 up to 500 mV (RMS) and at frequencies from 3 to 35 MHz. Any divide ratios from 8 to 2047 inclusive can be programmed.

1999 Jun 17 5

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1021M

Phase detector

The phase detector is driven by the output edges of the main and reference dividers. It produces current pulses at pins CP and CPF whose amplitudes are programmed. The pulse duration is equal to the difference in time of arrival of the edges from the two dividers. If the main divider edge arrives first, CP and CPF sink current. If the reference divider edge arrives first, CP and CPF source current.

The currents at CP and CPF are programmed via the serial bus as multiples of a reference current set by an external resistor connected between pin I

SET

and V

(see Table 3). CP remains active except in power-down. CPF is enabled via input pin FAST which is synchronized with respect to the phase detector to prevent output current pulses being interrupted. By appropriate connection to the loop filter, dual bandwidth loops can be designed; short time constant during frequency switching (FAST mode) to speed-up channel changes, and low bandwidth in the settled state to improve noise and breakthrough levels.

Additional circuitry is included to ensure that the gain of the phase detector remains linear even for small phase errors.

Out-of-lock detector

The out-of-lock detector is enabled (disabled) via the serial interface by setting bit OOL HIGH (LOW). An open drain transistor drives the output pin LOCK (pin 20). It is recommended that the pull-up resistor from this pin to V

is chosen to be of sufficient value to keep the sink current in the LOW state to below 400 µA. When the out-of-lock detector is enabled, LOCK is HIGH if the error at the phase detector input is less than approximately 25 ns, otherwise LOCK is LOW. If the out-of-lock detector is disabled, LOCK remains HIGH.

Serial programming bus

A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, clock (CLK) and enable (

E). The data sent to the device is loaded in bursts framed byE. Programming clock edges and their appropriate data bits are ignored untilE goes active LOW. The programmed information is loaded into the addressed latch when E returns HIGH.

During normal operation,

E should be kept HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data even during power-down.

When the synthesizer is powered-on, the presence of a TCXO signal at the reference divider input and a VCO signal at the main divider input is required for correct programming.

Data format

The leading bits (dt16 to dt0) make up the data field, while the trailing four bits (ad3 to ad0) are the address field. The UMA1021M uses 4 of the 16 available addresses. These are chosen for compatibility with other Philips Semiconductors radio telephone ICs. The data format is shown in Table 1. The first bit entered is dt16, the last bit is ad0. For the divider ratios, the first bits entered (PM16 and PR10) are the most significant (MSB).

The trailing address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To avoid erroneous divider ratios, the load pulse is not allowed during data reads by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer.

The test register (address 0000) does not normally need to be programmed. However if it is programmed, all bits in the data field should be set to logic 0.

Power-down mode

The synthesizer is on when both the input signals PON and the programmed bit sPON are active. The ‘active’ level for these two signals is chosen at pin POL (see Table 2). When turned on, the dividers and phase detector are synchronized to avoid random phase errors. When turned off, the phase detector is synchronized to avoid interrupting charge-pump pulses. For synchronisation functions to work correctly on power-up or power-down (using either hardware or software programming), the presence of TCXO and VCO signals is required to drive the appropriate divider inputs. The UMA1021M has a very low current consumption in the power-down mode.

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