Philips UMA1017M-C2, UMA1017M-C1 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of November 1994 File under Integrated Circuits, IC03

1995 Jul 10

INTEGRATED CIRCUITS

UMA1017M

Low-voltage frequency synthesizer for radio telephones

1995 Jul 10 2

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1017M

FEATURES

• Low current from 3 V supply

• Fully programmable RF divider

• 3-line serial interface bus

• Independent fully programmable reference divider,

driven from external crystal oscillator

• Dual phase detector outputs to allow fast frequency switching

• Dual power-down modes.

APPLICATIONS

• 900 MHz mobile telephones

• Portable battery-powered radio equipment.

GENERAL DESCRIPTION

The UMA1017M BICMOS device integrates prescalers, a programmable divider, and phase comparator to implement a phase-locked loop.

The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 5 V supplies.

The synthesizer operates at RF input frequencies up to

1.25 GHz. The synthesizer has a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus.

Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. Digital supplies V

DD1

and V

DD2

must also be at the same potential. V

must be equal to or greater than VDD (i.e. VDD= 3 V and VCC= 5 V for wider tuning range).

The phase detector uses two charge pumps, one provides normal loop feedback, while the other is only active during fast mode to speed-up switching. All charge pump currents (gain) are fixed by an external resistance at pin I

SET

(pin 14). Only passive loop filters are used; the charge-pumps function within a wide voltage compliance range to improve the overall system performance.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCC, V

supply voltage VCC≥ V

2.7 − 5.5 V

CC+IDD

supply current − 7.7 − mA

CCPD

, I

DDPD

current in power-down mode per supply − 10 −µA

VCO

RF input frequency 50 − 1250 MHz

XTAL

crystal reference input frequency 3 − 40 MHz

phase comparator frequency − 200 − kHz

amb

operating ambient temperature −30 − +85 °C

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

UMA1017M SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1995 Jul 10 3

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1017M

BLOCK DIAGRAM

Fig.1 Block diagram.

1995 Jul 10 4

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1017M

PINNING

SYMBOL PIN DESCRIPTION

FAST 1 control input to speed-up main

synthesizer CPF 2 speed-up charge-pump output CP 3 normal charge-pump output V

DD1

4 digital power supply 1

DD2

5 digital power supply 2 RFI 6 1 GHz RF main divider input DGND1 7 digital ground 1 f

XTAL

8 crystal frequency input from TCXO PON 9 power-on input n.c. 10 not connected CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input

(active LOW)

SET

14 regulator pin to set the charge-pump

currents n.c. 15 not connected AGND 16 analog ground n.c. 17 not connected V

18 supply for charge-pump DGND2 19 digital ground 2 LOCK 20 in-lock detect output; test mode

output

Fig.2 Pin configuration.

1995 Jul 10 5

Philips Semiconductors Product speciﬁcation

Low-voltage frequency synthesizer for radio telephones

UMA1017M

FUNCTIONAL DESCRIPTION General

Programmable reference and main dividers drive the phase detector. Two charge pumps produce phase error current pulses for integration in an external loop filter. A hardwired power-down input PON (pin 9) ensures that the dividers and phase comparator circuits can be disabled.

The RFI input (pin 6) drives a pre-amplifier to provide the clock to the first divider stage. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from 50 mV up to 225 mV (RMS), and at frequencies as high as 1.25 GHz. The high frequency divider circuits use bipolar transistors, slower bits are CMOS. Divider ratios (512 to 131071) allow a 1 MHz phase comparison with a 500 MHz RF input, and a 10 kHz phase comparison with a 1.25 GHz RF input.

The reference and main divider outputs are connected to a phase/frequency detector that controls two charge pumps. The two pumps have a common bias-setting current that is set by an external resistance. The ratio between currents in fast and normal operating modes can be programmed via the 3-wire serial bus. The low current pump remains active except in power-down. The high current pump is enabled via the control input FAST (pin 1). By appropriate connection to the loop filter, dual bandwidth loops are provided: short time constant during frequency switching (FAST mode) to speed-up channel changes and low bandwidth in the settled state (on-frequency) to reduce noise and breakthrough levels.

The synthesizer speed-up charge pump (CPF) is controlled by the FAST input in synchronization with phase detector operation in such a way that potential disturbances are minimized. The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by feedback from the normal pump output to the phase detector thereby improving linearity.

An open drain transistor drives the output pin LOCK (pin 20). It is recommended that the pull-up resistor from this pin to V

is chosen to be of sufficient value to keep the sink current in the LOW state to below 400 µA. The output will be a current pulse with the duration of the selected phase error. By appropriate external filtering and threshold comparison, an out-of-lock or an in-lock flag is generated. The out-of-lock function can be disabled via the serial bus.

Serial programming bus

A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and

E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored untilE goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data even during power-down.

However when the synthesizer is powered-on, the presence of a TCXO signal is required at pin 8 (f

XTAL

) for

correct programming.

Data format

Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The UMA1017M uses 4 of the 16 available addresses. These are chosen to allow direct compatibility with the UAA2072M integrated front-end. The data format is shown in Table 1. The first entered bit is p1, the last bit is p21.

The trailing address bits are decoded on the inactive edge of

E. This produces an internal load pulse to store the data in one of the addressed latches. To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is not allowed during data reads by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The corresponding relationship between data fields and addresses is given in Table 2.

Power-down mode

The device can be powered-down either by hardware PON or by software sPON. The dividers are on when both PON and sPON are at logic 1.

When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.

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