Philips UMA1015AM-C1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

UMA1015AM

Low-power dual frequency synthesizer for radio communications

Product specification

1997 Sep 03

Supersedes data of 1997 Jun 10

File under Integrated Circuits, IC17

Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

FEATURES

·Two fully programmable RF dividers up to 1.1 GHz

·Fully programmable reference divider up to 35 MHz

·2 : 1 or 1 : 1 ratio of selectable reference frequencies

·Fast three-line serial bus interface

·Adjustable phase comparator gain

·Programmable out-of-lock indication for both loops

·On-chip voltage doubler

·Low current consumption from 3 V supply

·Separate power-down mode for each synthesizer

·Up to 4 open-drain output ports

·Crystal input frequency signal inverted and buffered output on separate pin.

APPLICATIONS

·Cordless telephone

·Hand-held mobile radio.

QUICK REFERENCE DATA

GENERAL DESCRIPTION

The UMA1015AM is a low-power dual frequency synthesizer for radio communications which operates in the 50 to 1100 MHz frequency range. Each synthesizer consists of a fully programmable main divider, a phase and frequency detector and a charge pump. There is a fully programmable reference divider common to both synthesizers which operates up to 35 MHz.

The device is programmed via a 3-wire serial bus which operates up to 10 MHz. The charge pump currents (gains)

are fixed by an external resistance at pin 20 (ISET). The BiCMOS device is designed to operate from 2.7 V

(3 NiCd cells) to 5.5 V at low current. Digital supplies VDD1 and VDD2 must be at the same potential. The charge pump supply (VCC) can be provided by an external source or on-chip voltage doubler. VCC must be equal to or higher than VDD1.

Each synthesizer can be powered-down independently via the serial bus to save current. It is also possible to power-down the device via the HPD input (pin 5).

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VDD1, VDD2	digital supply voltage	VDD1 = VDD2	2.7	-	5.5	V
VCC	charge pump supply voltage	external supply; doubler	2.7	-	6.0	V
		disabled; VCC ³ VDD
VCCvd	charge pump supply from	doubler enabled	-	2VDD1 - 0.6	6.0	V
	voltage doubler
IDD1 + IDD2 + ICC	operating supply current	both synthesizers ON; doubler	-	8.7	-	mA
		disabled; VDD1 = VDD2 = 3 V
IDDpd + ICCpd	total current in power-down	doubler disabled;	-	3	-	mA
	mode	VDD1 = VDD2 = 3 V
IDDpd	current in power-down mode	doubler enabled;	-	0.25	-	mA
	from supply VDD1 and VDD2	VDD1 = VDD2 = 3 V
fRF	RF input frequency for each		50	-	1100	MHz
	synthesizer
fXTALIN	crystal input frequency		3	-	35	MHz
fpc(min)	minimum phase comparator		-	10	-	kHz
	frequency
fpc(max)	maximum phase		-	750	-	kHz
	comparator frequency
Tamb	operating ambient		-30	-	+85	°C
	temperature

1997 Sep 03

2

Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	UMA1015AM	SSOP20	plastic shrink small outline package; 20 leads; body width 4.4 mm	SOT266-1

BLOCK DIAGRAM
		VDD1	VDD2			DGND		AGND	ISET	VCC
		4		14			7	16	20	18
11
CLK	4-BIT SHIFT
12		17-BIT SHIFT REGISTER
	REGISTER
DATA
									PUMP	VOLTAGE
			CONTROL LATCH						BIAS	DOUBLER
13
	ADDRESS								VDB enable
E	DECODER
										RF/64
		power	OOL	current	port
		down	select	ratio	bits
			LATCH
6			MAIN DIVIDER						PHASE		3
RFA									DETECTOR		CPA
			TOOL A			RFA/64
5									LOCK	phase
HPD			SYNTHESIZER A						DETECTOR	error
10									TOOL A
fXTALO			LATCH
8							DIV			LOCK	19
		REFERENCE DIVIDER								SELECT	P0/OOL
fXTALIN						BY 2					1
											P1
						SR					2
		UMA1015AM							TOOL B		P2
											9
											P3
			SYNTHESIZER B						LOCK	phase
									DETECTOR	error
			LATCH
15			MAIN DIVIDER						PHASE		17
RFB									DETECTOR		CPB
			TOOL B				RFB/64
											MGG523

Fig.1 Block diagram.

1997 Sep 03

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Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

PINNING

	SYMBOL		PIN	DESCRIPTION
	P1		1	output Port 1
	P2		2	output Port 2
	CPA		3	charge pump output synthesizer A
	VDD1		4	digital supply voltage 1
	HPD		5	hardware power-down
				(input LOW = power-down)
	RFA		6	RF input synthesizer A
	DGND		7	digital ground
	fXTALIN		8	common crystal frequency input from
				TCXO
	P3		9	output Port 3
	fXTALO		10	open-drain output of fXTAL signal
	CLK		11	programming bus clock input
	DATA		12	programming bus data input
			13	programming bus enable input
	E
				(active LOW)
	VDD2		14	digital supply voltage 2
	RFB		15	RF input synthesizer B
	AGND		16	analog ground to charge pumps
	CPB		17	charge pump output synthesizer B
	VCC		18	analog supply to charge pump;
				external or voltage doubler output
	P0/OOL		19	Port output 0/out-of-lock output
	ISET		20	regulator pin to set charge pump
				currents

FUNCTIONAL DESCRIPTION

Main dividers

Each synthesizer has a fully programmable 17-bit main divider. The RF input drives a pre-amplifier to provide the clock to the first divider bit. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from below

50 mV (RMS) up to 250 mV (RMS), and at frequencies up to 1.1 GHz. The high frequency sections of the divider are implemented using bipolar transistors, while the slower section uses CMOS technology. The range of division ratios is 512 to 131071.

Reference divider

There is a common fully programmable 12-bit reference

divider for the two synthesizers. The input fXTALIN drives a pre-amplifier to provide the clock input for the reference

handbook, halfpage				ISET
P1	1		20
P2	2		19	P0/OOL
				VCC
CPA	3		18
VDD1
	4		17	CPB
HPD	5	UMA1015AM	16	AGND
RFA				RFB
	6		15
DGND				VDD2
	7		14
fXTALIN	8
			13		E
P3	9			DATA
			12
fXTALO				CLK
	10		11
		MGG522

Fig.2 Pin configuration.

divider. This clock signal is also inverted and output on pin

fXTALO (open drain). A crystal connected between fXTALIN and fXTALO with suitable feedback components can be used to make an oscillator. An extra divide-by-2 block

allows a reference comparison frequency for synthesizer B to be half the frequency of synthesizer A. This feature is selectable using the program bit SR. If the programmed reference divider ratio is R then the ratio for each synthesizer is as given in Table 1.

The range for the division ratio R is 8 to 4095. Opposite edges of the divider output are used to drive the phase detectors to ensure that active edges arrive at the phase detectors of each synthesizer at different times. This minimizes the potential for interference between the charge pumps of each loop. The reference divider consists of CMOS devices operating beyond 35 MHz.

1997 Sep 03

4

Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

Table 1 Synthesizer ratio of reference divider

SR	SYNTHESIZER A	SYNTHESIZER B
0	R	R
1	R	2R

Phase comparators

For each synthesizer, the outputs of the main and reference dividers drive a phase comparator where a charge pump produces phase error current pulses for integration in an external loop filter. The charge pump

current is set by an external resistance RSET at pin ISET, where a temperature-independent voltage of 1.1 V is

generated. RSET should be between 12 and 60 kΩ.

The charge pump current, ICP, can be programmed to be

either (12 × ISET) or (24 × ISET) with a maximum of 2.3 mA. The dead zone, caused by finite switching of current

pulses, is cancelled by an internal delay in the phase detector thus giving improved linearity. The charge pump has a separate supply, VCC, which helps to reduce the interference on the charge pump output from other parts of

the circuit. VCC can be higher than VDD1 if a wider range on the VCO input is required. VCC must not be less than VDD1.

Voltage doubler

If required, there is a voltage doubler on-chip to supply the charge pumps at a higher level than the nominal available supply. The doubler operates from the digital supply VDD1, and is internally limited to a maximum output of 6 V.

An external capacitor is required on pin VCC for smoothing, the capacitor required to develop the extra voltage is integrated on-chip. To minimize the noise being introduced to the charge pump output from the voltage doubler, the doubler clock is suppressed (provided both loops are in-lock) for the short time that the charge pumps are active. The doubler clock (RF/64) is derived from whichever main divider is operating (synthesizer A has priority). While both synthesizers are powered down (and the doubler is enabled), the doubler clock is supplied by a low-current internal oscillator. The doubler can be disabled by programming the bit VDON to logic 0, in order to allow an external charge pump supply to be used.

Out-of-lock indication/output ports

There is a common lock detector on-chip for the synthesizers. The lock condition of each, or both loops, is output via an open-drain transistor which drives

pin P0/OOL (when out-of-lock, the transistor is turned on and therefore the output is forced LOW). The lock condition output is software selectable (see Table 4).

An out-of-lock condition is flagged when the phase error is greater than TOOL, which is approximately 30 ns.

The out-of-lock flag is only released after the first reference cycle where the phase error is less than TOOL.

The out-of-lock function can be disabled, via the serial bus, and the pin P0/OOL can be used as a port output. Three other port outputs P1, P2 and P3 (open-drain transistors) are also available.

Serial programming bus

A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive (HIGH). This is allowed when CLK is in either state without causing any consequences to the register data. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during power-down of both synthesizers.

However when either synthesizer A or synthesizer B or both are powered-on, the presence of a TCXO signal is required at pin 8 (fXTALIN) for correct programming.

Data format

Data is entered with the most significant bit first.

The leading bits make up the data field, while the trailing four bits are an address field. The address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch.

To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The data format and register bit allocations are shown in Table 2.

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Table 2

Bit allocation

FIRST

REGISTER BIT ALLOCATION

LAST

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

p12

p13

p14

p15

p16

p17

p18

p19

p20

p21

dt16

dt15

dt14

dt13

dt12

DATA FIELD

dt4

dt3

dt2

dt1

dt0

ADDRESS

X

X

VDON

PO

OLA

OLB

CRA

CRB

X

X

sPDA

sPDB

P3

P2

P1

X

X

0

0

0

1

MA16

SYNTHESIZER A MAIN DIVIDER COEFFICIENT

MA0

0

1

0

0

0

0

0

0

SR

R11

REFERENCE DIVIDER COEFFICIENT

R0

0

1

0

1

MB16

SYNTHESIZER B MAIN DIVIDER COEFFICIENT

MB0

0

1

1

0

RESERVED FOR TEST(1)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

sPBF

0

0

1

0

0

0

Note

1. The test register should not be programmed with any other values except all zeros for normal operation.

Table 3 Bit allocation description

SYMBOL		DESCRIPTION
sPDA, sPDB	software power-down for synthesizers A and B (0 = power-down)
sPBF	software power-on for fxtal buffer (1 = buffer on)
P3, P2, P1 and P0	bits output to pins 1, 2, 9 and 19 (1 = high impedance)
VDON	voltage doubler enable (1 = doubler enabled)
OLA, OLB	out-of-lock select; selects signal output to pin 19 (see Table 4)
CRA, CRB	charge pump A/B current to ISET ratio select (see Table 5)
SR	reference frequency ratio select (see Table 6)
Table 4 Out-of-lock select
OLA	OLB	OUTPUT AT PIN 19
0	0	P0
0	1	lock status of loop B; OOLB
1	0	lock status of loop A; OOLA
1	1	logic OR function of loops A and B

synthesizer frequency dual power-Low communications radio for

UMA1015AM

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

Table 5 Charge pump current ratio

CRA/CRB	CURRENT AT PUMP
0	ICP = 12 × ISET
1	ICP = 24 × ISET
Table 6 Reference division ratio
SR	SYNTHESIZER A	SYNTHESIZER B
0	R	R
1	R	2R

Power-down modes

The device can be powered down either via pin HPD (active LOW = power-down) or via the serial bus (bits sPDA and sPDB, logic 0 = power-down).

LIMITING VALUES

The synthesizers are powered up when both hardware and software Power-down signals are at logic 1. When only one synthesizer is powered down, the functions common to both will be maintained (independent of the state of sPBF). When both synthesizers are powered down, the fxtal buffer can be maintained in an active state by setting sPBF to logic 1. This will allow any system clock

derived from the fXTALO buffered output to remain on in power-down. Note that sPBF is independent of the state of

HPD. When both synthesizers are switched off, the voltage doubler (if enabled) will remain active drawing a reduced current. An internal oscillator will drive the doubler in this situation. If both synthesizers have been in a power-down condition, then when one or both synthesizers are reactivated, the reference and main dividers restart in such a way as to avoid large random phase errors at the phase comparator.

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VDD1, VDD2	DC range of digital power supply voltage with respect to DGND	−0.3	+6.0	V
VCC	DC charge pump supply voltage with respect to AGND	−0.3	+6.0	V
VCC-DD	difference in voltage between VCC and VDD1, VDD2	−0.3	+6.0	V
Vn	DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with respect to DGND	−0.3	VDD1 + 0.3	V
V3, 17	DC voltage at pins 3 and 17 with respect to AGND	−0.3	VCC + 0.3	V
VGND	difference in voltage between AGND and DGND (these pins should be	−0.3	+0.3	V
	connected together)
Tstg	storage temperature	−55	+125	°C
Tamb	operating ambient temperature	−30	+85	°C

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.

1997 Sep 03

7

Philips Semiconductors	Product specification

Low-power dual frequency synthesizer

UMA1015AM

for radio communications

CHARACTERISTICS

VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 6.0 V; Tamb = 25 °C; unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies; (VDD1, VDD2 and VCC) voltage doubler disabled, external supply on VCC
VDD1, VDD2	digital supply voltage	VDD1 = VDD2	2.7	-	5.5	V
IDD1 + IDD2	total digital supply current	fXTAL = 12.8 MHz;	-	8.7	-	mA
	from VDD1 and VDD2	both synthesizers on;
		VDD1 = VDD2 = 3 V
		fXTAL = 12.8 MHz;	-	-	12.5	mA
		both synthesizers on;
		VDD1 = VDD2 = 5.5 V
IDDpda,	total digital supply current	fXTAL = 12.8 MHz; one	-	5.0	-	mA
IDDpdb	from VDD1 and VDD2 with	synthesizer powered down;
	one synthesizer in	VDD1 = VDD2 = 3 V
	power-down mode	fXTAL = 12.8 MHz; one	-	-	7.5	mA
		synthesizer powered down;
		VDD1 = VDD2 = 5.5 V
IDD(xtal)	digital supply current from	fXTAL = 12.8 MHz; VHPD = 0 V;	-	0.5	-	mA
	VDD1 with both	sPBF = 1; VDD1 = VDD2 = 3 V
	synthesizers powered	fXTAL = 12.8 MHz; VHPD = 0 V;	-	-	1.15	mA
	down and crystal buffer on	sPBF = 1; VDD1 = VDD2 = 5.5 V
IDDpd	digital supply current in	both synthesizers powered	-	-	60	mA
	power-down mode	down; VHPD = 0 V; sPBF = 0
VCC	charge pump supply	VCC ³ VDD	2.7	-	6.0	V
	voltage
ICC	charge pump supply	both synthesizers on and in	-	-	25	mA
	current	lock; fref = 12.5 kHz
ICCpd	charge pump supply	both synthesizers powered	-	-	25	mA
	current in power-down	down
	mode
Voltage doubler enabled
IDD	total digital supply current	fXTAL = 12.8 MHz; both	-	9.2	12	mA
	from VDD1 and VDD2	synthesizers on and in lock;
		VDD1 = 3 V; fRF = 900 MHz
IDDpd	total digital supply current	both synthesizers powered	-	0.25	0.4	mA
	in power-down mode from	down; VDD1 = 3 V; VHPD = 0 V;
	VDD1 and VDD2	sPBF = 0
VCCvd	charge pump supply	DC current drawn from	4.2	2VDD1 - 0.6	6.0	V
	voltage	VCC = 50 mA; fRF > 100 MHz

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