Philips uma1014 DATASHEETS

INTEGRATED CIRCUITS

DATA SHEET

UMA1014

Low-power frequency synthesizer for mobile radio communications

Product specification			October 1992
Supersedes data of October 1991
File under Integrated circuits, IC03

Philips Semiconductors	Product specification

Low-power frequency synthesizer for

UMA1014

mobile radio communications

FEATURES

∙Single chip synthesizer; compatible with Philips cellular radio chipset

∙Fully programmable RF divider

∙I2C interface for two-line serial bus

∙On-chip crystal oscillator/TCXO buffer from 3 to 16 MHz

∙16 reference division ratios allowing 5 to 100 kHz channel spacing

∙1/8 crystal frequency output

∙On-chip out-of-lock indication

∙Two extra VCO control outputs

∙Latched synthesizer alarm output

∙Status register including out-of-lock indication and power failure

∙Power-down mode.

APPLICATIONS

∙Cellular mobile radio (NMT, AMPS, TACS)

∙Private mobile radio (PMR)

∙Cordless telephones.

GENERAL DESCRIPTION

The UMA1014 is a low-power universal synthesizer which has been designed for use in channelized radio communication. The IC is manufactured in bipolar technology and is designed to operate at 5 to 100 kHz channel spacing with an RF input from 50 to 1100 MHz. The channel is programmed via a standard I2C-bus. A low-power sensitive RF divider is incorporated together with a dead-zone eliminated, 3-state phase comparator. The low-noise charge pump delivers 1 mA or 1/2 mA output current to enable a better compromise between fast switching and loop bandwidth. A power-down circuit enables the synthesizer to be set to idle mode.

QUICK REFERENCE DATA

SYMBOL	PARAMETER		MIN.		TYP.	MAX.	UNIT
VCC, VCP	supply voltage range	4.5		5.0		5.5	V
ICC + ICP	supply current	−		13		−	mA
ICCpd	ICC in power-down	−		2.5		−	mA
fref	phase comparator reference frequency	5		−		100	kHz
fRF	RF input frequency	50		−		1100	MHz
Tamb	operating ambient temperature range	−40		−		85	°C

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	UMA1014T	SO16	plastic small outline package; 16 leads; body width 3.9 mm	SOT109-1

October 1992

2

1992 October

3

							1/8 crystal
+5 V supply	ground						frequency	internally	+5 V charge
							output	connected	pump supply

4

6

16

14

3

oscillator input

1

BUFFER/

UMA1014

2

oscillator output

OSCILLATOR

8

MAIN

REFERENCE

PHASE

CHARGE

charge

COMPARATOR

5

RF input

31/32

DIVIDER

DIVIDER

PUMP

pump

18-BITS

4-BITS

1-BIT

1-BIT

output

hardware

11

power-down

slave address

12

MAIN

CONTROL

OUT-OF-

select input A

LOCK

3-BITS

15

9

10

7

13

VCO buffer switch output B

MRA396 - 1

VCO buffer switch output A

synthesizer

alarm serial data input/output output

serial clock input

handbook, full pagewidth

Fig.1 Block diagram.

DIAGRAM BLOCK	synthesizer frequency power-Low communications radio mobile
	for

UMA1014

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification

Low-power frequency synthesizer for

UMA1014

mobile radio communications

PINNING
	SYMBOL		PIN	DESCRIPTION
	OSCIN		1	oscillator or TCXO input
	OSCOUT		2	oscillator output		handbook, halfpage	1		16
						OSCIN				FX8
	VCP		3	5 V charge pump supply
	VCC		4	5 V supply		OSCOUT	2		15	SYA
	PCD		5	charge pump output		VCP	3		14	i.c.
	GND		6	ground		VCC	4		13	VCOB
								UMA1014
	VCOA		7	VCO buffer switch output A
				(including out-of-lock)		PCD	5		12	SAA
	RF		8	RF input		GND	6		11
										HPD
	SCL		9	serial clock input		VCOA	7		10	SDA
	SDA		10	serial data input/output
						RF	8		9	SCL
	HPD		11	hardware power-down (active LOW)
	SAA		12	slave address select input A				MRA397 - 1
	VCOB		13	VCO buffer switch output B
	i.c.		14	internally connected
	SYA		15	synthesizer alarm output		Fig.2		Pin configuration.
	FX8		16	1/8 crystal frequency output

October 1992

4

Philips Semiconductors	Product specification

Low-power frequency synthesizer for

UMA1014

mobile radio communications

FUNCTIONAL DESCRIPTION

The UMA1014 is a low-power frequency synthesizer for radio communication which operates in the

50 to 1100 MHz range. The device includes an oscillator/buffer circuit, a reference divider, an RF divider, a 3-state phase comparator, a charge pump and a main control circuit to transfer the serial data into the four internal 8-bit registers. The VCC supply feeds the logic part, the VCP supply feeds the charge-pump only. Both supplies are +5 V (±10%). The power-down facility puts the synthesizer in the idle mode (all current supplies are switched off except in the control part). This allows any I2C transfer and all information in the registers is retained thus enabling fast power-up.

Main divider

The main divider is a pulse swallow type counter which is fully programmable. After a sensitive input amplifier

(50 mV, −13 dBm), the RF signal is applied to a 31/32 duo-modulus counter. The output is then used as the clock for the 5-bit swallow counter R = (MD4 to MD0) and the 13-bit main counter N = (MD17 to MD5). The ratio is transferred via the I2C-bus to the registers B, C and D, and then buffered in an 18-bit latch. The ratio in the divider chain is updated with the new information when the least significant bit is received (i.e. D0). This update is synchronized to the output of the divider in order to limit the phase error during small jumps of the synthesized frequency.

The main divider can be programmed to any value between 2048 and 262143 (i.e. 218 −1). If ratio X, below 2048, is sent to the divider, the ratio (X + 2048) will be programmed. When it is required to switch between adjacent channels it is possible to program register D only, thus allowing shorter I2C programming time.

Oscillator

The oscillator is a common collector Colpitts type with external capacitive feedback. The oscillator has very small temperature drift and high voltage supply rejection. A TCXO or other type of clock can be used to drive the oscillator by connecting the source (preferably AC-coupled) to pin 1 and leaving pin 2 open-circuit. The oscillator acts as a buffer in this mode and requires no additional external components. The signal from the clock source should have a minimum space width of 31 ns.

Reference divider

The reference divider is semi-programmable with 16 division ratios which can be selected via the I2C-bus. The programming uses four bits of the register A (A3 to A0) as listed in Table 2. These ratios allow the use of a large number of crystal frequencies from 3 MHz up to 16 MHz. All main channel spacings can be obtained with a single crystal/TXCO frequency of 9.6 MHz.

Phase comparator

A diagram of the phase comparator and charge pump is illustrated in Fig.3.

The phase comparator is both a phase and frequency detector. The detector comprises dual flip-flops together with logic circuitry to eliminate the dead-zone. When a phase error is detected the UP or DOWN signal goes HIGH. This switches on the corresponding current generator which produces a source or sink current for the loop filter. When no phase error is detected PCD goes high impedance. The final tuning voltage for the VCO is provided by the loop filter. The charge pump current is programmable via the I2C-bus. When IPCD (bit 5) is set to logic 1 the charge pump delivers 1 mA; when IPCD is set to logic 0 the charge pump delivers 0.5 mA.

The phase comparator has a phase inverter logic input (PHI). This allows the use of inverted or non-inverted loop filter configurations. It is thus possible to use a passive loop filter which offers higher performances without an operational amplifier. The function of the phase comparator is given in Table 3 and a typical transfer curve is illustrated in Fig.4.

Out-of-lock detector

An out-of-lock detector using the UP and DOWN signals from the phase comparator is included on-chip. The pin VCOA is an open collector output which is forced LOW during an out-of-lock condition. The same information is also available via the I2C-bus in the status register (bit OOL). When the phase error (measured at the phase comparator) is greater than approximately 200 ns, an out-of-lock condition is immediately flagged. The flag is only released after 6 reference cycles when the phase error is less than 200 ns.

October 1992

5

Philips Semiconductors	Product specification

Low-power frequency synthesizer for

UMA1014

mobile radio communications

Table 1 Division ratio in the main divider

			MAIN COUNTER: N					SWALLOW COUNTER: R
MD17	MD16	MD15	...	MD8	MD7	...	MD5	MD4		...	MD0
B1	B0	C7	...	C0	D7	...	D5	D4		...	D0
MSB											LSB
Table 2 Reference divider programming
A3(RD3)	A2(RD2)	A1(RD1)	A0(RD0)	REFERENCE DIVISION			CHANNEL SPACING FOR 9.6 MHz AT
					RATIO			OSCIN
0	0	0	0		128			75 kHz
0	0	0	1		160			60 kHz
0	0	1	0		192			50 kHz
0	0	1	1		240			40 kHz
0	1	0	0		256			37.5 kHz
0	1	0	1		320			30 kHz
0	1	1	0		384			25 kHz
0	1	1	1		480			20 kHz
1	0	0	0		512			18.75 kHz
1	0	0	1		640			15 kHz
1	0	1	0		768			12.5 kHz
1	0	1	1		960			10 kHz
1	1	0	0		1024			9.375 kHz
1	1	0	1		1280			7.5 kHz
1	1	1	0		1536			6.25 kHz
1	1	1	1		1920			5 kHz

Table 3 Operation of the phase comparator

	PHI = 0 (PASSIVE LOOP FILTER)			PHI = 1 (ACTIVE LOOP FILTER)
	fref < fvar	fref > fvar	fref = fvar	fref < fvar	fref > fvar	fref = fvar
UP	0	1	0	1	0	0
DOWN	1	0	0	0	1	0
Ipcd	−1 mA	1 mA	< ±5 nA	1 mA	−1 mA	< ±5 nA

October 1992

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