Philips uma1014 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

UMA1014

Low-power frequency synthesizer for mobile radio communications

Product speciﬁcation Supersedes data of October 1991 File under Integrated circuits, IC03

October 1992

Philips Semiconductors Product speciﬁcation

Low-power frequency synthesizer for mobile radio communications

FEATURES

• Single chip synthesizer; compatible with Philips cellular radio chipset

• Fully programmable RF divider

• I2C interface for two-line serial bus

• On-chip crystal oscillator/TCXO buffer from 3 to 16 MHz

• 16 reference division ratios allowing 5 to 100 kHz

channel spacing

• 1/8 crystal frequency output

• On-chip out-of-lock indication

• Two extra VCO control outputs

• Latched synthesizer alarm output

• Status register including out-of-lock indication and

power failure

• Power-down mode.

APPLICATIONS

UMA1014

GENERAL DESCRIPTION

The UMA1014 is a low-power universal synthesizer which has been designed for use in channelized radio communication. The IC is manufactured in bipolar technology and is designed to operate at 5 to 100 kHz channel spacing with an RF input from 50 to 1100 MHz. The channel is programmed via a standard I low-power sensitive RF divider is incorporated together with a dead-zone eliminated, 3-state phase comparator. The low-noise charge pump delivers 1 mA or 1/2 mA output current to enable a better compromise between fast switching and loop bandwidth. A power-down circuit enables the synthesizer to be set to idle mode.

C-bus. A

• Cellular mobile radio (NMT, AMPS, TACS)

• Private mobile radio (PMR)

• Cordless telephones.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

CCpd

ref

amb

, V

+ I

supply voltage range 4.5 5.0 5.5 V supply current − 13 − mA ICC in power-down − 2.5 − mA phase comparator reference frequency 5 − 100 kHz RF input frequency 50 − 1100 MHz operating ambient temperature range −40 − 85 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

UMA1014T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

October 1992 2

October 1992 3

BLOCK DIAGRAM

mobile radio communications

Philips Semiconductors Product speciﬁcation

Low-power frequency synthesizer for

oscillator input

oscillator output

RF input

hardware

power-down

slave address

select input A

BUFFER/

OSCILLATOR

31/32

15 9 10 7 13

synthesizer

alarm

output

MAIN

CONTROL

1/8 crystal

ground+5 V supply

4 6 16 14 3

frequency

output

internally

connected

UMA1014

PHASE

COMPARATOR

OUT-OF-

LOCK

3-BITS

MAIN

DIVIDER

18-BITS 4-BITS 1-BIT 1-BIT

VCO buffer switch output B VCO buffer switch output A serial data input/output serial clock input

REFERENCE

DIVIDER

+5 V charge

pump supply

CHARGE

PUMP

MRA396 - 1

charge

pump output

handbook, full pagewidth

Fig.1 Block diagram.

UMA1014

Philips Semiconductors Product speciﬁcation

Low-power frequency synthesizer for mobile radio communications

PINNING

SYMBOL PIN DESCRIPTION

OSCIN 1 oscillator or TCXO input OSCOUT 2 oscillator output V

PCD 5 charge pump output GND 6 ground VCOA 7 VCO buffer switch output A

RF 8 RF input SCL 9 serial clock input SDA 10 serial data input/output HPD 11 hardware power-down (active LOW) SAA 12 slave address select input A VCOB 13 VCO buffer switch output B i.c. 14 internally connected SYA 15 synthesizer alarm output FX8 16 1/8 crystal frequency output

3 5 V charge pump supply 4 5 V supply

(including out-of-lock)

handbook, halfpage

OSCOUT

OSCIN

VCOA

215

PCD

GND

UMA1014

MRA397 - 1

Fig.2 Pin configuration.

UMA1014

FX8

SYA

i.c.

VCOB

SAA

HPD

SDA

SCL

October 1992 4

Philips Semiconductors Product speciﬁcation

Low-power frequency synthesizer for mobile radio communications

FUNCTIONAL DESCRIPTION

The UMA1014 is a low-power frequency synthesizer for radio communication which operates in the 50 to 1100 MHz range. The device includes an oscillator/buffer circuit, a reference divider, an RF divider, a 3-state phase comparator, a charge pump and a main control circuit to transfer the serial data into the four internal 8-bit registers. The VCC supply feeds the logic part, the VCP supply feeds the charge-pump only. Both supplies are +5 V (±10%). The power-down facility puts the synthesizer in the idle mode (all current supplies are switched off except in the control part). This allows any I transfer and all information in the registers is retained thus enabling fast power-up.

Main divider

The main divider is a pulse swallow type counter which is fully programmable. After a sensitive input amplifier (50 mV, −13 dBm), the RF signal is applied to a 31/32 duo-modulus counter. The output is then used as the clock for the 5-bit swallow counter R = (MD4 to MD0) and the 13-bit main counter N = (MD17 to MD5). The ratio is transferred via the I then buffered in an 18-bit latch. The ratio in the divider chain is updated with the new information when the least significant bit is received (i.e. D0). This update is synchronized to the output of the divider in order to limit the phase error during small jumps of the synthesized frequency.

The main divider can be programmed to any value between 2048 and 262143 (i.e. 218−1). If ratio X, below 2048, is sent to the divider, the ratio (X + 2048) will be programmed. When it is required to switch between adjacent channels it is possible to program register D only, thus allowing shorter I2C programming time.

Oscillator

The oscillator is a common collector Colpitts type with external capacitive feedback. The oscillator has very small temperature drift and high voltage supply rejection. A TCXO or other type of clock can be used to drive the oscillator by connecting the source (preferably AC-coupled) to pin 1 and leaving pin 2 open-circuit. The oscillator acts as a buffer in this mode and requires no additional external components. The signal from the clock source should have a minimum space width of 31 ns.

C-bus to the registers B, C and D, and

UMA1014

Reference divider

The reference divider is semi-programmable with 16 division ratios which can be selected via the I programming uses four bits of the register A (A3 to A0) as listed in Table 2. These ratios allow the use of a large number of crystal frequencies from 3 MHz up to 16 MHz. All main channel spacings can be obtained with a single crystal/TXCO frequency of 9.6 MHz.

Phase comparator

A diagram of the phase comparator and charge pump is

illustrated in Fig.3. The phase comparator is both a phase and frequency

detector. The detector comprises dual flip-flops together with logic circuitry to eliminate the dead-zone. When a phase error is detected the UP or DOWN signal goes HIGH. This switches on the corresponding current generator which produces a source or sink current for the loop filter. When no phase error is detected PCD goes high impedance. The final tuning voltage for the VCO is provided by the loop filter. The charge pump current is programmable via the I logic 1 the charge pump delivers 1 mA; when IPCD is set to logic 0 the charge pump delivers 0.5 mA.

The phase comparator has a phase inverter logic input (PHI). This allows the use of inverted or non-inverted loop filter configurations. It is thus possible to use a passive loop filter which offers higher performances without an operational amplifier. The function of the phase comparator is given in Table 3 and a typical transfer curve is illustrated in Fig.4.

Out-of-lock detector

An out-of-lock detector using the UP and DOWN signals from the phase comparator is included on-chip. The pin VCOA is an open collector output which is forced LOW during an out-of-lock condition. The same information is also available via the I OOL). When the phase error (measured at the phase comparator) is greater than approximately 200 ns, an out-of-lock condition is immediately flagged. The flag is only released after 6 reference cycles when the phase error is less than 200 ns.

C-bus. When IPCD (bit 5) is set to

C-bus in the status register (bit

C-bus. The

October 1992 5

Philips Semiconductors Product speciﬁcation

Low-power frequency synthesizer for

UMA1014

mobile radio communications

Table 1 Division ratio in the main divider

MAIN COUNTER: N SWALLOW COUNTER: R

MD17 MD16 MD15 ... MD8 MD7 ... MD5 MD4 ... MD0

B1 B0 C7 ... C0 D7 ... D5 D4 ... D0

MSB LSB

Table 2 Reference divider programming

A3(RD3) A2(RD2) A1(RD1) A0(RD0)

REFERENCE DIVISION

RATIO

0000 128 75 kHz 0001 160 60 kHz 0010 192 50 kHz 0011 240 40 kHz 0100 256 37.5 kHz 0101 320 30 kHz 0110 384 25 kHz 0111 480 20 kHz 1000 512 18.75 kHz 1001 640 15 kHz 1010 768 12.5 kHz 1011 960 10 kHz 1100 1024 9.375 kHz 1101 1280 7.5 kHz 1110 1536 6.25 kHz 1111 1920 5 kHz

CHANNEL SPACING FOR 9.6 MHz AT

OSCIN

Table 3 Operation of the phase comparator

PHI = 0 (PASSIVE LOOP FILTER) PHI = 1 (ACTIVE LOOP FILTER)

ref

< f

var

ref

> f

var

ref

= f

var

ref

< f

var

ref

> f

var

= f

ref

var

UP010100

DOWN 100010

pcd

−1 mA 1 mA <±5 nA 1 mA −1 mA <±5 nA

October 1992 6

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