Philips UMA1005T Datasheet
INTEGRATED CIRCUITS
DATA SH EET
UMA1005T
Dual low-power frequency
synthesizer
Preliminary specification
Supersedes data of September 1992
File under Integrated Circuits, IC03
Philips Semiconductors
November 1994
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
FEATURES
• Fast locking by ‘Fractional-N’ divider
• Auxiliary synthesizer
• Digital phase comparator with proportional and integral
charge pump output
• High-speed serial input
• Low-power consumption
• Programmable charge pump currents
• Supply voltage range 2.9 to 5.5 V.
APPLICATIONS
• Mobile telephony
• Portable battery-powered radio equipment.
ORDERING INFORMATION
TYPE NUMBER
NAME DESCRIPTION VERSION
UMA1005T SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
GENERAL DESCRIPTION
The UMA1005T is a low-power, high-performance dual
frequency synthesizer fabricated in CMOS technology.
Fractional-N division with selectable modulo 5 or 8 is
implemented in the main synthesizer.
The detectors and charge pumps are designated to
achieve 10 to 5000 kHz channel spacing using
fractional-N decreases the channel spacing by a factor
5 or 8. Together with an external standard 2, 3 or 4 ratio
prescaler the main synthesizer can operate in the GHz
frequency range.
Channel selection and programming is realized by a
high-speed 3-wire serial interface.
PACKAGE
November 1994 2
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
BLOCK DIAGRAM
1 page = 296 mm (Datasheet)
DATA
CLOCK
STROBE
INM1
INM2
INR
4
5
6
2
3
7
EM
EM + EA
PR
12
2
MAIN DIVIDERS
UMA1005T
REFERENCE DIVIDER
SERIAL INPUT + PROGRAM LATCHES
NM2
NM1
12
NR
NM3
8
NM4
4
EM
SM
2
SA
2
FMOD
MAIN
PHASE
DETECTOR
MAIN
REFERENCE
SELECT
AUXILIARY
REFERENCE
SELECT
NF
3
FRACTIONAL
ACCUMULATOR
FRD
2
222
CN
8
CL
2
CK
4
PRESCALER
FEEDBACK
NORMAL
OUTPUT
CHARGE
PUMP
SPEED-UP
OUTPUT
CHARGE
PUMP
INTEGRAL
OUTPUT
CHARGE
PUMP
27 mm
18
FB1
19
FB2
16
RF
RN
15
13
PHP
11
PHI
9
RA
EA
PA NA
12
41
AUXILIARY DIVIDER
INA
EA
8
Fig.1 Block diagram.
November 1994 3
AUXILIARY
PHASE
DETECTOR
2
V
DDDVDDA
AUXILIARY
OUTPUT
CHARGE
PUMP
20 12141
V
SS
V
SSA
10
17
PHA
LOCK
MEA668 - 1
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
PINNING
SYMBOL PIN DESCRIPTION
V
DDD
INM1 2 main divider positive input; rising edge
INM2 3 main divider negative input; falling
DATA 4 serial data input line
CLOCK 5 serial clock input line
STROBE 6 serial strobe input line
INR 7 reference divider input line; rising edge
INA 8 auxiliary divider input line; rising edge
RA 9 auxiliary current setting; resistor to V
PHA 10 auxiliary phase detector output
PHI 11 integral phase detector output
V
SSA
PHP 13 proportional phase detector output
V
DDA
RN 15 main current setting input; resistor to
RF 16 fractional compensation current setting
LOCK 17 lock detector output
FB1 18 feedback output 1 for prescaler
FB2 19 feedback output 2 for prescaler
V
SS
1 digital supply voltage
active
edge active
active
active
12 analog ground; internally connected to
V
SS
14 analog supply voltage
V
SS
input; resistor to V
SS
modulus control
modulus control
20 common ground connection
SS
1/2 page (Datasheet)
V
DDD
INM1
INM2
DATA
CLOCK
STROBE
INR
INA
PHA
RA
1
2
3
4
5
UMA1005T
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MEA667
Fig.2 Pin configuration.
V
SS
FB2
FB1
LOCK
RF
RN
V
DDA
PHP
V
SSA
PHI
22 mm
November 1994 4
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
FUNCTIONAL DESCRIPTION
Serial programming input
The serial input is a 3-wire input (CLOCK, STROBE and
DATA) to program all counter ratios, DACs, selection and
enable bits. The programming data is structured into
24 or 32-bit words. Each word includes 1 or 4 address
bits. Figure 3 shows the timing diagram of the serial input.
When the STROBE = LOW, the clock driver is enabled
and on the positive edges of the CLOCK the signal on the
DATA input is clocked into a shift register. When the
STROBE = HIGH, the clock is disabled and the data in the
shift register remains stable. Depending on the
1 or 4 address bits the data is latched into different
working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent:
1. D word.
2. C word.
3. B word.
4. A word.
Figure 4 shows the format and the contents of each word.
The E word is for testing purposes only. The E (test) word
is reset when programming the D word. The data for NM4,
CN and PR is stored by the B word temporary registers.
When the A word is loaded, the data of these temporary
registers is loaded together with the A word into the work
registers which avoids false temporary main divider input.
CN is only loaded from the temporary registers when a
short 24-bit A0 word is used. CN will be directly loaded by
programming a long 32-bit A1 word. The flag LONG in the
D word determines whether A0 (LONG = 0) or A1
(LONG = 1) format is applicable.
The A word contains new data for the main divider. The
A word is loaded only when a main divider synchronization
signal is also active, to avoid phase jumps when
reprogramming the main divider. The synchronization
signal is generated by the main divider. It disables the
loading of the A word each main divider cycle during
maximum 300 main divider input cycles. To make sure
that the A word will be correctly loaded the STROBE signal
must be HIGH for at least 300 main divider input cycles.
Programming the A word also means that the main charge
pumps on outputs PHP and PHI are set into the speed-up
mode as long as the STROBE remains HIGH.
handbook, full pagewidth
DATA
CLOCK
STROBE
data
valid
data
change
D0 D1 D30 D31
t
suDA
t
hDA
t
HC
clock enabled
shift in data
Fig.3 Serial input timing sequence.
t
t
LC
suST
clock disabled
store data
t
hST
V
V
V
V
V
V
MBE121
H
L
H
L
H
L
November 1994 5
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
ndbook, full pagewidth
MSB
word
D31
A1
D23
A0
0 NF NM1
B
1 NM4 CN
C
1NA0
D
1
NM2
NM3 NM2
D0
NM2
NM3 NM2
000 CK CL PR
1
000
0
010
000
NR
PA
SM SA
EM EA
F
L
M
O
O
N
D
G
LSB
D0
CN0 NF NM1
PR = ‘01’
PR ‘01’
1E111
address bits
TEST BITS
D0D23
MBE122
Fig.4 Serial input word format.
November 1994 6
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
Table 1 Description of symbols used in Fig.4
SYMBOL BITS
NM1 12 number of main divider cycles when prescaler is programmed in ratio
NM2 8 if PR = 01 number of main divider cycles when prescaler is programmed in ratio
4 if PR ≠ 01
NM3 4 if PR = 1X number of main divider cycles when prescaler is programmed in ratio
NM4 4 if PR = 11 or 00 number of main divider cycles when prescaler is programmed in ratio
PR 2 prescaler type in use:
NF 3 fractional-N increment
FMOD 1 fraction-N modulus selection flag:
LONG 1 A word format selection flag:
CN 8 binary current setting factor for main charge pumps
CL 2 binary acceleration factor for proportional charge pump current
CK 4 binary acceleration factor for integral charge pump current
EM 1 main divider enable flag
EA 1 auxiliary divider enable flag
SM 2 reference select for main phase detector
SA 2 reference select for auxiliary phase detector
NR 9 reference divider ratio
NA 9 auxiliary divider ratio
PA 1 auxiliary prescaler mode:
(1)
FUNCTION
R1 (FB1 = 1; FB2 = 0); note 2
R2 (FB1 = 0; FB2 = 0); note 2
R3 (FB1 = 0; FB2 = 1); note 2
R4 (FB1 = 1; FB2 = 1); note 2
PR = 01; modulus 2 prescaler
PR = 10; modulus 3 prescaler
PR = 11; modulus 4 prescaler
PR = 00; modulus 4 prescaler (inhibit ratio 3)
1 = modulo 8
0 = modulo 5
0 = 24-bit A0 format
1 = 32-bit A1 format
PA = 0; divide-by-4
PA = 1; divide-by-1
Notes
1. X = don’t care.
2. Not including reset cycles and fractional-N effects.
Auxiliary variable divider
The input signal on INA is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled if the
serial control bit EA = 1. Disabling means that all currents
November 1994 7
in the input stage are switched off. A fixed divide by 4 is
enabled if PA = 0. This divider has been optimized to
accept a high-frequency (90 MHz at a supply voltage
range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is
disabled and the input signal is fed directly to the second
Philips Semiconductors Preliminary specification
Dual low-power frequency synthesizer UMA1005T
stage, which is a 9-bit programmable divider with standard
input frequency (30 MHz). The division ratio can be
expressed as:
If PA = 0; N = 4 × NA.
If PA = 1; N = NA; with NA = 4 to 511.
Reference variable divider (Fig.5) The input signal on INR is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled by the
OR function of the serial input bits EA and EM. Disabling
means that all currents in the input stage are switched off.
The reference divider consists of a programmable divider
by NR (NR = 4 to 511) followed by a 3-bit binary counter.
The 2-bit SM determines which of the 4 output pulses is
selected as main phase detector input. The 2-bit SA
determines the selection of the auxiliary phase detector
signal. To obtain the best time spacing for the main and
auxiliary reference signals, the opposite output will be
used for the auxiliary phase detector, reducing the
possibility of unwanted interactions. For this reason the
programmable divider produces a symmetric output pulse
for even ratios and a 1 input cycle asymmetric pulse for
odd ratios.
Main variable divider
The input signals on INM1 and INM2 are amplified to a
logic level by a balanced input comparator giving a
common mode rejection. This input stage is enabled when
serial control bit EM = 1. Disabling means that all currents
in the comparator are switched off. The main divider is
built-up by a 12-bit counter plus a sign bit. Depending on
the serial input values of NM1, NM2, NM3, NM4 and the
prescaler select PR, the counter will select a prescaler
ratio during a number of input cycles in accordance with
the information in Table 2.
ook, full pagewidth
reference
input
MBE123
MAIN SELECT
SM = ‘00’
SM = ‘01’
SM = ‘10’
SM = ‘11’
divide by NR
2 22
AUXILIARY SELECT
SA = ‘11’
SA = ‘10’
SA = ‘01’
SA = ‘00’
Fig.5 Reference variable divider.
main
phase
detector
auxiliary
phase
detector
November 1994 8
Loading...