Page 1
UM10110_1
PNX8550 Programmable Source Decoder
with Integrated Peripherals
Rev. 02 — July 21 2004
Page 2
Philips Semiconductors
Contents
Chapter 1: Functional specification
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. PNX8550 Functional Overview . . . . . . . . . . . . 3
3. PNX8550 Feature Summary . . . . . . . . . . . . . . . 5
4. Compatibility with the PNX8525 . . . . . . . . . . . 6
5. Analog/Digital Standard Definition Video
Improvement Capabilities . . . . . . . . . . . . . . . . . 7
5.1 Temporal-Spatial Improvement Processing . . . . 7
5.2 Temporal Noise Reduction . . . . . . . . . . . . . . . . . . .8
6. HD Decode and Display Capabilities . . . . . . 8
6.1 Dual HD Decode/Display Using 2 PNX8550 . . . . 9
7. Internal Functional Overview . . . . . . . . . . . . . 11
8. Internal Functional Overview . . . . . . . . . . . . . 12
8.1 Overview of Function Partitioning . . . . . . . . . . . .12
9. Integrated Processors . . . . . . . . . . . . . . . . . . . .14
9.1 PR4450 General Purpose Processor . . . . . . . . . 14
9.2 Dual TM3260 VLIW Media Processors . . . . . . .15
9.2.1 Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Digital Video/Transport Stream Inputs. . . . 17
10.1 Backwards Compatibility . . . . . . . . . . . . . . . . . . . . 17
10.2 New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. MPEG2 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1 MPEG System Processor (MSP). . . . . . . . . . . . . 19
11.2 DVD Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
11.3 Software Processing of MPEG2 Streams . . . . . 21
11.4 VMPG - MPEG2 Decoder and VLD2 . . . . . . . . . 21
12. Image Processing Hardware . . . . . . . . . . . . . 22
12.1 Pixel Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
12.2 Video Input Processor (VIP) . . . . . . . . . . . . . . . . . 23
12.3 Tunnel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.4 Quality Temporal Noise Reduction (QTNR)
and Video Measurement . . . . . . . . . . . . . . . . . . . . 24
12.5 Memory Based Scaler (MBS). . . . . . . . . . . . . . . . 25
12.6 2D and DMA Engine . . . . . . . . . . . . . . . . . . . . . . .26
12.7 Quality Video Composition Processor
(QVCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.8 Integrated Digital Video Encoder (DENC) . . . . . 30
12.9 PNX8510/11 Analog Companion Chip . . . . . . . .30
13. Audio Processing and Input/Output. . . . . . 30
13.1 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.2 Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . .31
13.3 Audio Compatibility . . . . . . . . . . . . . . . . . . . . . . . . 31
14. Miscellaneous Functions . . . . . . . . . . . . . . . . 31
14.1 Enhanced DMA Controller (EDMA) . . . . . . . . . . 31
14.2 Semaphores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14.3 Inter-Processor Communication. . . . . . . . . . . . . 32
15. System Memory. . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.1 System DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.2 System EEPROM, ROM or Flash . . . . . . . . . . . 34
16. Security Provisions . . . . . . . . . . . . . . . . . . . . . . 34
16.1 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17. Peripheral Interfaces. . . . . . . . . . . . . . . . . . . . . 35
17.1 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.2 MemoryStick and MultiMediaCard . . . . . . . . . . . 36
17.3 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.1 Software I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.2 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.3 Event Sequence Monitoring and Signal
Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.3.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 38
17.3.5 Timer/Counter Capabilities . . . . . . . . . . . . . . . . . 38
17.3.6 GPIO Pin Reset Value . . . . . . . . . . . . . . . . . . . . . 39
17.3.7 Compatibility with PNX8525 . . . . . . . . . . . . . . . . 39
17.3.8 Remote Control Receiver/Blaster. . . . . . . . . . . . 39
17.4 PCI2.2 and XIO16 Bus Interface Unit . . . . . . . . 40
17.4.1 PCI Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17.4.2 Simple Peripheral Capabilities (XIO8/16) . . . . . 40
18. Endian Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
19. PNX8550 Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
20. Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . 43
21. Changes from PNX8550_RevA to
PNX8550_RevB . . . . . . . . . . . . . . . . . . . . . . . . . . 44
21.1 MBS2 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
21.1.1 Frequency of Operation and Performance . . . . 44
21.2 Vertical Peaking Block (VPK) . . . . . . . . . . . . . . . 44
21.2.1 Frequency of Operation and Performance . . . . 45
21.3 Video Streaming Connections . . . . . . . . . . . . . . 45
21.3.1 Tunnel Interface to QVCP . . . . . . . . . . . . . . . . . . 45
21.3.2 MBS2 Block to QVCP. . . . . . . . . . . . . . . . . . . . . . 45
21.3.3 Vertical Peaking Block to QVCP . . . . . . . . . . . . 45
21.4 Contrast Brightness Control with Soft Clipper
(CBSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 2: Bus Architecture and System Memory Map
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Bus Architecture Block Diagram . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Low Power Adapter Implementation . . . . . . . . . . . 3
3. DCS Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 DCS Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Standard System Memory Map . . . . . . . . . . . .6
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 i
4.1 Apertures in the Standard System Memory Map 6
4.2 Building the Standard System Memory Map . . . 7
4.3 Rationale for the Standard System Memory
Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Hardware Limitations to Object Visibility . 8
6. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 9
6.1 Aperture Control Registers . . . . . . . . . . . . . . . . . . 9
6.1.1 PCI, TM3260, and MIPS PR4450 . . . . . . . . . . . . 9
6.2 Global 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page 3
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
7. Alternate System Memory Map with
External Host CPU. . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 PCI Standard Boot and Memory Map
Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2 Internal MIPS PR4450 and External Host CPU 10
8. Memory Map Perspectives . . . . . . . . . . . . . . . 11
8.1 View from MIPS PR4450 . . . . . . . . . . . . . . . . . . .11
8.1.1 MIPS PR4450 Exception Vector Logic . . . . . . . . 12
Chapter 3: PMAN Hub
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 PNX8550 HUB Block . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 PMAN Arbiter (IP_1010) . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 PMAN Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 DMA Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.4 Memory Bandwidth Monitor . . . . . . . . . . . . . . . . . . 7
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Arbitration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4: DCS network and security
8.2 View from the TM3260 CPU Cores . . . . . . . . . . 13
8.3 View from PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . 14
8.3.1 PNX8550 as PCI Configuration Manager. . . . . 14
8.3.2 An External Host CPU as PCI Configuration
Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.4 View from the MDCS and TDCS Buses . . . . . . 15
8.5 MMIO Base Address Map . . . . . . . . . . . . . . . . . . 16
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Register Programming Guidelines. . . . . . . . . . . 11
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 12
4.1 PMAN Hub Arbiter Registers . . . . . . . . . . . . . . . 12
4.1.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 PMAN Security Registers . . . . . . . . . . . . . . . . . . 14
4.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Memory Bandwidth Monitor Registers . . . . . . . 25
4.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Protection Mechanisms . . . . . . . . . . . . . . . . . . . 2
2.1 MIPS PR4450 Protection Mechanisms . . . . . . . .2
2.2 TM3260 Protection Mechanisms . . . . . . . . . . . . . .2
3. DCS Target Access Control . . . . . . . . . . . . . . .3
3.1 DCS Controller Block Level Diagram . . . . . . . . . . 3
3.1.1 DCS Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 DCS Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Programmable Address Map . . . . . . . . . . . . . . . . . 5
3.1.4 Error Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Selective Blocking of Initiators (System
Security) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.6 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.7 Programmable Timeout. . . . . . . . . . . . . . . . . . . . . . 6
3.1.8 Null Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.9 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 DCS Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 DCS Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 5: Endian mode
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Endian Mode Theory . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Law 1: The “CPU Rule” . . . . . . . . . . . . . . . . . . . . . .2
2.2 Law 2: The “DMA Convention Rule” . . . . . . . . . . .4
3. Endian Mode Architecture Details . . . . . . . . . 4
3.3.1 Deadlock Handling . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 MIPS DCS Network Controller Configuration
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 MIPS DCS Network Controller Security
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 TriMedia DCS Network Controller
Configuration Registers . . . . . . . . . . . . . . . . . . . . 14
4.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 TriMedia DCS Network Controller Security
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Global Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Peripheral DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 SIMD Programming Issues . . . . . . . . . . . . . . . . . . 6
3.5 Optional Endian Mode Override . . . . . . . . . . . . . . 7
4. Audio In—Programmer’s View (Example) 7
5. Detailed Example . . . . . . . . . . . . . . . . . . . . . . . . . 8
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 ii
Page 4
Philips Semiconductors
Chapter 6: Pixel formats
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Summary of Native Pixel Formats . . . . . . . . . 2
3. Native Pixel Format Representation. . . . . . . 3
3.1 Indexed Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 16-Bit Pixel-Packed Formats . . . . . . . . . . . . . . . . . 4
3.3 32-Bit Pixel-Packed Formats . . . . . . . . . . . . . . . . . 4
3.4 Packed YUV 4:2:2 Formats . . . . . . . . . . . . . . . . . . 5
3.5 Planar YUV 4:2:0 and YUV 4:2:2 Formats . . . . . 6
3.5.1 Planar Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 7: Boot
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Boot Block Level Diagram. . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 MMIO Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 I2C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.3 Boot Control/State Machine . . . . . . . . . . . . . . . . . . 4
2.2.4 Internal Script Block . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 8: Clocks
3.5.2 Semi-Planar 10-Bit YUV 4:2:2 and 4:2:0
Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.3 Packed 10-bit YUV 4:2:2 format. . . . . . . . . . . . . 10
4. Universal Converter. . . . . . . . . . . . . . . . . . . . . . 10
5. Alpha Value and Pixel Transparency . . . . 11
6. YUV and RGB Values . . . . . . . . . . . . . . . . . . . . 11
7. Image Storage Format . . . . . . . . . . . . . . . . . . . 11
8. System Endian Mode . . . . . . . . . . . . . . . . . . . . 12
3.1 Boot Mode Configuration. . . . . . . . . . . . . . . . . . . . 5
3.2 Internal vs. External Boot. . . . . . . . . . . . . . . . . . . . 6
3.3 Symbolic Boot Language. . . . . . . . . . . . . . . . . . . . 6
3.4 Internal Boot Scripts . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 External Boot Scripts . . . . . . . . . . . . . . . . . . . . . . . 8
3.5.1 External I2C Boot EEPROM Types . . . . . . . . . . . 8
3.5.2 External EEPROM Boot Script Binary Format. . 9
3.5.3 Details on I2C Operation . . . . . . . . . . . . . . . . . . . 10
3.5.4 Internal Host Booting Using an External Script 10
3.5.5 External Host Boot . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Bootup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Clocks Block Level Diagram. . . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.0.1 System Level Clocks . . . . . . . . . . . . . . . . . . . . . . . . 4
3.0.2 Sources of the PNX8550 Clocks . . . . . . . . . . . . . .7
3.0.3 DDS Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.0.4 PLL Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0.5 Oscillator Pad Requirements . . . . . . . . . . . . . . . . 12
3.0.6 Special Clock Relationships . . . . . . . . . . . . . . . . .12
3.0.7 Clock Control and Selection Logic . . . . . . . . . . . 12
3.0.8 PLL Clock Blocking . . . . . . . . . . . . . . . . . . . . . . . .18
3.0.9 Bypass Clock Sources. . . . . . . . . . . . . . . . . . . . . . 18
3.0.10 Power-Up and Reset Sequence . . . . . . . . . . . . .20
Chapter 9: Reset
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Reset Block Level Diagram . . . . . . . . . . . . . . . . . . 1
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 2
3.0.11 Powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.0.12 DFT Clock Selection. . . . . . . . . . . . . . . . . . . . . . . 20
3.0.13 DFT Frequency Counter . . . . . . . . . . . . . . . . . . . 22
3.0.14 Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Power Management . . . . . . . . . . . . . . . . . . . . . . . 24
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Essential Operating Infrastructure During
Powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Special Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Peripheral Module Powerdown Sequence . . . . 25
4.4 Peripheral Module Wakeup Sequence . . . . . . . 26
4.5 DCS Network Power “Spreading” . . . . . . . . . . . 26
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 27
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.1 PERI_RST State Machine. . . . . . . . . . . . . . . . . . . 4
3.1.2 MIPS_RST State Machine. . . . . . . . . . . . . . . . . . . 5
3.1.3 SYS_RST_OUT State Machine . . . . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 7
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 10: Power management
1. Power Management Mechanisms . . . . . . . . . 1 1.1 Clock Management. . . . . . . . . . . . . . . . . . . . . . . . . 1
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 iii
Page 5
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
1.1.1 Essential Operating Infrastructure During
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Special Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.3 Peripheral Module Powerdown Sequence. . . . . . 2
1.1.4 Peripheral Module Wakeup Sequence . . . . . . . . . 3
1.2 Special Power Management Mechanisms. . . . . . 3
1.2.1 PR4450 MIPS Processor . . . . . . . . . . . . . . . . . . . . 3
1.2.2 TriMedia 3260 CPUs . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 11: Interrupts
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Interrupts Block Level Diagram . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 12: Global registers
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Global Register Descriptions. . . . . . . . . . . . . . 1
2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Global 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 13: PCI-XIO
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 PCI-XIO Block Level Diagram . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 NAND-Flash Interface Operation. . . . . . . . . . . . . . 5
3.1.2 Motorola Style Interface . . . . . . . . . . . . . . . . . . . . 10
3.1.3 NOR Flash Interface . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 IDE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.5 PCI Interrupt Enable Register . . . . . . . . . . . . . . .17
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .17
1.2.3 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. System Powerdown Mode Examples . . . . . 5
2.1 Reduced Power Mode . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Minimal Power Mode . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Procedure for Shutting Down . . . . . . . . . . . . . . . . 6
2.3.2 Procedure for Power Up . . . . . . . . . . . . . . . . . . . . 7
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Register Programming Guidelines. . . . . . . . . . . . 6
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 Global 2 Register Summary . . . . . . . . . . . . . . . . . 2
2.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Global 1 Register Descriptions. . . . . . . . . . . . . . . 3
2.2.2 Global 2 Register Descriptions. . . . . . . . . . . . . . . 7
4.1 DTL MMIO Interface. . . . . . . . . . . . . . . . . . . . . . . 17
4.2 DVP Memory Bus Interface. . . . . . . . . . . . . . . . . 18
4.3 XIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.1 Motorola Interface . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.2 NAND-Flash Interface . . . . . . . . . . . . . . . . . . . . . 19
4.3.3 NOR Flash Interface. . . . . . . . . . . . . . . . . . . . . . . 19
4.3.4 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 PCI Endian Support . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1 Known PCI Non-Compliance . . . . . . . . . . . . . . . 21
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 14: DDR SDRAM
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 DDR Controller Block Level Diagram . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Input processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Start and Warm Start . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.1 Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.2 Warm Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.3 Observing Start State . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.4 Sequence of Actions . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.1 First Level Arbitration: Between DMA and
CPUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.2 Second Level Arbitration: Among CPUs . . . . . . . 8
2.5.3 Dynamic Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 iv
2.5.4 Pre-Emption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.5 Back Log Buffer (BLB) . . . . . . . . . . . . . . . . . . . . . 11
2.5.6 PMAN (Hub) versus DDR Controller
Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.1 Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.2 Memory Region Mapping Scheme. . . . . . . . . . . 13
2.7 DDR Memory Rank Locations . . . . . . . . . . . . . . 15
2.7.1 Some Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. General Operations . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Asynchronous Reset Synchronization. . . . . . . . 16
3.3 Programming via the DTL Port . . . . . . . . . . . . . . 17
3.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Halting and Unhalting . . . . . . . . . . . . . . . . . . . . . . 17
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Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.4.2 Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3 MMIO Directed Halt . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.4 Auto Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.5 Observing Halt Mode . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.6 Sequence of Actions . . . . . . . . . . . . . . . . . . . . . . . 20
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .20
4.1 Memory Configurations . . . . . . . . . . . . . . . . . . . . .20
4.2 Error Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 15: CTL12 Tunnel
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 CTL12 Tunnel Block Level Diagram . . . . . . . . . . .2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Transaction Overview . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.2.3 Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Internal Interface Protocol. . . . . . . . . . . . . . . . . . . . 5
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Register Programming Guidelines . . . . . . . . . . . . 6
3.4 Tunnel Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Booting the DDR SDRAM Controller . . . . . . . . . 22
4.6 Data Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7 Programming the Internal Arbiter . . . . . . . . . . . . 26
4.8 Compatible DDR Parts List . . . . . . . . . . . . . . . . . 27
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 30
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 CTL12 Tunnel Overview . . . . . . . . . . . . . . . . . . . . 6
3.4.2 CTL12 Tunnel Transmit and Receive
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.3 Multiplexing Overview . . . . . . . . . . . . . . . . . . . . . . 9
3.4.4 CTL12 Tunnel Flow Control . . . . . . . . . . . . . . . . 10
3.4.5 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.6 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Tunnel Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 North Bound MTL Traffic . . . . . . . . . . . . . . . . . . . 13
3.5.2 South Bound, DCS Traffic . . . . . . . . . . . . . . . . . . 13
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 16: Smartcard UART
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Smartcard UART Module Block Level Diagram . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Cold and Warm Reset . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Cold Reset Procedure . . . . . . . . . . . . . . . . . . . . . . .4
3.1.2 Warm Reset Procedure . . . . . . . . . . . . . . . . . . . . . . 4
3.2 ISO 7816 UART Functional Description. . . . . . . . 5
Chapter 17: GPIO
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 GPIO Block Level Diagram. . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.2 Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 GPIO Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.4 Reading and Writing GPIO Data . . . . . . . . . . . . . . 4
3.1.5 Signal Monitoring and Pattern Generation. . . . . . 6
3.1.6 Master Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1.7 Timestamp Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Activation and Deactivation Sequence . . . . . . . . 5
3.2.2 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.4 ISO UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . 9
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 11
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Smartcard UART1 Registers . . . . . . . . . . . . . . . 12
4.2.2 Smartcard UART2 Registers . . . . . . . . . . . . . . . 27
3.1.8 Event Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.9 IR Wakeup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.10 Timer Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.12 Event Queue Interrupts . . . . . . . . . . . . . . . . . . . . 19
3.1.13 Timestamp Unit Interrupts . . . . . . . . . . . . . . . . . . 20
3.1.14 IR Wakeup and Counter/Timer Unit Interrupts 20
3.1.15 Direct Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Applications Notes. . . . . . . . . . . . . . . . . . . . . . . 20
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 v
Page 7
Philips Semiconductors
Chapter 18: UART
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 UART Block Level Diagram . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Clock Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Register Programming Guidelines . . . . . . . . . . . . 3
Chapter 19: USB
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 USB Block Level Diagram. . . . . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Components of USB System . . . . . . . . . . . . . . . . . 4
Chapter 20: High Performance I2C Ports (1 & 2)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 HP IIC Block Level Diagram . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Master Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Master Receive Mode . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Slave Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.4 Slave Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Clocking Constraints . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Interrupts from HS I2C. . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.3 Transmitter FIFO Function . . . . . . . . . . . . . . . . . . 4
3.2.4 Receiver FIFO Function. . . . . . . . . . . . . . . . . . . . . 4
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 4
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2.1 UART1 Module Registers . . . . . . . . . . . . . . . . . . . 5
4.2.2 UART2 Module Registers . . . . . . . . . . . . . . . . . . . 9
3.1.1 USB Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . 10
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 11
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Clearing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Enabling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Register Programming Guidelines. . . . . . . . . . . 16
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Module and Interrupt Status . . . . . . . . . . . . . . . . 16
4.1.1 Example of a Master Transmitter . . . . . . . . . . . . 16
4.2 Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 23
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 HP I2C1 Module Registers . . . . . . . . . . . . . . . . . 24
5.2.2 HP I2C2 Module Registers . . . . . . . . . . . . . . . . . 28
Chapter 21: Fast I2C Ports (3 & 4)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 Fast I2C Block Level Diagram . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Fast I2C Module Arbitration and Control Logic . . 3
3.1.2 Serial Clock Generator . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Bit Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.4 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.5 Status Decoder and Register . . . . . . . . . . . . . . . . .4
3.1.6 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.7 Address Register and Comparator . . . . . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 vi
3.1.8 Data Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.9 Related Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 Master Transmitter Mode. . . . . . . . . . . . . . . . . . . . 6
3.2.2 Master Receiver Mode. . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Slave Receiver Mode . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Slave Transmitter Mode. . . . . . . . . . . . . . . . . . . . . 8
3.2.5 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.1 Fast I2C3 Module Registers . . . . . . . . . . . . . . . . . 9
4.2.2 Fast I2C4 Module Registers . . . . . . . . . . . . . . . . 20
Page 8
Philips Semiconductors
Chapter 22: DV Input Ports
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. DV Input to VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 23: DVI Output Ports
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 24: Audio Input Ports
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Audio Input Block Level Diagram . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Chip Level External Interface . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Register Programming Guidelines . . . . . . . . . . . . 6
3.2 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 25: Audio Output
3. TS Mode of DV1, DV2 and DV3. . . . . . . . . . . . 1
3.1 Transport Stream Input Signal Descriptions . . . 3
3.2 Digital Video/TS Interface Timing Diagrams . . . 4
3.3.1 Endian Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Memory Buffers and Capture . . . . . . . . . . . . . . . 10
3.5 Data Bus Latency and HBE . . . . . . . . . . . . . . . . 10
3.6 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9.1 Audio In Operation . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Audio Output Block Level Diagram . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Endian Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.2 Audio Out Data DMA Operation . . . . . . . . . . . . . . 4
3.2.1 TRANS_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.1 Interrupt Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.1 Serial Frame Limitations . . . . . . . . . . . . . . . . . . . . . 7
3.5.2 WS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5.3 I2S Serial Framing Example . . . . . . . . . . . . . . . . . 8
3.6 Codec Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.7 Data Bus Latency and HBE . . . . . . . . . . . . . . . . . 9
3.8 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.9 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 11
3.9.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 13
3.9.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . 14
3.9.4 Register Programming Guidelines. . . . . . . . . . . 14
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 26: SPDIF Input
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 SPDIF IN Block Level Diagram . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Received Serial Format. . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Memory Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 SPDIF IN Endianness . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.4 Bandwidth and Latency Requirements. . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 vii
3.2 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 SPDIF IN Clock Domains . . . . . . . . . . . . . . . . . . . 6
3.2.2 SPDIF Receiver Sample Rate Tolerance and
IEC60958 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 SPDIF Receiver Jitter Tolerance . . . . . . . . . . . . . 6
3.2.4 SPDIF IN and the Oversampling Clock. . . . . . . . 7
3.3 Register Programming Guidelines. . . . . . . . . . . . 7
3.3.1 SPDIF IN Register Set . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 SPDI_STATUS Register Functions . . . . . . . . . . . 8
3.3.3 LOCK and UNLOCK State Behavior . . . . . . . . . . 8
3.3.4 UNLOCK Error Behavior and DMA . . . . . . . . . . . 9
3.3.5 SPDI_CTL and Functions . . . . . . . . . . . . . . . . . . 10
Page 9
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.3.6 SPDI_CBITSx and Channel Status Bits . . . . . . . 10
3.3.7 SPDI_UBITSx and User Bits . . . . . . . . . . . . . . . . 12
3.3.8 SPDI_BASEx and SPDI_SIZE Registers and
Memory Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.9 SPDI_SMPMASK and Sample Size Masking . . 12
3.3.10 SPDI_BPTR and the Start of an IEC60958
Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 27: SPDIF Output
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 SPDIF Out Block Level Diagram . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Register Programming Guidelines . . . . . . . . . . . . 3
3.2 Data Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 IEC-60958 Serial Format . . . . . . . . . . . . . . . . . . . .5
Chapter 28: MIPS RISC Core Processor
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 PNX8550 User ManualBlock Level Diagram. . . . 1
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Instruction Execution Units . . . . . . . . . . . . . . . 2
3.1 Computational Registers. . . . . . . . . . . . . . . . . . . . . 3
3.2 Coprocessor 0 (CP0) Registers . . . . . . . . . . . . . . . 4
4. Instruction Set Overview . . . . . . . . . . . . . . . . . . 5
4.1 MIPS32 Instruction Set . . . . . . . . . . . . . . . . . . . . . . 5
5. Pipeline Execution. . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Eight-Stage Pipeline . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Efficient Handling of Pipeline Stalls. . . . . . . . . . . 12
5.2.1 Interlocking for Data Dependency . . . . . . . . . . . .12
5.2.2 Branch-Likely Instructions. . . . . . . . . . . . . . . . . . . 13
3.3.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.12 Event Timestamping. . . . . . . . . . . . . . . . . . . . . . . 14
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 14
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Transparent Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Errors and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 DMA Error Conditions . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 HBE and Databus Latency . . . . . . . . . . . . . . . . . . 8
3.3.3 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.4 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 9
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. MIPS16 Supports . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 MIPS16 Instruction Set . . . . . . . . . . . . . . . . . . . . 13
6.1.1 Extend Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.2 PC-Relative Addressing. . . . . . . . . . . . . . . . . . . . 14
6.1.3 SP-Relative Addressing. . . . . . . . . . . . . . . . . . . . 14
6.1.4 Load/Store Offset Shifts. . . . . . . . . . . . . . . . . . . . 14
6.2 Switching Between MIPS16 and 32-Bit Modes 14
6.3 MIPS16 Registers. . . . . . . . . . . . . . . . . . . . . . . . . 15
7. MAD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8. Instruction and Data Caches. . . . . . . . . . . . . 15
9. Memory Architecture . . . . . . . . . . . . . . . . . . . . 16
9.1 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. Debug Support. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 29: TM3260 CPU Core Processor
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Programmable source decoder with integrated
peripherals CPU Core Block Level Diagram 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 DRAM Aperture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 MMIO Aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 Aperture1 (DCS Bus Aperture) . . . . . . . . . . . . . . .5
3.2 Special Event Handling . . . . . . . . . . . . . . . . . . . . . .5
3.2.1 Reset and Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 EXC (Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 INT and NMI (Maskable and Non-Maskable
Interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 viii
3.3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Debug Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 System Provisions . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1 TM32_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.2 TM32_MODID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.3 Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 10
3.6.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . 11
4. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Global 1 and 2 Registers . . . . . . . . . . . . . . . . . . . 12
4.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 TM3260 MMIO Register Descriptions . . . . . . . . 17
Page 10
Philips Semiconductors
Chapter 30: Video Input Processor (VIP)
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 VIP Block Level Diagram . . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Chip I/O and Connections. . . . . . . . . . . . . . . . . . . . 4
2.2.2 Data Routing and Video Modes . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 VIP Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Input Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 31: MBS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 MBS Block Level Diagram . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Horizontal Processing Pipeline . . . . . . . . . . . . . . .3
3.1.2 Vertical Processing Pipeline . . . . . . . . . . . . . . . . . 4
3.2 Data Processing in MBS . . . . . . . . . . . . . . . . . . . . . 5
3.3 MBS Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Task Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Video Source Controls. . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3 Video Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.4 Horizontal Video Filters (Sampling, Scaling, Color
Space Conversion) . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.5 Video Data Write to Memory. . . . . . . . . . . . . . . . 17
3.1.6 Auxiliary Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.7 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . 24
4. Register Definitions. . . . . . . . . . . . . . . . . . . . . . 25
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 Horizontal Video Filters . . . . . . . . . . . . . . . . . . . . . 9
3.3.4 Vertical Video Filters. . . . . . . . . . . . . . . . . . . . . . . 10
3.3.5 De-Interlacing in MBS . . . . . . . . . . . . . . . . . . . . . 10
3.3.6 Color-Key Processing. . . . . . . . . . . . . . . . . . . . . . 10
3.3.7 Alpha Processing . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.8 Video Data Output . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.9 Address Generation . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.10 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.11 Measurement Functions . . . . . . . . . . . . . . . . . . . 13
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 32: MBS2 (streaming)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Register Descriptions . . . . . . . . . . . . . . . . . . . . . 1
Chapter 33: QVCP (5L and 2L)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 QVCP Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 QVCP Top Level View. . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 QVCP Block Level Diagram . . . . . . . . . . . . . . . . . . 4
2.1.3 QVCP Data Flow Diagram . . . . . . . . . . . . . . . . . . . 5
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Layer Resources and Functions . . . . . . . . . . . . . . 7
3.1.1 Memory Access Control (DMA CTRL) . . . . . . . . . 7
3.1.2 Pixel Formatter Unit (PFU) . . . . . . . . . . . . . . . . . . . 8
3.1.3 Chroma Key and Undither (CKEY/UDTH) Unit. . 8
3.1.4 Chroma Up-Sample Filter (CUPS) . . . . . . . . . . .11
3.1.5 Linear Interpolator (LINT) . . . . . . . . . . . . . . . . . . . 11
3.1.6 Video/Graphics Contrast Brightness Matrix
(VCBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.7 Layer and Fetch Control . . . . . . . . . . . . . . . . . . . . 13
3.2 Pool Resources and Functions . . . . . . . . . . . . . . 13
3.2.1 CLUT (Color Look-Up Table) . . . . . . . . . . . . . . . . 13
2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 DCTI (Digital Chroma/Color Transient
Improvement). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 HSRU (Horizontal Sample Rate Upconverter). 14
3.2.4 HIST (Histogram Modification) Unit . . . . . . . . . . 14
3.2.5 LSHR (Luminance/Luma Sharpening) Unit . . . 14
3.2.6 CFTR (Color Features) Unit . . . . . . . . . . . . . . . . 15
3.2.7 PLAN (Semi Planar DMA) Unit. . . . . . . . . . . . . . 15
3.3 Screen Timing Generator . . . . . . . . . . . . . . . . . . 15
3.4 Mixer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Key Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Output Pipeline Structure. . . . . . . . . . . . . . . . . . . 20
3.5.1 Formatter (FRMT). . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.2 Chroma Down-Sampler (CDNS) . . . . . . . . . . . . 21
3.5.3 Contrast Brightness and Soft Clip (CBSC). . . . 21
3.5.4 Average Beam Current Limiter (ABCL) or Power
Meter (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.5 Noise-Shaping (GNSH and ONSH) . . . . . . . . . . 22
3.5.6 Interleaver and Muxes . . . . . . . . . . . . . . . . . . . . . 22
3.5.7 Layer Selection, Dual Stream Support . . . . . . . 22
3.6 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 ix
Page 11
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.6.1 Output Interface Modes. . . . . . . . . . . . . . . . . . . . . 23
3.6.2 Out Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.3 Auxiliary Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Programming and Resource
Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 MMIO and Task Based Programming . . . . . . . .26
4.2 Setup Order for the QVCP . . . . . . . . . . . . . . . . . . 28
4.2.1 Shadow Registers . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.2 Fast Access Registers. . . . . . . . . . . . . . . . . . . . . . 32
4.3 Programming the Layer and Pool Resources . .33
4.3.1 Resource Assignment and Selection . . . . . . . . . 33
4.3.2 Aperture Assignment . . . . . . . . . . . . . . . . . . . . . . .35
4.3.3 Data Flow Selection . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.4 Pool Resource Assignment Example . . . . . . . . . 37
4.4 Programming the STG. . . . . . . . . . . . . . . . . . . . . . 39
4.4.1 Changing Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5 Programming QVCP for Different Output
Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 34: QTNR
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 QTNR Block Level Diagram . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Pixel Fetch Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Summary of Required Functionality . . . . . . . . . . . 3
3.1.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .3
3.2 Temporal Noise Reduction . . . . . . . . . . . . . . . . . . .3
3.2.1 Summary of Required Functionality . . . . . . . . . . . 3
3.3 Pixel Store Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.3.1 Summary of Required Functionality . . . . . . . . . . . 4
3.3.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .4
3.4 Measurement Interface Block. . . . . . . . . . . . . . . . . 4
3.4.1 Summary of Required Functionality . . . . . . . . . . . 4
3.4.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .4
3.5 Noise Level Measurement . . . . . . . . . . . . . . . . . . . 4
3.5.1 Summary of Required Functionality . . . . . . . . . . . 4
3.5.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .5
3.6 Black Bar Measurement . . . . . . . . . . . . . . . . . . . . . 5
3.6.1 Summary of Required Functionality . . . . . . . . . . . 5
3.6.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .5
4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6.1 Signature Analysis . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7 Programming Help . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.1 LINT Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.2 HSRU Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.3 LSHR Parameters. . . . . . . . . . . . . . . . . . . . . . . . . 43
4.7.4 DCTI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7.5 CFTR Parameters. . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Underflow Behavior . . . . . . . . . . . . . . . . . . . . . . . 44
4.8.1 Layer Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.8.2 Underflow Symptoms . . . . . . . . . . . . . . . . . . . . . . 45
4.8.3 Underflow Recovery . . . . . . . . . . . . . . . . . . . . . . . 45
4.8.4 Underflow Troubleshooting . . . . . . . . . . . . . . . . . 45
4.8.5 Underflow Handling . . . . . . . . . . . . . . . . . . . . . . . 45
4.9 Clock Calculations . . . . . . . . . . . . . . . . . . . . . . . . 46
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 47
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7 Black Level Measurement. . . . . . . . . . . . . . . . . . . 5
3.7.1 Summary of Required Functionality. . . . . . . . . . . 5
3.7.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 5
3.8 Histogram Measurement . . . . . . . . . . . . . . . . . . . . 5
3.8.1 Summary of Required Functionality. . . . . . . . . . . 5
3.8.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.9 UV Bandwidth Detection . . . . . . . . . . . . . . . . . . . . 6
3.9.1 Summary of Required Functionality. . . . . . . . . . . 6
3.9.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.10 Measurement Only Mode . . . . . . . . . . . . . . . . . . . 6
3.10.1 Summary of Required Functionality. . . . . . . . . . . 6
3.10.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.11 PIO and Task FIFO. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.11.1 Software-Controlled Task Stack. . . . . . . . . . . . . . 6
3.11.2 Summary of Required Functionality. . . . . . . . . . . 6
3.11.3 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.12 Video Measurement Unit (VMU) . . . . . . . . . . . . . 7
3.12.1 VMU Functional Description . . . . . . . . . . . . . . . . . 7
3.12.2 VMU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 35: Video Encoder (DVI_DENC)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 DENC Block Level Diagram . . . . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Video Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Video DAC Control . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Signature Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 x
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 PAL/NTSC/SECAM Encoder . . . . . . . . . . . . . . . . 5
3.2.2 Luminance and Chrominance Processing . . . . . 6
3.2.3 Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.4 Macrovision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.5 VBI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.6 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.7 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . 9
Page 12
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.2.10 Register Programming Guidelines . . . . . . . . . . . . 9
3.3 Module-Specific Capabilities . . . . . . . . . . . . . . . . 12
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .12
Chapter 36: Vertical Peaking (VPK)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Vertical Peaking Block Level Diagram . . . . . . . . . 2
2.2 Vertical Peaking IP Block . . . . . . . . . . . . . . . . . . . . 2
2.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Vertical Peaking Core . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Y_Out According to Output Mode . . . . . . . . . . . . . 4
3.2.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.5 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.6 Powerdown Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 37: 2D Drawing Engine
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 PNX8550 User Manual Block Level Diagram . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.2 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.3 Color Expand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.4 Rotator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.5 Source FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.6 Pattern FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.7 Destination FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.8 Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.9 Source State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.10 Destination State . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.2.11 Address Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.12 Bit BLT Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.13 Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.14 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 12
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.7 Progressive Output Mode . . . . . . . . . . . . . . . . . . . 6
3.3 Module-Specific Capabilities . . . . . . . . . . . . . . . . . 6
3.3.1 Special Output Modes . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Video Input Interface Description . . . . . . . . . . . . . 8
3.3.3 Video Output Interface Description . . . . . . . . . . . 8
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1 Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Endianness Conversion. . . . . . . . . . . . . . . . . . . . 10
4.2 Suggested Coefficient Values for Effective
Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 10
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.15 Byte Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Source Data Location and Type . . . . . . . . . . . . . 6
3.1.4 Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Transparency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.6 Block Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Register Programming Guidelines. . . . . . . . . . . . 7
3.2.1 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Mono Expand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Mono BLT Register Setup . . . . . . . . . . . . . . . . . . 10
3.2.4 Solid Fill Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.5 Color BLT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.6 PatRam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 13
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 38: Transport Stream Network (TSIO)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Transport Stream Network Top Level View . . . . . 2
2.2 TSIO Block Level Diagram . . . . . . . . . . . . . . . . . . . 3
2.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 TS Input Interface Modes . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xi
3.1.2 TS OUT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 TS Input Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 Register Programming Guidelines. . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 7
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page 13
Philips Semiconductors
Programmable Source Decoder with Integrated Peripherals
Chapter 39: Transport Stream Direct Memory Access (TSDMA)
PNX8550
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Interface and Ports. . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 Output Signal Descriptions . . . . . . . . . . . . . . . . . . .2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 40: DVI_EDMA Controller
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 DVI_EDMA Block Level Diagram . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 DMA Engine Core. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.3 Source and Destination Location. . . . . . . . . . . . . . 3
2.2.4 DMA, CRC and AES Data Paths. . . . . . . . . . . . . . 3
2.2.5 DMA Scatter-Gather and Control Engine. . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Scatter-Gather DMA . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Scatter-Gather Mode Retriggering . . . . . . . . . . . .4
3.2 CRC Computation . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 DVI_AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 DMA Channel Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Packet Delivery Schedule . . . . . . . . . . . . . . . . . . . 5
3.1.4 Stream Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 6
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . 9
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Descriptor Overview . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 10
5.1 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . 10
5.1.2 Channel Link List Pointer Register. . . . . . . . . . . 10
5.1.3 CRC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.4 DMA Status Register . . . . . . . . . . . . . . . . . . . . . . 11
5.1.5 Reference Key Registers. . . . . . . . . . . . . . . . . . . 11
5.1.6 AES SRAM Key Valid Register . . . . . . . . . . . . . 11
5.1.7 AES SRAM Key Clear Register . . . . . . . . . . . . . 11
5.1.8 SCN Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.9 KMU Control Register . . . . . . . . . . . . . . . . . . . . . 11
5.1.10 KMU Status Register . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 41: VESPIC MPEG System Processor (VMSP)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 4
2.1 MSP Block Level Diagram . . . . . . . . . . . . . . . . . . . 4
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Packet Framer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Transport/De-Multiplexer RISC Engine . . . . . . . . 6
2.2.3 Hardware Section Filtering . . . . . . . . . . . . . . . . . . . 7
2.2.4 De-Scrambler Core . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.5 Memory Queue Manager Controller . . . . . . . . . . 10
2.2.6 Packet Direct Memory Access . . . . . . . . . . . . . . . 10
2.2.7 Transport RISC Engine . . . . . . . . . . . . . . . . . . . . .11
2.2.8 Hardware Section Filtering . . . . . . . . . . . . . . . . . . 12
2.2.9 De-Scrambler and Cipher Engine . . . . . . . . . . . . 17
2.2.10 Memory Queue Manager. . . . . . . . . . . . . . . . . . . 20
2.3 General Operations . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 MPEG System Processor Interrupt Handler . . 21
3. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 VMSP Configuration Register Summary . . . . . 23
3.1.2 PDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Memory Queue Manager Registers. . . . . . . . . . 27
3.2.2 Packet Framer Registers. . . . . . . . . . . . . . . . . . . 28
3.2.3 RISC Engine Registers . . . . . . . . . . . . . . . . . . . . 40
3.2.4 De-Scrambler Registers. . . . . . . . . . . . . . . . . . . . 42
3.2.5 VMSP Interrupt Sources and Control . . . . . . . . 46
3.2.6 VMSP Interrupt Registers . . . . . . . . . . . . . . . . . . 48
Chapter 42: MPEG Video Decoder
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 MPEG Video Decoder Block Level Diagram . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 VLD-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xii
2.2.2 Full MPEG/MPEG2 Decoding with Motion
Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 VLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.2 Run-Length Decoder/Inverse Scan . . . . . . . . . . . 5
3.1.3 Motion Compensation . . . . . . . . . . . . . . . . . . . . . . 5
Page 14
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 VLD Register Programming Guidelines . . . . . . . . 7
3.3.1 VLD Status (VLD_MC_STATUS) . . . . . . . . . . . . .7
3.3.2 VLD Interrupt Enable (VLD_IE) . . . . . . . . . . . . . . . 8
3.3.3 VLD Control (VLD_CTL) . . . . . . . . . . . . . . . . . . . . . 8
3.3.4 VLD DMA Current Read Address and Current
Read Count9
3.3.5 VLD DMA Macroblock Header Current Write
Address (VLD_MBH_ADR)10
3.3.6 VLD DMA Macroblock Header Current Write
Count10
3.3.7 VLD DMA Run-Level Current Write Address
(VLD_RL_ADR)10
3.3.8 VLD DMA Run-Level Current Write Count. . . . . 10
3.3.9 VLD Command (VLD_COMMAND) . . . . . . . . . .10
3.3.10 VLD Shift Register (VLD_SR) . . . . . . . . . . . . . . .13
3.3.11 VLD Quantizer Scale (VLD_QS) . . . . . . . . . . . . . 13
3.3.12 VLD Picture Info (VLD_PI) . . . . . . . . . . . . . . . . . . 13
3.3.13 VLD Bit Count (VLD_BIT_CNT). . . . . . . . . . . . . . 13
3.4 RL/ IQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1 Run-Length Decoder Statistics Registers . . . . . 13
3.4.2 Total Symbol Count . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.3 Total_Coded_Block_Count. . . . . . . . . . . . . . . . . . 14
3.4.4 Extra Picture Info (Extra_Pic_Info) . . . . . . . . . . . 14
3.5 Motion Compensation Registers . . . . . . . . . . . . . 14
3.5.1 MC Control Registers . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 MC Command Register. . . . . . . . . . . . . . . . . . . . . 14
3.5.3 MC Status Register . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 MC_PFCOUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.5 Line Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.6 VLD_MC_STATUS. . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 VLD Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 VLD Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2 VLD Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.3 Restart the VLD Parsing . . . . . . . . . . . . . . . . . . . 18
3.7 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.1 Unexpected Start Code . . . . . . . . . . . . . . . . . . . . 19
3.8.2 MC Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8.3 Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Run-Length Decoder/Inverse Scan Overview . 21
3.9.1 Run-Length Decoder . . . . . . . . . . . . . . . . . . . . . . 21
3.9.2 Inverse Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.3 Inverse Quantization. . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Coefficient Selection for Half Resolution Mode 24
3.11 Motion Compensation Operations . . . . . . . . . . . 24
3.11.1 Error Concealment Operation. . . . . . . . . . . . . . . 25
3.11.2 Bitstream Error Detection . . . . . . . . . . . . . . . . . . 26
3.11.3 Reducing Memory Bandwidth Utilization . . . . . 27
3.11.4 Fetching Macroblocks . . . . . . . . . . . . . . . . . . . . . 27
3.11.5 PEL Reconstruction Unit . . . . . . . . . . . . . . . . . . . 28
3.11.6 Storage Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.7 MC/VLD Error Recovery . . . . . . . . . . . . . . . . . . . 29
3.11.8 MPEG Software Reset . . . . . . . . . . . . . . . . . . . . . 29
3.11.9 MC Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11.10 MC Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 31
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 31
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 43: Variable Length Decoder (VLD)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 VLD Block Level Diagram . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 VLD MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 VLD Status (VLD_MC_STATUS) . . . . . . . . . . . . .3
3.2.2 VLD Interrupt Enable (VLD_IE) . . . . . . . . . . . . . . . 4
3.2.3 VLD Control (VLD_CTL) . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 VLD DMA Current Read Address
(VLD_INP_ADR) and
Read Count (VLD_INP_CNT)5
3.2.5 VLD DMA Macroblock Header Current Write
Address (VLD_MBH_ADR)5
3.2.6 VLD DMA Macroblock Header Current Write
Count5
3.2.7 VLD DMA Run-Level Current Write Address
(VLD_RL_ADR)6
3.2.8 VLD DMA Run-Level Current Write Count. . . . . . 6
3.2.9 VLD Command (VLD_COMMAND) . . . . . . . . . . .6
3.2.10 VLD Shift Register (VLD_SR) . . . . . . . . . . . . . . . .8
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xiii
3.2.11 VLD Quantizer Scale (VLD_QS) . . . . . . . . . . . . . 8
3.2.12 VLD Picture Info (VLD_PI). . . . . . . . . . . . . . . . . . . 8
3.2.13 VLD Bit Count (VLD_BIT_CNT) . . . . . . . . . . . . . . 8
3.3 VLD Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1 VLD Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 VLD Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Restart the VLD Parsing . . . . . . . . . . . . . . . . . . . 12
3.4 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Unexpected Start Code . . . . . . . . . . . . . . . . . . . . 13
3.5.2 RL Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 DVI_VLD Programming Differences vs. Other
Video Decoders14
4.1.1 TM1100 VLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.2 PNX8525 Video Decoder. . . . . . . . . . . . . . . . . . . 14
4.1.3 PNX8550 Video Decoder. . . . . . . . . . . . . . . . . . . 14
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
5.1 TM1100 and PNX8550 Register Differences. . 14
5.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page 15
Philips Semiconductors
Programmable Source Decoder with Integrated Peripherals
Chapter 44: DVDD
1. Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 45: Boundary Scan
PNX8550
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Boundary Scan Architecture Diagram . . . . . . . . .2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Principle of the Boundary Scan Architecture . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 46: EJTAG_DMA
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 EJTAG DMA Block Level Diagram . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 DTL-MMIO Master Interface. . . . . . . . . . . . . . . . . . 3
3.1.1 EJTAG Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 TimNet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 47: TM3260 Debug
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . 1
2.1.2 TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.3 PNX8550 JTAG Instruction Set . . . . . . . . . . . . . . .4
3.1 The IEEE 1149.1 Boundary Scan Standard. . . . 4
3.1.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . 7
3.1.4 JTAG Public Instruction Set . . . . . . . . . . . . . . . . . 7
3.2 Boundary Scan Description Language . . . . . . . . 8
3.2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.3 Register Programming Guidelines. . . . . . . . . . . . 5
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 Register Programming Guidelines. . . . . . . . . . . . 4
2.2 Module-Specific Capabilities . . . . . . . . . . . . . . . . . 6
2.2.1 Debug Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 48: Interrupt Control
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 PNX8550 User Manual Block Level Diagram . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Priority Masking Stage. . . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.4 Vector Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Register Descriptions . . . . . . . . . . . . . . . . . . . . . 5
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xiv
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Interrupt Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Interrupt Priority Mask Registers . . . . . . . . . . . . . 8
3.2.5 Interrupt Vector Registers . . . . . . . . . . . . . . . . . . . 9
3.2.6 Interrupt Pending Registers . . . . . . . . . . . . . . . . 10
3.2.7 Interrupt Features Register . . . . . . . . . . . . . . . . . 12
3.2.8 Interrupt Request Registers . . . . . . . . . . . . . . . . 12
3.2.9 Interrupt Module ID Register. . . . . . . . . . . . . . . . 18
3.2.10 Other GIC Registers . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.11 IPC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 16
1. Introduction
Chapter 1: Functional specification
PNX8550 User Manual
Rev. 02 — July 21 2004 Preliminary data
TS output
3x656
TS inputs
2x smartcard
2x I2S
S/PDIF
PNX8550
video/ts router
2D DE
TSout
10
1SD+1HD
YUV422
20
video in
dual
cond.
access
32-bit 225 MHz DDR
DVD-CSS
audio in
dual SD
single HD
MPEG2
decoder
Memory
Controller
scaler &
V Peaking
temporal
noise redux
250 MHz
MIPS32
CPU
optional external
video improvement
processing
5 layer
Tunnel
primary
video out
HD/VGA/656
2 layer
secondary
video out
scaler &
de-interlace
2x 240 MHz
TM3260
Media Processor
Streaming interface
from Tunnel
DENC
audio out
30 (dig)
analog
S-Video or
CVBS
2
s
2x i
S/PDIF
MemoryStick/
MultiMediaCard
UARTs
USB1.1
GPIO
Figure 1: PNX8550 Functional Block Diagram
The PNX8550 is a highly integrated media processor intended for deployment in
Analog, Digital and Hybrid Television receivers. The PNX8550 is targeted at the mid
to high-end TV sets, focusing on dual program analog/digital picture improved
Standard Definition capability and single program High Definition decode and display
capability. The PNX8550 can be used for 100 Hz interlaced as well as 60 Hz
progressive screens. It is fully capable of performing advanced video improvement
algorithms, such as DRC™ or Digital Natural Motion™, on Standard Definition analog
or digital sources. It includes an HD capable de-interlacer for converting interlaced
HD transmission signals to progressive output for driving wide-XGA class Plasma or
PCI2.2
Flash IDE
Page 17
Philips Semiconductors
LCD displays. The PNX8550 includes DVD content scramble system (CSS) to
support he DVD player function. The PNX8550 also supports VCD, S-VCD and
CD-Audio players.
The PNX8550 is responsible for the video improvement processing on analog
sources, and for all source decode functions and video improvement processing on
digital sources. It includes integrated dual program conditional access, dual program
MPEG2 transport stream de-mux, dual SD or single HD MPEG2 video decode, audio
decode and processing, graphics generation, video processing, and image
composition and display. Two 32-bit 240 MHz VLIW media processors, referred to as
the TriMedia TM3260 CPU core, carry out the advanced video improvement
processing as well as all audio operations. Fixed function hardware performs stable
core video functions, such as picture level MPEG2 decoding, scaling, image
composition and pixel post processing.
The PNX8550 includes an integrated Remote Control receiver, I2C, USB host and
UART peripherals. In addition, a software controlled General Purpose IO block
provides for connectivity to switches/indicators and arbitrary serial devices, and
includes capability to connect to MemoryStick™ or MultiMediaCard™ Flash. The
PNX8550 also provides an industry standard PCI 2.2, 32-bit wide, 33 MHz system
bus connection allowing a wide variety of low-cost PC peripherals to be gluelessly
attached. The system bus includes support for direct connection to 8 and 16-bit wide
system ROM or Flash memories and 8 and 16-bit simple M68k type slave devices.
Internal IDE control logic provides the capability for a medium performance
(5MB/sec) IDE interface using only two low-cost external TTL packages.
PNX8550
Chapter 1: Functional specification
An embedded MIPS32 processor (PR4450) running at 250 MHz is available to run
the OS. The PR4450 processor is primarily responsible for running the demand
paged graphics-intensive operating system, while the TM3260 media processors are
responsible for running all real-time media functions. All hardware resources inside
the PNX8550 are accessible by both the MIPS processor and the TM3260 CPUs. A
‘sandbox’ style system protection provision ensures that selected MIPS memory
regions and critical peripherals can not be corrupted or inspected.
The PNX8550 provides a primary digital (YUV or RGB) output to connect to the
display specific output processor. In addition, a secondary analog video output
(CVBS or S-Video) for a VCR is available. It can operate either in analog PAL/NTSC
or digital mode.
The PNX8550 optionally allows passing a selected video stream through an external
accelerator, and bringing it back in to the primary video output stream to be merged
with graphics or other video planes. This connection provides for up to 81 Mpix/sec
pixel rate, with up to 10-bit/component accuracy.
The PNX8550 is manufactured using an advanced 0.12u CMOS process.
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Philips Semiconductors
2. PNX8550 Functional Overview
32-bit DDR
PNX8550
Chapter 1: Functional specification
225 MHz
analog/digital
tuner + frontend
analog/digital
tuner + frontend
MemoryStick
MultiMediaCard
Remote Control
Smart
Card
1394 I/F
27 MHz
TD8004
Optional 1394
L2 Controller
656/TS
i2s
656/TS
i2s
DV1 / DV2
i2s_in1
DV3
i2s_in2
GPIO
2x ISO
UART
DV3
TS_OUT
PNX8550
PCI
DV_OUT1
VOUT2
i2s_out1
i2s_out2
USB 2x
UART 2x
S/PDIF
XIO
Expansion
Device
30b RGB
20b YUV
8 ch
display
output
processor
analog Y/C or CVBS
for VCR
DACs
external modem, USB1.1 devices,
frontpanel controller
to Dolby Digital™ receiver
to screen
to amp,
speakers
PCI 2.2
buffer
IDE
8/16 bit Flash
10/100 LAN/PHY
802.11a mini-PCI
home
network
Figure 2: Typical PNX8550 Dual SD/Single HD Hybrid TV Application
Figure 2 shows a typical configuration for the PNX8550. For simplicity, the optional
external video improvement processor is not shown here. In this configuration, the
PNX8550 performs the following functions:
• Conditional access for up to 2 cable/terrestrial transport stream sources
– DVB, Multi2 (M2), DES (triple and single, each in EBC or CBC)
• Audio and video decoding for up to 2 Standard Definition or 1 High Definition
MPEG-2 programs, coming in over the transport stream inputs, IEEE1394, LAN
or from an attached IDE DVD drive (not shown)
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Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• MPEG 2:1 compression mode video decoding in order to save memory
bandwidth for PIP application
• Acquisition of up to two CCIR656 pixel sources, one of which can be HD up to 81
Mpix/sec
• Temporal noise reduction on any internal video stream, but in particular the 656
source(s)
• Temporal-spatial video improvement processing, such as such as Digital Reality
Creation™ or Digital Natural Motion™ on 1 full resolution SD program or 2 half
resolution SD programs (MPEG2 or 656 source).
• Histogram measurement, histogram correction, black-stretch, luminance
sharpening (LTI, CDS, HDP), Digital Color Transient Improvement, color features
(green enhancement, skin tone correction, blue stretch) on the video
• Running an OS, such as Linux™ or VxWorks™, creating 1 or more graphics
surfaces
• Blending up to 5 video or graphics images for output towards the primary display
(CRT, LCD or Plasma)
• Blending 1 video and 1 graphics image for output towards the VCR over an
analog S-Video or CVBS output (VCR audio requires external low-cost stereo
DAC)
• Outputting multi-channel audio across S/PDIF (Sony/Philips Digital Interface) for
decoding in a receiver
• Decoding of image files or audio content from a MemoryStick™ or
MultiMediaCard™
• Transmitting 1 audio/video program or a transport stream across an external
1394 interface
• Transmission of 1 or more programs, subject to compute power and network
bandwidth over a home network
• Decoding/execution of Remote Control commands
• Connecting to an optional serial modem or USB modem
• Booting from Nor or Nand Flash
Since the PNX8550 is a highly flexible, highly programmable system that performs
the majority of video processing in software, a wide variety of other applications are
possible. Any application that fits the constraints of the external interfaces, the media
processing power and the available memory bandwidth can in principle be
accommodated.
Two PNX8550 can be used to create a dual HD PIP or side-by-side HD hybrid TV set.
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Preliminary data Rev. 02 — July 21 2004 1-4
Page 20
Philips Semiconductors
3. PNX8550 Feature Summary
• Dual TM3260 240 MHz, 5 instruction per clock cycle 32-bit VLIW media
processing cores
• PR4450 250 MHz MIPS32 ISA compliant general purpose CPU with demand
paging support (TLB)
• 2 simultaneous 10 bit YUV422 digital video input streams, one of which can be
HD/VGA up to 81 Mpix/s
• 2 stream MPEG2 transport stream processing (PID filtering, conditional access,
section filter, demux)
• Conditional access for DVB, Multi2 (M2), DES (triple and single, each in EBC or
CBC)
• 1 serial or parallel transport stream output (for external 1394 hookup)
• Integrated DVD-CSS, allowing full DVD playback functionality
PNX8550
Chapter 1: Functional specification
• Simultaneous hardware decode of two SD streams (MPEG2 MP@ML) or 1 HD
(MPEG2 MP@HL)
• MPEG 2:1 compression mode video decoding in order to save memory
bandwidth for PIP application
• High quality hardware image scaler and advanced de-interlacer, augmented with
media processing software to do motion compensated de-interlacing
• 5-layer compositing primary video output, with integrated scaling and video
improvement processing, supporting up to 81 Mpix/sec output (up to 1920x1080
60I or 1280 x 720 60P displays)
• 2-layer compositing secondary video output, supporting up to dual rate SD (60P
or 100i)
• Integrated PAL/NTSC Digital Video Encoder for secondary output, with Y/C or
CVBS output (single rate SD only)
• Integrated video Temporal Noise Reduction
• Integrated video measurement and histogram correction unit
• Simultaneous decode of multiple AC-3, AAC, MPEG2 L1 or L2, MP3 or similar
audio streams (media processor)
• The external memory will serve as audio delay lines for audio and video
synchronization purpose
• Dual stereo digital audio in and dual S/PDIF (Dolby Digital™) input
• Two octal channel digital audio output plus S/PDIF (Dolby Digital™) output
• High performance 2D drawing engine (line drawing, bitblt)
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Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• Integrated DDR SDRAM controller, 32-bit wide up to 2x225 MHz, supporting 16,
32, 64 and 128-MB unified memory configurations
• 4 programmable memory ranges that can be set as ‘sandboxes’, where each
system DMA agent can be assigned to only play in such a sandbox
• Programmable access rights for device control/status registers to prevent system
corruption or reading of confidential data by non-trusted masters
• Non-trusted masters include external CPU through PCI, and the TM-3260
processors.
• 32-bit, 33 MHz PCI 2.2 expansion bus interface
• Support for 8 and 16 bit ROM or Flash (NAND and NOR)
• 2x UART, 4xI2C (two I2C with multi master (400 KHz), and two I2C with DMA (3.4
MHz)), 2-port USB 1.1 host interface
• 4 system timers/counters, capable of counting internal and external events
• An integrated universal Remote Control receiver
• 16 dedicated General Purpose I/O pins, suitable as software I/O pins, external
interrupt pins, universal Remote Control Blaster, clock source/gate for system
event timers/counters and emulating high-speed serial protocols
• 45 additional multiplexed General Purpose I/O pins
• MemoryStick™ and MultiMediaCard™ interface capability (using GPIO pins)
• On-chip MPEG1 and MPEG2 VLD to facilitate transrating, transcoding and
software SD MPEG decoding
• Integrated low-speed IDE controller (shares PCI pins, requires 2 external buffers
to isolate)
• All video/audio timing derived from a single low-cost external crystal (no VCXOs
required)
4. Compatibility with the PNX8525
With some exceptions listed below, the PNX8550 is a functional superset of the
PNX8525 and, at the system level, is backwards compatible with the PNX8525.
Applications for the PNX8525 can be ported to the PNX8550.
The list below identifies the main functional backwards compatibility issues between
the two products:
• The PNX8550 has no on-chip 1394 or SSI interface.
• The PNX8550 has two MPEG system processors, versus three on the PNX8525.
• The PNX8550 does not have the third in or out serial audio port of the PNX8525.
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Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• The PNX8550 PR4450 CPU requires recompiling due to Instruction Set
architecture changes from the MIPSII-compliant PR3940 on the PNX8525 to the
new MIPS32 architecture-compliant PR4450 on the PNX8550. In addition, the
TLB has changed to become MIPS32-compliant, requiring source code changes
to memory management routines.
• The PNX8550 TM3260 CPUs are backwards binary compatible with the TM3218
CPU on the PNX8525, but recompiling allows higher performance due to
additional computational units
• MMIO addresses, and MMIO register layout are not identical - this is typically
hidden behind APIs
• The PNX8550 uses a different package, with similar (but not identical) pin
placement e.g., the PNX8525 used SDRAM while the PNX8550 uses DDR
memories.
• Everywhere else, the PNX8550 capabilities equal or exceed those of the
PNX8525
5. Analog/Digital Standard Definition Video Improvement Capabilities
5.1 Temporal-Spatial Improvement Processing
The media processors together with the advanced de-interlacer in Memory Based
Scaler block of the PNX8550, can provide sophisticated temporal-spatial video
improvement processing on either external analog sources or internally decoded
MPEG2 sources. There is sufficient media processor capability and system memory
bandwidth to perform Sony’s Digital Reality Creation™ or Philips Consumer
Electronics’ Digital Natural Motion™’ on a Standard Definition signal, decode 2
MPEG video sources and associated audio, drive a wide-XGA class progressive
screen and do discretionary additional processing.
In a dual tuner system, temporal-spatial video improvement processing can be
performed on the main (large) image, or on two half-resolution images, as shown in
Figure 3
Main Image
Program 1
PIP
Program 2
.
not improved
Program 1
improved, but at
half-resolution
Program 2
improved
Figure 3: TV Modes and Video Improvement Processing
The discretionary processing margin allows future features above and beyond those
of hardware implementations of these video improvement algorithms. For example,
an intelligent detection of regions of the screen with different type of video content
can be applied, performing different types of improvement processing depending on
the content.
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Preliminary data Rev. 02 — July 21 2004 1-7
Page 23
Philips Semiconductors
The external video improvement processor interface optionally allows running one
temporal-spatial video improved video stream through a proprietary external video
improvement device, and back directly into the PNX8550 primary video output.
5.2 Temporal Noise Reduction
Temporal Noise Reduction is typically applied only to analog sources, but can be
applied to any video stream in the system. The PNX8550 QTNR processor block
performs temporal noise reduction by reading two video fields from memory and
writing a filtered output image to memory.
6. HD Decode and Display Capabilities
One PNX8550 supports single stream HD decoding and HD display. It supports
screens of 1920x1080i or ‘wide XGA’ style progressive screens.
In HD-HD mode, all video improvement processing is available, but non motioncompensated de-interlacing is used instead of temporal-spatial processing.
PNX8550
Chapter 1: Functional specification
Table 1
below shows the key video algorithms involved in converting the ATSC
transmission to the selected display type. Display resolutions smaller than those
indicated in the table are also supported. Progressive screens larger than 1280x720
are not supported.
Table 1: HD - HD Algorithms of the PNX8550
Transmission Display Algorithm Used
1920 x 1080i 960H * 1080V 60 Hz I H downscaling
1920 x 1080i 1920H * 1080V 60 Hz I n/a
1920 x 1080i 1280H x 720V 60 Hz P
(mode 1)
1920 x 1080i 1280H x 720V 60 Hz P
(mode 2, highest quality)
1280 x 720 60 Hz P 1280H x 720V 60 Hz P n/a
1280 x 720 60 Hz P 960H x 1080V 60 Hz I Each 1280x720 frame gets scaled to a
1280 x 720 60 Hz P 1920H x 1080V 60 Hz I Each 1280x720 frame gets scaled to a
Each 1920x540 field is scaled to a 1280 x
720 frame, losing some vertical resolution.
Film detector active.
• In film mode, the telecine is undone to
create the original progressive film
images.
• In video mode, median filtering plus
slanted edge detection/reconstruction
are applied to each field pair to construct
a full resolution 1920 x 1080 frame and
then scale it back to 1280 x 720P.
960x540 field at vertically correct position.
1920x540 field at vertically correct position.
All applications use high-definition video display in order to show the maximum
performance capability of the PNX8550. The standard definition video processing
includes the software based digital natural motion application. The PNX8550
converts the standard definition video to the high-definition video using the
combination of natural motion software and the memory based scaler hardware. The
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Preliminary data Rev. 02 — July 21 2004 1-8
Page 24
Philips Semiconductors
software natural motion requires an external device to perform the back-end of the
natural motion application. The following quality tradeoffs may be made in order to
manage the memory bandwidth requirements for more than one video processing
using the 225MHz DDR-SDRAM memory.
Using a higher speed grade DDR creates additional discretionary bandwidth for more
discretionary features.
PNX8550
Chapter 1: Functional specification
• Using a lower number of bits per pixel for the video and graphics layers
• Using a lower number of pixels per line for graphics layers
• Using YUV420 instead of YUV422 for the memory based scaler processing
• Generating PIP picture from SD VCR output if possible
• Generating PIP and VCR output from same HD video stream adds more memory
bandwidth when compared with generating VCR output from HD and PIP from
VCR output.
• Reduced natural motion quality or no natural motion if one of the video input is
high-definition bit stream or video
6.1 Dual HD Decode/Display Using Two PNX8550s
32 MB
225 MHz DDR
program 1 (TS)
program 2 (TS)
Figure 4: Dual HD Decode/Display Application
DV1
DV3
decode program1 HD
scale to 0.5 HD
all audio processing
DV_OUT1
(75 MHz 8 bit)
Figure 4 shows two PNX8550-performing dual-HD decode/displays. The first
PNX8550 decodes program 1, scales it to one-half horizontal resolution and outputs
the images across the primary output in 10-bit 656 mode. This program 1 image will
be used as the PIP image or side-by-side half resolution image. The second
PNX8550 decodes program 2 at HD resolution for use as the main image in case of
PIP, or the half horizontal image in case of a side-by-side display.
The second PNX8550 scales program 1 and 2 as needed and runs the OS. Locally
drawn graphics and both programs are composited as needed for the primary display.
Either program 1 or 2, with optional overlay graphics is sent to the VCR. The first
PNX8550 also performs all audio and discretionary media processing, since it has the
higher bandwidth margin.
program1
0.5 HD
32 MB
225 MHz DDR
DV1
decode program2 HD
run OS, draw graphics
DV3
composite all
PIP or side-by-side
program 1 + 2
full HD
QVCP5L_OUT
QVCP2L_OUT
program 1 or 2
SD for VCR
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Preliminary data Rev. 02 — July 21 2004 1-9
Page 25
Philips Semiconductors
This same configuration can also be used as a superior quality dual SD TV. In that
case, the first PNX8550 performs temporal/spatial improvement processing on
program 1 (656 or MPEG source), and forwards it in 2, 3 or 4x pixel rate to the
second PNX8550. The second PNX8550 can perform additional SD to HD 2D local
improvement processing on program1, while decoding or receiving PIP program2
and compositing all results.
PNX8550
Chapter 1: Functional specification
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Preliminary data Rev. 02 — July 21 2004 1-10
Page 26
Philips Semiconductors
7. Internal Functional Overview
2x225 MHz, 32-bit wide DDR
PNX8550
Chapter 1: Functional specification
Optional external coprocessors
including video enhancement chip
DV1 656/TS
DV2* 656/TS
DV3 656/TS
I2S audio*
SPDIF audio
UART1-2*
Remote Control
Gen. Purpose I/O
USB host i/f (2 port)
Smartcard1-2*
I2C (4x)
PNX8550
656
656
TS
ts & 656 router
TS
16
VIP1
VIP2
MSP1
MSP2
AI1-2
SPDI 1-2
misc. I/O,
timers/
counters,
semaphores
MMI
Peak rate: 12bit/cycle each way
Tunnel
MBS2
V Peaking
QVCP1
QVCP2
AO1-2
SPDO
TSDMA
MBS
VMPG
(1 HD or 2 SD)
656/HD/VGA
30
10
DENC
8 ch + 8 ch
QTNR
VLD2
QVCP5L_OUT
QVCP2L_OUT*
656
analog Y/C,cvbs
TS_OUT*
I2S audio*
SPDIF audio
27 MHz
xtal
boot, reset, clock
DE (2D)
DVD-CSS
JTAG
2xTM3260 Media Processor
5 issue, 240 MHz
64 kB I$
16 kB 2-port D$
128 32-bit regs
bound. scan
TM-DBG (2x)
PCI
E-DMA
PR4450 MIPS CPU
250 MHz
16 kB I$
16 kB D$
MMU
EJTAG debug
33 MHz, 32-bit PCI 2.2
(includes NAND/nor flash, IDE drive and 68k peripheral capability)
* I/Os marked with * can also function as General Purpose I/O pins if not used for a primary function.
Figure 5: PNX8550 Functional Block Diagram
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Philips Semiconductors
8. Internal Functional Overview
8.1 Overview of Function Partitioning
The functionality achieved within the PNX8550 can be divided into four major
categories: control, decode, processing, and display. The audio, video and graphics
processing are controlled by the PR4450 and the TM3260-based control software.
Decode functions take input data streams and convert those streams into memory
based structures that the PNX8550 may further process. Decode functions may be
simple, as in the case of storing 656 input video into memory, or substantially more
complex, as in the case of MPEG2.
Processing functions are those that modify an existing data structure and prepare
that structure for display functions.
Display functions take the processed data structures from memory and generate the
appropriate output stream. As in the case of the decode functions, display functions
can be relatively simple, such as an I2S audio output or very complex, as in the case
of multi-surface composited displays.
PNX8550
Chapter 1: Functional specification
All decoded data structures are stored in memory, even when further processing is
not required. This mechanism implies that there is no direct path between input and
output data streams. The memory serves as the buffer to de-couple input and output
data streams. Based on the mode of operation, there may be multiple data structures
in memory for a given input stream. The PNX8550 uses the TM3260 CPUs and a
timestamping mechanism to determine when a specific memory data structure is to
be displayed.
The PNX8550 implements the required decode, processing, and display functions
with a combination of fixed function hardware and TM3260 CPU software modules.
The PR4450 MIPS processor is not intended to be involved with the three primary
function types other than to control them. The PNX8550 provides a good balance
between those functions that are implemented in fixed hardware and those that are
programmed to run on a TM3260 CPU.
Table 2
illustrates how the major tasks are implemented under each of the main
functional areas, and how they map to hardware resources or software.
Table 2: Partitioning of Functions to Resources
Function Resource Description
Video Decoding/Acquisition
Digital video acquisition VIP Includes optional h-scaling or color space conversion, and
conversion to a variety of memory pixel formats.
Conditional access, PID filtering, section
filtering, transport stream demux
En/decryption for copy protection MSP
MPEG2 HD or 2SD video decoding Software +
MPEG2 audio decoding Software
MSP MSP output streams separate video and audio elementary
streams into memory.
DES (triple and single, each in EBC or CBC)
EDMA
VMPG
AES en/decryption
Media processor software performs parsing of the video
elementary stream up to slice level. VMPG hardware block
performs decoding below slice level.
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PNX8550
Chapter 1: Functional specification
Table 2: Partitioning of Functions to Resources
Function Resource Description
DVD authentication and de-scrambling DVD-CSS Authentication and de-scrambling in hardware
Program stream demux Software
Single program transport stream demux Software or
MSP
HD JPEG decode Software
MPEG4 video decoding Software
Audio Decoding and Improvement Processing
Audio decoding AC3, AAC, MPEG L1,
L2, MP3, others
Audio processing Software Improvement processing and mixing
Graphics
2D graphics rendering and DMA 2D DE
Video Improvement Processing
Non-motion compensated de-interlacing MBS Median, 2-field majority select, 3-field majority select with or
Motion compensated de-interlacing Software +
Motion estimation Software Pixel accurate and quarter pixel accurate versions available
Temporal up conversion
(Natural Motion)
Luminance histogram measurement,
other key video measurements
Temporal noise reduction QTNR QTNR can perform temporal noise reduction on one or more
Image scaling VIP, MBS
Video format conversions, including
color space conversion
Histogram correction, black stretch,
luminance sharpening (LTI, CDS, HDP),
Digital Color Transient Improvement,
color features (green enhancement, skin
tone correction, blue stretch)
Proprietary video improvement
processing
Software Decoders for almost any audio format available
MBS
Software Creates images temporally between two originals using motion
QTNR or MBS QTNR can do any video measurement during temporal noise
QVCP
MBS, VIP,
QVCP
QVCP Performed during output to display
An external
chip connected
to the tunnel
Interface
…Continued
Software if no conditional access or section filtering, else MSP
without EDDI postpass for edge improvement
Software provides the MBS with a motion compensated field, to
which the MBS applies the chosen de-interlacing algorithm.
vectors.
reduction on analog sources, or by reading an image from
memory without producing an output. MBS can performs video
measurement during a de-interlace or scaling pass.
streams.
VIP can perform horizontal downscaling during acquisition.
MBS and MBS2 can perform up-and downscaling horizontal and
vertical in a single pass, optionally combined with format
conversions. The MBS can also perform de-interlacing.
QVCP can perform panoramic horizontal scaling during output.
MBS can convert any pixel format to any other format. VIP can
generate multiple video formats, QVCP can read multiple video
formats.
External video enhancement chip serves as a coprocessor to
the PNX8850 and reads the required data from the PNX8850
memory and writes the enhanced video pixel data to the
PNX8850 memory. The video pixel data returned from the
external chip can be either 8-bit or10-bit semi planar YUV422.
The PNX8850 CPUs will have access to the external chip
control and status registers through the tunnel interface.
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PNX8550
Chapter 1: Functional specification
Table 2: Partitioning of Functions to Resources
Function Resource Description
Display Processing
Input Color Look-Up 2x CLUT A CLUT may be switched into the data path for each of the 5
Surface composition with alpha
blending, chroma (range) keying
Video and graphics scaling QVCP Hi-quality panoramic horizontal scaler for video, linear
Final gamma correction
contrast, brightness, white point control
Discretionary Processing
MPEG4 video encoding Software
MPEG4 Simple or Advanced Simple
Profile decoding
H.26L video decoding Software
MPEG2 video encoding Software 1/2 D1 and other versions available
Transrating VLD +
DV decoding Software Full quality decoder available
Transcoding VMPG +
Video Conferencing.... A large variety of applications is available.
QVCP
QVCP Final gamma correction after compositing
Software
Software
Software
…Continued
QVCP layers.
interpolator for graphics
The VLD hardware can be used to parse a MPEG2 video
stream. Software composes a new MPEG2 stream including the
video stream with a reduced bit rate.
Transcoding from MPEG2 uses VMPG for decoding.
Transcoding from other standards use a software decoder.
Software performs the encode.
9. Integrated Processors
9.1 PR4450 General Purpose Processor
The PR4450 is a MIPS32 compatible general purpose CPU. It is intended for running
the demand-paged, graphics intensive operating system and user-interface, whereas
the TM3260 media processors are intended to run all real-time audio and video tasks.
The 250 MHz PR4450 processor implements a very low cost, low power and high
performance 32-bit processor ideal to be used in information appliances running
embedded operating systems such as VxWorks, or Linux.
PR4450 supports both the MIPS32 and MIPS16 instruction set architecture as
defined by MIPS Technologies Inc. MIPS16 encodes the instructions in 16-bits,
enabling a substantial reduction in the memory foot print requirements and thereby
reducing the overall system cost. The PR4450 requires re-compilation of PNX8525
source code, due to the ISA changes going from MIPS-II to MIPS32.
The PR4450 delivers 1.22 MIPS/MHz (Dhrystone 2.1) for a total of 325 MIPS. It has
an estimated power consumption of less than 1mW/Mhz which makes it an ideal core
for use in next generation information appliance system-on-silicon architectures.
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PNX8550
Chapter 1: Functional specification
Table 3: PR4450 MIPS Core Feature Summary
Feature Description
MIPS32 and MIPS16 ISA
16 kB 2-way set
associative I-Cache
Cache policies 16 kB 4-way set associative D-Cache
Line size Critical word first refill, write-back or write-through, write-allocate
MMU 32 bytes (both I-Cache and D-Cache)
Multiplier 64-entry (32 odd/even pairs) with page sizes from 4 kB to 16 MB
Debug Supports 1-cycle 32-bit multiplies and multiply-accumulate, multiply-subtract.
MIPS32 Instructions Standard built-in MIPS EJTAG 2.5 software debug support, including single step support, hardware
Register File MIPS32 adds conditional move, load-linked and store-conditional (for semaphore support), count
Pipeline 32 entry 32-bit register file for MIPS32, 11 of which are available for MIPS16 instructions
Branch Prediction Synchronous 8-stage pipeline with full hardware interlock support for data dependencies
Multiplication Dynamic branch prediction with a 4096-entry branch history table and a 256-entry branch address
MMU MAD (Multiply-Accumulate-Divide) unit with 64-bit accumulator, executing 32-bit multiply
Timers 4 GB address space support
Caches
breakpoints for instruction and data addresses and/or data value
leading zeros and ones and multiply-subtract instructions to the existing MIPS-II ISA.
cache for optimal performance
instructions with 1 cycle repetition rate
Separate user and kernel modes and TLB ASIDs (Address Space Identifiers) provide full memory
protection support.
Three 32-bit timers are provided in coprocessor zero. These timers can also be used as event
counters for performance analysis. One of the counters can also operate as a watchdog timer.
9.2 Dual TM3260 VLIW Media Processors
The two TM3260 CPUs in the PNX8550 are a version of the TriMedia 32-bit VLIW
media processor. Each processor is a 240 MHz, 5 instructions per clock cycle, Very
Long Instruction Word (VLIW) processor, with an extensive set of multimedia
instructions. It implements a superset of the TriMedia TM1300 instruction set, and
has a superset of the TM1300 functional units. It is fully binary backwards compatible
with the TM32 CPU on the PNX8525, but has a larger Instruction Cache for improved
performance. In addition, recompiling of source code results in higher media
performance due to several additional functional units.
The TM3260 supports 32-bit integer and IEEE-compatible 32-bit floating point data
formats. It also provides a Single Instruction Multiple Data (SIMD) style operation set
for operating on dual 16-bit or quad 8-bit packed data. It has a peak floating point
compute capacity of 1.1 G operations/s, and has 880 M multiply-add/s capability on
16-bit data. Its dual access 16 kB 8-way set-associative data cache provides a CPU
local data bandwidth of 1.8 GB/s. Its 64 kB 8-way set-associative instruction cache
provides 224 bits of instructions every clock cycle, for an instruction rate of 6.2 GB/s.
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In the PNX8550 HD operating mode, the TM3260s are responsible for dual audio
decode, control of the HL MPEG2 decoder and running a film-detector. Significant
processor capacity is leftover, and available for discretionary functions, such as a
software MPEG2 or MPEG4 decode, etc. subject only to memory bandwidth and
CPU cycle availability. In SD operating mode, the two TM3260s are responsible for all
temporal-spatial video improvement processing.
The TM3260s have sufficient compute performance to deal with a variety of future
operating modes. The processor by itself can decode most compressed video
streams and associated audio at full frame rate, such as decoding a DV camcorder
image stream arriving over 1394. One processor is also capable of doing all audio
and video compression, decompression and processing necessary for bi-directional
video conferencing.
The TM3260s are responsible for all media processing and real-time processing
functions within the PNX8550. They run a small real-time operating system (pSos),
which allows them to respond efficiently and predictably to real-time events. In some
cases, a TM3260 will handle a media processing function in conjunction with fixed
hardware, such as the HL MPEG2 decoder. Each TM3260 executes code from the
unified system DRAM memory.
PNX8550
Chapter 1: Functional specification
The TM3260 is capable of operating in little or big-endian mode. The mode is chosen
at compilation time. The compiled binary program startup code sets the mode shortly
after CPU startup by setting the endian bit in the Program Control Status Word
(PCSW). Note that the system architecture of the PNX8550 requires that the MIPS
and TriMedia cores all operate in the same endian mode after startup.
Debug of software running on a TM3260 is performed using an interactive source
debugger on a PC. The PC talks to the TM3260 through the PNX8550 EJTAG pins,
using the system level EJTAG2.0 controller. Two TM_DBG JTAG modules on the
JTAG/boundary scan port provide an improved version of the TM1300 JTAG debug
port for legacy debug applications.
9.2.1 Prefetch
The TM3260 is capability to prefetch the required data and instructions in hardware.
The hardware prefetch works in the background. This feature can be turned off by
resetting the prefetch bits in the global registers.
Table 4: TM3260 VLIW CPU Feature Summary
Feature Description
ISA TM1300 ISA extended with 22 new instructions, with 32-bit RISC style load/store/compute instruction
set and an extensive set of 8, 16-bit SIMD multimedia instructions.
Instruction issue 5 RISC or SIMD instructions every clock cycle
Data types Boolean, 8/16/32 bit signed and unsigned integer, 32 bit IEEE floats
Functional units 5 CONST, 5 Integer ALUs, 5 multi-bit SHIFTERs, 3 DSPALUs, 2 DSPMUL, 2 IFMUL, 2 FALU, 1
FCOMP, 1 FTOUGH (divide, sqrt) 3 BRANCH, 2 LD/ST
Caches 64 kB 8-way set associative I-Cache
16 kB 8-way set associative dual-ported D-Cache
Cache policies Critical word first refill, write-back, write-allocate, automatic heuristic hardware prefetch
Line size 64 bytes (both I-Cache and D-Cache)
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PNX8550
Chapter 1: Functional specification
Table 4: TM3260 VLIW CPU Feature Summary …Continued
Feature Description
MMU None, virtual = physical, full 4 GB space supported
Protection Base, limit style protection, where CPU can be set to only use part of system DRAM, and hardware
ensures no references take place outside this range.
Multipliers Up to 2 32x32 bit integer multiplies per clock
Up to 2 32 bit IEEE floating point multiplies per clock
Up to 4 16x16 multiply-adds per clock
Up to 8 8x8 multiplies per clock
Debug JTAG based software debugger, including hardware breakpoints for instruction and data addresses
Register file 128 entry 32-bit register file
Interrupts 64 auto-vectoring interrupts, with 8 programmable priority levels
Timers Four 32-bit timers/counters are provided. A wide selection of sources allows them to be used for
performance analysis, real-time interrupt generation and/or system event counting
System interface The TM3260 runs fully asynchronous from system DRAM, and can operate at a frequency lower than
system DRAM to save power, or higher than system DRAM to gain performance
Software
development
environment
Application software
architecture
The TM3260 is supported by the C/C++ compiler tools available for the TM1300 family
Applications use the TSSA, TriMedia Streaming Software Architecture, allowing modular
development of audio, video processing functions.
10. Digital Video/Transport Stream Inputs
10.1 Backwards Compatibility
The PNX8550 digital video/transport stream router and associated PNX8550 input
and output pins are a superset of the PNX8525 (Viper1). Any board/application
designed for PNX8525 can be ported to the PNX8550, except:
• Applications using the PNX8525 on-chip 1394 will require an external 1394 link
IC.
• Applications that require simultaneous use of 3 MSP Conditional Access Units on
input streams are not supported (each of the two MSPs can do 1 input stream + 1
memory stream).
• Applications that create a partial transport stream inside a MSP and route this to
TSOUT are not supported (established practice in the PNX8525 is to first go to
memory and create the partial transport stream in software - this is still supported
in the PNX8550).
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10.2 New Features
New video/transport stream router features introduced with the PNX8550 are:
PNX8550
Chapter 1: Functional specification
• Any of the DV1, DV2 or DV3 input pins can carry either a 656 Digital Video
Stream, a single parallel transport stream, or 2 serial transport streams.
• Pins from DV1/DV2 can be combined to provide a 20 bit Y,UV high-speed input
capable of receiving HD/VGA resolution YUV 4:2:2 video up to 81 Mpix/sec.
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11. MPEG2 Decoding
PNX8550
Chapter 1: Functional specification
TSIO Block
DV1
DV2
DV3
TS_OUT
DV1
TS_OUT Block
Interface Blocks
serial_to_parallel
conversion
serial_to_parallel
conversion
serial_to_parallel
conversion
TSIN11
TSIN12
TSIN21
TSIN22
TSIN31
TSIN32
*Routing not shown
Video Input Router Block
TSIN1x
TSIN2x
TSIN3x
TSDMA
TSIN1x
TSIN2x
TSIN3x
TSDMA
TSDMA Block
MSP1: de-scrambler
& transport demux
MSP2: de-scrambler
& transport demux
Ch A
Ch B
VIP1
HD capable
video input
DV2
DV3
Ch A
VIP2
video input
Ch B
Figure 6: Transport Stream Network and VIP Input Routing Block Diagram
11.1 MPEG System Processor (MSP)
Each MSP block performs PID filtering, packet arrival time-stamping, de-scrambling,
de-multiplexing and section-filtering on up to two transport streams simultaneous,
one from its streaming input (see Figure 6
from system memory. The MSP outputs de-multiplexed Elementary Stream data to
system memory.
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) and one lower-bandwidth transport stream
Page 35
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The streaming input typically carries a multi-program transport stream coming from
an external channel decoder through the DV1, DV2 or DV3 pins. The memory
transport stream capability is present to deal with encrypted transport streams
originating from elsewhere in the system, such as coming in over a TCP/IP
connection, or from a time shift hard-disk attached to a PCI-IDE controller or to the
network.
Internal de-scramblers are provided for both selected transport streams. Transport
streams may be passed through external POD (Point of deployment) or CI (Common
Interface) conditional access modules before being delivered to PNX8550. This
requires an external POD/CI interface chip, such as a CIMaX or similar.
The MSP blocks contains DVB, Multi2 (M2) and DES de-scramblers. These functions
are mutually exclusive - each MSP can only perform one de-scrambling type at a
time, but the two MSPs are independent and may simultaneously perform different
de-scramblers.
The MSPs each provide hardware support for:
PNX8550
Chapter 1: Functional specification
• DVB or DSS packet framing
• 64 PID filter
• 64 section filters each of 16 bytes (12 bytes if section filter information is split
across packets)
• Smaller width section filters are implemented by bit masking
• 4 PTS/DTS range filters
• De-multiplexing of Section or PES data to 96 output queues in the main unified
memory
The MSPs on the PNX8550 are a functional superset of the MSPs on the PNX8525,
providing dual-stream (1 live, 1 from memory) processing capability. They are not
backwards compatible.
Additional changes:
• Output queues increased from 48 to 96
• Programmable queue lock feature for the Memory Queue Manager
• Two small queue sizes have been changed to 2 MB and 4 MB to accommodate
HD program processing.
Note that de-multiplexing of a clear text Single Program Transport Stream is best
done in software on the TM3260s, and doesn’t require use of an MSP.
11.2 DVD Decoding
The DVD-CSS block is provided to allow integrated DVD playback capability. It
provides authentication and de-scrambling for DVDs.
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A DVD drive is attached to the integrated medium-bandwidth IDE controller, and
provides its data either across the IDE interface, an external PCI-IDE bridge chip or
across a multi-bit serial interface to GPIO. The resulting system memory scrambled
program stream is de-scrambled by invoking a memory-to-memory operation on the
DVD-CSS block. The clear text program stream is then de-multiplexed by software on
the TM3260s.
11.3 Software Processing of MPEG2 Streams
The TM3260s process the audio, video, and other Elementary Stream data types
output by an MSP or by a software program or transport stream demux.
Video Elementary Streams are parsed by software on a TM3260, which then sets up
the VMPG MPEG-2 decoder to decode at field/frame-level or for a given number of
macroblocks.
Audio Elementary Streams are parsed and decoded by a TM3260.
Other Elementary Stream types are processed by the TM3260 or MIPS CPU
depending on the real-time nature of the content and the application.
PNX8550
Chapter 1: Functional specification
Software on a TM3260 also performs clock recovery based on the transport stream
packet arrival timestamps.
11.4 VMPG - MPEG2 Decoder and VLD2
The PNX8550 contains a hardware high-level MPEG2 video decoder, VMPG. VMPG
parses and decodes a given number of macroblocks or entire field/frame. One HD
MPEG2 stream (MP@HL) in any of the 18 ATSC formats can be decoded.
Alternately, two SD MPEG2 streams (MP@ML) may be processed simultaneously.
The amount of MPEG2 processing is limited only by allocated system memory
bandwidth or by macro block processing time, which depends on the MPEG2
decoder clock rate.
VMPG provides a VLD only mode. In this mode, it outputs Run Length Pairs and
Motion Vectors of a slice to system memory, but the slice is not decoded to pixels.
This mode can be used for software processing on MPEG2 tokens, such as
transrating to a lower bit rate MPEG2 stream, or partial decoding and transcoding to
other video formats. In most cases, the VLD2 block on the PNX8550 can be used
instead, which provides the same capability without using up valuable VMPG clock
cycles.
The PNX8550 VMPG is compatible with the VMPG on the PNX8525 including the 0.5
horizontal resolution decode mode.
Second VLD Block (VLD2)
The VLD2 block performs variable length decoding by fetching the bitstream from the
external memory and outputs a stream of decoded macroblock headers and a stream
of run-level pairs to the external memory. The VLD2 block supports processing of
multiple streams. The multiple processing is controlled by the software.
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12. Image Processing Hardware
12.1 Pixel Formats
The on-chip hardware image processing blocks all use the same ‘native’ pixel
formats, as shown in Tab l e 5
can be read by another block.
• A limited number of native pixel formats are supported by all image subsystems,
as appropriate.
• The Memory Based Scaler supports conversion from arbitrary pixel formats to
any native format, during the anti-flicker filtering operation (this operation is
usually required on graphics images anyway, hence no extra passes are
introduced).
• Hardware subsystems support all native pixel formats in both little-endian and
big-endian system operation.
PNX8550
Chapter 1: Functional specification
. This ensures that image data produced by one block
• Software always sees the same component layout for a native pixel format unit,
whether it is running in little-endian or big-endian mode i.e., for a given native
format R, G, B (or Y,U,V) and alpha are always in the same place.
• Software (on the TM3260) can be written endian-mode independent, even when
doing SIMD style vectorized computations
The native formats of the PNX8550 include the most common indexed, packed RGB,
packed YUV and planar YUV formats used by Microsoft DirectX and Apple
Quicktime, with 100% bit layout compatibility in little and big-endian modes of
operation, respectively. This allows for easy porting of mainstream PC and Apple
software applications that create graphics or images.
TM3260 software image processing stages and encoders/decoders typically use
semi-planar or planar 4:2:0 or 4:2:2 formats as input and output.
.
Table 5: Native Pixel Format Summary
VIP
Name Note
1 bpp indexed CLUT entry = 24-bit color +
2 bpp indexed x x
4 bpp indexed x x
8 bpp indexed x x x
RGBa 4444 16-bit unit, containing one
RGBa 4534 (1) xxx x
RGB 565 16-bit unit, containing one
RGBa 8888 32-bit unit, containing one
8-bit alpha
pixel with alpha
pixel, no alpha
pixel with alpha
Out QTNR
(1) xxx x
(1) xxx x
(1) xxx x
MBS, MBS2
In Out
xx
2D Draw
Engine (2)
QVCP InVPK (3)
In/Out
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PNX8550
Chapter 1: Functional specification
Table 5: Native Pixel Format Summary …Continued
VIP
Name Note
packed YUVa 4:4:4 32-bit unit containing one
pixel with alpha
packed YUV 4:2:2 (UYVY) 16-bit unit, two successive
packed YUV 4:2:2 (YUY2,
2vuy)
planar YUV 4:2:2 Three arrays, one for each
semi-planar YUV 4:2:2 Two arrays, one with all Ys,
planar YUV 4:2:0 Three arrays, one for each
semi-planar YUV 4:2:0 Two arrays, one with all Ys,
semi-planar YUV 4:2:0
10-bit/pixel component
or
semi-planar YUV 4:2:2
10-bit/pixel component
Packed YUV 4:2:2
10-bit/pixel component
(1) The VIP RGB output is mutually exclusive with horizontal scaling.
(2) Shown are the 2D engine frame buffer formats where drawing, RasterOps and alpha-blending of surfaces can be
accelerated. Additionally, the 2D Drawing Engine host port supports 1 bpp monochrome font/pattern data, and 4 and 8-bit
alpha only data for host-initiated anti-aliased drawings.
(3) VPK = Vertical Peaking
units contain two horizontally
adjacent pixels, no alpha
component
one with U and Vs
component
one with U and Vs
Two arrays, one with all Ys,
one with U and Vs
3Ys are packed in 4Bytes
3UV pair is packed in 8Bytes
6Ys, 3Us and 3Vs are
packed in 16bytes
Out QTNR
xxxxx
xx x x x x/x
xx x x x
xxx
xx x x x
xxx x
MBS, MBS2
In Out
xx
2D Draw
Engine (2)
QVCP InVPK (3)
In/Out
x
QVCP5L only
x (out)
x
QVCP5L only
x (out)
12.2 Video Input Processor (VIP)
The Video Input Processors (VIP) handle incoming digital video and processes it for
use by other components of the PNX8550. The VIP provides the following functions:
• Receives 10-bit YUV4:2:2 digital video data from the selected DVx video port.
The data is dithered down to in-memory 8-bit data format. The YUV4:2:2 data
stream typically comes from devices such as the SAA 711X, which digitize PAL or
NTSC analog video.
• Performs horizontal downscaling to any resolution or upscaling by 2x.
• The upscaling feature is not available in HD video capture mode.
• Store video data inside the video acquisition window in system memory in any of
the native pixel formats indicated in
convert the 10-bit input to the selected 8-bit format.
Ta bl e 5. Perform error feedback rounding to
• Provides an internal Test Pattern Generator with NTSC, PAL, and variable format
support.
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The PNX8550 VIPs are backwards compatible with the PNX8525 VIP, but provide
10-bit accurate input processing.
HD Video
PNX8550
Chapter 1: Functional specification
• Acquires VBI data using a separate acquisition window from the video acquisition
window.
• ANC header decoding or window mode for VBI data extraction
• Interrupt generation for VBI or video written to memory
• Pixel frequency up to 40.5MHz, 81MHz input clock (SD VIP)
• Pixel frequency up to 81 MHz, 81MHz input clock (HD VIP using 20-bit (Y,UV)
input mode)
• Color space conversion (mutual exclusive with horizontal scaling)
• Raw data mode capture of 8- or 10-bit data
The HD video resolution stream is captured using the VIP1 block. The maximum pixel
frequency is 81MHz. Both 16-bit and 20-bit YUV 422 formats are supported. Both
embedded sync and explicit sync (HREF, VEF and FREF) are supported in the HD
video capture mode.
12.3 Tunnel Interface
The tunnel interface is used to connect an external chip. One or more coprocessors
in the external chip will act as on-chip coprocessors. The coprocessors in the external
chip will have read/write access to the PNX8550 DDR-SDRAM memory. The
PNX8550 CPUs will have access to the external coprocessor’s control and status
registers. The coprocessor’s interrupt will signal will be connected to the PNX8550
through the GPIO signal.
The external device will read and write the required data including video data, motion
vector data and video measurement data.
The peak data transfer rate across the tunnel is about 267 MB/sec each way and the
usable DMA bandwidth in each way is about 210 MB/sec. This performance figure is
for the 200 MHz tunnel.
12.4 Quality Temporal Noise Reduction (QTNR) and Video
Measurement
The QTNR block has two primary functions:
• Temporal Noise Reduction: reading two video fields from memory, “current”
(noisy) and “previous” (noise reduced) and producing a noise reduced version of
“current” in memory
– The temporal noise reduction can be performed on one video stream and the
maximum pixel rate is limited to 100Mpixel/sec
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Performance
The QTNR block simultaneously processes the video stream for video measurement,
noise measurement and noise reduction. The noise measurement is limited to one
video stream as the QTNR block maintains the context internally. The noise reduction
and video measurement functions can be performed on one or more video streams in
time multiplexed at filed or frame level. All functions are performed at one pixel per
cycle and the maximum pixel rate is 100 Mpixel/sec.
PNX8550
Chapter 1: Functional specification
• While doing this, or as a separate “measurement only” pass, perform video
measurements:
– Gather a histogram of luminance values (this data is used by software to
control histogram modification)
– Measure noise level inside a rectangular window
– Measure the lowest level luminance within a rectangular window (used to
control black stretch in QVCP)
– Measure UV bandwidth inside a rectangular window
– Measure the position of top and bottom black bars in the image
12.5 Memory Based Scaler (MBS)
The PNX8550 contains a Memory Based Scaler that performs operation on images in
main memory. The MBS can either be controlled task by task by a TM3260, or it can
be given a list of de-interlacing and scaling tasks. It reads images from memory,
performs a transformation, and writes the result back in memory. The performance of
the MBS is typically limited only by the 125 M pixel/sec internal processing rate or by
the allocated main memory bandwidth. The usable pixel rate will be reduced from the
maximum pixel rate if required real time memory bandwidth is not allocated to the
MBS block.
The PNX8550 MBS can perform:
• De-interlacing using either a median, 2-field majority select, or 3-field majority
select algorithm with an edge detect/correct post-pass (these three provide
increasing quality, at expense of increased bandwidth).
• Edge detect/correct on an input frame that has been software de-interlaced (this
provides future capabilities in case we develop a better core de-interlacer than
3-field majority select).
• Horizontal and vertical scaling (on the input image or on the result of edge detect/
correct stage).
• Linear and non-linear aspect ratio conversion
• Anti-flicker filtering
• Conversions from any input pixel format to any non-indexed pixel format,
including conversions between 4:2:0, 4:2:2 and 4:4:4, indexed to true color
conversion, color expansion/compression, de-planarization/planarization (to
convert between planar and packed pixel formats, programmable color space
conversion.
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Supported video measurement functions during scaling or de-interlacing pass:
Note that not all combinations of format conversion with scaling are supported, refer
to Chapter 31MBS.
The video processing functions are based on 4 and 6-tap polyphase filters with up to
64 phases. Three 6-tap filter units are used for horizontal scaling/filtering while three
4-tap filter units are assigned to vertical scaling/filtering. For some video formats
(e.g., YUV 4:2:x) the three 4-tap filters can be combined to work as two 6-tap filters.
PNX8550
Chapter 1: Functional specification
• Gather a histogram of luminance values (this data is used by software to control
histogram modification).
• Measure noise level inside a rectangular window.
• Measure the lowest level luminance within a rectangular window (used to control
black stretch in QVCP).
• Measure UV bandwidth inside a rectangular window.
• Measure the position of top and bottom black bars in the image.
The PNX8550 MBS is backwards compatible with the MBS of the PNX8525, but
provides the following improvements:
• The majority select de-interlacer and edge detect/correct de-interlace post-pass
• Larger line buffers that allow HD size images to be processed in a single pass
• Performs noise and video measurement. (Refer to Section 12.4 for measurement
function details.)
– The QTNR uses the same noise and video measurement functions and no
noise reduction function in the MBS.
12.6 2D and DMA Engine
A 2D rendering and DMA engine is included in the PNX8550 to perform high-speed
graphics operations. Solid fills, three operand BitBlt, lines, and monochrome data
expansion are available. Supported drawing formats include 8, 16, and 32-bits/pixel.
Monochrome data can be color expanded to any supported pixel format. Anti-aliased
lines and fonts are supported via a 16 level alpha blend bitblt.
A full 256-level alpha bitblt is available to blend source and destination images
together. Drawing is supported to any byte aligned memory location and at any image
stride. This block is compatible with the PNX8525 2D DE graphics engine.
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.
PNX8550
Chapter 1: Functional specification
Figure 7: QVCP Block Diagram
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12.7 Quality Video Composition Processor (QVCP)
The PNX8550 contains two QVCPs, which are responsible for combining and
displaying video and graphics images from the main memory. The primary QVCP
serves as the main display pipeline, the second one is targeted to be connected to a
record device (VCR). The primary QVCP allows composition of up to 5 layers, and
can output in 656/HD/VGA format in 10 bits per component up to 81 Mpix/sec.
The secondary QVCP allows composition of up to 2 layers, can output in 656 10-bit/
component mode up to 81 MHz (40.5 Mpix/sec). The secondary QVCP is connected
to an on-chip Digital Video Encoder, allowing direct analog CVBS or S-Video output.
In analog output mode, standard definition interlaced NTSC or PAL are supported.
The primary and secondary QVCP each contain a series of layers and mixers. The
QVCP creates a series of display data layers (pixel streams) and mixes them logically
from back to front to create the composited output picture.
In order to achieve high quality video and graphics, the QVCP performs the following
tasks:
PNX8550
Chapter 1: Functional specification
• Fetching of the image surfaces from memory
• Per component table lookup, allowing de-indexing or gamma equalization
• Video Quality Enhancement (Luminance Transient Improvement, Color
Dependant Sharpening, Horizontal Dynamic Peaking, Histogram Modification,
Digital Color Transient Improvement, Black Stretch, Skin Tone Correction, Blue
Stretch and Green Enhancement)
• Video and Graphics horizontal upscaling
• Color space unification of all the display surfaces
• Contrast and Brightness Control
• Positioning of the various surfaces
• Merging of the image surfaces (alpha blending and pixel selection based on
chroma range keying)
• Gamma correction on the merged result
• Screen timing generation adopted to the connected display requirements (SD-TV
standards, HD-TV standards, progressive, interlaced formats)
Two layers in the primary QVCP support the semi-planar YUV formats, one layer in
the secondary QVCP supports semi-planar YUV formats. All other layers support only
indexed, RGB and packed YUV formats. QVCP does not support planar video
formats. The indexed format is limited to two layers in QVCP5L and one layer in
QVCP2L. See Tab l e 6
.
Each QVCP contains a number of identical processing layers, a pool of processing
resources that can be switched into a layer under application control, mixers and a
post-processing stage.
Refer to Figure 7
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for a block diagram that shows how these are interconnected.
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Philips Semiconductors
Each QVCP layer contains (in processing order):
Table 6: QVCP Pool Elements
Pool Element
CLUT: Color Look-up Table 2 sets 1
DCTI: Digital Color Transient Improvement 2 sets 0
HSRU: Horizontal Sample Rate Up-converter, allowing
panoramic up scaling
HIST: Histogram Correction Unit, including black stretch 2 sets 0
LSHR: Luminance Sharpening (LTI, CDS, HDP) 1 set 0
CFTR: Color Features (green enhance, skin tone correction,
blue stretch)
PNX8550
Chapter 1: Functional specification
• PFU - Pixel Fetch and Formatting Unit, performing color expansion, undithering
and alpha value extraction
• CKEY - Chroma Range Keying
• CUSP - Color Up-sampling
• LINT - Linear Interpolator for graphics scaling
• VCBM - Video Contrast/Brightness Matrix
• LCU/FCU - receiving later fetch coordinates and sending pixels to the mixer,
subject to clipping outside screen coordinates
• The QVCP pool elements are indicated in Tab le 6 below:
Number in
Primary
QVCP
2 sets 0
2 0
Number in
Secondary
QVCP
The mixer stage combines images from back to front, also allowing mixing in of a
fixed backdrop color. The mix can be controlled by chroma range keying. Mixing
modes include per-pixel alpha blending, and inverting colors. MIX operation can be
programmed by a set of raster operations (ROP). Mixing is performed either entirely
in the RGB domain or the YUV domain, depending on the output mode of operation
of the QVCP.
After mixing, post-processing optionally down samples 4:4:4 to 4:2:2 in CDNS, the
Chroma Down Sampler. Then, VBI insertion is performed (656 mode only), and the
output is formatted to one of the forms below.
• 24 or 30-bit full parallel RGB or YUV (primary QVCP only)
• 16 or 20-bit Y and U/V multiplexed data (primary QVCP only)
• 8 or 10-bit 656 (full D1, 4:2:2 YUV with embedded sync codes)
• 8 or 10-bit 4:4:4 format in 656-style with RGB or YUV
In each of the output modes, an optional H-sync, V-sync and blanking or odd/even
output can be enabled (primary QVCP only).
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Semi Planar YUV422/YUV420 10-Bit Support
The primary QVCP is capable of reading the Semiplanar YUV422 or YUV420 in a
10 bits-per-pixel component. This format is provided in the Ch 6 Pixel Formats
10-bit component is inserted before the pedestal removal block within the prefetch
unit (PFU). The 10-bit support was added to the original “9 bits+1” format. The
parameter setting for the 10-bit support will be described in the QVCP document.
12.8 Integrated Digital Video Encoder (DENC)
The secondary QVCP is connected to an on-chip Digital Video Encoder, allowing
direct analog video output. In analog output mode, standard definition interlaced
NTSC or PAL are supported.
The encoder has two DACs. DAC1 provides CVBS or luminance for S-Video. DAC2
provides chrominance for S-Video. Internal sensors allow software to test loading on
the S-Video chroma line to decide whether to output luma or CVBS on DAC1.
Two current type analog outputs provide Y/C or CVBS for driving a traditional
composite video output or an S-Video output to a VCR.
PNX8550
Chapter 1: Functional specification
. The
12.9 PNX8510/11 Analog Companion Chip
In cases where the PNX8550 primary QVCP is not driving a display-specific digital
output processor, the PNX8510/11 can optionally be used to provide primary channel
analog video and dual stereo analog audio.
The PNX8510/11 has the following features:
• NTCS, PAL or SECAM Standard Definition CVBS, Y/C or SCART output
• HDTV RGB and YPrPb Output with 10 bits-per-component resolution including
the generation of tri-level syncs for various standards (e.g., SMPTE 295M, 296M
and EIA 807)
• Two stereo audio output DACs
• Control over I2C or primary QVCP VBI
13. Audio Processing and Input/Output
13.1 Audio Processing
All audio processing in the PNX8550 is performed in software on the TM3260s. This
includes decoding of audio from compressed formats, sample rate conversion, mixing
and special effects processing. There is sufficient performance, if required, to
transcode received audio to multi-channel compressed audio sent over S/PDIF to an
attached receiver.
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13.2 Audio Inputs/Outputs
The PNX8550 supports two I2S stereo input ports. These ports are typically used in
association with the two analog video input streams. The I2S data is transferred via
DMA to the unified system memory. The stereo audio inputs support up to 32 bits/
sample at sample rates up to 96 kHz. An optional synthesized clock is available to
drive the A/D conversion process. If this clock is used, software can precisely control
the sampling rate and/or lock the audio sampling process to any time reference in the
system.
There are two dedicated 8-channel based I2S outputs. They can be used with
discrete high-quality, low-noise audio DACs, or they can be used in a dual stereo
configuration with the companion PNX8510/11 analog video/audio IC. The audio
outputs support up to 32 bits/sample at sample rates up to 96 kHz. The sampling
output rate is precisely controlled by software and can be locked to any time
reference in the system.
The PNX8550 supports a Sony Philips Digital Interface (SPDIF) output with IEC-1937
capabilities. Transmitted data is generated by the TM3260 software. This output port
can carry either stereo PCM samples from an internal audio mix, or one of the
originally received compressed audio programs including 5.1 channel AC-3, and
MPEG1 Layer1, 2 and 3. Transcoding of audio is possible, but is not included in the
normal system operation CPU and memory bandwidth compute budget. Sample rate
of transmitted audio is set by software, allowing perfect synchronization to any time
reference in the system.
PNX8550
Chapter 1: Functional specification
The PNX8550 supports two SPDIF inputs to connect to external sources, such as a
DVD player. The incoming data is timestamped and written to unified system
memory. Data interpretation and sample rate recovery is by software on the TM3260.
The audio data received can be in a variety of formats, such as stereo PCM data, 5.1
channel AC-3 data per IEC-1937 or other. Software decoded audio can be used for
mixing with other audio for output along one of the audio outputs. The sample rate is
determined by the SPDIF source, and can not be software controlled.
13.3 Audio Compatibility
The Audio outputs and SPDIF input/output are 100% compatible with the PNX8525.
The I2S Audio inputs have been upgraded to support 32-bits/sample audio. This has
been done in a backwards compatible manner, except that the 8 bits/sample mode of
the PNX8525 is no longer supported.
14. Miscellaneous Functions
14.1 Enhanced DMA Controller (EDMA)
The Enhanced DMA Controller supports memory-to-memory (move) transfers from
any byte location in the PNX8550 system memory DRAM to any other byte location in
the PNX8550 system memory DRAM. The DMA Controller has the following features:
• Support for 4 independent DMA channels
• Buffer Mode DMA with a 16-byte data buffer
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DMA Controller can compute DVB-compliant cyclic redundancy checksum (CRC)
during a move operation.
DMA Controller can perform AES encryption or decryption during a move operation.
14.2 Semaphores
The SEM block provides semaphores for mutual exclusion in a multi-processor
environment. It implements a total of 16 semaphores. Each processor in the system
can request a particular semaphore. Only one processor at a time can get the
semaphore.
There is no built-in mapping of semaphores to sharable hardware system resources.
Such mapping is by software convention.
PNX8550
Chapter 1: Functional specification
• Support for Scatter-Gather mode DMA
– Large blocks of contiguous data may be transferred to smaller buffer areas.
– Many small data buffers may be combined into a large buffer.
14.3 Inter-Processor Communication
The PNX8550 has hardware support for Inter-Processor Communication (IPC). The
top eight interrupts of the TM3260 are allocated for software generated interrupts.
Other processors can communicate to the TM3260 through the top eight interrupt
registers.
There is one IPC hardware block (MIPC). The MIPC block has eight software
controlled interrupt bits. The interrupt signal from the MIPC block is connected to the
MIPS. Another interrupt signal from the MIPC block is also connected to all GICs. A
processor can interrupt other processors by setting an interrupt bit in the target
processor’s IPC block. The target processor will service the interrupt and clear that
interrupt in its IPC block.
15. System Memory
15.1 System DRAM
The PNX8550 has an integrated DDR controller that supports 32-bit wide Dual Data
Rate (DDR) SDRAM memory at speeds up to 2x 225 MHz or PC2900 DDR SDRAM
(equivalent bandwidth to a 225 MHz 64-bit wide SDRAM). The memory interface can
support memory footprints of 16, 32, 64 or 128 MB.
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Table 7 lists the supported memory configurations:
Table 7: Memory Configurations for Memory Interface
Tot al
Memory
Size
16 MB 1 x32 128 Mbit
32
32
32 MB 2 x16 128 Mbit
64 MB 4 x16 128 Mbit Max. freq. may be limited due to dual ranks
64 MB 2 x32 256 Mbit Max. freq. may be limited due to dual ranks
64 MB 2 x16 256 Mbit
128 MB 4 x16 256 Mbit Max. freq. may be limited due to dual ranks
128 MB 2 x16 512 Mbit
128 MB 2 x32 512 Mbit Max. freq. may be limited due to dual ranks
128 MB 4 x8 256 Mbit
PNX8550
Chapter 1: Functional specification
No. of
Parts
MB 1 x32 256 Mbit
MB 2 x32 128 Mbit Max. freq. may be limited due to dual ranks
Component
Config.
Component
Density Remarks
of memory.
of memory.
of memory.
of memory.
of memory.
Commercial DDR memory parts that will operate with the PNX8550 include:
Table 8: Memory Part Numbers
Component
Density
128 Mbit x32 MT46V4M32-4
128 Mbit x16 K4261638E-TC_R11 (Jan. 2003)
256 Mbit x32 K4D553238E
256 Mbit x16 K4D551638D-TC_R11 (Mar. 2003)
256 Mbit x8
512 Mbit x32 TBD
512 Mbit x16
Component
Config. Part Number
HY5DU283222F-4
HY5DU283222Q-4
K4D263238A-GC40
K4D263238D-GC45 (222 MHz max)
Strongly recommended by the IC development team
The memory interface also performs the arbitration of the memory highway
guaranteeing adequate bandwidth and latency to the PR4450, the TM3260s, and
other internal resources that require memory access. A programmable list-based
memory arbitration scheme is used in order to customize the memory bandwidth
usage of various hardware blocks for a given application. CPUs in the system are
given the ability to intersect long DMA transfers up to a programmable number of
times per interval. This allows optimal CPU performance at high DDR DMA utilization
rates while guaranteeing real-time needs of audio/video DMA peripherals.
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Refer to the datasheets listed in the above table for the supported memory
parameters.
15.2 System EEPROM, ROM or Flash
EEPROM, ROM or Nand/Nor Flash memory connect to the PNX8550 by sharing
some PCI bus pins. The XIO bus created by this sharing supports 8 and 16-bit
storage devices, using only 8 separate data lines and a few control signals.
The PNX8550 provides 5 chip selects in order to support five external devices
including the system’s EEPROM, ROM or Flash device that holds all application code
and read-only data. Address range and wait states for this device are programmable.
Each chip select supports up to 64 MB of address space and five chip selects
together support 128 MB.
The PR4450 and TM3260s can execute or read from direct addressable device
types, but not from Nand Flash. Such execution is low performance and only
recommended for boot usage. After that, it is recommended to take compressed files
with code from Flash, decompress them and store them in DRAM, and execute from
DRAM. The TM3260 can be enabled or disabled to access Flash. The PR4450 can
reprogram Flash using special software. Flash can not be the target of a peripheral
DMA write. Writes require a software flash programming protocol.
PNX8550
Chapter 1: Functional specification
Execution from and direct addressed read only apply to addressable memory types,
such as EEPROM, ROM or traditional Nor Flash, and not to the more Nand-Flash file
system.
Peak page mode read performance is 33 MB/sec for 16-bit devices and 16 MB/sec
for 8-bit devices such as Intel StrataFlash (28FxxxJ3A, 32M, 64M, 128M) and ST
MLC-NOR Flash (M58LW064A, 64M). Cross-page random read accesses each take
4 to 5 PCI clock cycles depending on the access time of the device.
Flash is mostly active during system booting or with low bandwidth during system
operation in order to implement a small non-volatile Flash file system.
16. Security Provisions
The PNX8550 contains hardware provisions to ensure that critical or confidential
data, such as for example MIPS kernel memory or keys in conditional access devices
can be protected from corruption or inspection by agents other than trusted agents.
Each on-chip device has control/status registers that can be given distinct accessrights for each of the masters in the system: read-only, read/writable or invisible.
The DMA hierarchy that connects devices to system DRAM has 4 programmable
ranges or ‘sandboxes.’ Each device can optionally be set to be associated with a
given sandbox. It can only write to and read from memory locations in the sandbox
range. An attempt to access outside the assigned sandbox leads to dropped writes,
zero read values and raising of an interrupt.
The control over these security mechanisms is initially by ‘boot.’ Boot can then further
restrict access or leave access to the security control mechanisms to a trusted
master (e.g., MIPS).
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These mechanisms are a superset of the mechanisms in the PNX8525. Of particular
use is the ability to ensure that a TriMedia processor can not write or read the MIPS
kernel mode memory. Devices controlled by the TriMedias can be placed in a
sandbox that also ensures they can not access the MIPS kernel memory.
16.1 Power Modes
PNX8550
Chapter 1: Functional specification
• The PNX8550 system, with its programmable clocks, can be set to operate in
many different power modes. For example, to save power, the clocks to the
TM3260 CPUs and/or the PR4450 CPU can be reduced to a low frequency, and
individual unused blocks can be turned off altogether. All CPUs have powerdown
mechanisms, and can be powered down awaiting an interrupt. These modes are
not managed by a hardware power mode controller, but by software using the
standard provisions of the CPUs and clock system.
• The PNX8550 can in particular go to a very low dissipation ‘hibernate’ mode.
• Hibernation is entered under the PR4450 software control. Software powers
down the TM3260 CPUs completely, turns off all video/audio and I/O blocks of
the system, turns the clocks into a state where all PLLs are off, and where the
system bus clocks are driven from the 27 MHz crystal oscillator frequency divided
by 16. Software then sets wakeup conditions by programming the interrupt mask
registers in its interrupt controller and puts the PR4450 in ‘coma mode’ and
memory in self-refresh.
• During hibernation, memory content is retained and the GPIO block remains
active (on a reduced clock). The PCI outgoing clock is reduced to 27 MHz divided
by 16. The system will not respond to incoming PCI transactions or generate
outgoing PCI transactions, but other PCI components may remain operational.
All other system activity is halted.
• Any enabled interrupt will wake the PR4450 up from ‘coma mode’. In practice,
such an interrupt can only come from a few sources:
– An external GPIO input pin edge transition, on a pin designated as monitored
or as active interrupt pin i.e., an external device signaling wakeup
– An incoming Remote Control ‘power on’ command
– One of the timers/counters in GPIO i.e., a scheduled wakeup, or programmed
number of external events
• After wakeup from ‘coma mode,’ the PR4450 can examine the full RC event or
other tentative wakeup attempts, and if the wakeup is genuine, bring the system
back to full operational mode.
17. Peripheral Interfaces
The PNX8550 supports the required peripherals to build a baseline DTV system.
Peripheral functionality beyond what is supported in the PNX8550 may be achieved
by using commercially available low-cost PCI devices. The PNX8550 has the
following on-chip peripherals:
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PNX8550
Chapter 1: Functional specification
• 1 USB Root Hub with 2 ports, with a shared overcurrent detector and powerdown
control. The Root Hub complies with revision 1.1 of the USB specification
(Universal Host Controller).
• 2 Smart Card UART Interfaces (requires external TDA8004 or similar)
• Four I2C interfaces (two I2C with multimaster (400 kHz) and two I2C with DMA
(3.4 MHz))
• 2 UARTs (general purpose: one 2-wire, one 4-wire including large data FIFO)
• 16 dedicated General Purpose Software I/O (GPIO) pins which serve as system
interrupt inputs, software inputs/outputs as well as support arbitrary serial
protocol formats, including MemoryStick™ and MultiMediaCard™
– Only level interrupt is supported and the level is programmable for high or low
level based interrupts.
• There are 45 pins that can double as GPIO pins if their primary function is not
used.
• 1 Universal Remote Control receiver input with RC5/RC6/RC-MM and other
serial IR or RF protocol capabilities. Capable of waking the system up from
hibernate mode (uses GPIO).
• 1 or more universally programmable RC Blaster using GPIO outputs
17.1 IDE Interface
The PNX8550 contains all logic to control two IDE drives. Two external low-cost TTL
devices
controller shares PCI pins.
The IDE (ATA) interface pins operate in PIO-4 mode transfer with a theoretical
maximum transfer rate of 16.6 MB/s. The processors see disk accesses as
autonomous DMA. Entire data blocks are fetched from or written to system DRAM.
All IDE disk registers (eight command and one control) are indirectly accessible by
processors through the PCI-XIO registers.
The IDE interface uses an XIO select pin for IDE_ENABLE and a GPIO pin for
INTRQ.
1
are required to capture/buffer and isolate the IDE signals, since the IDE
17.2 MemoryStick and MultiMediaCard
Interface to a MemoryStick™ is accomplished using software and 3 GPIO pins. This
uses up 2 of the GPIO timestamp/sampled queue resources. Sustained file transfer
rates of 800 kB/sec have been demonstrated.
Interface to a MultiMediaCard is accomplished using software and 3 or 4 GPIO pins
(for MMC mode or SPI mode). If operation in both MMC mode followed by MMI mode
is required, a total of 5 GPIO pins are used. Either mode uses 2 of the GPIO
timestamp/sampled queue resources.
1. A 74LS16245 plus a 74LS244 device.
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Decoding of audio or picture files on flash cards is performed by software.
Flash card types other than MemoryStick™ and MultiMediaCard™ are not gluelessly
supported and require an external interface chip on USB or PCI.
17.3 GPIO
The PNX8550 has 16 dedicated GPIO pins. In addition, 45 other pins that have a
high likelihood of not being used in certain applications are designated as optional
GPIO pins that can either operate in regular mode or in GPIO mode. As an example,
the 10 data pins of the VCR output are available as fully functional GPIO in case the
on-chip Digital Video Encoder is used. Unused smartcard or regular UARTs can be
used as GPIO pins, etc. If the XIO use is limited to 8-bit devices or if XIO chip selects
are unused, additional GPIO lines are available.
The GPIO block is connected to many pins. Hence it is the ideal place to provide
useful central system functions. It performs the following major functions, each
detailed below:
PNX8550
Chapter 1: Functional specification
• Software I/O - set a pin or pin group, enable a pin (group), inspect pin values.
• Precise timestamping of internal and external events (up to 16 simultaneous
signals)
• Signal event sequence monitoring or signal generation (up to 6 simultaneous
signals)
• Generation of CPU interrupts
• Timer/counter capability (4 timers/counters)
17.3.1 Software I/O
Each GPIO pin is a tri-state pin that can be individually enabled, disabled, written or
read by software. Pins are grouped in groups of 16, signals within a group can be
simultaneously enabled and changed or observed. Changes can use a mask to allow
certain pins to remain unchanged.
Note that this capability is useful for low/medium speed software implemented
protocols, as well as for observing switches, driving LEDs etc. It is highly
recommended to first use the powerful GPIO pins as protocol emulators, and not just
for static switches/LEDs (for which a solution such as a PCF8574 I2C parallel I/O is
well-suited).
17.3.2 Timestamping
The GPIO block contains 16 timestamp units, each of which can be designated to
monitor an external GPIO pin or internal system events. For a monitored event, a
timestamp unit can be set to trigger on rising edge, falling edge or either edge. When
a trigger occurs, a precise occurrence time (31-bit timestamp value, 75 nsec
resolution) is put in a register and an interrupt is generated.
This capability is particularly valuable for precise monitoring of key audio/video
events and controlling the internal software phase-locked loops that lock to broadcast
time references. It can also be used for medium speed signal analysis.
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17.3.3 Event Sequence Monitoring and Signal Generation
The GPIO contains 6 queue units, each capable of monitoring or generating highspeed signals on up to 4 GPIO pins.
This capability creates a universal protocol emulator capable of emulating many
medium speed (0 - 20 Mbit/sec) protocols using software on the media processor.
Complex protocols, such as the MemoryStick™ protocol with 20 Mbit/sec peak rate
and an 800 kB/sec sustained file transfer rate, have been successfully implemented
on the PNX8525 GPIO, which also supports MultiMediaCard serial protocol. The
PNX8550 GPIO is a superset of the PNX8525 GPIO.
High speed signal analysis uses one of two modes:
PNX8550
Chapter 1: Functional specification
• Event queue hardware samples 1 to 4 GPIO inputs using one out of a variety of
clocks in the system, including clocks input to or generated by other GPIO pins.
Samples are packed in a word and stored in a list in system memory for software
analysis. Sampling can be applied to 1, 2 or 4 pins simultaneously.
• Event queue hardware builds an in-system memory list of timestamped GPIO pin
change events, individual per monitored GPIO pin. Edge events are timestamped
with 75 ns resolution.
Signal generation uses the same 2 capabilities, but in reverse, i.e., a sampled signal
is emitted or an in-memory timestamped list of change events is output over a pin.
The event sequence monitoring mechanism can be used for many functions and is
particularly useful for interpreting Remote Control commands. Signal generation is
useful for RC Blaster applications.
The GPIO block has a total of 6 complex signal analysis/signal synthesis resources
capable of sampling or timestamped list generation/creation.
17.3.4 Interrupt Generation
A GPIO pin can be programmed to generate a level based interrupt on a low or high
transition. An interrupt line is connected to any CPU through generic interrupt
controller (GIC) block or directly to the TM3260’s vector interrupt block.
17.3.5 Timer/Counter Capabilities
The GPIO contains 4 timers/counters, each capable of
Counting events on external or internal GPIO signals
Counting on a system clock
Generating an interrupt and wrapping around when a programmed count is reached
Optionally gating the clock by a second GPIO signal
The timers/counters are particularly useful to schedule a future interrupt in
preparation for hibernate mode. Another use is measuring the interval in which a
certain number of key audio/video events occur, e.g. audio sample input rate, etc. For
creation of pulse width modulated signals, the use of the generic GPIO signal
generation capability is recommended, rather than the use of a counter/timer.
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Philips Semiconductors
17.3.6 GPIO Pin Reset Value
The default mode after reset is input mode.
17.3.7 Compatibility with PNX8525
The PNX8550 is a superset of the PNX8525 GPIO.
PNX8550
Chapter 1: Functional specification
• It has 16 dedicated GPIO pins.
• It has 6 event queues instead of 4.
• It has 16 timestamp units instead of 12.
• It allows any GPIO pin to act as low or high ‘level’ interrupt input to the system.
– Edge triggered interrupt is not supported.
• It provides separated interrupts at system level, allowing association of a given
CPU with a given GPIO task.
• It has better support for remote control, in particular ‘power-on’ detection and low-
power operating mode (see
Section 17.3.8).
• It allows a lower clock of operation with associated reduced timestamp accuracy.
• The reset value of dedicated GPIO pins has been changed.
17.3.8 Remote Control Receiver/Blaster
The PNX8550 contains a dedicated hardware RC receiver input pin. This pin is
connected to the GPIO block. This is a regular GPIO input pin, except that it also has
a ‘power-on’ code detector as described below. The general signal analysis
capabilities of the GPIO block are used to interpret remote control keys.
Driver software uses GPIO pins to implement any remote control protocol, such as
the Philips RC5/RC6/RC-MM protocols or similar bit-serial remote control protocols.
The RC receiver driver uses the GPIO event sequence timestamping capability,
which can resolve edge events on signals with 75 ns accuracy when running at full
GPIO clock speed. A sequence of edge events followed by a period of inactivity
causes generation of an interrupt. Software then interprets the “character” by looking
at the in-system memory event list consisting of (time, direction of change). This
allows interpretation of arbitrary remote control protocols in software.
The GPIO block input connected to the RC input pin contains a “power-on” RC code
detector. This detector monitors the RC input pin and generates a wakeup interrupt to
the PR4450 if an event sequence passes a simple filter criteria set. The criteria
consist of a ‘high/low’ or ‘low/high’ or ‘either way’ sequence where each signal state
has a duration falling between two programmed limits. These criteria do not
guarantee that the key pressed was a ‘power-on’ key, but filter most spurious events
so that a minimum of unnecessary PR4450 wakeups occur.
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Philips Semiconductors
Upon wakeup, software needs to examine the full event list to perform true ‘power-on’
key recognition. The ‘power-on’ detector can be used while GPIO is running at
reduced clock rates, as long as the clock is chosen to allow for error-free recognition
of the ‘power on’ character by its timestamped memory list. After the ‘power on’ key is
recognized, the system, including the GPIO clock, is brought up to full speed.
Any GPIO pins can be used for one or more RC blaster output(s). The event
synthesis capability of GPIO can likewise be used to emit an arbitrary RC event
sequence. A modulator to create an IR carrier is included in the GPIO. Any GPIO
pin(s) can hence be used as RC blaster(s) subject to GPIO queue resource
availability (6 total).
17.4 PCI2.2 and XIO16 Bus Interface Unit
The PNX8550 contains an expansion bus interface unit ‘PCI-XIO16’ that allows easy
connection of a variety of board level memory components and peripherals. The bus
interface is a single set of pins that allows simultaneous connection of 32-bit PCI
master/slave devices as well as separated address/data style 8 and 16-bit micro
processor slave peripherals and standard (NOR) or disk-type (NAND) Flash memory.
PNX8550
Chapter 1: Functional specification
The bus interface unit contains a built-in single-channel DMA unit that can move
blocks of data from a peripheral to or from the PNX8550 SDRAM. The DMA unit can
access the PCI as well as 8 and 16-bit wide XIO devices. The DMA unit packs XIO
device data to/from 32-bit words, so that no CPU involvement is required to pre/post
process data.
17.4.1 PCI Capabilities
The PNX8550 complies with Revision 2.2 of the PCI Bus specification and operates
as a 32-bit PCI master/target at 33 MHz.
The PNX8550 as PCI master allows any of its processors to generate single cycle
PCI transaction types, including memory cycles, I/O cycles, configuration cycles and
interrupt acknowledge cycles. As PCI target, the PNX8550 responds to memory
transactions and configuration type cycles, not to I/O cycles.
The PNX8550 can act as PCI bus arbiter for up to 3 external masters without external
logic. If the DSACK signal is used then the PCI bus arbiter supports only 2 external
masters.
The PCI clock is an input to the PNX8550, but if desired the general purpose
PNX8550 ‘PLL_OUT’ clock output, which upon reset automatically generates a 33
MHz clock, can be used as the PCI clock for the entire system.
17.4.2 Simple Peripheral Capabilities (XIO8/16)
The 16-bit microprocessor peripheral interface is a master-only interface and
provides non-multiplexed address and data lines. A total of 26 address bits are
provided, as well as a bi-directional 16-bit data bus. Five device profiles are provided,
each generating a chip select for external devices. Up to 64 MB of address space is
allowed per device profile. The interface control signals are compatible with a
Motorola 68360 bus interface and support both fixed wait-state or dynamic
completion acknowledgment.
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Philips Semiconductors
A total of 5 pre-decoded chip Select pins are available to accommodate typical
outside slave configurations with minimal or no external glue logic. Each chip select
pin has an associated programmable address range within the XIO address space.
Each chip select supports 64 MB of address space, and five chip selects together
support 128 MB. Each chip select pin can also choose to obey external DTACK
completion signaling or be set to have a preprogrammed number of wait cycles.
The peripheral interface derives 24 of the 26 address wires and 8 of the 16 data wires
from the PCI AD[31:0] pins. The remaining pins are XIO-specific and non-PCI shared.
During XIO transactions, the PCI signals FRAME, DEVSEL, IRDY, TRDY remain
quiescent, so that other PCI agents ignore the activity. Unused XIO pins are available
as GPIO pins.
PNX8550
Chapter 1: Functional specification
Table 9
Table 9: PCI-XIO16 Bus Interface Unit Capabilities
External Device Device Type Capabilities
External PCI
master
External PCI slave 32 bits, 33 MHz PCI
External 8-bit
slave
Standard Flash 8/16 bits wide The PNX8550 provides 5 chip selects, one of which is available for a Flash
NAND Flash 8/16 bits wide Direct execution, random access read or write from this Flash type is not
32 bits, 33 MHz PCI
masters
targets
8 bits wide,
demuxed address/
data devices on’XIO
bus’
summarizes extension capabilities of the bus interface unit.
Arbitration built-in for up to 3 external PCI masters. Additional external masters
can be supported with external arbitration. External PCI bus masters can perform
high bandwidth, low latency DMA into and out of PNX8550 SDRAM. Large block
transfer-capable devices can sustain up to 100 MB/sec into SDRAM.
Glueless connection supported for multiple devices subject only to capacitive
loading constraints. The PR4450 can perform low-latency 8/16/32-bit memory or
I/O writes and reads to/from PCI targets. Access by TM3260s can be enabled or
disabled.
Up to 5 devices supported gluelessly or unlimited number subject to capacitive
loading rules with external address decode logic. The PR4450 can perform 8/16/
32-bit reads and writes to these XIO’ devices, which are automatically mapped to
8/16-bit wide transfers by the bus interface unit.
device. Address range and wait states for a Flash device are programmable. The
PR4450 and TM3260s can execute or read from Flash. Execution is low
performance and only recommended for boot usage. The MIPS CPU can reprogram Flash using special software. Flash can not be the target of a peripheral
DMA write. Writes require a software flash programming protocol.
Peak page mode read performance is at 33 MB/sec for 16-bit devices and 16
MB/sec for 8-bit devices such as Intel StrataFlash (28FxxxJ3A, 32M, 64M, 128M)
and ST MLC-NOR flash (M58LW064A, 64M). Cross-page random read accesses
each take 4 to 5 PCI clock cycles depending upon the access-time of the device.
Flash is mostly active during system booting or with low bandwidth during system
operation in order to implement a small non-volatile file system.
supported. Explicitly programmed I/O through special nand Flash PCI-XIO8/16
control/status registers is used to implement a file system on this disk-like Flash
type. Using the nand-Flash XIO provisions, a peak bandwidth of 13 MB/sec and a
sustained bandwidth of 11 MB/sec can be obtained from an AM30LV0064D 8Mx8
UltraNAND or equivalent Flash device. Maximum throughput for serial burst
accesses is 33MB/sec for 16-bit devices such as Samsung K9F5616U0B
(16 Mbits x 16).
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Philips Semiconductors
PNX8550
Chapter 1: Functional specification
Table 9: PCI-XIO16 Bus Interface Unit Capabilities
External Device Device Type Capabilities
CIMaX device 8-bit data, 26-bit
address
1394 link core 8-bit data and 9-bit
address (Philips
PDI1394LXX)
DOCSIS devices Future DOCSIS devices are expected to be PCI bus mastering devices. They
External SRAM,
ROM, EEPROM
External SDRAM not supported Not supported on PCI-XIO
External Motorola
style masters
External 8/16 bits
XIO DMA devices
8/16 bits wide Counts as generic XIO slave device.
not supported The PNX8550 PCI-XIO does NOT support external Motorola style masters. The
not supported Not supported. Use one of the streaming DV inputs or outputs instead.
The external logic for conditional access consists of a CIMaX device with 2 PCMCIA slot devices and glue logic (373, 245). This entire subsystem behaves as an
8-bit wide slave with an up to 26-bit address space. This subsystem interfaces
gluelessly to the XIO bus except for the possible logic needed to combine the
DTACK signaling of multiple devices.
There is a medium bandwidth of communication between CIMaX and the
PNX8550, which is not expected to be an issue w.r.t. PCI performance.
The Philips PDI1394LXX family connects glueless to the XIO in 8-bit data mode
using 8-bit data and a 9-bit address with dedicated read and write strobes,
optional wait signal and a separate chip select. For systems which require high
asynchronous performance, a 1394 link device with direct PCI connection can be
used.
connect gluelessly.
PNX8550 assumes that it always is the master on the XIO bus.
…Continued
18. Endian Modes
19. PNX8550 Boot
The PNX8550 fully supports little- and big-endian software stacks.
The PNX8550 always starts its on-chip MIPS device in a fixed endianness, which is
determined by the boot script. There is a system provision for MIPS software to reset
and restart the MIPS in the opposite endianness, such that a field software Flash
upgrade can release a ‘endianness opposite boot’ operating system upgrade.
The PNX8550 on-chip peripherals and coprocessors observe the system global
endianness flag, as does the PR4450. The TM3260 endianness is set by the TM3260
program module itself and should always be set identical to system endianness.
When selecting PCI peripherals for a dual-endianness product, care must be taken to
ensure that they can operate without “CPU fixup” in either endianness. Typically,
PowerPC compatible PCI devices support both endianness types in the exact same
way as the PNX8550.
The PNX8550 boot occurs on an externally initiated hardware reset, a software reset,
or on watchdog timer timeout.
The PNX8550 uses a scripted boot i.e., a hardware block (the Boot module) within
the PNX8550 executes a script consisting of simple commands (write a given value
at a given address, delay xxx cycles, etc.).
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Philips Semiconductors
Three BOOT_MODE resistor strapping pins determine which script is executed.
The PNX8550 on-chip PR4450 and TM3260 processors are capable of executing
code directly from standard Flash ROM to allow for a second-level of booting.
Remark: Direct execution from NAND Flash or “Disk” Flash is not supported.
Direct execution from Flash ROM has very limited performance. Hence, the MIPS
typically copies a Flash file to high-performance system DRAM and executes the
code from DRAM. The Flash file may contain a self-decompressing system
initialization application. Implementing a multi-stage boot process in this manner can
help to minimize the system memory cost.
The System designer may choose to customize the initial boot that is executed via
the Boot module by connecting an appropriately programmed I2C EEPROM and by
configuring the Boot module to read the initial boot commands from the EEPROM.
A standalone PNX8550 system is able to reliably update its own Flash boot image,
whether the Flash is standard NOR or NAND Flash ROM. In most systems this is
done by an extra Flash storage capacity that is used by the Flash update software to
guarantee atomicity of a boot image update under power failure. The update either
succeeds or the old boot image is retained. In some systems it may, however, be cost
effective to use a medium-sized boot I2C EEPROM instead. This boot EEPROM
holds the code to recover a corrupted Flash from some system resource, such as a
network or disk drive.
PNX8550
Chapter 1: Functional specification
20. Boundary Scan
In the presence of an external host processor, the PNX8550 must execute an I2C
EEPROM boot script that loads a small amount of board level personality data. Once
this data is obtained, the PNX8550 is ready to follow the standardized PCI
enumeration and configuration protocol executed by the external host processor. In
external host configurations, a single small I2C EEPROM is required and no Flash
memory is needed. The host is responsible for configuring a list of PNX8550 internal
registers, loading an application software image into the PNX8550 SDRAM and
starting the TM3260. In the presence of an external host, the on-chip PR4450 is
generally not used.
The PNX8550 is compliant with the IEEE1149.1 Boundary Scan standard. It can be
seamlessly integrated with other IEEE 1149.1 compliant devices to perform boardlevel testing. The PNX8550 scan chain implementation has all I/O signal pins except
the analog signals in the boundary scan registers. The boundary scan registers can
be connected between TDI and TDO pins by executing the required instructions. The
boundary scan instructions are used to capture the signal pins data from the input
pins and also to force fixed values to the output signal pins. A detail description of the
boundary scan usage for the PNX8550 is given in the “PNX8550 Test Block
Specification” document.
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Preliminary data Rev. 02 — July 21 2004 1-43
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Philips Semiconductors
Chapter 1: Functional specification
21. Changes from PNX8550_RevA to PNX8550_RevB
There are two new hardware blocks and one sub IP block for the second tape-out or
“RevB” of the PNX8550. The new hardware blocks are the modified MBS block
(MBS2) and the Vertical Peaking block (VPK). A contrast reserve with soft-clipping
hardware IP block is added to the QVCP-5L hardware IP block.
21.1 MBS2 Block
The MBS2 block is a derivative of the current memory based scaler (MBS) block.
Refer Section 12.5 on page 1-25
block contains only horizontal and vertical scaler functions. All other functions
including the video measurement, all modes of de-interlacing and the edgedependent de-interlacing functions are not available in the MBS2 block.
21.1.1 Frequency of Operation and Performance
The MBS2 block operates at 145 MHz. The MBS2 block output data is optionally
directed to either an external memory or to the QVCP-5L block by setting the
appropriate control registers. The direct streaming mode to QVCP generates
proportionately more bandwidth for the video downscaling function.
for the description of the MBS block. The MBS2
PNX8550
21.2 Vertical Peaking Block (VPK)
The Vertical Peaking unit is intended to increase the overall vertical sharpness of the
input video signal. In Figure 8
Vertical Peaking unit is shown.
Y
Un-
8bi t
dithe
YUV i n
(DTL
32bit )
PFU
(DTL)
Figure 8: VPK Block Diagram
r
UV 8bit
MMI O
Programmable
9 tap Peaking
9 bit s
UV delay
fil ter
Horiz ontal
Low-Pass
filter
Un-
dither
, a block diagram of the functional description of the
+
9+1 bit s
+
Yout
Semipl anar Y out
or Packed YUV out
(DTL 32bit)
C
R
O
P
PSU
INTL
Semip lan ar
UV out
(DTL 32bit)
F
R
M
T
CLIP, Coring,
Smart nes s
Control
from Eagle 1c
9+1 bit s
UVout
pedest al
For luminance, vertical peaking is achieved by means of applying a programmable
vertical high-pass filter to the original data and adding the filtered versions in a
controlled manner to the original video data. Two of the three filters operate in a fixed
frequency band, having fixed filter coefficients, while the third filter is a fully
programmable 9 taps filter. The three filters have a separate gain control, which can
be programmed and adjusted on a field-by-field basis.
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Philips Semiconductors
Furthermore, coring is provided to obtain an improved performance when noisy
signals are present. The coring threshold can be programmed on a field-by-field
basis. Finally, the smartness control realizes a gain reduction in areas where large
peaking values are expected. This significantly reduces the sensitivity for alias
creation.
The Vertical Peaking unit can produce either progressive or interlaced output. In case
the output is interlaced, every other output line is omitted.
The following additional features are included in the Vertical Peaking unit:
Cropping
A programmable output window may be programmed that is cropped out of the input.
Demo mode
The Vertical Peaking supports a demo mode, meaning that a window may be
programmed in which the vertical peaking is applied. This mode is typically used to
show the end-user the difference between processed and nonprocessed parts of an
image. The output of the Vertical Peaking block is transferred to the QVCP-5L.
PNX8550
Chapter 1: Functional specification
Bypass
The vertical peaking unit can be optionally bypassed in order to transfer the video
stream directly from MBS2 to QVCP-5L. The HD resolution video from the MBS2 can
be bypassed through the vertical peaking unit.
21.2.1 Frequency of Operation and Performance
The Vertical Peaking block operates at 81 MHz and the maximum pixel rate of the
vertical peaking operation is 81 Mpixel/sec. The Vertical Peaking block output data is
optionally directed to the QVCP-5L block by setting the appropriate control registers.
The peaking function only supports a maximum of 720 pixels per line; however the
bypass mode supports a maximum of 1920 pixels/line.
21.3 Video Streaming Connections
21.3.1 Tunnel Interface to QVCP
The video data from an external chip through Tunnel interface can be either stored in
memory or transferred directly to QVCP-5L. The selection is controlled by a global
control register. This control register should be used during the system initialization
time and is not meant to be used for dynamic switching.
21.3.2 MBS2 Block to QVCP
The output of the MBS2 can be either stored in an external memory or directly
transferred to QVCP-5L through the Vertical Peaking unit.
21.3.3 Vertical Peaking Block to QVCP
The Vertical Peaking output data is directly transferred to the QVCP-5L. The VPK unit
can only receive the input data from the MBS2 block.
See Figure 9
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Preliminary data Rev. 02 — July 21 2004 1-45
for more information.
Page 61
Philips Semiconductors
From
From
Memor y
Memor y
SP/P
SP/P
MBS2
MBS2MBS2
External
External
Chip
Chip
SP/P
SP/P
Tunnel
TunnelTunnel
SP/P
SP/P
SP/P 8bit,
SP/P 8bit,
10bit
10bit
To
To
Memor y
Memor y
To
To
Memor y
Memor y
SP/P
SP/P
SP/P
SP/P
P
P
To
To
Memo ry
Memo ry
VPkg
VPkgVPkg
From
From
Memo ry
Memo ry
(layer0)
(layer0)
P 8bit, 10bi t
P 8bit, 10bi t
SP/P
SP/P
PNX8550
Chapter 1: Functional specification
SP/P
SP/P
Layer 0
Layer 0
QVCP
QVCPQVCP
P 8bit, 10bi t
P 8bit, 10bi t
Layer 1
Layer 1
SP: Semi-planar f ormat, P: Packed format
SP: Semi-planar f ormat, P: Packed format
Figure 9: Video Streaming Connections Block Diagram
21.4 Contrast Brightness Control with Soft Clipper (CBSC)
The contrast reserve with soft clipper block enhances the visual quality of the video
when it is displayed on a matrix display including the LCD-TV. The CBSC block performs contrast and brightness control, color space conversion, soft clipping and face
(large bright region) detection.
For weak signals, application of high (up to 2.0x) contrast gain is preferred. Without
protection, a high contrast gain can cause hard clipping, which will distort the image
quality. The Contrast Reserve algorithm will reduce the clipping artifacts both locally
and globally. Even for signals at normal level, in order to achieve strong contrast
perception, the contrast and brightness controller deliberately try to overdrive the
display, and the soft clipper prevents artifacts by applying the following four functions:
• local reduction of color saturation
• local reduction of contrast
• global reduction of contrast and/or brightness
• global reduction of clipper characteristics from hard to soft
The local reduction is controlled by two programmable non-linear gain factor Look Up
Tables (LUTs), in which a high gain factor is set for small signals and a low gain factor
is set for large signals. The last two actions are partially based on software feedback
of the hardware face detector output. Software adjusts contrast and brightness
control parameters based on the face detector output and other measurement
results.
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Philips Semiconductors
The CBSC block supports both YUV and RGB video input/output formats. The
supported contrast range is from 50% to 200% with sufficient quality. Color saturation
control is only available when the input is YUV.
Input and output data formats:
Input
Y/R, U/G and V/B 10 bits signed with nominal data range -256~255.
(the same as the internal QVCP data format)
Output
R/Y, G/U and B/V 10 bits signed with nominal data range -512~511.
The CBSC block is placed in front of the CDNS sub IP block within the QVCP-5L.
PNX8550
Chapter 1: Functional specification
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-47
Page 63
1. Introduction
Chapter 2: Bus Architecture and System Memory Map
PNX8550 User Manual
Rev. 02 — July 21 2004 Preliminary data
The PNX8550 contains three different bus interconnect networks (see Figure 1
PNX8550 System Block Diagram):
• MIPS Device Control and Status Network (MDCS)
• Tri-Media Device Control and Status Network (TDCS)
• Pipelined Memory Access Network (PMAN), which is referred to as the Hub
The MDCS and TDCS are networks used exclusively for MMIO (Memory Mapped IO)
traffic. Every block requiring IO programming has a memory mapped set of registers
and the formats of these registers are designed to be software enumerable.
The PMAN Network is used by all blocks requiring access to memory via DMA.
The separation of DCS and PMAN networks ensures that MMIO traffic does not
disturb memory accesses. The blocks on the TDCS MMIO network are typically
controlled by the TriMedia processor, while the blocks on the MDCS MMIO network
are typically controlled by the MIPS CPU.
All on-chip and off-chip CPUs and devices in the PNX8550 can be set to access
memory-mapped resources. To implement protection, not all masters in the system
are allowed to access all memory-mapped resources. As an example, it is possible to
set registers such that processes on the TM3260 CPU core can not access devices
and memory ranges that are mission critical.
This chapter describes the following:
• Standard PNX8550 system memory map (internal MIPS PR4450 host CPU)
• Object visibility rules and protection mechanisms
• Registers controlling the system memory map and protection mechanisms
• Alternate system memory map (external PCI host CPU).
Memory map view from the MIPS PR4450 CPU, TM3260 CPU, DCS-Bus masters
and external PCI devices.
Alternate PNX8550 system configurations exist, but are not supported.
Page 64
Philips Semiconductors
2. Functional Description
2.1 Bus Architecture Block Diagram
The PNX8550 architecture block diagram is shown in Figure 1.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
CAB
CAB
DCS
DCS
Security
Security
DCS Ctrl
DCS Ctrl
GIC-MIPS
GIC-MIPS
IPC-MIPS
IPC-MIPS
CLOCKSCAB
CLOCKSCAB
BOOT
BOOT
GLB REG1
GLB REG1
GLB REG2
GLB REG2
RESET
RESET
TM DBG1
TM DBG1
TM DBG2
TM DBG2
UART1
UART1
UART2
UART2
IIC3
IIC3
IIC4
IIC4
DDR
DDR
T
T
Controller
Controller
R
R
R
DMA
DMA
DMA
DMA
R
W
W
W
W
Pipelined Memory Access Network
Pipelined Memory Access Network
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
T
T
T
T
T
T
T
T
T
T
I
I
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
I
I
PR4450
PR4450
T
T
Monitor
Monitor
PMAN
PMAN
T
T
MIPS – Device Control and Status Network
MIPS – Device Control and Status Network
T
T
T
T
T
T
PCI/XIO
PCI/XIO
I
I
T
T
T
T
T
T
T
T
USB Host
USB Host
T
T
Scard1
Scard1
T
T
SCard2
SCard2
T
T
DMA Gate
DMA Gate
DMA Gate
DMA Gate
Security
Security
PMAN
PMAN
Arbiter
Arbiter
EJTAG
EJTAG
DE
DE
IIC1
IIC1
IIC2
IIC2
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
TM32_1
TM32_1
TM32_2
TM32_2
QVCP5L
QVCP5L
QVCP2L
QVCP2L
VPK
VPK
DVD/CSS
DVD/CSS
VIP1
VIP1
VIP2
VIP2
MBS
MBS
MBS2
MBS2
QTNR
QTNR
EDMA
EDMA
VLD
VLD
TSDMA
TSDMA
VMPG
VMPG
MSP1
MSP1
MSP2
MSP2
T
T
I
I
T
T
I
I
TR
TR
TR
TR
TM – Device Control and Status Network
TM – Device Control and Status Network
T
T
T
T
TW
TW
TW
TW
T
T
T
T
T
T
T
T
T
T
TR
TR
T
T
T
T
T
T
T
T
Security
Security
T
T
DCS Ctrl
DCS Ctrl
T
T
GIC-TM32_1
GIC-TM32_1
T
T
GIC-TM32_2
GIC-TM32_2
T
T
IPC-TM32_1
IPC-TM32_1
T
T
IPC-TM32_2
IPC-TM32_2
T
T
DENC
DENC
T
T
SPDI-O
SPDI-O
T
T
SPDI-I1
SPDI-I1
T
T
SPDI-I2
SPDI-I2
T
T
AI1
AI1
T
T
AI2
AI2
T
T
AO1
AO1
T
T
AO2
AO2
T
T
GPIO
GPIO
T
T
Tunnel
Tunnel
DCS
DCS
DAC
DAC
R
R
W
W
W
W
W
W
W
W
R
R
R
R
R
R
W
W
R
R
W
W
Pipelined Memory Access Network
Pipelined Memory Access Network
T
T
T
Bridge
Bridge
Bridge
I
I
I
MDCN TDCNPMAN
MDCN TDCNPMAN
I
I
I
T
T
T
PMAN
PMAN
Figure 1: PNX8550 System Block Diagram
2.2 Architecture
There are two MMIO networks in the PNX8550: the MIPS DCS (MDCS) network and
the TriMedia DCS (TDCS) network. The MDCS and TDCS are intended for MMIO
traffic to configure the various devices in the system. Each peripheral on the DCS
network is located as close as possible to the CPU that is expected to typically control
that peripheral.
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The GPIO interrupts that may require fast service will be serviced by the TriMedia
cores. Therefore, the GPIO module is located on the TDCS network.
Global (1 and 2) register peripherals contain configuration registers for the chip. Most
of the system optimization features are programmable via the Global 2 registers.
All peripherals can be accessed from the MIPS, TriMedia cores, PCI, Boot, and
EJTAG. Due to system security issues, access to any of the peripherals can be
blocked for any of these DCS network initiators. (See Chapter 4 DCS Network &
Security.) Access between the MDCS and TDCS networks is provided by the
DCS2DCS network bridge. All other modules in the PNX8550 are not allowed to
access peripherals.
A generic “Device Transaction Level” (DTL) point-to-point initiator-target
communication protocol is used on the boundary between a peripheral and the DCS
network. MMIO communication through the DTL protocol always consists of a single
32-bit data element.
2.3 Low Power Adapter Implementation
PNX8550
Chapter 2: Bus Architecture and System Memory Map
In order to minimize the power consumed in the DCS network, system designers can
choose to use the power management features provided with the architecture. There
are several options described below. Only options 1-3 are supported by the default
implementation of the standard DCS network modules:
1. Utilize the asynchronous interface option and reduce adapter and network controller frequency.
2. Implement a hierarchical network with some segments operating at very low frequency.
3. Clock gating for network controller and adapters. A dcs_start_clk signal is
generated based on registered versions of dcs_cmd_req_i and
dcs_cmd_complete_t. This allows the dcs_clk to most of the network controller
and all the target adapters to be gated when there is no access in progress.
There is no access latency impact for this implementation and it still allows a very
high power saving for typical systems.
The selected power management architecture does not enforce the use of the power
management features, but allows system designers to make the choice. The
dcs_start_clk is an asynchronous signal broadcast to all chiplets where the dcs_clk
will be gated. Synchronization of dcs_start_clk will be done in the chiplet. In the
network controller there is a software enable for the dcs_start_clk signal. The default
for dcs_start_clk is logic 1.
It should be noted that there are no clock gates for the initiator adapters. There are
very few initiators and they can have separate clock inputs (e.g. use their core_clock)
for the DCS network interface. Therefore, the total power consumption of the initiator
interfaces are expected to be very small compared to the overall chip power and thus
clock gating was omitted.
The network utilization is expected to be below 0.5% in many systems. i.e.,
approximately a factor 200 in power could be saved by enabling the interconnect
clocks only when a transfer is in progress. That will ensure the power consumption of
the DCS network will be significantly below most other components in the system.
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3. DCS Network
3.1 DCS Controllers
There are two DCS networks in the PNX8550, the MDCS and the TDCS. Each
network has its own network controller (MDCSC and TDCSC respectively), as shown
in Figure 2
PNX8550
Chapter 2: Bus Architecture and System Memory Map
Monitors
Timeout & Error Control
Arbitration
Security
Initiator 0
Initiator 1
l l l
Initiator N
DTL
DTL
DTL
DCS
DCS
DCS
Bridge In Bridge Out
Figure 2: Device Control and Status Network
Multiplexing
DCS DCS
Target 0
DTL
DCS
Target 1
DTL
DCS
l l l
Target M
DTL
DCS
The DCS network controllers provide the following functions:
• Support 1 to 8 initiators interfaces.
• Support 2 to 64 target interfaces.
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PNX8550
Chapter 2: Bus Architecture and System Memory Map
• Provide programmable address map:
– Optionally, address map information may be input signals to the DCS
controller.
– Each target will have a defined aperture of a given size, offset from a defined
base address register. A given bus controller may be configured to have up to
4 different base address register shared by various targets.
– In addition, each target may have additional regions which will be steered to it.
This would be used primarily by bridges, but possibly other targets. Each of
these additional apertures are defined using a High/Low Address method with
a programmable width for each address.
• Provide programmable timeout generation.
• Capture error and timeout information:
– Initiator ID of the currently granted DCS Initiator
– 32-bit address of the currently granted DCS transaction
– Encoded target number for the currently selected DCS device
– Additional command information including cmd_mask and cmd_read
• Allow interrupt generation for any non-masked timeouts and errors.
• Allow optional selective blocking of initiators via read/write registers with
programmable power on defaults.
• Allow optional blocking of errors on 32-bit reads (needed for TriMedia).
• Include timing closure flops for all dcs*_cmd_sel_t and dcs*_cmd_req_i signals.
• Conform to signaling protocol of the DCS Network Specification
See Chapter 4, DCS Network & Security for details regarding the DCS Network.
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4. Standard System Memory Map
The standard system memory map applies to PNX8550 configurations without an
external PCI host processor. In such systems, the PNX8550 hardware reset and boot
block script initialize on-chip registers and start the on-chip MIPS PR4450 CPU.
Initialization software on the MIPS PR4450 completes system initialization. The
resulting standard system memory map is shown in Figure 3
0xFFFF FFFF
PNX8550
Chapter 2: Bus Architecture and System Memory Map
0x2000 0000
Base18 (XIO_BASE)
Base14 (MMIO_BASE)
PCI_BASE1_HI
PCI_BASE1_LO
Base10 (DRAM_BASE)
Figure 3: PNX8550 Standard System Memory Map (Internal MIPS PR4450 Host)
0x0000 0000
XIO Bus Peripherals & Flash (8..128 MB)
MMIO On-Chip Device Registers (2 MB)
PCI Bus Aperture
Local DRAM (max 128 MB)
Flash is set against top of this range
4.1 Apertures in the Standard System Memory Map
The PNX8550 local DRAM aperture is 16, 32, 64 or 128 MB and it is used for
accessing the DRAM.
The XIO bus aperture is not used in all systems. If used, it can be set from 8..128 MB
in size. An access to this aperture goes to external XIO peripherals attached to the
PNX8550 PCI-XIO bus, such as an IDE disk drive, ROM, Flash, SRAM memory, or
8-bit peripheral devices. Due to the sharing of wires between PCI and XIO devices,
the XIO aperture is not accessible to PCI bus masters. It is however claimed as an
aperture upon building the PCI bus memory map to prevent a local XIO peripheral
from being assigned the same address as a PCI device.
The MMIO aperture is a fixed 2 MB in size. It contains the 32-bit wide control and
status registers of all on-chip devices of the PNX8550.
The PCI bus aperture starts above DRAM and ends at the first MMIO aperture
address. An access to this aperture goes to PCI bus target devices, which may be a
range of memory or a PCI device control/status register. See Chapter 13
PCI-XIO for
more information.
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Philips Semiconductors
An example of a typical system configuration and its standard memory map is shown
in Figure 4
PNX8550
Chapter 2: Bus Architecture and System Memory Map
. This is the configuration set by all the PNX8550 built-in boot scripts.
0xFFFF FFFF
Unused
0x1FFF FFFF
64 MB XIO
0x1C00 0000
0x1BE0 0000
0x01FF FFFF
2 MB MMIO
Unused
(map to PCI after boot)
PCI Bus
32 MB DRAM
0x0000 0000
Figure 4: System Configuration and Standard Memory Map (Boot Script #1)
PCI Device Nor Flash/ROM
4.2 Building the Standard System Memory Map
The system memory map is built according to the following rules:
• DRAM is set to start at address 0, with a size equal to or greater than the actual
DRAM size in the system. The aperture size must be a power of 2 between 2 MB
and 128 MB.
• If used in the system, the XIO aperture is set against the top of the first 512 MB. It
must have a size equal to or greater than the actual peripheral address range.
The aperture size must be a power of 2 between 2 MB and 256 MB, and
allocated on a natural boundary i.e., a 128-MB aperture must start on an address
that is a multiple of 128 MB.
32 MB DRAM
PNX8550
Boot Mode
RESET_IN
001
XIO_SEL0
• The 2-MB MMIO aperture, with on-chip device control/status registers, is set
against XIO. It must be allocated on a 2-MB boundary.
• The area between the top of DRAM and MMIO is designated as a bridge to the
PCI bus.
The PNX8550 built-in boot scripts perform the first three of the above steps. MIPS
PR4450 software is responsible for the last step. If the size assumptions by the builtin boot scripts are inappropriate, a custom boot script can be used. Refer to
Chapter 7
Boot.
4.3 Rationale for the Standard System Memory Map
The PNX8550 address decoder logic requires that all three apertures are powers of
two in size and are “naturally aligned” i.e., a 32-MB aperture must start on an address
that is a multiple of 32 MB.
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It is required that MIPS PR4450 kernel mode processes can access any object in the
system. Due to the nature of the virtual to physical address translation in the on-chip
MIPS PR4450, kernel mode access is limited to the first 512 MB of physical address
space. Hence, the standard system memory map puts all objects in the lower
512 MB.
Furthermore, the MIPS PR4450 exception vectors must reside in the lower part of the
physical address space, necessitating DRAM at this address.
The MIPS PR4450 starts execution from a virtual address provided from the global
register module. This address is mapped to a physical address inside the MIPS
PR4450. This address may be in the XIO aperture, allowing MIPS PR4450 to start
from external ROM or Flash. Note that the system has a special MIPS PR4450 boot
provision, described in Section 8.1.1
without any direct addressable XIO to external ROM or Flash.
The choice of MMIO positioned below XIO is arbitrary.
The PCI aperture must be kept as large as possible to allow for multiple PCI devices
with attached local memories. Hence, it fills all left over space.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
, which can be used to boot MIPS PR4450
When changing the values in above mentioned aperture boundary registers of an
aperture, the following steps should be taken to avoid a temporary overlapping with
other apertures:
1. When moving to a higher address:
a. set the lower boundary register content to the new higher boundary.
b. set the higher boundary register content to the new higher boundary.
c. set the lower boundary register content to the new lower boundary.
2. When moving to a lower address:
a. set the higher boundary register content to the new lower boundary.
b. set the lower boundary register content to the new lower boundary.
c. set the higher boundary register content to the new higher boundary.
5. Hardware Limitations to Object Visibility
The PNX8550 hardware imposes the following limits:
• No DMA device can access MMIO aperture.
• Only the DMA engine within the PCI/XIO module can target the PCI or XIO
aperture.
In addition, the TM3260 CPU cores are set up such that they never map the PCI or
XIO aperture into their address space. This convention is highly recommended as
certain PCI and XIO devices may have side effects from read operations, and
TM3260 CPU generate speculative reads.
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Table 1: PNX8550 Hardware Limitations to Object Visibility
Master Type DRAM MMIO PCI XIO
On-chip MIPS PR4450 CPU yes yes yes yes
On-chip TM3260 CPU cores yes yes Note A Note A
On-chip MDCS DMA devices yes no yes yes
On-chip TDCS DMA devices yes no no no
Off-chip PCI bus masters yes yes yes no
Note: The TM3260 CPU core is not normally set to see PCI or XIO directly in its address
map. It can however use explicit MMIO transactions to the PCI-XIO block to perform any
single cycle type PCI transaction, including memory, I/O and intack. Using the same method,
it can also perform XIO bus transactions.
6. Register Descriptions
6.1 Aperture Control Registers
PNX8550
Chapter 2: Bus Architecture and System Memory Map
6.1.1 PCI, TM3260, and MIPS PR4450
The following registers relate to the PNX8550 System Memory Map and Object
Visibility. For more information, see Chapter 13
PCI-XIO, Chapter 29 TM3260 CPU
Core Processor, and Section 4. Standard System Memory Map.
Table 2: Aperture Control Registers
Offset Symbol Description
BASE Registers (PCI-XIO)
0x04 0050 BASE10 (DRAM_BASE) Shadow of PCI config register that determines DRAM base address in memory
map for external PCI masters.
0x04 0054 BASE14 (MMIO_BASE) Shadow of PCI config register that determines MMIO base address in memory
map
0x04 0058 BASE18 (XIO_BASE) Shadow of PCI config register that determines XIO base address in memory map
0x04 0018 PCI_base1_lo Low address of region 1 of DCS-bus that gets bridged to PCI
0x04 001C PCI_base1_hi High address of region 1 of DCS-bus that gets bridged to PCI
0x04 0020 PCI_base2_lo Low address of region 2 of DCS-bus that gets bridged to PCI
0x04 0024 PCI_base2_hi High address of region 2 of DCS-bus that gets bridged to PCI
TM3260 CPU Aperture Control Registers (TM3260 CPU)
00x10 0034 TM32_DRAM_LO Low address of DRAM
00x10 0038 TM32_DRAM_HI High address of DRAM
00x10 003C TM32_DRAM_CLIMIT Cacheable limit (addresses above this are not cached)
6.2 Global 2 Registers
Table 3 on page 2-10 lists the Global 2 registers relative to the PNX8550 System
Memory Map. Detailed information on these registers can be found in Ch12 Global
Registers.
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Chapter 2: Bus Architecture and System Memory Map
Table 3: Global2 Register Summary
Offset Symbol Description
0x04 D200 DMA_GATE_LO Internal bus DRAM low address register
0x04 D204 DMA_GATE_HI Internal bus DRAM high address register
0x04 D208 APERTURE_WE Enable DCS_DRAM_LO and DCS_DRAM_HI registers to be writable.
PNX8550
7. Alternate System Memory Map with External Host CPU
7.1 PCI Standard Boot and Memory Map Assembly
If an external host CPU (MIPS PR4450 or other) is present on the PCI bus, it has the
responsibility to enumerate and configure all PCI resident devices, including each
PNX8550. This configuration process builds an address map where apertures of all
devices (including each PNX8550) are given unique PCI addresses. The
standardized protocol that accomplishes this is described in the PCI Local Bus
Specification, Revision 2.2, Section 6.2.5.1, “Address Maps.”
The configuration process of the PNX8550 in this case is summarized below:
1. The boot block writes to the PCI_SETUP register to set the desired size for each
of the DRAM, MMIO and XIO apertures—typically equal to attached DRAM size
on a particular board; 2 MB for MMIO and up to 128 MB for XIO. The PCI-XIO
block generates a “retry” on any attempt by the host to access it until the
PCI_SETUP write is completed.
2. The host PCI BIOS reads each base address PCI configuration register of a PCI
device, in particular the lsb to determine if the requested aperture is a PCI
memory or I/O space aperture. The PNX8550 has three such base addresses,
each requesting a PCI memory space type aperture. They are Base10 (DRAM),
Base14 (MMIO) and Base18 (XIO).
3. The host writes an “all 1” value to each base address register and reads it back.
The PCI block hardware returns 0s in all “don’t care bits” and 1s in all actually
writable bits, from which the host deduces the size of the requested memory
aperture.
4. The host writes a unique address value to each base address register to set the aperture base address of DRAM, MMIO and XIO.
Note the outcome of this host configuration process is three apertures (DRAM,
MMIO, XIO) that will most likely be adjacent to each other in the PCI address space
and anywhere between 0x0 to 0xFFFF FFFF.
7.2 Internal MIPS PR4450 and External Host CPU
The address decoding logic for DRAM, XIO and on-chip MMIO devices is designed to
decode addresses relative to the base address values established by the PCI
memory map building protocol. The TM3260 CPU core is able to execute code and
load/store data at any physical address. However, the on-chip MIPS PR4450 CPU is
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Philips Semiconductors
not able to execute in this unpredictable PCI host address map environment, since it
expects a certain physical memory layout e.g., DRAM and MMIO must be within the
first 512 MB.
Hence, the internal MIPS PR4450 CPU is not used when an external host is present.
In certain instances e.g., if the code on the external host is developed specifically for
the PNX8550, and it can guarantee “MIPS PR4450-friendly” base address values,
the internal MIPS PR4450 can still be used.
8. Memory Map Perspectives
8.1 View from MIPS PR4450
The on-chip MIPS PR4450 CPU is only active when no external host CPU is present.
If MIPS PR4450 is active, it is in the “standard system memory map” environment,
where all system resources are in the first 512 MB of the physical address space.
The chosen virtual-to-physical addressing scheme for the internal MIPS PR4450
CPU is shown in the following diagram.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
0xFFFF FFFF
sw-debug
kseg2
(kernel cached)
0xC000 0000
0xBFFF FFFF
0xA000 0000
0x9FFF FFFF
0x8000 0000
0x7FFF FFFF
0x0000 0000
Note: Shaded areas are TLB mappable.
kseg1
(kernel uncached)
kseg0
(kernel cached)
kuseg
(user cached)
Virtual Address
4GB
3GB
2.5GB
2GB
4GB
3GB
1GB
0.5GB
Physical Address
Mapping only
if TLB is OFF
optional DRAM
shadow
Not Accessible
0xFFFF FFFF
0xC000 0000
0xBFFF FFFF
0x4000 0000
0x3FFF FFFF
0x2000 0000
0x1FFF FFFF
0x0000 0000
Figure 5: MIPS PR4450 Address Map
Kseg0 and kseg1 are not mappable via the TLB. They map directly to the lower
0.5-GB where all system resources (DRAM, PCI, MMIO, XIO) reside.
The software debug area is the only part of kseg2 that is used in the PNX8550. This
SW debug area is non-cacheable and can not be mapped with a TLB. The mapping
of this area can be enabled/disabled in the PNX8550.
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User-Mode processes will reside in kuseg. They will almost always be mapped via
the MIPS PR4450 TLB. The TLB allows per page translation to any physical address
in the 4 GB physical memory space.
8.1.1 MIPS PR4450 Exception Vector Logic
The exception vectors for the MIPS PR4450 reside in kseg0 or kseg1 depending on
the value of the MIPS PR4450 internal Boot Exception Vector (BEV) bit. These
exception vectors and the corresponding virtual and physical address locations are
shown in the following table.
Table 4: MIPS PR4450 Exception Vector Addresses
Exception BEV = 0 BEV = 1 (Reset Default)
Reset 0xbfc0 0000 0x1fc0 0000 0xbfc0 0000 0x1fc0 0000
Soft Reset
UTLB Miss 0x8000 0000 0x0000 0000 0xbfc0 0100 0x1fc0 0100
TLB Miss 0x8000 0080 0x0000 0080 0xbfc0 0180 0x1fc0 0180
TLB Modification
Bus Error
Non-Maskable
Interrupt
Address Error 0x8000 0080 0x0000 0080 0xbfc0 0180 0x1fc0 0180
Overflow
System Call
Break Point
Reserved
Instruction
Coprocessor
unusable
Interrupt
Debug 0xbfc0 0200 0x1fc0 0200 or
Note: The BEV bit is set to 1 during reset and typically set to 0 after boot of the operating
system.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
Virtual Address Physical
Address
0xbfc0 0000 0x1fc0 0000 0xbfc0 0000 0x1fc0 0000
0xff20 0200
Virtual Address Physical
Address
0xbfc0 0200 or
0xff20 0200
0x1fc0 0200 or
0xff20 0200
The MIPS PR4450 CPU on the PNX8550 has the option to relocate the except vector
base in kseg1 (when BEV=1) to a different address. The configurable bits are [28:12].
These bits can be programmed by writing into the MIPS_RESET_VECTOR register
in the global register 2 module during boot.
The boot script can use the reset remap mechanism to start the MIPS PR4450 at any
desired address e.g., from an XIO non-volatile memory or from initialized DRAM.
See Ch28 MIPS RISC Core Processor
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for more information.
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8.2 View from the TM3260 CPU Cores
The memory map seen by each TM3260 CPU core contains three apertures. Each
aperture is independent. Any address is a legal base address, including
0x0000 0000. Apertures for each TM3260 CPU should not be set to overlap or
extend across the 0xFFFF FFFF limit of 32-bit addressing conventions. The
apertures for each TM3260 are shown in the following block diagram.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
0xFFFF FFFFF
MMIO_BASE
TM32_APERT1_HI
TM32_APERT1_LO
TM32_DRAM_HI
TM32_DRAM_CLIMIT
TM32_DRAM_LO
0x0000 0000
Figure 6: Memory Map for TM3260 CPU Core
Inaccessible
2 MB
MMIO Aperture
Inaccessible
Aperture_1
Inaccessible
Non-cacheable
DRAM Aperture
Inaccessible
Each TM3260 CPU core requires all its apertures to be a multiple of 64 kB and reside
on a 64-kB boundary. They are programmed by writing to MMIO registers inside the
TM3260 CPU core, with the exception of the MMIO_BASE, which is directly taken
from the PCI Base14 register content. In the PNX8550, the TM32_DRAM_LO/HI
registers must be set to view the entire PNX8550 DRAM aperture. Protection can be
accomplished by using the TM_REGION_LO/HI registers, as described in
Section 7.2
.
Each TM3260 CPU can access the DRAM aperture with all load and store
instructions. Loads and stores in the cacheable area use the data cache. Loads and
stores in the non-cacheable area bypass the data cache and go directly to memory
across the memory interface. Execution is supported from the entire DRAM aperture,
which always uses the instruction cache.
Upon either reset, TM3260 CPU puts all registers and cache control in its defined
initial state. It does not start program execution. Program execution is started when
the code for “start” is written to the TM32_CTL MMIO register. Execution starts at the
address contained in the TM32_START_ADDR MMIO register and the boot address
is therefore flexible. Also, the addresses for the exception vectors are programmable
and do not put any constraints on the system design.
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Aperture_1 is not normally used in the PNX8550. It is enabled by writing a
TM32_APERT1_HI greater than TM32_APERT1_LO. In that case, loads/stores to
such addresses cause (non-cached) accesses across the TDCS bus. In special
applications of the PNX8550, this could be used to map (part of) PCI and/or XIO
directly into the TM3260 address map.
Remark: Due to the TM3260 CPU core architecture and compiler code generator, it does
speculative loads i.e., it may perform loads to any location in its address map without an explicit
request. The MMIO devices inside the
or XIO devices may be able to do so. For this reason, direct mapping of PCI or XIO is not
generally recommended.
See Ch29 TM3260 CPU Core Processor for more information.
8.3 View from PCI Bus
There are two different cases to consider for PCI:
PNX8550
Chapter 2: Bus Architecture and System Memory Map
PNX8550 are designed to cope with this, but not all PCI
• The PNX8550 is PCI configuration manager. Its CPU allocates base addresses
for all PCI components in the system.
• An external CPU is PCI configuration manager on the PCI bus and the PNX8550
is one of the components.
8.3.1 PNX8550 as PCI Configuration Manager
As PCI configuration manager, the PNX8550 builds the standard system memory
map. External PCI bus masters see the memory map, but can only access the
PNX8550 DRAM and MMIO apertures and other PCI target devices, not the XIO
aperture
0xFFFF FFFF
Base14 (MMIO_BASE)
Base10 (DRAM_BASE)
Figure 7: PNX8550 (as seen from a PCI Bus Master - #1)
0x0000,0000
PNX8550 MMIO (2 MB)
PNX8550 DRAM
8.3.2 An External Host CPU as PCI Configuration Manager
In this case, the host CPU PCI BIOS builds the system memory map. The host CPU
assigns each PNX8550 in the system a unique Base10, Base14 and Base18 per the
procedure described in Section 6.1
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.
Page 77
Philips Semiconductors
Usually, apertures of a given device end up adjacent to one another. In a X86 PC,
apertures typically end up near the high-end of the 4-GB address space. Address 0 is
never used as the first 640 kB are used by the PC. Other host CPUs may have their
own conventions. In general, no assumptions should be made about the resulting
memory layout, other than that apertures don’t overlap.
Note the PCI specification requires an aperture to be aligned at a boundary which is
the same size as the aperture e.g., a 128-MB aperture will be located at a 128-MB
boundary. External PCI bus masters see the memory map, but can only directly
access the PNX8550 DRAM and MMIO apertures, not the XIO aperture.
See Figure 8
It is possible for the external host CPU to do an indirect access to PNX8550 XIO by
writing to the PCI XIO module MMIO registers to request a single cycle XIO access or
a XIO DMA transaction.
PNX8550
Chapter 2: Bus Architecture and System Memory Map
.
0xFFFF FFFF
PNX8550 MMIO (2 MB)
Base14 (MMIO_BASE)
PNX8550 DRAM
Base10 (DRAM_BASE)
0x0000 0000
Figure 8: PNX8550 (as seen from a PCI Bus Master - #2)
8.4 View from the MDCS and TDCS Buses
Accessibility from the MDCS and TDCS buses is shown in Figure 9 on page 2-16.
DRAM is accessible to all peripherals.
Peripherals on the MDCS bus can access DRAM, PCI, or XIO apertures. On the
TDCS bus, only the DRAM aperture is visible to the peripherals. Each TM3260 will
typically be enabled to access its DRAM and MMIO apertures only due to the fact that
XIO and PCI peripherals may be sensitive to speculative reads generated by the
TM3260’s. However, both TM3260’s can be enabled to also access the PCI1/2 and
XIO apertures if the speculative read feature is disabled during code compilation.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Philips Semiconductors
Only the Boot, PCI, MIPS PR4450, TM3260 and EJTAG modules are allowed to
access MMIO space. Accesses from all other peripherals are blocked.
Base18
Aperture size
Base18
2MB
PNX8550
Chapter 2: Bus Architecture and System Memory Map
4GB
XIO
MMIO - TDCSC
Base14
pci_base2_hi
pci_base2_lo
pci_base1_hi
pci_base1_lo
dram_hi
dram_lo
MMIO - MDCSC
PCI2
PCI1
DRAM
0
Figure 9: View from MDCSC and TDCSC Buses
8.5 MMIO Base Address Map
Table 5 lists the peripherals accessed using the MMIO aperture. This is the PCI
Configuration register 14.
Table 5: MMIO Segments
Aperture
Module Name
Start
MDCS Bus
M-Default Slv 00_0000 248 kB MDCS MMIO (Base 14) Ch04
GIC_MIPS 03_E000 4 kB MDCS MMIO (Base 14) Ch11
IPC_MIPS 03_F000 4 kB MDCS MMIO (Base 14) Ch11
PCI/XIO 04_0000 4 kB MDCS MMIO (Base 14) Ch13
JTAG DMA 04_1000 4 kB MDCS MMIO (Base 14) Ch46
M-Default Slv 04_2000 4 kB MDCS MMIO (Base 14) Ch04
SmartCard1 04_3000 4 kB MDCS MMIO (Base 14) Ch16
SmartCard2 04_4000 4 kB MDCS MMIO (Base 14)
IIC1 04_5000 4 kB MDCS MMIO (Base 14) Ch20
IIC2 04_6000 4 kB MDCS MMIO (Base 14)
Clocks 04_7000 4 kB MDCS MMIO (Base 14) Ch08
USB 04_8000 4 kB MDCS MMIO (Base 14) Ch19
M-Default Slv 04_9000 4 kB MDCS MMIO (Base 14) Ch04
UART1 04_A000 4 kB MDCS MMIO (Base 14) Ch18
UART2 04_B000 4 kB MDCS MMIO (Base 14)
Aperture
Size
MMIO
Segment
Reference Base
Address
DRAM
Refer to
Chapter
-
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Page 79
Philips Semiconductors
PNX8550
Chapter 2: Bus Architecture and System Memory Map
Table 5: MMIO Segments
Module Name
IIC4 04_C000 4 kB MDCS MMIO (Base 14) Ch21
Global Regs 2 04_D000 4 kB MDCS MMIO (Base 14) Ch12
MDCSC 04_E000 4 kB MDCS MMIO (Base 14) Ch04
D2D 04_F000 68 kB MDCS MMIO (Base 14) Ch37
Reset 06_0000 4 kB MDCS MMIO (Base 14) Ch09
TMDBG1 06_1000 4 kB MDCS MMIO (Base 14) Ch47
TMDBG2 06_2000 4 kB MDCS MMIO (Base 14)
Global Regs 1 06_3000 4 kB MDCS MMIO (Base 14) Ch12
PMAN Arbiter 06_4000 4 kB MDCS MMIO (Base 14) Ch03
MCU 06_5000 4 kB MDCS MMIO (Base 14) Ch14
PMAN Security 06-6000 4 kB MDCS MMIO (Base 14) Ch03
PMAN Monitor 06-7000 4 kB MDCS MMIO (Base 14) Ch03
MDCN Security 06_8000 4 kB MDCS MMIO (Base 14) Ch04
IIC3 06_9000 4 kB MDCS MMIO (Base 14) Ch21
M-Default Slv 06_A000 600 kB MDCS MMIO (Base 14) Ch04
Aperture End 0F-FFFF Total size
TDCS Bus
T-Default Slv 10_0000 8 kB TDCS MMIO (Base 14) Ch04
GIC-TM32_1 10_2000 4 kB TDCS MMIO (Base 14) Ch11
TDCSC 10_3000 4 kB TDCS MMIO (Base 14) Ch04
GPIO 10_4000 4 kB TDCS MMIO (Base 14) Ch17
VMPG 10_5000 4 kB TDCS MMIO (Base 14) Ch42
VIP1 10_6000 4 kB TDCS MMIO (Base 14) Ch30
VIP2 10_7000 4 kB TDCS MMIO (Base 14)
VLD 10_8000 4 kB TDCS MMIO (Base 14) Ch43
SPDO 10_9000 4 kB TDCS MMIO (Base 14) Ch27
SPDI1 10_A000 4 kB TDCS MMIO (Base 14) Ch26
DVDD 10_B000 4 kB TDCS MMIO (Base 14) Ch44
MBS1 10_C000 4 kB TDCS MMIO (Base 14) Ch31
QTNR 10_D000 4 kB TDCS MMIO (Base 14) Ch34
QVCP1 10_E000 4 kB TDCS MMIO (Base 14) Ch33
QVCP2 10_F000 4 kB TDCS MMIO (Base 14)
AO1 11_0000 4 kB TDCS MMIO (Base 14) Ch25
AI1 11_1000 4 kB TDCS MMIO (Base 14) Ch24
AO2 11_2000 4 kB TDCS MMIO (Base 14) Ch25
AI2 11_3000 4 kB TDCS MMIO (Base 14) Ch24
EDMA 11_4000 4 kB TDCS MMIO (Base 14) Ch40
…Continued
Aperture
Start
Aperture
Size
= 1MB
MMIO
Segment
Reference Base
Address
Refer to
Chapter
-
-
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Page 80
Philips Semiconductors
Table 5: MMIO Segments …Continued
Module Name
TDCN Security 11_5000 4 kB TDCS MMIO (Base 14) Ch04
TSDMA 11_6000 4 kB TDCS MMIO (Base 14) Ch39
DENC 11_7000 4 kB TDCS MMIO (Base 14) Ch35
MSP1 11_8000 32 kB TDCS MMIO (Base 14) Ch41
MSP2 12_0000 32 kB TDCS MMIO (Base 14)
T-Default Slv 12_8000 32 kB TDCS MMIO (Base 14) Ch04
T-Default Slv
Reserved for
TM3260_1 Cache
Ta gs
TM3260_1 MMIO
T Default Slv 14_2000 56 kB TDCS MMIO (Base 14) Ch04
T-Default Slv
Reserved for
TM3260_2 Cache
Ta gs
TM3260_2 MMIO
T Default Slv 16_2000 56 kB TDCS MMIO (Base 14) Ch04
GIC_TM32_2 17_0000 4 kB TDCS MMIO (Base 14) Ch11
IPC_TM32_1 17_1000 4 kB TDCS MMIO (Base 14)
IPC_TM32_2 17_2000 4 kB TDCS MMIO (Base 14)
VPK 17_3000 4 kB TDCS MMIO (Base 14) Ch36
MBS2 17_4000 4 kB TDCS MMIO (Base 14) Ch32
SPDI2 17_5000 4 kB TDCS MMIO (Base 14) Ch26
T -Default Slv 17_6000 36 kB TDCS MMIO (Base 14) Ch04
Tunnel
Configuration
Tunnel MMIO
Aperture End 1F-FFFF Total size
1 This aperture is the TM3260 internal view of the TM3260 registers.
Each TM3260 only sees it’s own registers here i.e., PNX8550 aperture
14_0000 maps to TM1 10_0000. PNX8550 aperture 16_0000 maps to TM2
10_0000.
2
Each TriMedia sees the lower 64 kB of the MMIO aperture as cache i.e.,
PNX8550 aperture 13_0000 maps to TM1 00_0000. PNX8550 aperture
15_0000 maps to TM2 00_0000.
3
The tunnel configuration sets its aperture size from 4kB to 514kB if the tunnel
is not in use.
4
DRAM access from an external PCI master uses the Base 10 register from
PCI Configuration space when the en_pci2mmi is set to 1. Any address in the
XIO range is routed to the XIO block in the PCI module. Transactions to XIO
originating on the TDCS network are forwarded across a bridge.
Chapter 2: Bus Architecture and System Memory Map
Aperture
Start
2
13_0000 64 kB TDCS MMIO (Base 14) Ch04
1
14_0000 8 kB TDCS MMIO (Base 14) Ch29
2
15_0000 64 kB TDCS MMIO (Base 14)
1
16_0000 8 kB TDCS MMIO (Base 14) Ch29
17_F000 4 kB TDCS MMIO (Base 14) Ch15
3
4
18_0000 512 kB TDCS MMIO (Base 14)
Aperture
Size
= 1MB
MMIO
Segment
Reference Base
Address
PNX8550
Refer to
Chapter
-
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Page 81
Philips Semiconductors
PNX8550
Chapter 2: Bus Architecture and System Memory Map
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Preliminary data Rev. 02 — July 21 2004 2-19
Page 82
1. Introduction
Chapter 3: PMAN Hub
PNX8550 User Manual
Rev. 02 — July 21 2004 Preliminary data
This document describes the design details of the DVI_HUB Memory Access
Infrastructure (aka DMA-HUB or “the HUB”) in the PNX8550. The design is based on
the Pipelined Memory Access Network (PMAN) technology specification. In addition
to the Network function, the HUB includes a generic arbiter for data flow control within
complex memory systems and the PMAN Security block. See Figure 1
for more details.
The PMAN or Hub provides DMA data paths and control which link most of the
Peripheral devices with the main memory controller, allowing data to be read from or
written to main memory at a very high rate. The Arbiter controls which Peripheral
gains access to the main memory controller via the Hub and the PMAN Security block
provides for the separation of memory areas within main memory, so as to limit
unintentional interference by a mis-programmed peripheral.
and Figure 2
1.1 Features
The key features of the HUB are:
• Provides a hierarchical memory access network that connects Peripheral DMA
ports to a single access port of the System Memory Controller.
• Includes simple round-robin sub-arbitration for lower levels of hierarchy.
• Utilizes the IP_1010 arbiter to provide sophisticated intermediate arbitration for
upper levels of the network hierarchy.
• Includes a security mechanism to limit memory access of Peripherals to
programmable regions in system memory (dvi_msec).
• Provides data synchronization, transaction buffering and partitioning
mechanisms.
• Supports Tunnel-to-QVCP data streaming mode.
• Supports MBS2→VPK→QVCP data streaming mode.
• Includes a memory access “gate” for MMIO transactions, for debug applications
via EJTAG.
Page 83
Philips Semiconductors
2. Functional Description
2.1 PNX8550 HUB Block
The following diagram shows the Hub as it interconnects within the PNX8550 system.
PNX8550
Chapter 3: PMAN Hub
CAB
CAB
DCS
DCS
Security
Security
DCS Ctrl
DCS Ctrl
GIC-MIPS
GIC-MIPS
IPC-MIPS
IPC-MIPS
CLOCKSCAB
CLOCKSCAB
BOOT
BOOT
GLB REG1
GLB REG1
GLB REG2
GLB REG2
RESET
RESET
TM DBG1
TM DBG1
TM DBG2
TM DBG2
UART1
UART1
UART2
UART2
IIC3
IIC3
IIC4
IIC4
DDR
DDR
T
T
Controller
Controller
R
R
R
DMA
DMA
DMA
DMA
R
W
W
W
W
Pipelined Memory Access Network
Pipelined Memory Access Network
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
T
T
T
T
T
T
T
T
T
T
I
I
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
I
I
PR4450
PR4450
T
T
Monitor
Monitor
PMAN
PMAN
T
T
MIPS – Device Control and Status Network
MIPS – Device Control and Status Network
T
T
T
T
T
T
PCI/XIO
PCI/XIO
I
I
T
T
T
T
T
T
T
T
USB Host
USB Host
T
T
Scard1
Scard1
T
T
SCard2
SCard2
T
T
DMA Gate
DMA Gate
DMA Gate
DMA Gate
Security
Security
PMAN
PMAN
Arbiter
Arbiter
EJTAG
EJTAG
DE
DE
IIC1
IIC1
IIC2
IIC2
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
TM32_1
TM32_1
TM32_2
TM32_2
QVCP5L
QVCP5L
QVCP2L
QVCP2L
VPK
VPK
DVD/CSS
DVD/CSS
VIP1
VIP1
VIP2
VIP2
MBS
MBS
MBS2
MBS2
QTNR
QTNR
EDMA
EDMA
VLD
VLD
TSDMA
TSDMA
VMPG
VMPG
MSP1
MSP1
MSP2
MSP2
T
T
I
I
T
T
I
I
TR
TR
TR
TR
TM – Device Control and Status Network
TM – Device Control and Status Network
T
T
T
T
TW
TW
TW
TW
T
T
T
T
T
T
T
T
T
T
TR
TR
T
T
T
T
T
T
T
T
Security
Security
T
T
DCS Ctrl
DCS Ctrl
T
T
GIC-TM32_1
GIC-TM32_1
T
T
GIC-TM32_2
GIC-TM32_2
T
T
IPC-TM32_1
IPC-TM32_1
T
T
IPC-TM32_2
IPC-TM32_2
T
T
DENC
DENC
T
T
SPDI-O
SPDI-O
T
T
SPDI-I1
SPDI-I1
T
T
SPDI-I2
SPDI-I2
T
T
AI1
AI1
T
T
AI2
AI2
T
T
AO1
AO1
T
T
AO2
AO2
T
T
GPIO
GPIO
T
T
Tunnel
Tunnel
DCS
DCS
DAC
DAC
R
R
W
W
W
W
W
W
W
W
R
R
R
R
R
R
W
W
R
R
W
W
Pipelined Memory Access Network
Pipelined Memory Access Network
T
T
T
Bridge
Bridge
Bridge
I
I
I
MDCN TDCNPMAN
MDCN TDCNPMAN
I
I
I
T
T
T
PMAN
PMAN
Figure 1: PNX8550 System Block Diagram
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-2
Page 84
Philips Semiconductors
Figure 2 shows the Hub and Peripheral Devices that transfer data via the Hub.
DTL- M MIO
DTL- M MIO
PMAN
PMAN
Security
Security
PMAN
PMAN
Arbiter
Arbiter
PCI/XIO
PCI/XIO
DE
DE
IIC1
IIC1
IIC2
IIC2
USB Host
USB Host
Scard1
Scard1
SCard2
SCard2
DMA Gate
DMA Gate
SPDI-O
SPDI-O
SPDI-I1
SPDI-I1
SPDI-I2
SPDI-I2
AI1
AI1
AI2
AI2
PNX8550
Chapter 3: PMAN Hub
MTL
MTL
R
R
QVCP2L
QVCP2L
R
R
DVD/CSS
DVD/CSS
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
W
W
W
W
W
W
Pipelined Memory Access Network (PMAN)
Pipelined Memory Access Network (PMAN)
W
W
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
R
R
W
W
VIP1
VIP1
VIP2
VIP2
MBS
MBS
QTNR
QTNR
EDMA
EDMA
VLD
VLD
TSDMA
TSDMA
VMPG
VMPG
MSP1
MSP1
MSP2
MSP2
MSP2
MSP2
MBS2
MBS2
VPK
VPK
R
AO1
AO1
AO2
AO2
GPIO Tunnel
GPIO Tunnel
R
R
R
R
R
W
W
Figure 2: PMAN or Hub Block Diagram
2.2 Architecture
The DVI_HUB module contains the following blocks:
• PMAN Arbiter (IP_1010)
• PMAN Security (DVI_MSEC)
• PMAN Infrastructure Blocks
• DMA Adapters (DTL to MTL) (aka “Gizmos”)
• DMA Gate (MGATE)
R
R
W
W
R
R
QVCP5L
QVCP5L
Alterna te
Alterna te
Streaming
Streaming
Interface
Interface
Paths
Paths
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-3
Page 85
Philips Semiconductors
2.2.1 PMAN Arbiter (IP_1010)
The Arbiter module is used as an arbiter between different DMA channel clusters.
Inside these clusters traffic from related DMA channels of Peripherals are combined
by applying round-robin arbitration. (See Tab l e 1
arbitrated DMA channels.)
The arbitration engine combines Time-Division Multiple Access (TDMA), priority, and
round-robin methods; resulting in a guaranteed and high-level quality of service. The
arbitration engine ensures programmable maximum latency and programmable
minimal bandwidth to the unified resource. It also makes sure that best effort agents
are fairly granted when higher priority agents do not request the channel.
The priority table can be dynamically altered by software. Two priority tables are
implemented from which the inactive table can be changed on-the-fly. The Arbiter
hardware takes care of smooth switching between the two tables.
After reset, the Arbiter is in “boot” mode and guarantees that each requesting agent is
given a “grant” to main memory (Round Robin is the default arbitration method).
PNX8550
Chapter 3: PMAN Hub
for a list of clusters and sub-
Arbiter Features
• Time-Division Multiple Access (TDMA) arbitration
– guarantees maximum allowed latency
– 128 TDMA slots
• Priority arbitration
– guarantees minimum required bandwidth
– 16 Priority slots
• Two-level Round Robin arbitration
– provides equal opportunities to the lower priority “best effort” or DMA write
agents
– 16 round robin slots in the first level
– 8 round robin slots in the second level
• Dynamic arbitration scheme
– Two sets of arbitration parameters can be defined. Selection can be made
dynamically via software based on system needs.
ID Mapping
Table 1 shows the mapping of each peripheral device to unique identification
numbers. It also shows the amount of subarbitration for the given peripherals. Unless
otherwise noted, the amount of buffering per DMA channel is 256 bytes.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-4
Page 86
Philips Semiconductors
.
Table 1: Peripheral ID and Subarbitration
ID Peripheral Monitor ID
0 VMPG 0x00 0x00 0x0 2 x R, 3 x W
1 DVDD 0x04 0x01 0x0 1 x R, 1 x W
2 EDMA 0x08 0x02 0x0 1 x R, 1 x W
3 VLD 0x20 0x03 0x0 1 x R, 2 x W
4 QVCP2L 0x24 0x04 0x0 4 x R
5 MBS (R) 0x40 0x05 0x0 3 x R
6 MBS (W) 0x44 0x06 0x0 3 x W
7 MBS2 (R) 0x48 0x07 0x0 3 x R
8 MBS2 (W) 0x4C 0x08 0x0 3 x W
9 QTNR (R) 0x50 0x09 0x0 3 x R
10 QTNR (W) 0x54 0x0A 0x0 3 x W
11 QVCP5L 0x60 0x0B 0x0 8 x R
12 SPDIF I/O 0x80 0x0C 0x0 1 x R, 1 x W
13 TUNNEL 0x84 0x0D 0x0 1 x R/W
14 USB 0xA0 0x0E 0x0 1 x R, 1 x W
15 DE 0xA4 0x0F 0x0 1 x R, 1 x W
16 PCI 0xA8 0x10 0x0 2 x R, 2 x W
17 SMC1, SMC2 0xAC 0x11 0x0 2 x R, 2 x W
18 IIC 0xB0 0x12 0x0 2 x R/W
19 MGATE 0xB4 0x13 0x0 1 x R/W
20 VIP1 0xC0 0x14 0x0 3 x W
21 VIP2 0xC4 0x15 0x0 3 x W
22 VPK 0xC8 0x16 0x0 1 x R, 2 x W
23 TSDMA 0xCC 0x17 0x0 1 x R/W
24 MSP1 0xE0 0x18 0x0 2 x R, 3 x W
25 MSP2 0xE4 0x19 0x0 2 x R, 3 x W
PNX8550
Chapter 3: PMAN Hub
Security
Status ID
AI/O1 0x81 0x0C 0x1 1 x R, 1 x W
AI/O2 0x82 0x0C 0x2 1 x R, 1 x W
GPIO 0x83 0x0C 0x3 1 x R, 1 x W
Security
Status Sub ID
DMA Channels
2.2.2 PMAN Security
The PMAN Security block (dvi_msec for “memory security”) will invalidate memory
access to all locations that are not inside any of a peripheral’s assigned sandbox
(memory access region). There are four sandboxes defined via a lower and upper
address limit for each sandbox. Each peripheral device can be associated with each
sandbox under software control. The sandbox access information is held in a set of
registers with a dedicated entry for each peripheral (some blocks share a common
set of registers, for example SMC1 and SMC2).
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-5
Page 87
Philips Semiconductors
Access to these registers can be enabled/disabled for every initiator via the DCS
security module. In the
by the MIPS processor.
Implementing 4 sandboxes allows a sandbox for both the MIPS and TM3260controlled peripherals, plus 2 additional sandboxes for special purposes. The
sandboxes adhere to the following rules:
PNX8550
Chapter 3: PMAN Hub
PNX8550 system, the sandbox registers can only be written
• Sandbox address ranges can be overlapping.
• Granularity of the address range is 64 kB.
• There are 2 registers for each sandbox:
– Sandbox Base Address
– Sandbox Top Address
• A peripheral can be assigned to several or no sandboxes.
• There is no support for an inverted sandbox (Base_Address > Top_Address).
In case a peripheral attempts an access where the address is not within the range of
any of the enabled sandboxes (or if no sandbox is enabled for this peripheral), the
following will happen:
• ‘0xdeadda7a’ is returned on reads.
• Writes will be blocked by setting all write mask bits to zero.
• An interrupt is generated. (If the interrupt is enabled, then a processor is notified
of the event.)
In the case of an access violation, the address value and ID value of the attempted
access is stored in the “Protection Error Address” and Interrupt Status registers within
the dvi_msec module. In case of multiple violators, only the address and ID of the first
violator are stored. The Protection Error Address register can be ‘re-opened’ to store
the new Address and ID values by clearing the “Memory Access protection Error”
status bit (STAT_PROT_ERR).
2.2.3 DMA Gate
The DMA gate is simply a DTL-to-DTL connection between a DTL-MMIO “initiator”
and a DTL-DMA “target” within the Hub. Any 32-bit read or write transaction that is in
the range of DMA_GATE_LO to DMA_GATE_HI will cause a read or write transaction
to main memory via the DMA Gate. This is provided as a special test path by EJTAG
and is not generally used by normal operating software. See Figure 3
Address Mapping.
DMA Gate
The DMA_GATE_LO and DMA_GATE_HI registers are located in the Global
Registers. See Chapter 12
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Global registers.
Page 88
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PNX8550
Chapter 3: PMAN Hub
DMA_GATE_HI
DMA_GATE_LO
dram_hi
dram_lo
Figure 3: DMA Gate Address Mapping
Memory Space
4GB
DDR Memory
0
2.2.4 Memory Bandwidth Monitor
The Memory Bandwidth Monitor block contains three 40-bit counters that are capable
of counting memory transaction events as they arrive at the DDR Memory Controller.
Each counter has a configuration register that will determine the transaction type,
monitor mode, the specific memory interface (MTL) port of the DDR Memory
Controller that shall be selected for monitoring, and the Hub device ID (if the Hub is
selected for monitoring). A single control register is used to start or stop the counting
process so that the counters will start or stop together, assuring consistency in the
measurements that are obtained.
Each counter is capable of counting in units of memory clocks, number of
transactions (memory requests), bandwidth (i.e., the number of bytes transferred),
memory controller idle time (in memory clock cycles), and latency (in memory clock
cycles).
By using different combinations of units and by monitoring different memory ports,
one can obtain information that can be extremely useful in determining the
performance of the memory subsystem and/or the overall PNX8550 system.
See Section 4.2
PMAN Security Registers for more information on the programming
of this unit.
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3. General Operations
3.1 Data Flow and Control
3.1.1 Arbitration Algorithm
One of the most important purposes of the arbiter is to guarantee a high level of
quality service to the DMA agents (peripheral devices). In technical terms this means:
• the ability to guarantee a programmable maximum latency to DMA agents
• the ability to guarantee a programmable amount of bandwidth to DMA agents
• the ability to provide equal opportunity to DMA agents
• any (complex) combination of the three mechanisms mentioned above
The arbiter does not process requests for memory access from CPUs (MIPs and
TriMedia). Typically the performance of CPUs depends directly on the access latency
to memory and for this reason they require the lowest possible memory latency. To
realize this CPUs can best get their performance requirements via a private port on a
multi-port memory controller. Therefore, the CPUs are not connected to the arbiter
and do not route memory requests via the Hub.
PNX8550
Chapter 3: PMAN Hub
To support the quality of service features as mentioned above the arbiter algorithm
consists of a combination of three basic arbitration mechanisms. These are:
• Time-Division Multiple Access (TDMA) arbitration to guarantee maximum latency
• priority arbitration to guarantee bandwidth to reading Soft Real Time DMA (SRT
DMA) agents
• round-robin arbitration to guarantee bandwidth to writing SRT DMA agents
• round-robin arbitration to provide equal opportunity for Best Effort (BE) DMA
agents
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The combination of these three basic algorithms operate together in the arbiter as
shown in Figure 4
.
Timing Wheel
PNX8550
Chapter 3: PMAN Hub
TDMA
highest
high
priority list
low
overall priority
round robin #1
round robin #2
lowest
Figure 4: Arbitration Scheme
The TDMA timing wheel is implemented with 128 entries, numbered 1 to 128. The
TDMA_entries field in the NR_entries_A
1
register will determine the actual number of
entries that are used. TDMA entries higher than this value will be ignored. If the
TDMA_entries is greater than 128 then all 128 entries are used, but no more. If
TDMA_entries is set to zero then the TDMA timing wheel is not used for arbitration.
The priority list is implemented with 16 entries, numbered 1 to 16. The Priority_entries
field in the NR_entries_A register will determine the actual number of entries that are
used. If a value greater than 16 is written all 16 entries are used, but no more. If the
Priority_entries is set to zero then the priority list is not used for arbitration.
The round robin #1 list is implemented with 16 entries, numbered 1 to 16. The
round_robin1_entries field in the NR_entries_A register will determine the actual
number of entries that are used. If a value greater than 16 is written all 16 entries are
used, but no more. If the
round_robin1_entries is set to zero then the round robin #1 list
is not used for arbitration.
The round robin #2 list is implemented with 16 entries, numbered 1 to 8. The
round_robin2_entries field in the NR_entries_A register will determine the actual
number of entries that are used. If a value greater than 8 is written all 8 entries are
used, but no more. If the
round_robin2_entries is set to zero then the round robin #2 list
is not used for arbitration.
1. All references to “Set A” registers also apply equally to “Set B”.
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Assuming the arbiter has been configured to include the priority list and both roundrobin lists, any arbiter decision is made through the following four steps:
1. First the DMA requests are compared against the current entry in the TDMA
2. If the agent in the current entry is not requesting the DMA requests will be
3. If none of the DMA requests matches the current entry in the TDMA timing wheel
4. If none of the DMA requests matches (e.g., the current entry in the TDMA timing
PNX8550
Chapter 3: PMAN Hub
timing wheel. If the agent in the current entry is requesting this agent will be
granted.
compared against the agents in the priority list and if one or more of the agents in
the priority list is requesting the one that has the highest priority will be granted.
or one or more entries in the priority list, the arbiter will grant the DMA agent that
has not been served for the longest time by choosing from the round robin #1 list.
Every time the arbiter provides a grant to any DMA agent, the round robin #1
arbiter checks if this agent is in it’s list and makes that agent the lowest priority
entry in the round robin #1 list. If a certain agent is granted because of it’s entry in
the TDMA timing wheel or priority list and the same agent has also an entry in the
round-robin #1 list, then in the next clock cycle this agent will have the lowest
priority in the round-robin #1 list. Also, in case there are multiple entries of the
same agent in the round-robin #1 list, the highest entry in the list gets the lowest
priority during the next cycle. The other entries of the same agents do not get the
lowest priority.
wheel, or one or more entries in the priority list, or one or more entries in the first
round-robin list), the arbiter will grant the DMA agent that has not been served for
the longest time from the round robin #2 list of entries. The round-robin #2 list
operates the same way as the round-robin #1 list, but all entries in the #2 list
have a lower priority than those in the #1 list.
The TDMA wheel will only proceed to the next entry if one of the two following
situations applies:
• there is a grant at the level of the TDMA wheel
• there is no match in the complete list (TDMA, priority and both round-robin lists)
All entries in the TDMA wheel, priority list and both round-robin lists are fully
programmable via the DTL MMIO interface of the arbiter. The same is true for the
number of entries in any of these four. It is also possible to set the number of entries
in the TDMA wheel, priority list and/or round-robin lists to zero. This allows the user to
use only one of the four mechanisms or any combination of them. In case all four are
set to zero for the active set of entries, the arbiter defaults to a round-robin arbitration
over all agents.
The arbitration algorithm only starts after the arbiter has been properly initialized via
the programming registers. Following the de-assertion of a hard reset, the arbiter
uses a simple counting algorithm to arbitrate between all request inputs. In this boot
mode, agents are granted in the order that they are internally wired.
Arbiter Startup Behavior
After reset is de-asserted, the arbiter is placed in boot mode. In this mode, the arbiter
sequentially grants each agent access to the memory if the agent has asserted its
request. After de-assertion of rst_an starting with req[0], then req[1], etc. Four agents
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are checked in each clock cycle. This means that in the situation that only req[15] is
asserted, it will take four clock cycles before the arbiter will grant this agent. In the
first clock cycle it will check req[0] up to req[3], in the second clock cycle req[4] up to
req[7], in the third clock cycle req[8] up to req[11] and the fourth clock cycle req[12] up
to req[15]. The boot counter increments to next value when all agents corresponding
to that count value have been serviced or when there is no request from the agents
corresponding to that count value.
This mode is not intended to intelligently allocate memory bandwidth. Its goal is to
simply make sure that all agent requests are granted. While in boot mode, it is
expected that the system software will set up the arbiter via the DTL MMIO port and
switch to the normal operation mode. As there are two sets of configuration registers
(A and B), software should initialize one of the sets and then select the normal
operation mode that corresponds to that set via a write to the Arbiter Control register.
If necessary, the alternate set may be configured differently and the new
configuration may be engaged by simply writing the new mode in the Arbiter Control
register.
3.2 Standard Features
PNX8550
Chapter 3: PMAN Hub
3.2.1 Clock Programming
The Hub operates with the Memory Controller clock, as well as the clocks of all the
peripheral modules that connect to the Hub. There is no separate clock for the Hub.
3.2.2 Reset-Related Issues
A partial reset of the HUB data transfer buffers not possible on a global basis. Each
peripheral device may use an Abort at the DTL-DMA interface to clear transactions
that may be pending within the data transfer buffers for that peripheral.
3.2.3 Register Programming Guidelines
The default configuration of the Arbiter is to provide Round Robin access to all
peripheral devices. This can be altered by software by programming the Arbiter. Once
the Arbiter configuration is completed, the system should be able to operate without
further change to the Arbiter; however it is possible for software to change the Arbiter
configuration on-the-fly in order to change the minimum latency or the minimum
memory bandwidth that is available to each peripheral device.
Note that the active set of configuration registers (set A or set B) cannot be read by
software once that set is activated. The inactive set may be safely written or read. If
software needs to have access to the values within the active set, then a copy of
these values should be maintained in main memory as a reference.
The PMAN Security sandbox register settings must be initialized by software since
the default is for all peripherals to use sandbox #1. It is recommended that the
sandboxes be organized so that each processor (MIPS, TriMedia1 and TriMedia2)
and the peripherals that are associated with each processor have access to a
separate memory region. The memory regions may overlap if there is a need to share
I/O buffers with more than one processor. Note that there are separate enable bits for
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Chapter 3: PMAN Hub
“read” access and “write” access, allowing one processor and its peripherals to fully
access a memory region; while another processor may only have “read” access to
shared buffer or data space.
The fourth sandbox may be used for special purposes, such as inter-process
communication buffers and semaphores, etc.
4. Register Descriptions
4.1 PMAN Hub Arbiter Registers
4.1.1 Register Summary
.
Table 2: PMAN Hub Arbiter Register Summary
Offset Symbol Description
0x06 4000—41FC TDMA A 128 entries of TDMA timing wheel for set A
0x06 4200—423C PRIORITY A 16 entries of priority list for set A
0x06 4240—427C Reserved
0x06 4280—42BC FIRST Round Robin A 16 entries of first round robin list for set A
0x06 42C0—42FC Reserved
0x06 4300—431C LAST Round Robin A 8 entries of last round robin list for set A
0x06 4320—43FC Reserved
0x06 4400—45FC TDMA B 128 entries of TDMA timing wheel for set B
0x06 4600—463C PRIORITY B 16 entries of priority list for set B
0x06 4640—467C Reserved
0x06 4680—46BC FIRST Round Robin B 16 entries of first round robin list for set B
0x06 46C0—46FC Reserved
0x06 4700—471C LAST Round Robin B 8 entries of last round robin list for set B
0x06 4720—47FC Reserved
0x06 4800 NR Entries A Number of valid entries in arbitration lists for set A
0x06 4804 NR Entries B Number of valid entries in arbitration lists for set B
0x06 4808—48FC Reserved
0x06 4900 Control Register to control operation mode of arbiter
0x06 4904 Status Register to monitor operation mode of arbiter
0x06 4908—4FF8 Reserved
0x06 4FFC MODULE_ID Module ID and revision information
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PNX8550
Chapter 3: PMAN Hub
4.1.2 Register Table
Table 3: PMAN Hub Arbiter Registers
Bit Symbol Access Va lue Description
Arbiter Registers (Set A)
Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set A)
31:10 Reserved R 0 Ignored on write, read as zero.
9:8 R/W Grant R/W 0 Grant on read, write or both. This field must be a zero.
0x0 = grant independent whether it is a read or write
0x1 = reserved
0x2 = reserved
0x3 = reserved
7:5 Reserved R 0 Ignored on write, read as zero.
4:0 Agent_ID R/W 0 ID of the agent that is identified by this entry.
Offset 0x06 4200—423C Entries of Priority List (Set A)
Note: Offset 0x200 has the highest priority.
This register is identical to Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set A).
Offset 0x06 4280—42BC Entries of Round Robin List #1 (Set A)
This register is identical to Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set A).
Offset 0x06 4300—431C Entries of Round Robin List #2 (Set A)
This register is identical to Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set A).
Arbiter Registers (Set B)
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B)
31:10 Reserved R 0 Ignored on write, read as zero.
9:8 R/W Grant R/W 0 Grant on read, write or both. This field must be a zero.
0x0 = grant independent whether it is a read or write
0x1 = reserved
0x2 = reserved
0x3 = reserved
7:5 Reserved R 0 Ignored on write, read as zero.
4:0 Agent_ID R/W 0 ID of the agent that is identified by this entry.
Offset 0x06 4600—463F Entries of Priority List (Set B)
Note: Offset 0x06 4600 has the highest priority.
This register is identical to Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B).
Offset 0x06 4680—46BC Entries of Round Robin List #1 (Set B)
This register is identical to Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B).
Offset 0x06 4700—471C Entries of Round Robin List #2 (Set B)
This register is identical to Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B)
Offset 0x06 4800 NR_ENTRIES_A (Set A)
31:28 Reserved R/W 0 Ignored on write, read as zero.
27:24 round_robin2_entries R/W 0 Number of valid entries in last round robin list #2
Programming any value > SIZE_LAST_RR_LIST will result in use of
the full round-robin list.
23:21 Reserved R/W 0 Ignored on write, read as zero.
.
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PNX8550
Chapter 3: PMAN Hub
Table 3: PMAN Hub Arbiter Registers
Bit Symbol Access Va lue Description
20:16 round_robin1_entries R/W 0 Number of valid entries in first round robin list #1
15:13 Reserved R/W 0 Ignored on write, read as zero.
12:8 priority_entries R/W 0 Number of valid entries in priority list
7:0 TDMA_entries R/W 0 Number of valid entries in TDMA wheel
Offset 0x06 4804 NR_ENTRIES_B (Set B)
This register is identical to Offset 0x06 4800 NR_ENTRIES_A (Set A).
Offset 0x06 4900 Arbiter Control
31:2 Reserved R/W 0 Ignored on write, read as zero.
1:0 Arbiter_mode R/W 0 Operational mode of the Arbiter
Offset 0x06 4904 Arbiter Status
31:2 Reserved R 0 Ignored on write, read as zero.
1:0 Arbiter_status R 0 Operational status of the Arbiter
Offset 0x06 4FFC Arbiter Module_ID
31:16 Module_ID R 0x1010 Arbiter module ID number
15:12 Major_revision R 0
11:8 Minor_revision R 0
7:0 Aperture R 0 4 kB aperture size
…Continued
Programming any value > SIZE_FIRST_RR_LIST will result in use
of the full round-robin list.
Programming any value > SIZE_PRIO_LIST will result in use of full
priority list.
Programming any value > 0x080 will result in use of all 128 entries.
00 = Boot mode
01 = Use register set A.
10 = Use register set B.
11 = Reserved
00 = Boot mode
01 = Use register set A.
10 = Use register set B.
11 = Reserved
4.2 PMAN Security Registers
4.2.1 Register Summary
Table 4: PMAN Security Register Summary
Offset Symbol Description
0x06 6000 stat_addr_viol Protection Error Address
0x06 6004 write_protect Register Write Protect
0x06 6080 sbox1_lower Sandbox 1 lower
0x06 6084 sbox1_upper Sandbox 1 upper
0x06 6088 sbox2_lower Sandbox 2 lower
0x06 608C sbox2_upper Sandbox 2 upper
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PNX8550
Chapter 3: PMAN Hub
Table 4: PMAN Security Register Summary
Offset Symbol Description
0x06 6090 sbox3_lower Sandbox 3 lower
0x06 6094 sbox3_upper Sandbox 3 upper
0x06 6098 sbox4_lower Sandbox 4 lower
0x06 609C sbox4_upper Sandbox 4 upper
0x06 6100 sbox_enableVMPG Sandbox assignment VMPG
0x06 6104 sbox_enableDVDD Sandbox assignment DVDD
0x06 6108 sbox_enableEDMA Sandbox assignment EDMA
0x06 610C sbox_enableVLD Sandbox assignment VLD
0x06 6110 sbox_enableQVCP2L Sandbox assignment QVCP2L
0x06 6114 sbox_enableMBS_R Sandbox assignment MBS (read)
0x06 6118 sbox_enableMBS_W Sandbox assignment MBS (write)
0x06 611C sbox_enableMBS2_R Sandbox assignment MBS2 (read)
0x06 6120 sbox_enableMBS2_W Sandbox assignment MBS2 (write)
0x06 6124 sbox_enableQTNR_R Sandbox assignment QTNR (read)
0x06 6128 sbox_enableQTNR_W Sandbox assignment QTNR (write)
0x06 612C sbox_enableQVCP5L Sandbox assignment QVCP5L
0x06 6130 sbox_enableID12 Sandbox assignment SPDIO (1+2)
0x06 6134 sbox_enableTUNNEL Sandbox assignment TUNNEL
0x06 6138 sbox_enableUSB Sandbox assignment USB
0x06 613C sbox_enableDE Sandbox assignment DE
0x06 6140 sbox_enablePCI Sandbox assignment PCI
0x06 6144 sbox_enableSMC Sandbox assignment SMC (1+2)
0x06 6148 sbox_enableI2C Sandbox assignment I2C
0x06 614C sbox_enableMGATE Sandbox assignment MGATE
0x06 6150 sbox_enableVIP1 Sandbox assignment VIP1
0x06 6154 sbox_enableVIP2 Sandbox assignment VIP2
0x06 6158 sbox_enableVPK Sandbox assignment VPK
0x06 615C sbox_enableTSDMA Sandbox assignment TSDMA
0x06 6160 sbox_enableMSP1 Sandbox assignment MSP1
0x06 6164 sbox_enableMSP2 Sandbox assignment MSP2
0x06 6168—6FDC Reserved
0x06 6FE0 Interrupt Status PMAN Security Interrupt Status
0x06 6FE4 Interrupt Enable PMAN Security Interrupt Enable
0x06 6FE8 Interrupt Clear PMAN Security Interrupt Clear
0x06 6FEC Interrupt Set PMAN Security Interrupt set
0x06 6FFC Module ID
…Continued
Sandbox assignment AIO1
Sandbox assignment AIO2
Sandbox assignment GPIO
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Chapter 3: PMAN Hub
4.2.2 Register Table
Table 5: PMAN Security Registers
Bit Symbol Access Value Description
Offset 0x06 6000 Protection Error Address
31:3 STAT_ADDR[31:3] R 0x0 Address of transaction causing protection error
2:0 STAT_ADDR[2:0] R 0x0 Fixed
Offset 0x06 6004 Register Write Protect
31:1 R 0x0 Reserved
0 WRITE_PROTECT R/W 0x0 Writing a one to this register disables write access to the PSEC
module (except IRQ registers). Once set, this bit can only be
cleared by a hardware reset.
Offset 0x06 6080 Sandbox 1 Lower
31:16 SB1_BASE[31:16] R/W 0x0 Lower limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB1_BASE[15:0] R 0x0 Fixed at 0x0
Offset 0x06 6084 Sandbox 1 Upper
31:16 SB1_TOP[31:16] R/W 0xFFFF Upper limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic
15:0 SB1_TOP[15:0] R 0xFFFF Fixed at 0xFFFF
Offset 0x06 6088 Sandbox 2 Lower
31:16 SB2_BASE[31:16] R/W 0x0 Lower limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB2_BASE[15:0] R 0x0 Fixed at 0x0
Offset 0x06 608C Sandbox 2 Upper
31:16 SB2_TOP[31:16] R/W 0xFFFF Upper limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB2_TOP[15:0] R 0xFFFF Fixed at 0xFFFF
Offset 0x06 6090 Sandbox 3 Lower
31:16 SB2_BASE[31:16] R/W 0x0 Lower limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB2_BASE[15:0] R 0x0 Fixed at 0x0
Offset 0x06 6094 Sandbox 3 Upper
31:16 SB3_TOP[31:16] R/W 0xFFFF Upper limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB3_TOP[15:0] R 0xFFFF Fixed at 0xFFFF
Offset 0x06 6098 Sandbox 4 Lower
31:16 SB4_BASE[31:16] R/W 0x0 Lower limit of accessible space (this addess is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB4_BASE[15:0] R 0x0 Fixed at 0x0
Offset 0x06 609C Sandbox 4 Upper
31:16 SB4_TOP[31:16] R/W 0xFFFF Upper limit of accessible space (this address is included). Bits
[31:28] are ignored and not included in the comparison logic.
15:0 SB4_TOP[15:0] R 0xFFFF Fixed at 0xFFFF
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PNX8550
Chapter 3: PMAN Hub
Table 5: PMAN Security Registers
Bit Symbol Access Value Description
Offset 0x06 6100 Sandbox Enable VMSP
31:8 Reserved R 0x0
7 SB4_VMSP_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_VMSP_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_VMSP_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_VMSP_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_VMSP_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_VMSP_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_VMSP_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_VMSP_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6104 Sandbox Enable DVDD
31:8 Reserved R 0x0
7 SB4_DVDD_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_DVDD_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_DVDD_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_DVDD_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_DVDD_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_DVDD_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_DVDD_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_DVDD_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6108 Sandbox Enable EDMA
31:8 Reserved R 0x0
7 SB4_EDMA_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_EDMA_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_EDMA_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_EDMA_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_EDMA_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_EDMA_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_EDMA_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_EDMA_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 610C Sandbox Enable VLD
31:8 Reserved R 0x0
7 SB4_VLD_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_VLD_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_VLD_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_VLD_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_VLD_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_VLD_REN R/W 0x0 Sandbox 2 Read enable
…Continued
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PNX8550
Chapter 3: PMAN Hub
Table 5: PMAN Security Registers
Bit Symbol Access Value Description
1 SB1_VLD_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_VLD_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6110 Sandbox Enable QVCP2L
31:8 Reserved R 0x0
7 SB4_QVCP2L_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_QVCP2L_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_QVCP2L_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_QVCP2L_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_QVCP2L_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_QVCP2L_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_QVCP2L_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_QVCP2L_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6114 Sandbox Enable MBS_R
31:8 Reserved R 0x0
7 SB4_MBS_R_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_MBS_R_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_MBS_R_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_MBS_R_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_MBS_R_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_MBS_R_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_MBS_R_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_MBS_R_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6118 Sandbox Enable MBS_W
31:8 Reserved R 0x0
7 SB4_MBS_W_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_MBS_W_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_MBS_W_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_MBS_W_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_MBS_W_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_MBS_W_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_MBS_W_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_MBS_W_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 611C Sandbox Enable MBS2_R
31:8 Reserved R 0x0
7 SB4_MBS2_R_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_MBS2_R_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_MBS2_R_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_MBS2_R_REN R/W 0x0 Sandbox 3 Read enable
…Continued
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-18
Page 100
Philips Semiconductors
Table 5: PMAN Security Registers …Continued
Bit Symbol Access Value Description
3 SB2_MBS2_R_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_MBS2_R_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_MBS2_R_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_MBS2_R_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6120 Sandbox Enable MBS2_W
31:8 Reserved R 0x0
7 SB4_MBS2_W_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_MBS2_W_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_MBS2_W_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_MBS2_W_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_MBS2_W_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_MBS2_W_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_MBS2_W_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_MBS2_W_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6124 Sandbox Enable QTNR_R
31:8 Reserved R 0x0
7 SB4_QTNR_R_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_QTNR_R_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_QTNR_R_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_QTNR_R_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_QTNR_R_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_QTNR_R_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_QTNR_R_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_QTNR_R_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 6128 Sandbox Enable QTNR_W
31:8 R 0x0 Reserved
7 SB4_QTNR_W_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_QTNR_W_REN R/W 0x0 Sandbox 4 Read enable
5 SB3_QTNR_W_WEN R/W 0x0 Sandbox 3 Write enable
4 SB3_QTNR_W_REN R/W 0x0 Sandbox 3 Read enable
3 SB2_QTNR_W_WEN R/W 0x0 Sandbox 2 Write enable
2 SB2_QTNR_W_REN R/W 0x0 Sandbox 2 Read enable
1 SB1_QTNR_W_WEN R/W 0x1 Sandbox 1 Write enable
0 SB1_QTNR_W_REN R/W 0x1 Sandbox 1 Read enable
Offset 0x06 612C Sandbox Enable QVCP5L
31:8 Reserved R 0x0
7 SB4_QVCP5L_WEN R/W 0x0 Sandbox 4 Write enable
6 SB4_QVCP5L_REN R/W 0x0 Sandbox 4 Read enable
PNX8550
Chapter 3: PMAN Hub
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 3-19
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