Philips UM10110 Service Manual
UM10110_1
PNX8550 Programmable Source Decoder
with Integrated Peripherals
Rev. 02 — July 21 2004
Philips Semiconductors
Contents
Chapter 1: Functional specification
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. PNX8550 Functional Overview . . . . . . . . . . . . 3
3. PNX8550 Feature Summary . . . . . . . . . . . . . . . 5
4. Compatibility with the PNX8525 . . . . . . . . . . . 6
5. Analog/Digital Standard Definition Video
Improvement Capabilities . . . . . . . . . . . . . . . . . 7
5.1 Temporal-Spatial Improvement Processing . . . . 7
5.2 Temporal Noise Reduction . . . . . . . . . . . . . . . . . . .8
6. HD Decode and Display Capabilities . . . . . . 8
6.1 Dual HD Decode/Display Using 2 PNX8550 . . . . 9
7. Internal Functional Overview . . . . . . . . . . . . . 11
8. Internal Functional Overview . . . . . . . . . . . . . 12
8.1 Overview of Function Partitioning . . . . . . . . . . . .12
9. Integrated Processors . . . . . . . . . . . . . . . . . . . .14
9.1 PR4450 General Purpose Processor . . . . . . . . . 14
9.2 Dual TM3260 VLIW Media Processors . . . . . . .15
9.2.1 Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Digital Video/Transport Stream Inputs. . . . 17
10.1 Backwards Compatibility . . . . . . . . . . . . . . . . . . . . 17
10.2 New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. MPEG2 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1 MPEG System Processor (MSP). . . . . . . . . . . . . 19
11.2 DVD Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
11.3 Software Processing of MPEG2 Streams . . . . . 21
11.4 VMPG - MPEG2 Decoder and VLD2 . . . . . . . . . 21
12. Image Processing Hardware . . . . . . . . . . . . . 22
12.1 Pixel Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
12.2 Video Input Processor (VIP) . . . . . . . . . . . . . . . . . 23
12.3 Tunnel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.4 Quality Temporal Noise Reduction (QTNR)
and Video Measurement . . . . . . . . . . . . . . . . . . . . 24
12.5 Memory Based Scaler (MBS). . . . . . . . . . . . . . . . 25
12.6 2D and DMA Engine . . . . . . . . . . . . . . . . . . . . . . .26
12.7 Quality Video Composition Processor
(QVCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.8 Integrated Digital Video Encoder (DENC) . . . . . 30
12.9 PNX8510/11 Analog Companion Chip . . . . . . . .30
13. Audio Processing and Input/Output. . . . . . 30
13.1 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.2 Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . .31
13.3 Audio Compatibility . . . . . . . . . . . . . . . . . . . . . . . . 31
14. Miscellaneous Functions . . . . . . . . . . . . . . . . 31
14.1 Enhanced DMA Controller (EDMA) . . . . . . . . . . 31
14.2 Semaphores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14.3 Inter-Processor Communication. . . . . . . . . . . . . 32
15. System Memory. . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.1 System DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.2 System EEPROM, ROM or Flash . . . . . . . . . . . 34
16. Security Provisions . . . . . . . . . . . . . . . . . . . . . . 34
16.1 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17. Peripheral Interfaces. . . . . . . . . . . . . . . . . . . . . 35
17.1 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.2 MemoryStick and MultiMediaCard . . . . . . . . . . . 36
17.3 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.1 Software I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.2 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3.3 Event Sequence Monitoring and Signal
Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.3.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 38
17.3.5 Timer/Counter Capabilities . . . . . . . . . . . . . . . . . 38
17.3.6 GPIO Pin Reset Value . . . . . . . . . . . . . . . . . . . . . 39
17.3.7 Compatibility with PNX8525 . . . . . . . . . . . . . . . . 39
17.3.8 Remote Control Receiver/Blaster. . . . . . . . . . . . 39
17.4 PCI2.2 and XIO16 Bus Interface Unit . . . . . . . . 40
17.4.1 PCI Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17.4.2 Simple Peripheral Capabilities (XIO8/16) . . . . . 40
18. Endian Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
19. PNX8550 Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
20. Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . 43
21. Changes from PNX8550_RevA to
PNX8550_RevB . . . . . . . . . . . . . . . . . . . . . . . . . . 44
21.1 MBS2 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
21.1.1 Frequency of Operation and Performance . . . . 44
21.2 Vertical Peaking Block (VPK) . . . . . . . . . . . . . . . 44
21.2.1 Frequency of Operation and Performance . . . . 45
21.3 Video Streaming Connections . . . . . . . . . . . . . . 45
21.3.1 Tunnel Interface to QVCP . . . . . . . . . . . . . . . . . . 45
21.3.2 MBS2 Block to QVCP. . . . . . . . . . . . . . . . . . . . . . 45
21.3.3 Vertical Peaking Block to QVCP . . . . . . . . . . . . 45
21.4 Contrast Brightness Control with Soft Clipper
(CBSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 2: Bus Architecture and System Memory Map
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Bus Architecture Block Diagram . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Low Power Adapter Implementation . . . . . . . . . . . 3
3. DCS Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 DCS Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Standard System Memory Map . . . . . . . . . . . .6
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 i
4.1 Apertures in the Standard System Memory Map 6
4.2 Building the Standard System Memory Map . . . 7
4.3 Rationale for the Standard System Memory
Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Hardware Limitations to Object Visibility . 8
6. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 9
6.1 Aperture Control Registers . . . . . . . . . . . . . . . . . . 9
6.1.1 PCI, TM3260, and MIPS PR4450 . . . . . . . . . . . . 9
6.2 Global 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . 9
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
7. Alternate System Memory Map with
External Host CPU. . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 PCI Standard Boot and Memory Map
Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2 Internal MIPS PR4450 and External Host CPU 10
8. Memory Map Perspectives . . . . . . . . . . . . . . . 11
8.1 View from MIPS PR4450 . . . . . . . . . . . . . . . . . . .11
8.1.1 MIPS PR4450 Exception Vector Logic . . . . . . . . 12
Chapter 3: PMAN Hub
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 PNX8550 HUB Block . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 PMAN Arbiter (IP_1010) . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 PMAN Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 DMA Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.4 Memory Bandwidth Monitor . . . . . . . . . . . . . . . . . . 7
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Arbitration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4: DCS network and security
8.2 View from the TM3260 CPU Cores . . . . . . . . . . 13
8.3 View from PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . 14
8.3.1 PNX8550 as PCI Configuration Manager. . . . . 14
8.3.2 An External Host CPU as PCI Configuration
Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.4 View from the MDCS and TDCS Buses . . . . . . 15
8.5 MMIO Base Address Map . . . . . . . . . . . . . . . . . . 16
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Register Programming Guidelines. . . . . . . . . . . 11
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 12
4.1 PMAN Hub Arbiter Registers . . . . . . . . . . . . . . . 12
4.1.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 PMAN Security Registers . . . . . . . . . . . . . . . . . . 14
4.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Memory Bandwidth Monitor Registers . . . . . . . 25
4.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Protection Mechanisms . . . . . . . . . . . . . . . . . . . 2
2.1 MIPS PR4450 Protection Mechanisms . . . . . . . .2
2.2 TM3260 Protection Mechanisms . . . . . . . . . . . . . .2
3. DCS Target Access Control . . . . . . . . . . . . . . .3
3.1 DCS Controller Block Level Diagram . . . . . . . . . . 3
3.1.1 DCS Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 DCS Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Programmable Address Map . . . . . . . . . . . . . . . . . 5
3.1.4 Error Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Selective Blocking of Initiators (System
Security) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.6 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.7 Programmable Timeout. . . . . . . . . . . . . . . . . . . . . . 6
3.1.8 Null Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.9 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 DCS Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 DCS Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 5: Endian mode
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Endian Mode Theory . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Law 1: The “CPU Rule” . . . . . . . . . . . . . . . . . . . . . .2
2.2 Law 2: The “DMA Convention Rule” . . . . . . . . . . .4
3. Endian Mode Architecture Details . . . . . . . . . 4
3.3.1 Deadlock Handling . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 MIPS DCS Network Controller Configuration
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 MIPS DCS Network Controller Security
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 TriMedia DCS Network Controller
Configuration Registers . . . . . . . . . . . . . . . . . . . . 14
4.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 TriMedia DCS Network Controller Security
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Global Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Peripheral DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 SIMD Programming Issues . . . . . . . . . . . . . . . . . . 6
3.5 Optional Endian Mode Override . . . . . . . . . . . . . . 7
4. Audio In—Programmer’s View (Example) 7
5. Detailed Example . . . . . . . . . . . . . . . . . . . . . . . . . 8
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 ii
Philips Semiconductors
Chapter 6: Pixel formats
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Summary of Native Pixel Formats . . . . . . . . . 2
3. Native Pixel Format Representation. . . . . . . 3
3.1 Indexed Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 16-Bit Pixel-Packed Formats . . . . . . . . . . . . . . . . . 4
3.3 32-Bit Pixel-Packed Formats . . . . . . . . . . . . . . . . . 4
3.4 Packed YUV 4:2:2 Formats . . . . . . . . . . . . . . . . . . 5
3.5 Planar YUV 4:2:0 and YUV 4:2:2 Formats . . . . . 6
3.5.1 Planar Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 7: Boot
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Boot Block Level Diagram. . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 MMIO Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 I2C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.3 Boot Control/State Machine . . . . . . . . . . . . . . . . . . 4
2.2.4 Internal Script Block . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 8: Clocks
3.5.2 Semi-Planar 10-Bit YUV 4:2:2 and 4:2:0
Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.3 Packed 10-bit YUV 4:2:2 format. . . . . . . . . . . . . 10
4. Universal Converter. . . . . . . . . . . . . . . . . . . . . . 10
5. Alpha Value and Pixel Transparency . . . . 11
6. YUV and RGB Values . . . . . . . . . . . . . . . . . . . . 11
7. Image Storage Format . . . . . . . . . . . . . . . . . . . 11
8. System Endian Mode . . . . . . . . . . . . . . . . . . . . 12
3.1 Boot Mode Configuration. . . . . . . . . . . . . . . . . . . . 5
3.2 Internal vs. External Boot. . . . . . . . . . . . . . . . . . . . 6
3.3 Symbolic Boot Language. . . . . . . . . . . . . . . . . . . . 6
3.4 Internal Boot Scripts . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 External Boot Scripts . . . . . . . . . . . . . . . . . . . . . . . 8
3.5.1 External I2C Boot EEPROM Types . . . . . . . . . . . 8
3.5.2 External EEPROM Boot Script Binary Format. . 9
3.5.3 Details on I2C Operation . . . . . . . . . . . . . . . . . . . 10
3.5.4 Internal Host Booting Using an External Script 10
3.5.5 External Host Boot . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Bootup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Clocks Block Level Diagram. . . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.0.1 System Level Clocks . . . . . . . . . . . . . . . . . . . . . . . . 4
3.0.2 Sources of the PNX8550 Clocks . . . . . . . . . . . . . .7
3.0.3 DDS Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.0.4 PLL Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0.5 Oscillator Pad Requirements . . . . . . . . . . . . . . . . 12
3.0.6 Special Clock Relationships . . . . . . . . . . . . . . . . .12
3.0.7 Clock Control and Selection Logic . . . . . . . . . . . 12
3.0.8 PLL Clock Blocking . . . . . . . . . . . . . . . . . . . . . . . .18
3.0.9 Bypass Clock Sources. . . . . . . . . . . . . . . . . . . . . . 18
3.0.10 Power-Up and Reset Sequence . . . . . . . . . . . . .20
Chapter 9: Reset
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Reset Block Level Diagram . . . . . . . . . . . . . . . . . . 1
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 2
3.0.11 Powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.0.12 DFT Clock Selection. . . . . . . . . . . . . . . . . . . . . . . 20
3.0.13 DFT Frequency Counter . . . . . . . . . . . . . . . . . . . 22
3.0.14 Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Power Management . . . . . . . . . . . . . . . . . . . . . . . 24
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Essential Operating Infrastructure During
Powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Special Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Peripheral Module Powerdown Sequence . . . . 25
4.4 Peripheral Module Wakeup Sequence . . . . . . . 26
4.5 DCS Network Power “Spreading” . . . . . . . . . . . 26
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 27
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.1 PERI_RST State Machine. . . . . . . . . . . . . . . . . . . 4
3.1.2 MIPS_RST State Machine. . . . . . . . . . . . . . . . . . . 5
3.1.3 SYS_RST_OUT State Machine . . . . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 7
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 10: Power management
1. Power Management Mechanisms . . . . . . . . . 1 1.1 Clock Management. . . . . . . . . . . . . . . . . . . . . . . . . 1
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 iii
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
1.1.1 Essential Operating Infrastructure During
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Special Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.3 Peripheral Module Powerdown Sequence. . . . . . 2
1.1.4 Peripheral Module Wakeup Sequence . . . . . . . . . 3
1.2 Special Power Management Mechanisms. . . . . . 3
1.2.1 PR4450 MIPS Processor . . . . . . . . . . . . . . . . . . . . 3
1.2.2 TriMedia 3260 CPUs . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 11: Interrupts
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Interrupts Block Level Diagram . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 12: Global registers
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Global Register Descriptions. . . . . . . . . . . . . . 1
2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Global 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 13: PCI-XIO
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 PCI-XIO Block Level Diagram . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 NAND-Flash Interface Operation. . . . . . . . . . . . . . 5
3.1.2 Motorola Style Interface . . . . . . . . . . . . . . . . . . . . 10
3.1.3 NOR Flash Interface . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 IDE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.5 PCI Interrupt Enable Register . . . . . . . . . . . . . . .17
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .17
1.2.3 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. System Powerdown Mode Examples . . . . . 5
2.1 Reduced Power Mode . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Minimal Power Mode . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Procedure for Shutting Down . . . . . . . . . . . . . . . . 6
2.3.2 Procedure for Power Up . . . . . . . . . . . . . . . . . . . . 7
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Register Programming Guidelines. . . . . . . . . . . . 6
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 Global 2 Register Summary . . . . . . . . . . . . . . . . . 2
2.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Global 1 Register Descriptions. . . . . . . . . . . . . . . 3
2.2.2 Global 2 Register Descriptions. . . . . . . . . . . . . . . 7
4.1 DTL MMIO Interface. . . . . . . . . . . . . . . . . . . . . . . 17
4.2 DVP Memory Bus Interface. . . . . . . . . . . . . . . . . 18
4.3 XIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.1 Motorola Interface . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.2 NAND-Flash Interface . . . . . . . . . . . . . . . . . . . . . 19
4.3.3 NOR Flash Interface. . . . . . . . . . . . . . . . . . . . . . . 19
4.3.4 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 PCI Endian Support . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1 Known PCI Non-Compliance . . . . . . . . . . . . . . . 21
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 14: DDR SDRAM
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 DDR Controller Block Level Diagram . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Input processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Start and Warm Start . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.1 Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.2 Warm Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.3 Observing Start State . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.4 Sequence of Actions . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.1 First Level Arbitration: Between DMA and
CPUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.2 Second Level Arbitration: Among CPUs . . . . . . . 8
2.5.3 Dynamic Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 iv
2.5.4 Pre-Emption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.5 Back Log Buffer (BLB) . . . . . . . . . . . . . . . . . . . . . 11
2.5.6 PMAN (Hub) versus DDR Controller
Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.1 Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.2 Memory Region Mapping Scheme. . . . . . . . . . . 13
2.7 DDR Memory Rank Locations . . . . . . . . . . . . . . 15
2.7.1 Some Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. General Operations . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Asynchronous Reset Synchronization. . . . . . . . 16
3.3 Programming via the DTL Port . . . . . . . . . . . . . . 17
3.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Halting and Unhalting . . . . . . . . . . . . . . . . . . . . . . 17
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.4.2 Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . 18
3.4.3 MMIO Directed Halt . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.4 Auto Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.5 Observing Halt Mode . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.6 Sequence of Actions . . . . . . . . . . . . . . . . . . . . . . . 20
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .20
4.1 Memory Configurations . . . . . . . . . . . . . . . . . . . . .20
4.2 Error Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 15: CTL12 Tunnel
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 CTL12 Tunnel Block Level Diagram . . . . . . . . . . .2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Transaction Overview . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.2.3 Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Internal Interface Protocol. . . . . . . . . . . . . . . . . . . . 5
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Register Programming Guidelines . . . . . . . . . . . . 6
3.4 Tunnel Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Booting the DDR SDRAM Controller . . . . . . . . . 22
4.6 Data Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7 Programming the Internal Arbiter . . . . . . . . . . . . 26
4.8 Compatible DDR Parts List . . . . . . . . . . . . . . . . . 27
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 30
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 CTL12 Tunnel Overview . . . . . . . . . . . . . . . . . . . . 6
3.4.2 CTL12 Tunnel Transmit and Receive
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.3 Multiplexing Overview . . . . . . . . . . . . . . . . . . . . . . 9
3.4.4 CTL12 Tunnel Flow Control . . . . . . . . . . . . . . . . 10
3.4.5 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.6 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Tunnel Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 North Bound MTL Traffic . . . . . . . . . . . . . . . . . . . 13
3.5.2 South Bound, DCS Traffic . . . . . . . . . . . . . . . . . . 13
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 16: Smartcard UART
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Smartcard UART Module Block Level Diagram . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Cold and Warm Reset . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Cold Reset Procedure . . . . . . . . . . . . . . . . . . . . . . .4
3.1.2 Warm Reset Procedure . . . . . . . . . . . . . . . . . . . . . . 4
3.2 ISO 7816 UART Functional Description. . . . . . . . 5
Chapter 17: GPIO
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 GPIO Block Level Diagram. . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.2 Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 GPIO Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.4 Reading and Writing GPIO Data . . . . . . . . . . . . . . 4
3.1.5 Signal Monitoring and Pattern Generation. . . . . . 6
3.1.6 Master Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1.7 Timestamp Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Activation and Deactivation Sequence . . . . . . . . 5
3.2.2 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.4 ISO UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . 9
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 11
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 Smartcard UART1 Registers . . . . . . . . . . . . . . . 12
4.2.2 Smartcard UART2 Registers . . . . . . . . . . . . . . . 27
3.1.8 Event Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.9 IR Wakeup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.10 Timer Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.12 Event Queue Interrupts . . . . . . . . . . . . . . . . . . . . 19
3.1.13 Timestamp Unit Interrupts . . . . . . . . . . . . . . . . . . 20
3.1.14 IR Wakeup and Counter/Timer Unit Interrupts 20
3.1.15 Direct Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Applications Notes. . . . . . . . . . . . . . . . . . . . . . . 20
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 v
Philips Semiconductors
Chapter 18: UART
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 UART Block Level Diagram . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Clock Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Register Programming Guidelines . . . . . . . . . . . . 3
Chapter 19: USB
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 USB Block Level Diagram. . . . . . . . . . . . . . . . . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Components of USB System . . . . . . . . . . . . . . . . . 4
Chapter 20: High Performance I2C Ports (1 & 2)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 HP IIC Block Level Diagram . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 Master Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Master Receive Mode . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Slave Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.4 Slave Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Clocking Constraints . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Interrupts from HS I2C. . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.3 Transmitter FIFO Function . . . . . . . . . . . . . . . . . . 4
3.2.4 Receiver FIFO Function. . . . . . . . . . . . . . . . . . . . . 4
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 4
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2.1 UART1 Module Registers . . . . . . . . . . . . . . . . . . . 5
4.2.2 UART2 Module Registers . . . . . . . . . . . . . . . . . . . 9
3.1.1 USB Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . 10
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 11
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Clearing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Enabling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Register Programming Guidelines. . . . . . . . . . . 16
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Module and Interrupt Status . . . . . . . . . . . . . . . . 16
4.1.1 Example of a Master Transmitter . . . . . . . . . . . . 16
4.2 Status Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 23
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 HP I2C1 Module Registers . . . . . . . . . . . . . . . . . 24
5.2.2 HP I2C2 Module Registers . . . . . . . . . . . . . . . . . 28
Chapter 21: Fast I2C Ports (3 & 4)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 Fast I2C Block Level Diagram . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Fast I2C Module Arbitration and Control Logic . . 3
3.1.2 Serial Clock Generator . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Bit Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.4 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.5 Status Decoder and Register . . . . . . . . . . . . . . . . .4
3.1.6 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.7 Address Register and Comparator . . . . . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 vi
3.1.8 Data Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.9 Related Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 Master Transmitter Mode. . . . . . . . . . . . . . . . . . . . 6
3.2.2 Master Receiver Mode. . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Slave Receiver Mode . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Slave Transmitter Mode. . . . . . . . . . . . . . . . . . . . . 8
3.2.5 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2.1 Fast I2C3 Module Registers . . . . . . . . . . . . . . . . . 9
4.2.2 Fast I2C4 Module Registers . . . . . . . . . . . . . . . . 20
Philips Semiconductors
Chapter 22: DV Input Ports
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. DV Input to VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 23: DVI Output Ports
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 24: Audio Input Ports
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Audio Input Block Level Diagram . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Chip Level External Interface . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Register Programming Guidelines . . . . . . . . . . . . 6
3.2 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 25: Audio Output
3. TS Mode of DV1, DV2 and DV3. . . . . . . . . . . . 1
3.1 Transport Stream Input Signal Descriptions . . . 3
3.2 Digital Video/TS Interface Timing Diagrams . . . 4
3.3.1 Endian Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Memory Buffers and Capture . . . . . . . . . . . . . . . 10
3.5 Data Bus Latency and HBE . . . . . . . . . . . . . . . . 10
3.6 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9 Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9.1 Audio In Operation . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Raw Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Audio Output Block Level Diagram . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Endian Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.2 Audio Out Data DMA Operation . . . . . . . . . . . . . . 4
3.2.1 TRANS_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.1 Interrupt Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.1 Serial Frame Limitations . . . . . . . . . . . . . . . . . . . . . 7
3.5.2 WS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.5.3 I2S Serial Framing Example . . . . . . . . . . . . . . . . . 8
3.6 Codec Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.7 Data Bus Latency and HBE . . . . . . . . . . . . . . . . . 9
3.8 Error Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.9 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 11
3.9.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 13
3.9.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . 14
3.9.4 Register Programming Guidelines. . . . . . . . . . . 14
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 26: SPDIF Input
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 SPDIF IN Block Level Diagram . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Received Serial Format. . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Memory Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 SPDIF IN Endianness . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.4 Bandwidth and Latency Requirements. . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 vii
3.2 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 SPDIF IN Clock Domains . . . . . . . . . . . . . . . . . . . 6
3.2.2 SPDIF Receiver Sample Rate Tolerance and
IEC60958 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 SPDIF Receiver Jitter Tolerance . . . . . . . . . . . . . 6
3.2.4 SPDIF IN and the Oversampling Clock. . . . . . . . 7
3.3 Register Programming Guidelines. . . . . . . . . . . . 7
3.3.1 SPDIF IN Register Set . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 SPDI_STATUS Register Functions . . . . . . . . . . . 8
3.3.3 LOCK and UNLOCK State Behavior . . . . . . . . . . 8
3.3.4 UNLOCK Error Behavior and DMA . . . . . . . . . . . 9
3.3.5 SPDI_CTL and Functions . . . . . . . . . . . . . . . . . . 10
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.3.6 SPDI_CBITSx and Channel Status Bits . . . . . . . 10
3.3.7 SPDI_UBITSx and User Bits . . . . . . . . . . . . . . . . 12
3.3.8 SPDI_BASEx and SPDI_SIZE Registers and
Memory Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.9 SPDI_SMPMASK and Sample Size Masking . . 12
3.3.10 SPDI_BPTR and the Start of an IEC60958
Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 27: SPDIF Output
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 SPDIF Out Block Level Diagram . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Register Programming Guidelines . . . . . . . . . . . . 3
3.2 Data Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 IEC-60958 Serial Format . . . . . . . . . . . . . . . . . . . .5
Chapter 28: MIPS RISC Core Processor
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 PNX8550 User ManualBlock Level Diagram. . . . 1
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Instruction Execution Units . . . . . . . . . . . . . . . 2
3.1 Computational Registers. . . . . . . . . . . . . . . . . . . . . 3
3.2 Coprocessor 0 (CP0) Registers . . . . . . . . . . . . . . . 4
4. Instruction Set Overview . . . . . . . . . . . . . . . . . . 5
4.1 MIPS32 Instruction Set . . . . . . . . . . . . . . . . . . . . . . 5
5. Pipeline Execution. . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Eight-Stage Pipeline . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Efficient Handling of Pipeline Stalls. . . . . . . . . . . 12
5.2.1 Interlocking for Data Dependency . . . . . . . . . . . .12
5.2.2 Branch-Likely Instructions. . . . . . . . . . . . . . . . . . . 13
3.3.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.12 Event Timestamping. . . . . . . . . . . . . . . . . . . . . . . 14
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 14
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 15
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Transparent Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Errors and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 DMA Error Conditions . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 HBE and Databus Latency . . . . . . . . . . . . . . . . . . 8
3.3.3 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.4 Timestamp Events . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 9
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. MIPS16 Supports . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 MIPS16 Instruction Set . . . . . . . . . . . . . . . . . . . . 13
6.1.1 Extend Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.2 PC-Relative Addressing. . . . . . . . . . . . . . . . . . . . 14
6.1.3 SP-Relative Addressing. . . . . . . . . . . . . . . . . . . . 14
6.1.4 Load/Store Offset Shifts. . . . . . . . . . . . . . . . . . . . 14
6.2 Switching Between MIPS16 and 32-Bit Modes 14
6.3 MIPS16 Registers. . . . . . . . . . . . . . . . . . . . . . . . . 15
7. MAD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8. Instruction and Data Caches. . . . . . . . . . . . . 15
9. Memory Architecture . . . . . . . . . . . . . . . . . . . . 16
9.1 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2 Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. Debug Support. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 29: TM3260 CPU Core Processor
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Programmable source decoder with integrated
peripherals CPU Core Block Level Diagram 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.1 DRAM Aperture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 MMIO Aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 Aperture1 (DCS Bus Aperture) . . . . . . . . . . . . . . .5
3.2 Special Event Handling . . . . . . . . . . . . . . . . . . . . . .5
3.2.1 Reset and Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 EXC (Exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 INT and NMI (Maskable and Non-Maskable
Interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 viii
3.3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Debug Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 System Provisions . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1 TM32_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.2 TM32_MODID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.3 Endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . 10
3.6.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . 11
4. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Global 1 and 2 Registers . . . . . . . . . . . . . . . . . . . 12
4.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 TM3260 MMIO Register Descriptions . . . . . . . . 17
Philips Semiconductors
Chapter 30: Video Input Processor (VIP)
PNX8550
Programmable Source Decoder with Integrated Peripherals
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 VIP Block Level Diagram . . . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Chip I/O and Connections. . . . . . . . . . . . . . . . . . . . 4
2.2.2 Data Routing and Video Modes . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 VIP Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Input Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 31: MBS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 MBS Block Level Diagram . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Horizontal Processing Pipeline . . . . . . . . . . . . . . .3
3.1.2 Vertical Processing Pipeline . . . . . . . . . . . . . . . . . 4
3.2 Data Processing in MBS . . . . . . . . . . . . . . . . . . . . . 5
3.3 MBS Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Task Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Video Source Controls. . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3 Video Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.4 Horizontal Video Filters (Sampling, Scaling, Color
Space Conversion) . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.5 Video Data Write to Memory. . . . . . . . . . . . . . . . 17
3.1.6 Auxiliary Data Path . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.7 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . 24
4. Register Definitions. . . . . . . . . . . . . . . . . . . . . . 25
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 Horizontal Video Filters . . . . . . . . . . . . . . . . . . . . . 9
3.3.4 Vertical Video Filters. . . . . . . . . . . . . . . . . . . . . . . 10
3.3.5 De-Interlacing in MBS . . . . . . . . . . . . . . . . . . . . . 10
3.3.6 Color-Key Processing. . . . . . . . . . . . . . . . . . . . . . 10
3.3.7 Alpha Processing . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.8 Video Data Output . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.9 Address Generation . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.10 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.11 Measurement Functions . . . . . . . . . . . . . . . . . . . 13
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 32: MBS2 (streaming)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Register Descriptions . . . . . . . . . . . . . . . . . . . . . 1
Chapter 33: QVCP (5L and 2L)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 QVCP Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 QVCP Top Level View. . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 QVCP Block Level Diagram . . . . . . . . . . . . . . . . . . 4
2.1.3 QVCP Data Flow Diagram . . . . . . . . . . . . . . . . . . . 5
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Layer Resources and Functions . . . . . . . . . . . . . . 7
3.1.1 Memory Access Control (DMA CTRL) . . . . . . . . . 7
3.1.2 Pixel Formatter Unit (PFU) . . . . . . . . . . . . . . . . . . . 8
3.1.3 Chroma Key and Undither (CKEY/UDTH) Unit. . 8
3.1.4 Chroma Up-Sample Filter (CUPS) . . . . . . . . . . .11
3.1.5 Linear Interpolator (LINT) . . . . . . . . . . . . . . . . . . . 11
3.1.6 Video/Graphics Contrast Brightness Matrix
(VCBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.7 Layer and Fetch Control . . . . . . . . . . . . . . . . . . . . 13
3.2 Pool Resources and Functions . . . . . . . . . . . . . . 13
3.2.1 CLUT (Color Look-Up Table) . . . . . . . . . . . . . . . . 13
2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 DCTI (Digital Chroma/Color Transient
Improvement). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 HSRU (Horizontal Sample Rate Upconverter). 14
3.2.4 HIST (Histogram Modification) Unit . . . . . . . . . . 14
3.2.5 LSHR (Luminance/Luma Sharpening) Unit . . . 14
3.2.6 CFTR (Color Features) Unit . . . . . . . . . . . . . . . . 15
3.2.7 PLAN (Semi Planar DMA) Unit. . . . . . . . . . . . . . 15
3.3 Screen Timing Generator . . . . . . . . . . . . . . . . . . 15
3.4 Mixer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 Key Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Output Pipeline Structure. . . . . . . . . . . . . . . . . . . 20
3.5.1 Formatter (FRMT). . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.2 Chroma Down-Sampler (CDNS) . . . . . . . . . . . . 21
3.5.3 Contrast Brightness and Soft Clip (CBSC). . . . 21
3.5.4 Average Beam Current Limiter (ABCL) or Power
Meter (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.5 Noise-Shaping (GNSH and ONSH) . . . . . . . . . . 22
3.5.6 Interleaver and Muxes . . . . . . . . . . . . . . . . . . . . . 22
3.5.7 Layer Selection, Dual Stream Support . . . . . . . 22
3.6 Output Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 ix
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.6.1 Output Interface Modes. . . . . . . . . . . . . . . . . . . . . 23
3.6.2 Out Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.3 Auxiliary Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Programming and Resource
Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 MMIO and Task Based Programming . . . . . . . .26
4.2 Setup Order for the QVCP . . . . . . . . . . . . . . . . . . 28
4.2.1 Shadow Registers . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.2 Fast Access Registers. . . . . . . . . . . . . . . . . . . . . . 32
4.3 Programming the Layer and Pool Resources . .33
4.3.1 Resource Assignment and Selection . . . . . . . . . 33
4.3.2 Aperture Assignment . . . . . . . . . . . . . . . . . . . . . . .35
4.3.3 Data Flow Selection . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.4 Pool Resource Assignment Example . . . . . . . . . 37
4.4 Programming the STG. . . . . . . . . . . . . . . . . . . . . . 39
4.4.1 Changing Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5 Programming QVCP for Different Output
Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 34: QTNR
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 QTNR Block Level Diagram . . . . . . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Pixel Fetch Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Summary of Required Functionality . . . . . . . . . . . 3
3.1.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .3
3.2 Temporal Noise Reduction . . . . . . . . . . . . . . . . . . .3
3.2.1 Summary of Required Functionality . . . . . . . . . . . 3
3.3 Pixel Store Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.3.1 Summary of Required Functionality . . . . . . . . . . . 4
3.3.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .4
3.4 Measurement Interface Block. . . . . . . . . . . . . . . . . 4
3.4.1 Summary of Required Functionality . . . . . . . . . . . 4
3.4.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .4
3.5 Noise Level Measurement . . . . . . . . . . . . . . . . . . . 4
3.5.1 Summary of Required Functionality . . . . . . . . . . . 4
3.5.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .5
3.6 Black Bar Measurement . . . . . . . . . . . . . . . . . . . . . 5
3.6.1 Summary of Required Functionality . . . . . . . . . . . 5
3.6.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . .5
4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6.1 Signature Analysis . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7 Programming Help . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.1 LINT Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.2 HSRU Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.3 LSHR Parameters. . . . . . . . . . . . . . . . . . . . . . . . . 43
4.7.4 DCTI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7.5 CFTR Parameters. . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Underflow Behavior . . . . . . . . . . . . . . . . . . . . . . . 44
4.8.1 Layer Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.8.2 Underflow Symptoms . . . . . . . . . . . . . . . . . . . . . . 45
4.8.3 Underflow Recovery . . . . . . . . . . . . . . . . . . . . . . . 45
4.8.4 Underflow Troubleshooting . . . . . . . . . . . . . . . . . 45
4.8.5 Underflow Handling . . . . . . . . . . . . . . . . . . . . . . . 45
4.9 Clock Calculations . . . . . . . . . . . . . . . . . . . . . . . . 46
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 47
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7 Black Level Measurement. . . . . . . . . . . . . . . . . . . 5
3.7.1 Summary of Required Functionality. . . . . . . . . . . 5
3.7.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 5
3.8 Histogram Measurement . . . . . . . . . . . . . . . . . . . . 5
3.8.1 Summary of Required Functionality. . . . . . . . . . . 5
3.8.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.9 UV Bandwidth Detection . . . . . . . . . . . . . . . . . . . . 6
3.9.1 Summary of Required Functionality. . . . . . . . . . . 6
3.9.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.10 Measurement Only Mode . . . . . . . . . . . . . . . . . . . 6
3.10.1 Summary of Required Functionality. . . . . . . . . . . 6
3.10.2 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.11 PIO and Task FIFO. . . . . . . . . . . . . . . . . . . . . . . . . 6
3.11.1 Software-Controlled Task Stack. . . . . . . . . . . . . . 6
3.11.2 Summary of Required Functionality. . . . . . . . . . . 6
3.11.3 Design Requirements. . . . . . . . . . . . . . . . . . . . . . . 6
3.12 Video Measurement Unit (VMU) . . . . . . . . . . . . . 7
3.12.1 VMU Functional Description . . . . . . . . . . . . . . . . . 7
3.12.2 VMU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 35: Video Encoder (DVI_DENC)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 DENC Block Level Diagram . . . . . . . . . . . . . . . . . . 1
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Video Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Video DAC Control . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Signature Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 x
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.1 PAL/NTSC/SECAM Encoder . . . . . . . . . . . . . . . . 5
3.2.2 Luminance and Chrominance Processing . . . . . 6
3.2.3 Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.4 Macrovision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.5 VBI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.6 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.7 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.9 Power Management . . . . . . . . . . . . . . . . . . . . . . . . 9
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.2.10 Register Programming Guidelines . . . . . . . . . . . . 9
3.3 Module-Specific Capabilities . . . . . . . . . . . . . . . . 12
4. Application Notes . . . . . . . . . . . . . . . . . . . . . . . .12
Chapter 36: Vertical Peaking (VPK)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Vertical Peaking Block Level Diagram . . . . . . . . . 2
2.2 Vertical Peaking IP Block . . . . . . . . . . . . . . . . . . . . 2
2.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Vertical Peaking Core . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.2 Y_Out According to Output Mode . . . . . . . . . . . . . 4
3.2.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.5 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2.6 Powerdown Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 37: 2D Drawing Engine
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 PNX8550 User Manual Block Level Diagram . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.2 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.3 Color Expand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.4 Rotator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.5 Source FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.6 Pattern FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.7 Destination FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.8 Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.9 Source State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.10 Destination State . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.2.11 Address Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.12 Bit BLT Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.13 Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.14 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 12
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.7 Progressive Output Mode . . . . . . . . . . . . . . . . . . . 6
3.3 Module-Specific Capabilities . . . . . . . . . . . . . . . . . 6
3.3.1 Special Output Modes . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Video Input Interface Description . . . . . . . . . . . . . 8
3.3.3 Video Output Interface Description . . . . . . . . . . . 8
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1 Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Endianness Conversion. . . . . . . . . . . . . . . . . . . . 10
4.2 Suggested Coefficient Values for Effective
Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 10
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.15 Byte Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Source Data Location and Type . . . . . . . . . . . . . 6
3.1.4 Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Transparency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.6 Block Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Register Programming Guidelines. . . . . . . . . . . . 7
3.2.1 Alpha Blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Mono Expand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Mono BLT Register Setup . . . . . . . . . . . . . . . . . . 10
3.2.4 Solid Fill Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.5 Color BLT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.6 PatRam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . 13
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 38: Transport Stream Network (TSIO)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Transport Stream Network Top Level View . . . . . 2
2.2 TSIO Block Level Diagram . . . . . . . . . . . . . . . . . . . 3
2.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 TS Input Interface Modes . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xi
3.1.2 TS OUT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 TS Input Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 Register Programming Guidelines. . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 7
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Philips Semiconductors
Programmable Source Decoder with Integrated Peripherals
Chapter 39: Transport Stream Direct Memory Access (TSDMA)
PNX8550
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 1
2.1 Interface and Ports. . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 Output Signal Descriptions . . . . . . . . . . . . . . . . . . .2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Memory Data Formats. . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 40: DVI_EDMA Controller
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 DVI_EDMA Block Level Diagram . . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 DMA Engine Core. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.3 Source and Destination Location. . . . . . . . . . . . . . 3
2.2.4 DMA, CRC and AES Data Paths. . . . . . . . . . . . . . 3
2.2.5 DMA Scatter-Gather and Control Engine. . . . . . . 4
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Scatter-Gather DMA . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Scatter-Gather Mode Retriggering . . . . . . . . . . . .4
3.2 CRC Computation . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 DVI_AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2 DMA Channel Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3 Packet Delivery Schedule . . . . . . . . . . . . . . . . . . . 5
3.1.4 Stream Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.5 Synchronization Logic . . . . . . . . . . . . . . . . . . . . . . 6
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 6
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . 9
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Descriptor Overview . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 10
5.1 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . 10
5.1.2 Channel Link List Pointer Register. . . . . . . . . . . 10
5.1.3 CRC Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.4 DMA Status Register . . . . . . . . . . . . . . . . . . . . . . 11
5.1.5 Reference Key Registers. . . . . . . . . . . . . . . . . . . 11
5.1.6 AES SRAM Key Valid Register . . . . . . . . . . . . . 11
5.1.7 AES SRAM Key Clear Register . . . . . . . . . . . . . 11
5.1.8 SCN Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.9 KMU Control Register . . . . . . . . . . . . . . . . . . . . . 11
5.1.10 KMU Status Register . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 41: VESPIC MPEG System Processor (VMSP)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 4
2.1 MSP Block Level Diagram . . . . . . . . . . . . . . . . . . . 4
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Packet Framer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Transport/De-Multiplexer RISC Engine . . . . . . . . 6
2.2.3 Hardware Section Filtering . . . . . . . . . . . . . . . . . . . 7
2.2.4 De-Scrambler Core . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.5 Memory Queue Manager Controller . . . . . . . . . . 10
2.2.6 Packet Direct Memory Access . . . . . . . . . . . . . . . 10
2.2.7 Transport RISC Engine . . . . . . . . . . . . . . . . . . . . .11
2.2.8 Hardware Section Filtering . . . . . . . . . . . . . . . . . . 12
2.2.9 De-Scrambler and Cipher Engine . . . . . . . . . . . . 17
2.2.10 Memory Queue Manager. . . . . . . . . . . . . . . . . . . 20
2.3 General Operations . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 MPEG System Processor Interrupt Handler . . 21
3. Register Descriptions. . . . . . . . . . . . . . . . . . . . 21
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 VMSP Configuration Register Summary . . . . . 23
3.1.2 PDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Memory Queue Manager Registers. . . . . . . . . . 27
3.2.2 Packet Framer Registers. . . . . . . . . . . . . . . . . . . 28
3.2.3 RISC Engine Registers . . . . . . . . . . . . . . . . . . . . 40
3.2.4 De-Scrambler Registers. . . . . . . . . . . . . . . . . . . . 42
3.2.5 VMSP Interrupt Sources and Control . . . . . . . . 46
3.2.6 VMSP Interrupt Registers . . . . . . . . . . . . . . . . . . 48
Chapter 42: MPEG Video Decoder
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 MPEG Video Decoder Block Level Diagram . . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 VLD-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xii
2.2.2 Full MPEG/MPEG2 Decoding with Motion
Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. General Operations . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Data Flow and Control . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 VLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.2 Run-Length Decoder/Inverse Scan . . . . . . . . . . . 5
3.1.3 Motion Compensation . . . . . . . . . . . . . . . . . . . . . . 5
Philips Semiconductors
PNX8550
Programmable Source Decoder with Integrated Peripherals
3.2 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.3 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 VLD Register Programming Guidelines . . . . . . . . 7
3.3.1 VLD Status (VLD_MC_STATUS) . . . . . . . . . . . . .7
3.3.2 VLD Interrupt Enable (VLD_IE) . . . . . . . . . . . . . . . 8
3.3.3 VLD Control (VLD_CTL) . . . . . . . . . . . . . . . . . . . . . 8
3.3.4 VLD DMA Current Read Address and Current
Read Count9
3.3.5 VLD DMA Macroblock Header Current Write
Address (VLD_MBH_ADR)10
3.3.6 VLD DMA Macroblock Header Current Write
Count10
3.3.7 VLD DMA Run-Level Current Write Address
(VLD_RL_ADR)10
3.3.8 VLD DMA Run-Level Current Write Count. . . . . 10
3.3.9 VLD Command (VLD_COMMAND) . . . . . . . . . .10
3.3.10 VLD Shift Register (VLD_SR) . . . . . . . . . . . . . . .13
3.3.11 VLD Quantizer Scale (VLD_QS) . . . . . . . . . . . . . 13
3.3.12 VLD Picture Info (VLD_PI) . . . . . . . . . . . . . . . . . . 13
3.3.13 VLD Bit Count (VLD_BIT_CNT). . . . . . . . . . . . . . 13
3.4 RL/ IQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1 Run-Length Decoder Statistics Registers . . . . . 13
3.4.2 Total Symbol Count . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.3 Total_Coded_Block_Count. . . . . . . . . . . . . . . . . . 14
3.4.4 Extra Picture Info (Extra_Pic_Info) . . . . . . . . . . . 14
3.5 Motion Compensation Registers . . . . . . . . . . . . . 14
3.5.1 MC Control Registers . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 MC Command Register. . . . . . . . . . . . . . . . . . . . . 14
3.5.3 MC Status Register . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 MC_PFCOUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.5 Line Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.6 VLD_MC_STATUS. . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 VLD Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 VLD Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2 VLD Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.3 Restart the VLD Parsing . . . . . . . . . . . . . . . . . . . 18
3.7 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.1 Unexpected Start Code . . . . . . . . . . . . . . . . . . . . 19
3.8.2 MC Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8.3 Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Run-Length Decoder/Inverse Scan Overview . 21
3.9.1 Run-Length Decoder . . . . . . . . . . . . . . . . . . . . . . 21
3.9.2 Inverse Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.3 Inverse Quantization. . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Coefficient Selection for Half Resolution Mode 24
3.11 Motion Compensation Operations . . . . . . . . . . . 24
3.11.1 Error Concealment Operation. . . . . . . . . . . . . . . 25
3.11.2 Bitstream Error Detection . . . . . . . . . . . . . . . . . . 26
3.11.3 Reducing Memory Bandwidth Utilization . . . . . 27
3.11.4 Fetching Macroblocks . . . . . . . . . . . . . . . . . . . . . 27
3.11.5 PEL Reconstruction Unit . . . . . . . . . . . . . . . . . . . 28
3.11.6 Storage Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11.7 MC/VLD Error Recovery . . . . . . . . . . . . . . . . . . . 29
3.11.8 MPEG Software Reset . . . . . . . . . . . . . . . . . . . . . 29
3.11.9 MC Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11.10 MC Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 31
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 31
5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 43: Variable Length Decoder (VLD)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 VLD Block Level Diagram . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 VLD MMIO Registers . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2.1 VLD Status (VLD_MC_STATUS) . . . . . . . . . . . . .3
3.2.2 VLD Interrupt Enable (VLD_IE) . . . . . . . . . . . . . . . 4
3.2.3 VLD Control (VLD_CTL) . . . . . . . . . . . . . . . . . . . . . 4
3.2.4 VLD DMA Current Read Address
(VLD_INP_ADR) and
Read Count (VLD_INP_CNT)5
3.2.5 VLD DMA Macroblock Header Current Write
Address (VLD_MBH_ADR)5
3.2.6 VLD DMA Macroblock Header Current Write
Count5
3.2.7 VLD DMA Run-Level Current Write Address
(VLD_RL_ADR)6
3.2.8 VLD DMA Run-Level Current Write Count. . . . . . 6
3.2.9 VLD Command (VLD_COMMAND) . . . . . . . . . . .6
3.2.10 VLD Shift Register (VLD_SR) . . . . . . . . . . . . . . . .8
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xiii
3.2.11 VLD Quantizer Scale (VLD_QS) . . . . . . . . . . . . . 8
3.2.12 VLD Picture Info (VLD_PI). . . . . . . . . . . . . . . . . . . 8
3.2.13 VLD Bit Count (VLD_BIT_CNT) . . . . . . . . . . . . . . 8
3.3 VLD Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1 VLD Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 VLD Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Restart the VLD Parsing . . . . . . . . . . . . . . . . . . . 12
3.4 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Unexpected Start Code . . . . . . . . . . . . . . . . . . . . 13
3.5.2 RL Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Application Notes. . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 DVI_VLD Programming Differences vs. Other
Video Decoders14
4.1.1 TM1100 VLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1.2 PNX8525 Video Decoder. . . . . . . . . . . . . . . . . . . 14
4.1.3 PNX8550 Video Decoder. . . . . . . . . . . . . . . . . . . 14
5. Register Descriptions. . . . . . . . . . . . . . . . . . . . 14
5.1 TM1100 and PNX8550 Register Differences. . 14
5.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Philips Semiconductors
Programmable Source Decoder with Integrated Peripherals
Chapter 44: DVDD
1. Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 45: Boundary Scan
PNX8550
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 Boundary Scan Architecture Diagram . . . . . . . . .2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 Principle of the Boundary Scan Architecture . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 46: EJTAG_DMA
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description . . . . . . . . . . . . . . . . . . . . 2
2.1 EJTAG DMA Block Level Diagram . . . . . . . . . . . . 2
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 DTL-MMIO Master Interface. . . . . . . . . . . . . . . . . . 3
3.1.1 EJTAG Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 TimNet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 47: TM3260 Debug
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. General Operations. . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Data Flow and Control. . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . 1
2.1.2 TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.3 PNX8550 JTAG Instruction Set . . . . . . . . . . . . . . .4
3.1 The IEEE 1149.1 Boundary Scan Standard. . . . 4
3.1.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . 7
3.1.4 JTAG Public Instruction Set . . . . . . . . . . . . . . . . . 7
3.2 Boundary Scan Description Language . . . . . . . . 8
3.2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.1 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3.3 Register Programming Guidelines. . . . . . . . . . . . 5
4. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 Register Programming Guidelines. . . . . . . . . . . . 4
2.2 Module-Specific Capabilities . . . . . . . . . . . . . . . . . 6
2.2.1 Debug Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Register Descriptions. . . . . . . . . . . . . . . . . . . . . 8
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 48: Interrupt Control
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description . . . . . . . . . . . . . . . . . . . . 3
2.1 PNX8550 User Manual Block Level Diagram . . . 3
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Priority Masking Stage. . . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.4 Vector Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Register Descriptions . . . . . . . . . . . . . . . . . . . . . 5
3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 5
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 02 — 21 July 2004 xiv
3.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Interrupt Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.4 Interrupt Priority Mask Registers . . . . . . . . . . . . . 8
3.2.5 Interrupt Vector Registers . . . . . . . . . . . . . . . . . . . 9
3.2.6 Interrupt Pending Registers . . . . . . . . . . . . . . . . 10
3.2.7 Interrupt Features Register . . . . . . . . . . . . . . . . . 12
3.2.8 Interrupt Request Registers . . . . . . . . . . . . . . . . 12
3.2.9 Interrupt Module ID Register. . . . . . . . . . . . . . . . 18
3.2.10 Other GIC Registers . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.11 IPC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1. Introduction
Chapter 1: Functional specification
PNX8550 User Manual
Rev. 02 — July 21 2004 Preliminary data
TS output
3x656
TS inputs
2x smartcard
2x I2S
S/PDIF
PNX8550
video/ts router
2D DE
TSout
10
1SD+1HD
YUV422
20
video in
dual
cond.
access
32-bit 225 MHz DDR
DVD-CSS
audio in
dual SD
single HD
MPEG2
decoder
Memory
Controller
scaler &
V Peaking
temporal
noise redux
250 MHz
MIPS32
CPU
optional external
video improvement
processing
5 layer
Tunnel
primary
video out
HD/VGA/656
2 layer
secondary
video out
scaler &
de-interlace
2x 240 MHz
TM3260
Media Processor
Streaming interface
from Tunnel
DENC
audio out
30 (dig)
analog
S-Video or
CVBS
2
s
2x i
S/PDIF
MemoryStick/
MultiMediaCard
UARTs
USB1.1
GPIO
Figure 1: PNX8550 Functional Block Diagram
The PNX8550 is a highly integrated media processor intended for deployment in
Analog, Digital and Hybrid Television receivers. The PNX8550 is targeted at the mid
to high-end TV sets, focusing on dual program analog/digital picture improved
Standard Definition capability and single program High Definition decode and display
capability. The PNX8550 can be used for 100 Hz interlaced as well as 60 Hz
progressive screens. It is fully capable of performing advanced video improvement
algorithms, such as DRC™ or Digital Natural Motion™, on Standard Definition analog
or digital sources. It includes an HD capable de-interlacer for converting interlaced
HD transmission signals to progressive output for driving wide-XGA class Plasma or
PCI2.2
Flash IDE
Philips Semiconductors
LCD displays. The PNX8550 includes DVD content scramble system (CSS) to
support he DVD player function. The PNX8550 also supports VCD, S-VCD and
CD-Audio players.
The PNX8550 is responsible for the video improvement processing on analog
sources, and for all source decode functions and video improvement processing on
digital sources. It includes integrated dual program conditional access, dual program
MPEG2 transport stream de-mux, dual SD or single HD MPEG2 video decode, audio
decode and processing, graphics generation, video processing, and image
composition and display. Two 32-bit 240 MHz VLIW media processors, referred to as
the TriMedia TM3260 CPU core, carry out the advanced video improvement
processing as well as all audio operations. Fixed function hardware performs stable
core video functions, such as picture level MPEG2 decoding, scaling, image
composition and pixel post processing.
The PNX8550 includes an integrated Remote Control receiver, I2C, USB host and
UART peripherals. In addition, a software controlled General Purpose IO block
provides for connectivity to switches/indicators and arbitrary serial devices, and
includes capability to connect to MemoryStick™ or MultiMediaCard™ Flash. The
PNX8550 also provides an industry standard PCI 2.2, 32-bit wide, 33 MHz system
bus connection allowing a wide variety of low-cost PC peripherals to be gluelessly
attached. The system bus includes support for direct connection to 8 and 16-bit wide
system ROM or Flash memories and 8 and 16-bit simple M68k type slave devices.
Internal IDE control logic provides the capability for a medium performance
(5MB/sec) IDE interface using only two low-cost external TTL packages.
PNX8550
Chapter 1: Functional specification
An embedded MIPS32 processor (PR4450) running at 250 MHz is available to run
the OS. The PR4450 processor is primarily responsible for running the demand
paged graphics-intensive operating system, while the TM3260 media processors are
responsible for running all real-time media functions. All hardware resources inside
the PNX8550 are accessible by both the MIPS processor and the TM3260 CPUs. A
‘sandbox’ style system protection provision ensures that selected MIPS memory
regions and critical peripherals can not be corrupted or inspected.
The PNX8550 provides a primary digital (YUV or RGB) output to connect to the
display specific output processor. In addition, a secondary analog video output
(CVBS or S-Video) for a VCR is available. It can operate either in analog PAL/NTSC
or digital mode.
The PNX8550 optionally allows passing a selected video stream through an external
accelerator, and bringing it back in to the primary video output stream to be merged
with graphics or other video planes. This connection provides for up to 81 Mpix/sec
pixel rate, with up to 10-bit/component accuracy.
The PNX8550 is manufactured using an advanced 0.12u CMOS process.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-2
Philips Semiconductors
2. PNX8550 Functional Overview
32-bit DDR
PNX8550
Chapter 1: Functional specification
225 MHz
analog/digital
tuner + frontend
analog/digital
tuner + frontend
MemoryStick
MultiMediaCard
Remote Control
Smart
Card
1394 I/F
27 MHz
TD8004
Optional 1394
L2 Controller
656/TS
i2s
656/TS
i2s
DV1 / DV2
i2s_in1
DV3
i2s_in2
GPIO
2x ISO
UART
DV3
TS_OUT
PNX8550
PCI
DV_OUT1
VOUT2
i2s_out1
i2s_out2
USB 2x
UART 2x
S/PDIF
XIO
Expansion
Device
30b RGB
20b YUV
8 ch
display
output
processor
analog Y/C or CVBS
for VCR
DACs
external modem, USB1.1 devices,
frontpanel controller
to Dolby Digital™ receiver
to screen
to amp,
speakers
PCI 2.2
buffer
IDE
8/16 bit Flash
10/100 LAN/PHY
802.11a mini-PCI
home
network
Figure 2: Typical PNX8550 Dual SD/Single HD Hybrid TV Application
Figure 2 shows a typical configuration for the PNX8550. For simplicity, the optional
external video improvement processor is not shown here. In this configuration, the
PNX8550 performs the following functions:
• Conditional access for up to 2 cable/terrestrial transport stream sources
– DVB, Multi2 (M2), DES (triple and single, each in EBC or CBC)
• Audio and video decoding for up to 2 Standard Definition or 1 High Definition
MPEG-2 programs, coming in over the transport stream inputs, IEEE1394, LAN
or from an attached IDE DVD drive (not shown)
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-3
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• MPEG 2:1 compression mode video decoding in order to save memory
bandwidth for PIP application
• Acquisition of up to two CCIR656 pixel sources, one of which can be HD up to 81
Mpix/sec
• Temporal noise reduction on any internal video stream, but in particular the 656
source(s)
• Temporal-spatial video improvement processing, such as such as Digital Reality
Creation™ or Digital Natural Motion™ on 1 full resolution SD program or 2 half
resolution SD programs (MPEG2 or 656 source).
• Histogram measurement, histogram correction, black-stretch, luminance
sharpening (LTI, CDS, HDP), Digital Color Transient Improvement, color features
(green enhancement, skin tone correction, blue stretch) on the video
• Running an OS, such as Linux™ or VxWorks™, creating 1 or more graphics
surfaces
• Blending up to 5 video or graphics images for output towards the primary display
(CRT, LCD or Plasma)
• Blending 1 video and 1 graphics image for output towards the VCR over an
analog S-Video or CVBS output (VCR audio requires external low-cost stereo
DAC)
• Outputting multi-channel audio across S/PDIF (Sony/Philips Digital Interface) for
decoding in a receiver
• Decoding of image files or audio content from a MemoryStick™ or
MultiMediaCard™
• Transmitting 1 audio/video program or a transport stream across an external
1394 interface
• Transmission of 1 or more programs, subject to compute power and network
bandwidth over a home network
• Decoding/execution of Remote Control commands
• Connecting to an optional serial modem or USB modem
• Booting from Nor or Nand Flash
Since the PNX8550 is a highly flexible, highly programmable system that performs
the majority of video processing in software, a wide variety of other applications are
possible. Any application that fits the constraints of the external interfaces, the media
processing power and the available memory bandwidth can in principle be
accommodated.
Two PNX8550 can be used to create a dual HD PIP or side-by-side HD hybrid TV set.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-4
Philips Semiconductors
3. PNX8550 Feature Summary
• Dual TM3260 240 MHz, 5 instruction per clock cycle 32-bit VLIW media
processing cores
• PR4450 250 MHz MIPS32 ISA compliant general purpose CPU with demand
paging support (TLB)
• 2 simultaneous 10 bit YUV422 digital video input streams, one of which can be
HD/VGA up to 81 Mpix/s
• 2 stream MPEG2 transport stream processing (PID filtering, conditional access,
section filter, demux)
• Conditional access for DVB, Multi2 (M2), DES (triple and single, each in EBC or
CBC)
• 1 serial or parallel transport stream output (for external 1394 hookup)
• Integrated DVD-CSS, allowing full DVD playback functionality
PNX8550
Chapter 1: Functional specification
• Simultaneous hardware decode of two SD streams (MPEG2 MP@ML) or 1 HD
(MPEG2 MP@HL)
• MPEG 2:1 compression mode video decoding in order to save memory
bandwidth for PIP application
• High quality hardware image scaler and advanced de-interlacer, augmented with
media processing software to do motion compensated de-interlacing
• 5-layer compositing primary video output, with integrated scaling and video
improvement processing, supporting up to 81 Mpix/sec output (up to 1920x1080
60I or 1280 x 720 60P displays)
• 2-layer compositing secondary video output, supporting up to dual rate SD (60P
or 100i)
• Integrated PAL/NTSC Digital Video Encoder for secondary output, with Y/C or
CVBS output (single rate SD only)
• Integrated video Temporal Noise Reduction
• Integrated video measurement and histogram correction unit
• Simultaneous decode of multiple AC-3, AAC, MPEG2 L1 or L2, MP3 or similar
audio streams (media processor)
• The external memory will serve as audio delay lines for audio and video
synchronization purpose
• Dual stereo digital audio in and dual S/PDIF (Dolby Digital™) input
• Two octal channel digital audio output plus S/PDIF (Dolby Digital™) output
• High performance 2D drawing engine (line drawing, bitblt)
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-5
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• Integrated DDR SDRAM controller, 32-bit wide up to 2x225 MHz, supporting 16,
32, 64 and 128-MB unified memory configurations
• 4 programmable memory ranges that can be set as ‘sandboxes’, where each
system DMA agent can be assigned to only play in such a sandbox
• Programmable access rights for device control/status registers to prevent system
corruption or reading of confidential data by non-trusted masters
• Non-trusted masters include external CPU through PCI, and the TM-3260
processors.
• 32-bit, 33 MHz PCI 2.2 expansion bus interface
• Support for 8 and 16 bit ROM or Flash (NAND and NOR)
• 2x UART, 4xI2C (two I2C with multi master (400 KHz), and two I2C with DMA (3.4
MHz)), 2-port USB 1.1 host interface
• 4 system timers/counters, capable of counting internal and external events
• An integrated universal Remote Control receiver
• 16 dedicated General Purpose I/O pins, suitable as software I/O pins, external
interrupt pins, universal Remote Control Blaster, clock source/gate for system
event timers/counters and emulating high-speed serial protocols
• 45 additional multiplexed General Purpose I/O pins
• MemoryStick™ and MultiMediaCard™ interface capability (using GPIO pins)
• On-chip MPEG1 and MPEG2 VLD to facilitate transrating, transcoding and
software SD MPEG decoding
• Integrated low-speed IDE controller (shares PCI pins, requires 2 external buffers
to isolate)
• All video/audio timing derived from a single low-cost external crystal (no VCXOs
required)
4. Compatibility with the PNX8525
With some exceptions listed below, the PNX8550 is a functional superset of the
PNX8525 and, at the system level, is backwards compatible with the PNX8525.
Applications for the PNX8525 can be ported to the PNX8550.
The list below identifies the main functional backwards compatibility issues between
the two products:
• The PNX8550 has no on-chip 1394 or SSI interface.
• The PNX8550 has two MPEG system processors, versus three on the PNX8525.
• The PNX8550 does not have the third in or out serial audio port of the PNX8525.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-6
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
• The PNX8550 PR4450 CPU requires recompiling due to Instruction Set
architecture changes from the MIPSII-compliant PR3940 on the PNX8525 to the
new MIPS32 architecture-compliant PR4450 on the PNX8550. In addition, the
TLB has changed to become MIPS32-compliant, requiring source code changes
to memory management routines.
• The PNX8550 TM3260 CPUs are backwards binary compatible with the TM3218
CPU on the PNX8525, but recompiling allows higher performance due to
additional computational units
• MMIO addresses, and MMIO register layout are not identical - this is typically
hidden behind APIs
• The PNX8550 uses a different package, with similar (but not identical) pin
placement e.g., the PNX8525 used SDRAM while the PNX8550 uses DDR
memories.
• Everywhere else, the PNX8550 capabilities equal or exceed those of the
PNX8525
5. Analog/Digital Standard Definition Video Improvement Capabilities
5.1 Temporal-Spatial Improvement Processing
The media processors together with the advanced de-interlacer in Memory Based
Scaler block of the PNX8550, can provide sophisticated temporal-spatial video
improvement processing on either external analog sources or internally decoded
MPEG2 sources. There is sufficient media processor capability and system memory
bandwidth to perform Sony’s Digital Reality Creation™ or Philips Consumer
Electronics’ Digital Natural Motion™’ on a Standard Definition signal, decode 2
MPEG video sources and associated audio, drive a wide-XGA class progressive
screen and do discretionary additional processing.
In a dual tuner system, temporal-spatial video improvement processing can be
performed on the main (large) image, or on two half-resolution images, as shown in
Figure 3
Main Image
Program 1
PIP
Program 2
.
not improved
Program 1
improved, but at
half-resolution
Program 2
improved
Figure 3: TV Modes and Video Improvement Processing
The discretionary processing margin allows future features above and beyond those
of hardware implementations of these video improvement algorithms. For example,
an intelligent detection of regions of the screen with different type of video content
can be applied, performing different types of improvement processing depending on
the content.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-7
Philips Semiconductors
The external video improvement processor interface optionally allows running one
temporal-spatial video improved video stream through a proprietary external video
improvement device, and back directly into the PNX8550 primary video output.
5.2 Temporal Noise Reduction
Temporal Noise Reduction is typically applied only to analog sources, but can be
applied to any video stream in the system. The PNX8550 QTNR processor block
performs temporal noise reduction by reading two video fields from memory and
writing a filtered output image to memory.
6. HD Decode and Display Capabilities
One PNX8550 supports single stream HD decoding and HD display. It supports
screens of 1920x1080i or ‘wide XGA’ style progressive screens.
In HD-HD mode, all video improvement processing is available, but non motioncompensated de-interlacing is used instead of temporal-spatial processing.
PNX8550
Chapter 1: Functional specification
Table 1
below shows the key video algorithms involved in converting the ATSC
transmission to the selected display type. Display resolutions smaller than those
indicated in the table are also supported. Progressive screens larger than 1280x720
are not supported.
Table 1: HD - HD Algorithms of the PNX8550
Transmission Display Algorithm Used
1920 x 1080i 960H * 1080V 60 Hz I H downscaling
1920 x 1080i 1920H * 1080V 60 Hz I n/a
1920 x 1080i 1280H x 720V 60 Hz P
(mode 1)
1920 x 1080i 1280H x 720V 60 Hz P
(mode 2, highest quality)
1280 x 720 60 Hz P 1280H x 720V 60 Hz P n/a
1280 x 720 60 Hz P 960H x 1080V 60 Hz I Each 1280x720 frame gets scaled to a
1280 x 720 60 Hz P 1920H x 1080V 60 Hz I Each 1280x720 frame gets scaled to a
Each 1920x540 field is scaled to a 1280 x
720 frame, losing some vertical resolution.
Film detector active.
• In film mode, the telecine is undone to
create the original progressive film
images.
• In video mode, median filtering plus
slanted edge detection/reconstruction
are applied to each field pair to construct
a full resolution 1920 x 1080 frame and
then scale it back to 1280 x 720P.
960x540 field at vertically correct position.
1920x540 field at vertically correct position.
All applications use high-definition video display in order to show the maximum
performance capability of the PNX8550. The standard definition video processing
includes the software based digital natural motion application. The PNX8550
converts the standard definition video to the high-definition video using the
combination of natural motion software and the memory based scaler hardware. The
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-8
Philips Semiconductors
software natural motion requires an external device to perform the back-end of the
natural motion application. The following quality tradeoffs may be made in order to
manage the memory bandwidth requirements for more than one video processing
using the 225MHz DDR-SDRAM memory.
Using a higher speed grade DDR creates additional discretionary bandwidth for more
discretionary features.
PNX8550
Chapter 1: Functional specification
• Using a lower number of bits per pixel for the video and graphics layers
• Using a lower number of pixels per line for graphics layers
• Using YUV420 instead of YUV422 for the memory based scaler processing
• Generating PIP picture from SD VCR output if possible
• Generating PIP and VCR output from same HD video stream adds more memory
bandwidth when compared with generating VCR output from HD and PIP from
VCR output.
• Reduced natural motion quality or no natural motion if one of the video input is
high-definition bit stream or video
6.1 Dual HD Decode/Display Using Two PNX8550s
32 MB
225 MHz DDR
program 1 (TS)
program 2 (TS)
Figure 4: Dual HD Decode/Display Application
DV1
DV3
decode program1 HD
scale to 0.5 HD
all audio processing
DV_OUT1
(75 MHz 8 bit)
Figure 4 shows two PNX8550-performing dual-HD decode/displays. The first
PNX8550 decodes program 1, scales it to one-half horizontal resolution and outputs
the images across the primary output in 10-bit 656 mode. This program 1 image will
be used as the PIP image or side-by-side half resolution image. The second
PNX8550 decodes program 2 at HD resolution for use as the main image in case of
PIP, or the half horizontal image in case of a side-by-side display.
The second PNX8550 scales program 1 and 2 as needed and runs the OS. Locally
drawn graphics and both programs are composited as needed for the primary display.
Either program 1 or 2, with optional overlay graphics is sent to the VCR. The first
PNX8550 also performs all audio and discretionary media processing, since it has the
higher bandwidth margin.
program1
0.5 HD
32 MB
225 MHz DDR
DV1
decode program2 HD
run OS, draw graphics
DV3
composite all
PIP or side-by-side
program 1 + 2
full HD
QVCP5L_OUT
QVCP2L_OUT
program 1 or 2
SD for VCR
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-9
Philips Semiconductors
This same configuration can also be used as a superior quality dual SD TV. In that
case, the first PNX8550 performs temporal/spatial improvement processing on
program 1 (656 or MPEG source), and forwards it in 2, 3 or 4x pixel rate to the
second PNX8550. The second PNX8550 can perform additional SD to HD 2D local
improvement processing on program1, while decoding or receiving PIP program2
and compositing all results.
PNX8550
Chapter 1: Functional specification
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-10
Philips Semiconductors
7. Internal Functional Overview
2x225 MHz, 32-bit wide DDR
PNX8550
Chapter 1: Functional specification
Optional external coprocessors
including video enhancement chip
DV1 656/TS
DV2* 656/TS
DV3 656/TS
I2S audio*
SPDIF audio
UART1-2*
Remote Control
Gen. Purpose I/O
USB host i/f (2 port)
Smartcard1-2*
I2C (4x)
PNX8550
656
656
TS
ts & 656 router
TS
16
VIP1
VIP2
MSP1
MSP2
AI1-2
SPDI 1-2
misc. I/O,
timers/
counters,
semaphores
MMI
Peak rate: 12bit/cycle each way
Tunnel
MBS2
V Peaking
QVCP1
QVCP2
AO1-2
SPDO
TSDMA
MBS
VMPG
(1 HD or 2 SD)
656/HD/VGA
30
10
DENC
8 ch + 8 ch
QTNR
VLD2
QVCP5L_OUT
QVCP2L_OUT*
656
analog Y/C,cvbs
TS_OUT*
I2S audio*
SPDIF audio
27 MHz
xtal
boot, reset, clock
DE (2D)
DVD-CSS
JTAG
2xTM3260 Media Processor
5 issue, 240 MHz
64 kB I$
16 kB 2-port D$
128 32-bit regs
bound. scan
TM-DBG (2x)
PCI
E-DMA
PR4450 MIPS CPU
250 MHz
16 kB I$
16 kB D$
MMU
EJTAG debug
33 MHz, 32-bit PCI 2.2
(includes NAND/nor flash, IDE drive and 68k peripheral capability)
* I/Os marked with * can also function as General Purpose I/O pins if not used for a primary function.
Figure 5: PNX8550 Functional Block Diagram
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-11
Philips Semiconductors
8. Internal Functional Overview
8.1 Overview of Function Partitioning
The functionality achieved within the PNX8550 can be divided into four major
categories: control, decode, processing, and display. The audio, video and graphics
processing are controlled by the PR4450 and the TM3260-based control software.
Decode functions take input data streams and convert those streams into memory
based structures that the PNX8550 may further process. Decode functions may be
simple, as in the case of storing 656 input video into memory, or substantially more
complex, as in the case of MPEG2.
Processing functions are those that modify an existing data structure and prepare
that structure for display functions.
Display functions take the processed data structures from memory and generate the
appropriate output stream. As in the case of the decode functions, display functions
can be relatively simple, such as an I2S audio output or very complex, as in the case
of multi-surface composited displays.
PNX8550
Chapter 1: Functional specification
All decoded data structures are stored in memory, even when further processing is
not required. This mechanism implies that there is no direct path between input and
output data streams. The memory serves as the buffer to de-couple input and output
data streams. Based on the mode of operation, there may be multiple data structures
in memory for a given input stream. The PNX8550 uses the TM3260 CPUs and a
timestamping mechanism to determine when a specific memory data structure is to
be displayed.
The PNX8550 implements the required decode, processing, and display functions
with a combination of fixed function hardware and TM3260 CPU software modules.
The PR4450 MIPS processor is not intended to be involved with the three primary
function types other than to control them. The PNX8550 provides a good balance
between those functions that are implemented in fixed hardware and those that are
programmed to run on a TM3260 CPU.
Table 2
illustrates how the major tasks are implemented under each of the main
functional areas, and how they map to hardware resources or software.
Table 2: Partitioning of Functions to Resources
Function Resource Description
Video Decoding/Acquisition
Digital video acquisition VIP Includes optional h-scaling or color space conversion, and
conversion to a variety of memory pixel formats.
Conditional access, PID filtering, section
filtering, transport stream demux
En/decryption for copy protection MSP
MPEG2 HD or 2SD video decoding Software +
MPEG2 audio decoding Software
MSP MSP output streams separate video and audio elementary
streams into memory.
DES (triple and single, each in EBC or CBC)
EDMA
VMPG
AES en/decryption
Media processor software performs parsing of the video
elementary stream up to slice level. VMPG hardware block
performs decoding below slice level.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-12
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
Table 2: Partitioning of Functions to Resources
Function Resource Description
DVD authentication and de-scrambling DVD-CSS Authentication and de-scrambling in hardware
Program stream demux Software
Single program transport stream demux Software or
MSP
HD JPEG decode Software
MPEG4 video decoding Software
Audio Decoding and Improvement Processing
Audio decoding AC3, AAC, MPEG L1,
L2, MP3, others
Audio processing Software Improvement processing and mixing
Graphics
2D graphics rendering and DMA 2D DE
Video Improvement Processing
Non-motion compensated de-interlacing MBS Median, 2-field majority select, 3-field majority select with or
Motion compensated de-interlacing Software +
Motion estimation Software Pixel accurate and quarter pixel accurate versions available
Temporal up conversion
(Natural Motion)
Luminance histogram measurement,
other key video measurements
Temporal noise reduction QTNR QTNR can perform temporal noise reduction on one or more
Image scaling VIP, MBS
Video format conversions, including
color space conversion
Histogram correction, black stretch,
luminance sharpening (LTI, CDS, HDP),
Digital Color Transient Improvement,
color features (green enhancement, skin
tone correction, blue stretch)
Proprietary video improvement
processing
Software Decoders for almost any audio format available
MBS
Software Creates images temporally between two originals using motion
QTNR or MBS QTNR can do any video measurement during temporal noise
QVCP
MBS, VIP,
QVCP
QVCP Performed during output to display
An external
chip connected
to the tunnel
Interface
…Continued
Software if no conditional access or section filtering, else MSP
without EDDI postpass for edge improvement
Software provides the MBS with a motion compensated field, to
which the MBS applies the chosen de-interlacing algorithm.
vectors.
reduction on analog sources, or by reading an image from
memory without producing an output. MBS can performs video
measurement during a de-interlace or scaling pass.
streams.
VIP can perform horizontal downscaling during acquisition.
MBS and MBS2 can perform up-and downscaling horizontal and
vertical in a single pass, optionally combined with format
conversions. The MBS can also perform de-interlacing.
QVCP can perform panoramic horizontal scaling during output.
MBS can convert any pixel format to any other format. VIP can
generate multiple video formats, QVCP can read multiple video
formats.
External video enhancement chip serves as a coprocessor to
the PNX8850 and reads the required data from the PNX8850
memory and writes the enhanced video pixel data to the
PNX8850 memory. The video pixel data returned from the
external chip can be either 8-bit or10-bit semi planar YUV422.
The PNX8850 CPUs will have access to the external chip
control and status registers through the tunnel interface.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-13
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
Table 2: Partitioning of Functions to Resources
Function Resource Description
Display Processing
Input Color Look-Up 2x CLUT A CLUT may be switched into the data path for each of the 5
Surface composition with alpha
blending, chroma (range) keying
Video and graphics scaling QVCP Hi-quality panoramic horizontal scaler for video, linear
Final gamma correction
contrast, brightness, white point control
Discretionary Processing
MPEG4 video encoding Software
MPEG4 Simple or Advanced Simple
Profile decoding
H.26L video decoding Software
MPEG2 video encoding Software 1/2 D1 and other versions available
Transrating VLD +
DV decoding Software Full quality decoder available
Transcoding VMPG +
Video Conferencing.... A large variety of applications is available.
QVCP
QVCP Final gamma correction after compositing
Software
Software
Software
…Continued
QVCP layers.
interpolator for graphics
The VLD hardware can be used to parse a MPEG2 video
stream. Software composes a new MPEG2 stream including the
video stream with a reduced bit rate.
Transcoding from MPEG2 uses VMPG for decoding.
Transcoding from other standards use a software decoder.
Software performs the encode.
9. Integrated Processors
9.1 PR4450 General Purpose Processor
The PR4450 is a MIPS32 compatible general purpose CPU. It is intended for running
the demand-paged, graphics intensive operating system and user-interface, whereas
the TM3260 media processors are intended to run all real-time audio and video tasks.
The 250 MHz PR4450 processor implements a very low cost, low power and high
performance 32-bit processor ideal to be used in information appliances running
embedded operating systems such as VxWorks, or Linux.
PR4450 supports both the MIPS32 and MIPS16 instruction set architecture as
defined by MIPS Technologies Inc. MIPS16 encodes the instructions in 16-bits,
enabling a substantial reduction in the memory foot print requirements and thereby
reducing the overall system cost. The PR4450 requires re-compilation of PNX8525
source code, due to the ISA changes going from MIPS-II to MIPS32.
The PR4450 delivers 1.22 MIPS/MHz (Dhrystone 2.1) for a total of 325 MIPS. It has
an estimated power consumption of less than 1mW/Mhz which makes it an ideal core
for use in next generation information appliance system-on-silicon architectures.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-14
Philips Semiconductors
PNX8550
Chapter 1: Functional specification
Table 3: PR4450 MIPS Core Feature Summary
Feature Description
MIPS32 and MIPS16 ISA
16 kB 2-way set
associative I-Cache
Cache policies 16 kB 4-way set associative D-Cache
Line size Critical word first refill, write-back or write-through, write-allocate
MMU 32 bytes (both I-Cache and D-Cache)
Multiplier 64-entry (32 odd/even pairs) with page sizes from 4 kB to 16 MB
Debug Supports 1-cycle 32-bit multiplies and multiply-accumulate, multiply-subtract.
MIPS32 Instructions Standard built-in MIPS EJTAG 2.5 software debug support, including single step support, hardware
Register File MIPS32 adds conditional move, load-linked and store-conditional (for semaphore support), count
Pipeline 32 entry 32-bit register file for MIPS32, 11 of which are available for MIPS16 instructions
Branch Prediction Synchronous 8-stage pipeline with full hardware interlock support for data dependencies
Multiplication Dynamic branch prediction with a 4096-entry branch history table and a 256-entry branch address
MMU MAD (Multiply-Accumulate-Divide) unit with 64-bit accumulator, executing 32-bit multiply
Timers 4 GB address space support
Caches
breakpoints for instruction and data addresses and/or data value
leading zeros and ones and multiply-subtract instructions to the existing MIPS-II ISA.
cache for optimal performance
instructions with 1 cycle repetition rate
Separate user and kernel modes and TLB ASIDs (Address Space Identifiers) provide full memory
protection support.
Three 32-bit timers are provided in coprocessor zero. These timers can also be used as event
counters for performance analysis. One of the counters can also operate as a watchdog timer.
9.2 Dual TM3260 VLIW Media Processors
The two TM3260 CPUs in the PNX8550 are a version of the TriMedia 32-bit VLIW
media processor. Each processor is a 240 MHz, 5 instructions per clock cycle, Very
Long Instruction Word (VLIW) processor, with an extensive set of multimedia
instructions. It implements a superset of the TriMedia TM1300 instruction set, and
has a superset of the TM1300 functional units. It is fully binary backwards compatible
with the TM32 CPU on the PNX8525, but has a larger Instruction Cache for improved
performance. In addition, recompiling of source code results in higher media
performance due to several additional functional units.
The TM3260 supports 32-bit integer and IEEE-compatible 32-bit floating point data
formats. It also provides a Single Instruction Multiple Data (SIMD) style operation set
for operating on dual 16-bit or quad 8-bit packed data. It has a peak floating point
compute capacity of 1.1 G operations/s, and has 880 M multiply-add/s capability on
16-bit data. Its dual access 16 kB 8-way set-associative data cache provides a CPU
local data bandwidth of 1.8 GB/s. Its 64 kB 8-way set-associative instruction cache
provides 224 bits of instructions every clock cycle, for an instruction rate of 6.2 GB/s.
UM10110_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data Rev. 02 — July 21 2004 1-15
Loading...