Philips UM10109 User Manual

Download

UM10109

P89LPC932A1 8-bit microcontroller with two-clock 80C51 core

Rev. 02 — 23 May 2005 User manual

Document information

Info Content

Keywords P89LPC932, P89LPC932A1

Abstract Technical information for the P89LPC932A1 device.

Philips Semiconductors

Revision history

Rev Date Description

2 20050523

1 20040802 Initial version

• Corrected typographical error in Table 35 “Capture compare control register (CCRx -

address Exh) bit description”.

• Corrected Table 92 “Data EEPROM control register (DEECON address F1h) bit

allocation” and Table 93 “Data EEPROM control register (DEECON address F1h) bit description”.

• Removed “with 8-bit A/D” from title.

• Revised Table 37 “Output compare pin behavior” for OCMx1:0 =10.

UM10109

P89LPC932A1 User manual

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual Rev. 02 — 23 May 2005 2 of 133

Philips Semiconductors

1. Introduction

The P89LPC932A1 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC932A1 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC932A1 in order to reduce component count, board space, and system cost.

1.1 Comparison to the P89LPC932 device

The P89LPC932A1 includes several improvements compared to the P89LPC932. These improvements are described below.

1.1.1 Byte-erasability (IAP-Lite)

The original P89LPC932 allowed from 1 byte to 64 bytes of user code memory, in a single page, to be programmed using an IAP function call. The bytes to be programmed needed to have been previously erased using either a page erase, sector erase, or chip erase (in a parallel programmer) command. Thus code memory was erased in 64 byte, 1 kB, or 8 kB groups. The P89LPC932A1 allows from 1 byte to 64 bytes of a page of user code memory to be erased and reprogrammed in a single operation. The bytes to be erased and reprogrammed may be randomly addressed within a single page. Only the bytes so addressed will be affected. See Section 18.4 “

page 109.

1.1.2 Serial in-circuit programming (ICP)

UM10109

P89LPC932A1 User manual

Using Flash as data storage: IAP-Lite” on

In-Circuit Programming is a method intended to allow low cost commercial programmers to program and erase these devices without removing the microcontroller from the system. The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC932A1 through a two-wire serial interface. Philips has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins (V be available to interface your application to an external programmer in order to use this feature. This function was not available on the P89LPC932 device.

1.1.3 ‘On-the-fly’ clock selection

The RC Oscillator can be selected as the source for the CPU clock (CCLK) by using the RCCLK bit in the TRIM register (TRIM.7). This bit allows for fast ‘on-the-fly’ switching between the RC Oscillator and the clock source selected by the oscillator type select bits, FOSC[2:0], in UCFG1, without the need to reset the device. This functionality was not available on the P89LPC932. See Table 5 “

address 96h) bit description” on page 22.

, VSS, P0.5, P0.4, and RST). Only a small connector needs to

On-chip RC oscillator trim register (TRIM -

User manual Rev. 02 — 23 May 2005 3 of 133

Philips Semiconductors

1.1.4 Increased ISP/IAP functionality

1.1.4.1 Support for the watchdog timer

The ISP code has been modified to set the WDT prescaler (in WDCON) and WDL register to their maximum values. Other WDCON bits are unchanged and the ISP code does not explicitly enable or disable the WDT. Periodic feeds are provided within the ISP code to support applications that entered the ISP code with an enabled WDT. This functionality was not provided in the ISP code on the P89LPC932.

1.1.4.2 XDATA data buffer option added for programming code memory

The “program user code page” function on the P89LPC932 used IDATA as the 64 byte data buffer. An option is provided to allow the user to specify that XDATA is to be used instead as the buffer source. If the F1 flag (PSW.1) is set, then XDATA is used. If the F1 flag (PSW.1) is cleared, then IDATA is used.

1.1.4.3 Port 0 initialization

On the P89LPC932 the ISP code during initialization programmed all bits of Port 0 to the quasi-bidirectional mode and set these port pins HIGH. This has been changed such that only the TxD and RxD pins have their port mode programmed during ISP initialization. All other Port 0 pins remain in their previous state (for example, input-only mode following a reset).

UM10109

P89LPC932A1 User manual

1.1.4.4 Direct load of UART baud rate fix

A bug identified in the “direct load of baud rate” ISP function has been fixed. The baud rate source for this function has been changed from Timer 1 to the BRG.

1.1.4.5 Boot Vector and IAP entry points modified

To protect against errant code execution incrementing into the ISP or IAP routines, software reset instructions have been added to the beginning of these code blocks. This required that the ISP and IAP entry points be changed. The ISP entry point has changed to 1F00H resulting in a default Boot Vector of 1FH. The IAP entry point has changed to FF03H.

1.1.4.6 IAP authorization key

IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call. This authorization key is set by writing 96H to RAM location FFH. See Section 18.13 “

After the function call is processed by the IAP routine, the authorization key will be cleared. Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key. If an IAP routine that requires an authorization key is called without a valid authorization key present, the MCU will perform a reset.

1.1.4.7 Hardware write enable (WE) key

This device has hardware write enable protection. This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes (UCFG1, BOOTVEC, and BOOTSTAT). This protection does not apply to commercial programmer modes. When enabled, user code requesting a write function via IAP or IAP-Lite will need to explicitly set a Write Enable flag prior to requesting the write function. See Section 18.14 “

Flash write enable” on page 119

IAP authorization key” on page 118

User manual Rev. 02 — 23 May 2005 4 of 133

Philips Semiconductors

1.1.4.8 Configuration byte protection

A separate write protection bit has been provided for the “configuration bytes”. These bytes include UCFG1, BootStat, Boot Vector, and the sector security bytes. This write protection applies for ISP and IAP modes. It does not apply to commercial programmer modes. See Section 18.15 “

1.1.5 Previous errata fix

Most known errata on the P89LPC932 devices has been fixed on the P89LPC932A1 device. For current errata information on the P89LPC932A1, if any, please see the P89LPC932A1 errata sheet.

1.2 Pin configuration

UM10109

P89LPC932A1 User manual

Configuration byte protection” on page 119

P89LPC932A1FDH

ICB/P2.0

OCD/P2.1

KBI0/CMP2/P0.0

OCC/P1.7

OCB/P1.6

RST/P1.5

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

INT1/P1.4

SDA/INT0/P1.3

SCL/T0/P1.2

MOSI/P2.2

MISO/P2.3

Fig 1. P89LPC932A1 TSSOP28 pin configuration.

002aaa886

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

User manual Rev. 02 — 23 May 2005 5 of 133

Philips Semiconductors

P1.7/OCC

P0.0/CMP2/KBI0

P2.1/OCD

P2.0/ICB

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

UM10109

P89LPC932A1 User manual

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P89LPC932A1FA

121314

P1.2/T0/SCL

P2.4/SS

P2.2/MOSI

P2.3/MISO

Fig 2. P89LPC932A1 PLCC28 pin configuration.

terminal 1

index area

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.7/OCC

P2.1/OCD

P2.0/ICB

P0.0/CMP2/KBI0

28272625242322

1 21

2 20

4 18

P89LPC932A1FHN

5 17

6 16

7 15

1011121314

161718

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

002aaa887

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

002aaa889

P2.4/SS

P2.2/MOSI

P2.3/MISO

P1.2/T0/SCL

Transparent top view

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

Fig 3. P89LPC932A1 HVQFN28 pin configuration.

User manual Rev. 02 — 23 May 2005 6 of 133

Philips Semiconductors

1.3 Pin description

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P0.0 to P0.7 3, 26, 25,

24, 23, 22, 20, 19

327I/OP0.0 — Port 0 bit 0.

26 22 I/O P0.1 — Port 0 bit 1.

25 21 I/O P0.2 — Port 0 bit 2.

24 20 I/O P0.3 — Port 0 bit 3.

23 19 I/O P0.4 — Port 0 bit 4.

22 18 I/O P0.5 — Port 0 bit 5.

HVQFN28

27, 22, 21, 20, 19, 18, 16, 15

I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.

During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 “Port configurations” and the P89LPC932A1 data sheet, Static characteristics for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

O CMP2 — Comparator 2 output.

I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B.

I KBI1 — Keyboard input 1.

I CIN2A — Comparator 2 positive input A.

I KBI2 — Keyboard input 2.

I CIN1B — Comparator 1 positive input B.

I KBI3 — Keyboard input 3.

I CIN1A — Comparator 1 positive input A.

I KBI4 — Keyboard input 4.

I CMPREF — Comparator reference (negative) input.

I KBI5 — Keyboard input 5.

UM10109

P89LPC932A1 User manual

User manual Rev. 02 — 23 May 2005 7 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P0.0 to P0.7 (continued)

20 16 I/O P0.6 — Port 0 bit 6.

19 15 I/O P0.7 — Port 0 bit 7.

…continued

HVQFN28

O CMP1 — Comparator 1 output.

I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overflow output.

I KBI7 — Keyboard input 7.

User manual Rev. 02 — 23 May 2005 8 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P1.0 to P1.7 18, 17, 12,

11, 10, 6, 5, 4

18 14 I/O P1.0 — Port 1 bit 0.

17 13 I/O P1.1 — Port 1 bit 1.

12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

11 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

10 6 I P1.4 — Port 1 bit 4.

62 IP1.5 — Port 1 bit 5 (input only).

51 I/OP1.6 — Port 1 bit 6.

428I/OP1.7 — Port 1 bit 7.

…continued

HVQFN28

14, 13, 8, 7, 6, 2, 1, 28

[1]

I/O, I

O TXD — Transmitter output for the serial port.

I RXD — Receiver input for the serial port.

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain

I/O SCL — I

I INT0

I/O SDA — I

I INT1

I RST

O OCB — Output Compare B

O OCC — Output Compare C

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 4.1 “ and the P89LPC932A1 data sheet, Static characteristics for details.

P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

when used as output).

— External interrupt 0 input.

— External interrupt 1 input.

— External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until V specified level. When system power is removed V the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

Port configurations”

C serial clock input/output.

C serial data input/output.

has reached its

falls below the minimum specified operating voltage.

will fall below

User manual Rev. 02 — 23 May 2005 9 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P2.0 to P2.7 1, 2, 13,

14, 15, 16, 27, 28

125I/OP2.0 — Port 2 bit 0.

226I/OP2.1 — Port 2 bit 1.

13 9 I/O P2.2 — Port 2 bit 2.

14 10 I/O P2.3 — Port 2 bit 3.

15 11 I/O P2.4 — Port 2 bit 4.

16 12 I/O P2.5 — Port 2 bit 5.

27 23 I/O P2.6 — Port 2 bit 6.

28 24 I/O P2.7 — Port 2 bit 7.

…continued

HVQFN28

25, 26, 9, 10, 11, 12, 23, 24

I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.

During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 “ the P89LPC932A1 data sheet, Static characteristics for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

I ICB — Input Capture B

O OCD — Output Compare D

I/O MOSI — SPI master out slave in. When configured as master, this pin is

output; when configured as slave, this pin is input.

I/O MISO — When configured as master, this pin is input, when configured

as slave, this pin is output.

I SS

I/O SPICLK — SPI clock. When configured as master, this pin is output;

O OCA — Output Compare A

I ICA — Input Capture A

— SPI Slave select.

when configured as slave, this pin is input.

Port configurations” and

User manual Rev. 02 — 23 May 2005 10 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P3.0 to P3.1 9, 8 5, 4 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.

95 I/OP3.0 — Port 3 bit 0.

84 I/OP3.1 — Port 3 bit 1.

73 IGround: 0 V reference.

21 17 I Power Supply: This is the power supply voltage for normal operation as

…continued

HVQFN28

During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 data sheet, Static characteristics for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator

option is selected via the FLASH configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer.

I XTAL1 — Input to the oscillator circuit and internal clock generator

circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer.

well as Idle and Power-down modes.

and the P89LPC932A1

[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

User manual Rev. 02 — 23 May 2005 11 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

P89LPC932A1

8 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM

512-BYTE

DATA EEPROM

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

ACCELERATED 2-CLOCK 80C51 CPU

internal

bus

UART

I2C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

CCU (CAPTURE/ COMPARE UNIT)

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CRYSTAL

RESONATOR

CONFIGURABLE

OSCILLATOR

Fig 4. P89LPC932A1 block diagram.

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

CPU clock

ON-CHIP

OSCILLATOR

002aaa885

User manual Rev. 02 — 23 May 2005 12 of 133

Philips Semiconductors

1.4 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

UM10109

P89LPC932A1 User manual

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

User manual Rev. 02 — 23 May 2005 13 of 133

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 02 — 23 May 2005 14 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 0000 0000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0

B* B register F0H 00 0000 0000

BRGR0

BRGR1

BRGCON Baud rate generator

CCCRA Capture compare A control

CCCRB Capture compare B control

CCCRC Capture compare C control

CCCRD Capture compare D control

CMP1 Comparator 1 control

CMP2 Comparator 2 control

DEECON Data EEPROM control

DEEDAT Data EEPROM data

DEEADR Data EEPROM address

DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

[2]

Baud rate generator rate low

[2]

Baud rate generator rate high

control

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

BEH 00 0000 0000

BFH 00 0000 0000

BDH------SBRGSBRGEN00

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 0000 0000

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 0000 0000

ECH-----FCOCOCMC1OCMC000xxxxx000

EDH-----FCODOCMD1OCMD000xxxxx000

ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

F1H EEIF HVERR ECTL1 ECTL0 - - - EADR8 0E 0000 1110

F2H 00 0000 0000

F3H 00 0000 0000

95H 00 0000 0000

MSB LSB Hex Binary

[2]

[1]

Philips Semiconductors

xxxx xx00

xx00 0000

P89LPC932A1 User manual

UM10109

User manual Rev. 02 — 23 May 2005 15 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

DPH Data pointer high 83H 00 0000 0000

DPL Data pointer low 82H 00 0000 0000

I2ADR I

I2CON* I

I2DAT I

I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

ICRAH Input capture A register

ICRAL Input capture A register

ICRBH Input capture B register

ICRBL Input capture B register

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

IEN1* Interrupt enable 1 E8H EIEE EST - ECCU ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PIEE PST - PCCU PSPI PC PKBI PI2C 00

IP1H Interrupt priority 1 high F7H PIEEH PSTH - PCCUH PSPIH PCH PKBIH PI2CH 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

Bit address DF DE DD DC DB DA D9 D8

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

C data register DAH

DDH 00 0000 0000

duty cycle register high

DCH 00 0000 0000

duty cycle register low

C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000

ABH 00 0000 0000

high

AAH 00 0000 0000

low

AFH 00 0000 0000

high

AEH 00 0000 0000

low

Bit address AF AE AD AC AB AA A9 A8

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

Bit address FF FE FD FC FB FA F9 F8

MSB LSB Hex Binary

[1]

PT1H PX1H PT0H PX0H 00

PSRH

[1]

00x0 0000

x000 0000

00x0 0000

Philips Semiconductors

P89LPC932A1 User manual

UM10109

User manual Rev. 02 — 23 May 2005 16 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 1111 1111

OCRAH Output compare A register

OCRAL Output compare A register

OCRBH Output compare B register

OCRBL Output compare B register

OCRCH Output compare C register

OCRCL Output compare C register

OCRDH Output compare D register

OCRDL Output compare D register

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H OCC OCB RST

P2* Port 2 A0H ICA OCA SPICLK SS

P3*Port3 B0H------XTAL1XTAL2

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

86H 00 0000 0000

EFH 00 0000 0000

high

EEH 00 0000 0000

low

FBH 00 0000 0000

high

FAH 00 0000 0000

low

FDH 00 0000 0000

high

FCH 00 0000 0000

low

FFH 00 0000 0000

high

FEH 00 0000 0000

low

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address B7 B6 B5 B4 B3 B2 B1 B0

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

CIN1A

/KB4

INT1 INT0/

CIN1B

/KB3

SDA

MISO MOSI OCD ICB

KBIF 00

_SEL

CIN2A

/KB2

T0/SCL RXD TXD

CIN2B

/KB1

CMP2

/KB0

[1]

Philips Semiconductors

xxxx xx00

[1]

P89LPC932A1 User manual

[1]

UM10109

[1]

1111 1111

User manual Rev. 02 — 23 May 2005 17 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

P3M1Port3 output mode1B1H------(P3M1.1)(P3M1.0)03

P3M2Port3 output mode2B2H------(P3M2.1)(P3M2.0)00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000

PCONA Power control register A B5H RTCPD DEEPD VCPD - I2PD SPPD SPD CCUPD 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register

RTCL Real-time clock register

SADDR Serial port address

SADEN Serial port address enable B9H 00 0000 0000

SBUF Serial Port data buffer

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address D7 D6 D5 D4 D3 D2 D1 D0

D2H 00

high

D3H 00

low

A9H 00 0000 0000

99H xx xxxx xxxx

MSB LSB Hex Binary

[1]

[1][6]

[6]

Philips Semiconductors

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000

xxxx xx11

xxxx xx00

0000 0000

[3]

011x xx00

0000 0000

P89LPC932A1 User manual

UM10109

User manual Rev. 02 — 23 May 2005 18 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

SSTAT Serial port extended status

SP Stack pointer 81H 07 0000 0111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

SPSTAT SPI status register E1H SPIF WCOL - - ----0000xxxxxx

SPDAT SPI data register E3H 00 0000 0000

TAMOD Timer 0 and 1 auxiliary

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

TCR20* CCU control register 0 C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000

TCR21 CCU control register 1 F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0 00 0xxx 0000

TH0 Timer 0 high 8CH 00 0000 0000

TH1 Timer 1 high 8DH 00 0000 0000

TH2 CCU timer high CDH 00 0000 0000

TICR2 CCU interrupt control

TIFR2 CCU interrupt flag register E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A 00 0000 0x00

TISE2 CCU interrupt status

TL0 Timer 0 low 8AH 00 0000 0000

TL1 Timer 1 low 8BH 00 0000 0000

TL2 CCU timer low CCH 00 0000 0000

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T

TOR2H CCU reload register high CFH 00 0000 0000

TOR2L CCU reload register low CEH 00 0000 0000

TPCR2H Prescaler control register

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000

8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0

mode

Bit address 8F 8E 8D 8C 8B 8A 89 88

C9H TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A - TICIE2B TICIE2A 00 0000 0x00

DEH-----ENCINT.

encode register

CBH------TPCR2H.

high

…continued

Bit functions and addresses Reset value

MSB LSB Hex Binary

ENCINT.1ENCINT.000 xxxx x000

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000

TPCR2H.000 xxxx xx00

Philips Semiconductors

P89LPC932A1 User manual

UM10109

User manual Rev. 02 — 23 May 2005 19 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TPCR2L Prescaler control register

TRIM Internal oscillator trim

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

WDL Watchdog load C1H FF 1111 1111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

[1] All por ts are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

CAH TPCR2L.7TPCR2L.6TPCR2L.5TPCR2L.4TPCR2L.3TPCR2L.2TPCR2L.1TPCR2L.000 0000 0000

low

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

xx110000.

Other resets will not affect WDTOF.

…continued

Bit functions and addresses Reset value

MSB LSB Hex Binary

[5] [6]

[4] [6]

Philips Semiconductors

P89LPC932A1 User manual

UM10109

Philips Semiconductors

1.5 Memory organization

FF00h

FFEFh

1FFFh

1E00h

1C00h 1BFFh

1800h 17FFh

1400h 13FFh

1000h

0FFFh

0C00h 0BFFh

0800h 07FFh

0400h 03FFh

0000h

IAP entry-

points

ISP CODE

(512B)*

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

read-protected

IAP calls only

IDATA routines

entry points for:

-51 ASM. code

-C code

ISP serial loader

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.*

flexible choices:

-as supplied (UART)

-Philips libraries*

-user-defined

FFEFh

FF1Fh

FF00h

1FFFh

1E00h

entry points

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

UM10109

P89LPC932A1 User manual

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

002aaa948

Fig 5. P89LPC932A1 memory map.

The various P89LPC932A1 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC932A1 has 8 kB of on-chip Code memory.

Table 3: Data RAM arrangement

Type Data RAM Size (bytes)

DATA Directly and indirectly addressable memory 128

IDATA Indirectly addressable memory 256

User manual Rev. 02 — 23 May 2005 20 of 133

Philips Semiconductors

2. Clocks

2.1 Enhanced CPU

The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC932A1 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 6

Section 2.8 “

OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is

P89LPC932A1 User manual

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

⁄2.

UM10109

and

is defined as the

osc

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC932A1 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

2.2.2 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

2.2.3 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.2.4 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this configuration.

2.3 Clock output

The P89LPC932A1 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC932A1. This output is enabled by the ENCLK bit in the TRIM register

User manual Rev. 02 — 23 May 2005 21 of 133

Philips Semiconductors

P89LPC932A1 User manual

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

UM10109

2.4 On-chip RC oscillator option

The P89LPC932A1 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ± 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC932A1 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

Table 4: On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

Table 5: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset,

1TRIM.1

2TRIM.2

3TRIM.3

4TRIM.4

5TRIM.5

6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

being used.

fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle. The original P89LPC932 required a reset

cycle in order to switch between clock sources.

⁄2 is output on the XTAL2 pin provided the crystal oscillator is not

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until V

has reached its specified

User manual Rev. 02 — 23 May 2005 22 of 133

Philips Semiconductors

level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low

Fig 6. Using the crystal oscillator.

UM10109

P89LPC932A1 User manual

quartz crystal or

ceramic resonator

P89LPC932A1

XTAL1

(1)

XTAL2

002aab008

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

frequency crystals (see text).

XTAL1

XTAL2

(7.3728 MHz ±1 %)

(400 kHz )

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

OSCILLATOR

WATCHDOG

OSCILLATOR

+20 %

−30 %

RCCLK

TIMER 0 AND

TIMER 1

OSCCLK

I2C-BUS

PCLK

DIVM

SPI

CCLK

PCLK

÷2

UART

(P89LPC932A1)

Fig 7. Block diagram of oscillator control.

2.7 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC932A1 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 µs to 100 µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

RTC

CPU

WDT

32 × PLL

CCU

002aaa891

User manual Rev. 02 — 23 May 2005 23 of 133

Philips Semiconductors

2.8 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

UM10109

P89LPC932A1 User manual

2.9 Low power select

3. Interrupts

osc

/ (2N)

osc

to f

osc

/510.

CCLK frequency = f

Where: f

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f (for N = 0, CCLK = f

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

The P89LPC932A1 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

is the frequency of OSCCLK, N is the value of DIVM.

osc

The P89LPC932A1 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC932A1’s 15 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level. Ta bl e 7 addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake-up the CPU from a Power-down mode.

summarizes the interrupt sources, flag bits, vector

User manual Rev. 02 — 23 May 2005 24 of 133

Philips Semiconductors

3.1 Interrupt priority structure

Table 6: Interrupt priority level

Priority bits

IPxH IPx Interrupt priority level

0 0 Level 0 (lowest priority)

01Level 1

10Level 2

11Level 3

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Tab le 7

The P89LPC932A1 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn triggered. In this mode if consecutive samples of the INTn cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

UM10109

P89LPC932A1 User manual

pin. If ITn = 1, external interrupt n is edge

pin show a high level in one

Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC932A1 is put into Power-down mode or Idle mode, the interrupt occurrence will cause the processor to wake-up and resume operation. Refer to Section 5.3 “

reduction modes” for details.

3.2 External Interrupt pin glitch suppression

Most of the P89LPC932A1 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0 suppression circuits. Therefore, INT1

/P1.3 and SCL/T0/P1.2 do not have the glitch

has glitch suppression while INT0 does not.

Power

User manual Rev. 02 — 23 May 2005 25 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 7: Summary of interrupts

Description Interrupt flag

bit(s)

External interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes

Timer 0 interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No

External interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 7 Yes

Timer 1 interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 10 No

Serial port Tx and Rx TI and RI 0023h ES/ESR (IEN0.4) IP0H.4, IP0.4 13 No

Serial port Rx RI

Brownout detect BOF 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes

Watchdog timer/Real-time clock

C interrupt SI 0033h EI2C (IEN1.0) IP0H.0, IP0.0 5 No

KBI interrupt KBIF 003Bh EKBI (IEN1.1) IP0H.0, IP0.0 8 Yes

Comparators 1 and 2 interrupts

SPI interrupt SPIF 004Bh ESPI (IEN1.3) IP1H.3, IP1.3 14 No

Capture/Compare Unit 005Bh ECCU(IEN1.4) IP1H.4, IP1.4 6 No

Serial port Tx TI 006Bh EST (IEN1.6) IP0H.0, IP0.0 12 No

Data EEPROM ADCI1, BNDI1 0073h EAD (IEN1.7) IP1H.7, IP1.7 15 (lowest) No

WDOVF/RTCF 0053h EWDRT (IEN0.6) IP0H.6, IP0.6 3 Yes

CMF1/CMF2 0043h EC (IEN1.2) IP0H.0, IP0.0 11 Yes

Vector address

Interrupt enable bit(s)

Interrupt priority

UM10109

Arbitration ranking

Powerdown wake-up

User manual Rev. 02 — 23 May 2005 26 of 133

Philips Semiconductors

RTCF ERTC

(RTCCON.1)

WDOVF

any CCU interrupt (1)

IE0

EX0

IE1

EX1

BOPD

EBO

KBIF EKBI

EWDRT

CMF2 CMF1

EA (IE0.7)

TF0 ET0

TF1 ET1

TI & RI/RI

ES/ESR

EST

EI2C

SPIF ESPI

ECCU

EEIF EIEE

UM10109

P89LPC932A1 User manual

wake-up (if in power-down)

interrupt to CPU

002aaa892

(1) See Section 9 “

Capture/Compare Unit (CCU)”.

Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources.

4. I/O ports

The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1, and 2 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Ta bl e 8

Table 8: Number of I/O pins available

Clock source Reset option Number of I/O

On-chip oscillator or watchdog oscillator

External clock input No external reset (except during power up) 25

Low/medium/high speed oscillator (external crystal or resonator)

[1] Required for operation above 12 MHz.

No external reset (except during power up) 26

External RST

pin supported 25

pin supported

No external reset (except during power up) 24

External RST

pin supported

pins

[1]

User manual Rev. 02 — 23 May 2005 27 of 133

Philips Semiconductors

4.1 Port configurations

All but three I/O port pins on the P89LPC932A1 may be configured by software to one of four types on a pin-by-pin basis, as shown in Ta b le 9 (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

UM10109

P89LPC932A1 User manual

. These are: quasi-bidirectional

P1.5 (RST

P1.2 (SCL/T0) and P1.3 (SDA/INT0 open drain.

Table 9: Port output configuration settings

PxM1.y PxM2.y Port output mode

0 0 Quasi-bidirectional

0 1 Push-pull

1 0 Input only (high-impedance)

1 1 Open drain

) can only be an input and cannot be configured.

) may only be configured to be either input-only or

4.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

The quasi-bidirectional port configuration is shown in Figure 9

Although the P89LPC932A1 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit

User manual Rev. 02 — 23 May 2005 28 of 133

causing extra power consumption. Therefore, applying 5 V to pins

Philips Semiconductors

(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

UM10109

P89LPC932A1 User manual

port latch

data

Fig 9. Quasi-bidirectional output.

4.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

2 CPU

CLOCK DELAY

PP P

input

data

very

weak

weakstrong

glitch rejection

PORT

002aaa914

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open drain port configuration is shown in Figure 10

An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications.

PORT

port latch

data

input data

glitch rejection

Fig 10. Open drain output.

User manual Rev. 02 — 23 May 2005 29 of 133

002aaa915

Philips Semiconductors

4.4 Input-only configuration

The input port configuration is shown in Figure 11. It is a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

UM10109

P89LPC932A1 User manual

input

data

glitch rejection

Fig 11. Input only.

PORT

002aaa916

4.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 12

A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

strong

PORT

port latch

data

input data

Fig 12. Push-pull output.

User manual Rev. 02 — 23 May 2005 30 of 133

glitch rejection

002aaa917

Philips Semiconductors

4.6 Port 0 and Analog Comparator functions

The P89LPC932A1 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Figure 11

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively. Setting the corresponding bit in PT0AD disables that pin’s digital input. Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port.

On any reset, PT0AD bits 1 through 5 default to logic 0s to enable the digital functions.

4.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

UM10109

P89LPC932A1 User manual

• After power-up, all I/O pins except P1.5, may be configured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or

open drain.

Every output on the P89LPC932A1 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC932A1 data sheet for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

Table 10: Port output configuration

Port pin Configuration SFR bits

PxM1.y PxM2.y Alternate usage Notes

P0.0 P0M1.0 P0M2.0 KBIO, CMP2

P0.1 P0M1.1 P0M2.1 KBI1, CIN2B Refer to Section 4.6 “

P0.2 P0M1.2 P0M2.2 KBI2, CIN2A

P0.3 P0M1.3 P0M2.3 KBI3, CIN1B

P0.4 P0M1.4 P0M2.4 KBI4, CIN1A

P0.5 P0M1.5 P0M2.5 KBI5, CMPREF

P0.6 P0M1.6 P0M2.6 KBI6, CMP1

P0.7 P0M1.7 P0M2.7 KBI7, T1

P1.0 P1M1.0 P1M2.0 TxD

P1.1 P1M1.1 P1M2.1 RxD

P1.2 P1M1.2 P1M2.2 T0, SCL Input-only or open-drain

P1.3 P1M1.3 P1M2.3 INTO

P1.4 P1M1.4 P1M2.4 INT1

P1.5 P1M1.5 P1M2.5 RST

Port 0 and Analog Comparator functions” for

usage as analog inputs.

, SDA input-only or open-drain

User manual Rev. 02 — 23 May 2005 31 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 10: Port output configuration

Port pin Configuration SFR bits

PxM1.y PxM2.y Alternate usage Notes

P1.6 P1M1.6 P1M2.6

P1.7 P1M1.7 P1M2.7

P3.0 P3M1.0 P3M2.0 CLKOUT, XTAL2

P3.1 P3M1.1 P3M2.1 XTAL1

5. Power monitoring functions

The P89LPC932A1 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.

5.1 Brownout detection

The Brownout Detect function determines if the power supply voltage drops below a certain level. The default operation for a Brownout Detection is to cause a processor reset. However, it may alternatively be configured to generate an interrupt by setting the BOI (PCON.4) bit and the EBO (IEN0.5) bit.

Enabling and disabling of Brownout Detection is done via the BOPD (PCON.5) bit, bit field PMOD1/PMOD0 (PCON[1:0]) and user configuration bit BOE (UCFG1.5). If BOE is in an unprogrammed state, brownout is disabled regardless of PMOD1/PMOD0 and BOPD. If BOE is in a programmed state, PMOD1/PMOD0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled. PMOD1/PMOD0 is used to select the power reduction mode. If PMOD1/PMOD0 = ‘11’, the circuitry for the Brownout Detection is disabled for lowest power consumption. BOPD defaults to logic 0, indicating brownout detection is enabled on power-on if BOE is programmed.

…continued

If Brownout Detection is enabled, the brownout condition occurs when V Brownout trip voltage, VBO (see P89LPC932A1 data sheet, Static characteristics), and is negated when V power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

If Brownout Detect is enabled (BOE programmed, PMOD1/PMOD0 ≠ ‘11’, BOPD = 0), BOF (RSTSRC.5) will be set when a brownout is detected, regardless of whether a reset or an interrupt is enabled. BOF will stay set until it is cleared in software by writing a logic 0 to the bit. Note that if BOE is unprogrammed, BOF is meaningless. If BOE is programmed, and a initial power-on occurs, BOF will be set in addition to the power-on flag (POF - RSTSRC.4).

For correct activation of Brownout Detect, certain V observed. Please see the data sheet for specifications.

User manual Rev. 02 — 23 May 2005 32 of 133

rises above VBO. If the P89LPC932A1 device is to operate with a

rise and fall times must be

falls below the

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 11: Brownout options

BOE (UCFG1.5)

0 (erased) XX X X X X Brownout disabled. V

1(program med)

PMOD1/ PMOD0 (PCON[1:0])

11 (total power-down)

≠ 11 (any mode other than total power-down)

[1]

BOPD (PCON.5)

XXXX

1 (brownout detect power-down)

0 (brownout detect active)

BOI (PCON.4)

X X X Brownout disabled. V

0 (brownout detect generates reset)

1 (brownout detect generates an interrupt)

EBO (IEN0.5)

X X Brownout reset enabled. V

1 (enable brownout interrupt)

0 X Both brownout reset and

EA (IEN0.7) Description

1 (global interrupt enable)

operating range is 2.4 V to 3.6 V.

operating range is 2.4 V to 3.6 V. However, BOPD is default to logic 0 upon power-up.

operating range is 2.7 V to 3.6 V. Upon a brownout reset, BOF (RSTSRC.5) will be set to indicate the reset source. BOF can be cleared by writing a logic 0 to the bit.

Brownout interrupt enabled. V operating range is 2.7 V to 3.6 V. Upon a brownout interrupt, BOF (RSTSRC.5) will be set. BOF can be cleared by writing a logic 0 to the bit.

interrupt disabled. V range is 2.4 V to 3.6 V. However, BOF (RSTSRC.5) will be set when V Detection trip point. BOF can be cleared by writing a logic 0 to the bit.

falls to the Brownout

operating

[1] Cannot be used with operation above 12 MHz as this requires VDD of 3.0 V or above.

5.2 Power-on detection

The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function. The POF flag (RSTSRC.4) is set to indicate an initial power-on condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. Note that if BOE (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless.

5.3 Power reduction modes

The P89LPC932A1 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Ta b le 1 2

User manual Rev. 02 — 23 May 2005 33 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 12: Power reduction modes

PMOD1 (PCON.1)

0 0 Normal mode (default) - no power reduction.

0 1 Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the

1 0 Power-down mode:

PMOD0 (PCON.0)

Description

processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC932A1 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set. External interrupts should be programmed to level-triggered mode to be used to exit Power-down mode.

In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V wake-up the processor via Reset in this situation. V before the Power-down mode is exited.

When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. Oscillator stability is determined by counting 1024 CPU clocks after start-up when one of the crystal oscillator configurations is used, or 256 clocks after start-up for the internal RC or external clock input configurations.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include:

has been lowered to VRAM, therefore it is recommended to

must be raised to within the operating range

UM10109

• Brownout Detect

• Watchdog Timer if WDCLK (WDCON.0) is logic 1.

• Comparators (Note: Comparators can be powered down separately with PCONA.5 set to

logic 1 and comparators disabled);

• Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless

RTCPD, i.e., PCONA.7 is logic 1).

1 1 Total Power-down mode: This is the same as Power-down mode except that the Brownout

Detection circuitry and the voltage comparators are also disabled to conserve additional power. Note that a brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

The following are the wake-up options supported:

• Watchdog Timer if WDCLK (WDCON.0) is logic 1. Could generate Interrupt or Reset, either

one can wake up the device

• External interrupts INTO/INT1 (when programmed to level-triggered mode).

• Keyboard Interrupt

• Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless

RTCPD, i.e., PCONA.7 is logic 1).

Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock is running during power-down.

User manual Rev. 02 — 23 May 2005 34 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 13: Power Control register (PCON - address 87h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0

Reset00000000

Table 14: Power Control register (PCON - address 87h) bit description

Bit Symbol Description

0 PMOD0 Power Reduction Mode (see Section 5.3

1PMOD1

2 GF0 General Purpose Flag 0. May be read or written by user software, but has no effect

on operation

3 GF1 General Purpose Flag 1. May be read or written by user software, but has no effect

on operation

4 BOI Brownout Detect Interrupt Enable. When logic 1, Brownout Detection will generate a

interrupt. When logic 0, Brownout Detection will cause a reset

5 BOPD Brownout Detect power-down. When logic 1, Brownout Detect is powered down and

therefore disabled. When logic 0, Brownout Detect is enabled. (Note: BOPD must be logic 0 before any programming or erasing commands can be issued. Otherwise these commands will be aborted.)

6 SMOD0 Framing Error Location:

)

• When logic 0, bit 7 of SCON is accessed as SM0 for the UART.

• When logic 1, bit 7 of SCON is accessed as the framing error status (FE) for the

UART

7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud

rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When logic 0, the Timer 1 overflow rate is divided by two before being supplied to the UART. (See Section 10

)

Table 15: Power Control register A (PCONA - address B5h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RTCPD DEEPD VCPD - I2PD SPPD SPD CCUPD

Reset00000000

Table 16: Power Control register A (PCONA - address B5h) bit description

Bit Symbol Description

0 CCUPD Compare/Capture Unit (CCU) power-down: When logic 1, the internal clock to the

CCU is disabled. Note that in either Power-down mode or Total Power-down mode, the CCU clock will be disabled regardless of this bit. (Note: This bit is overridden by the CCUDIS bit in FCFG1. If CCUDIS = 1, CCU is powered down.)

1 SPD Serial Port (UART) power-down: When logic 1, the internal clock to the UART is

disabled. Note that in either Power-down mode or Total Power-down mode, the UART clock will be disabled regardless of this bit.

2 SPPD SPI power-down: When logic 1, the internal clock to the SPI is disabled. Note that in

either Power-down mode or Total Power-down mode, the SPI clock will be disabled regardless of this bit.

3I2PDI

User manual Rev. 02 — 23 May 2005 35 of 133

C power-down: When logic 1, the internal clock to the I2C-bus is disabled. Note that in either Power-down mode or Total Power-down mode, the I disabled regardless of this bit.

C clock will be

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 16: Power Control register A (PCONA - address B5h) bit description

Bit Symbol Description

4- reserved

5 VCPD Analog Voltage Comparators power-down: When logic 1, the voltage comparators

are powered down. User must disable the voltage comparators prior to setting this bit.

6 DEEPD Data EEPROM power-down: When logic 1, the Data EEPROM is powered down.

Note that in either Power-down mode or Total Power-down mode, the Data EEPROM will be powered down regardless of this bit.

7 RTCPD Real-time Clock power-down: When logic 1, the internal clock to the Real-time

Clock is disabled.

…continued

6. Reset

The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. When using an

oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until V

has reached its specified level. When system power is removed VDD will fall

below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V specified operating voltage.

falls below the minimum

Note: During a power-on sequence, The RPE selection is overridden and this pin will

always functions as a reset input. An external circuit connected to this pin should not hold this pin low during a Power-on sequence as this will keep the device in reset. After power-on this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-on reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.

Note: During a power cycle, V Static characteristics) before power is reapplied, in order to ensure a power-on reset.

Reset can be triggered from the following sources (see Figure 13

must fall below V

(see P89LPC932A1 data sheet,

POR

• External reset pin (during power-on or if user configured via UCFG1);

• Power-on Detect;

• Brownout Detect;

• Watchdog Timer;

• Software reset;

• UART break detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are

cleared.

User manual Rev. 02 — 23 May 2005 36 of 133

Philips Semiconductors

• For any other reset, any previously set flag bits that have not been cleared will remain

set.

UM10109

P89LPC932A1 User manual

RPE (UCFG1.6)

RST pin

WDTE (UCFG1.7)

watchdog timer reset

software reset SRST (AUXR1.3)

power-on detect

UART break detect

EBRR (AUXR1.6)

brownout detect reset

BOPD (PCON.5)

Fig 13. Block diagram of reset.

Table 17: Reset Sources register (RSTSRC - address DFh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - - BOF POF R_BK R_WD R_SF R_EX

[1]

Reset

xx110000

chip reset

002aaa91

[1] The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

Table 18: Reset Sources register (RSTSRC - address DFh) bit description

Bit Symbol Description

0 R_EX external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared by software by writing a

logic 0 to the bit or a Power-on reset. If RST

1 R_SF software reset Flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset

2 R_WD Watchdog Timer reset flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset.(NOTE:

UCFG1.7 must be = 1)

3 R_BK break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1, a system reset will occur.

This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a logic 0 to the bit or on a Power-on reset.

4 POF Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up

condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)

5 BOF Brownout Detect Flag. When Brownout Detect is activated, this bit is set. It will remain set until cleared by

software by writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag bits are cleared.)

6:7 - reserved

is still asserted after the Power-on reset is over, R_EX will be set.

User manual Rev. 02 — 23 May 2005 37 of 133

Philips Semiconductors

6.1 Reset vector

Following reset, the P89LPC932A1 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has been forced into ISP mode. Otherwise, instructions will be fetched from address 0000H.

7. Timers 0 and 1

The P89LPC932A1 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see Ta bl e 2 0 overflow has been added.

In the ‘Timer’ function, the timer is incremented every PCLK.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition on its corresponding external input pin (T0 or T1). The external input is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes two machine cycles (four CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

UM10109

P89LPC932A1 User manual

). An option to automatically toggle the Tx pin upon timer

⁄4 of the

The ‘Timer’ or ‘Counter’ function is selected by control bits TnC/T and 1 respectively) in the Special Function Register TMOD. Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6), which are selected by bit-pairs (TnM1, TnM0) in TMOD and TnM2 in TAMOD. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different. The operating modes are described later in this section.

Table 19: Timer/Counter Mode register (TMOD - address 89h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol T1GATE T1C/T

Reset00000000

Table 20: Timer/Counter Mode register (TMOD - address 89h) bit description

Bit Symbol Description

0 T0M0 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

1T0M1

2T0C/T

3 T0GATE Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0

Timer 0 mode (see Ta b le 2 2

Timer or Counter selector for Timer 0. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T0 input pin).

control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0

(x = 0 and 1 for Timers 0

pin is high and the TR0

User manual Rev. 02 — 23 May 2005 38 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 20: Timer/Counter Mode register (TMOD - address 89h) bit description

Bit Symbol Description

4 T1M0 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

5T1M1

6T1C/T

7 T1GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1

Table 21: Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol----T1M2---T0M2

Resetxxx0xxx0

Table 22: Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description

Bit Symbol Description

0 T0M2 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

1:3 - reserved

4 T1M2 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

5:7 - reserved

Timer 1 mode (see Ta b le 2 2 ).

Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T1 input pin).

control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.

Timer 0 mode (see Ta b le 2 2

Timer 1 mode (see Ta b le 2 2

The following timer modes are selected by timer mode bits TnM[2:0]:

000 — 8048 Timer ‘TLn’ serves as 5-bit prescaler. (Mode 0)

001 — 16-bit Timer/Counter ‘THn’ and ‘TLn’ are cascaded; there is no prescaler.(Mode 1)

010 — 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.

(Mode 2)

011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text). Timer 1 in this mode is stopped. (Mode 3)

100 — Reserved. User must not configure to this mode.

101 — Reserved. User must not configure to this mode.

110 — PWM mode (see Section 7.5

111 — Reserved. User must not configure to this mode.

…continued

pin is high and the TR1

7.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 14

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either TnGATE = 0 or INTn Timer to be controlled by external input INTn TRn is a control bit in the Special Function Register TCON (Tab le 2 4 in the TMOD register.

User manual Rev. 02 — 23 May 2005 39 of 133

shows Mode 0 operation.

= 1. (Setting TnGATE = 1 allows the

, to facilitate pulse width measurements).

). The TnGATE bit is

Philips Semiconductors

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

UM10109

P89LPC932A1 User manual

Mode 0 operation is the same for Timer 0 and Timer 1. See Figure 14 different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

. There are two

7.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 15

7.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 16 contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

. Overflow from TLn not only sets TFn, but also reloads TLn with the

7.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 17 T0GATE, TR0, INT0 cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt.

, and TF0. TH0 is locked into a timer function (counting machine

. TL0 uses the Timer 0 control bits: T0C/T,

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC932A1 device can look like it has three Timer/Counters.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

7.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks (see Figure 18

). Its structure is similar to mode 2, except that:

• TFn (n = 0 and 1 for Timers 0 and 1 respectively) is set and cleared in hardware;

• The low period of the TFn is in THn, and should be between 1 and 254, and;

• The high period of the TFn is always 256−THn.

• Loading THn with 00h will force the Tx pin high, loading THn with FFh will force the Tx

pin low.

Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn can still be cleared in software like in any other modes.

User manual Rev. 02 — 23 May 2005 40 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 23: Timer/Counter Control register (TCON) - address 88h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Reset00000000

Table 24: Timer/Counter Control register (TCON - address 88h) bit description

Bit Symbol Description

0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external

interrupts.

1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware

when the interrupt is processed, or by software.

2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external

interrupts.

3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware

when the interrupt is processed, or by software.

4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor

vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)

6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off

7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt

is processed, or by software (except in mode 6, see above, when it is cleared in hardware).

PCLK

Tn pin

TRn

gate

INTn pin

C/T = 0

C/T = 1

control

Fig 14. Timer/counter 0 or 1 in Mode 0 (13-bit counter).

PCLK

Tn pin

TRn

gate

INTn pin

C/T = 0

C/T = 1

control

TLn

(5-bits)

TLn

(8-bits)

THn

(8-bits)

THn

(8-bits)

toggle

overflow

toggle

overflow

TFn

ENTn

002aaa919

TFn

ENTn

002aaa920

interrupt

Tn pin

interrupt

Tn pin

Fig 15. Timer/counter 0 or 1 in mode 1 (16-bit counter).

User manual Rev. 02 — 23 May 2005 41 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

PCLK

Tn pin

TRn

gate

INTn pin

C/T = 0

C/T = 1

control

Fig 16. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload).

PCLK

T0 pin

TR0

gate

INT0 pin

C/T = 0

C/T = 1

osc/2

TR1

control

TL0

(8-bits)

TH0

(8-bits)

TLn

(8-bits)

THn

(8-bits)

reload

overflow

toggle

overflow

toggle

TFn

ENTn

002aaa921

TF0

ENT0

(AUXR1.4)

TF1

interrupt

Tn pin

interrupt

T0 pin

(P1.2 open drain)

interrupt

T1 pin (P0.7)

ENT1

(AUXR1.5)

002aaa922

Fig 17. Timer/counter 0 Mode 3 (two 8-bit counters).

PCLK

TRn

gate

INTn pin

C/T = 0

control

TLn

(8-bits)

THn

(8-bits)

overflow

reload THn on falling transition

and (256 − THn) on rising transition

toggle

TFn

ENTn

002aaa923

interrupt

Tn pin

Fig 18. Timer/counter 0 or 1 in mode 6 (PWM auto-reload).

7.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs and PWM outputs are also used for the timer toggle outputs. This function is enabled by

User manual Rev. 02 — 23 May 2005 42 of 133

Philips Semiconductors

control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting PCLK as the clock source for the timer.

8. Real-time clock system timer

The P89LPC932A1 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time Clock can be an interrupt or a wake-up source (see Figure 19

The Real-time Clock is a 23-bit down counter. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL1-2 oscillator, provided that the XTAL1-2 oscillator is not being used as the CPU clock. If the XTAL1-2 oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source regardless of the state of the RTCS1:0 in the RTCCON register. There are three SFRs used for the RTC:

RTCCON — Real-time Clock control.

RTCH — Real-time Clock counter reload high (bits 22 to 15).

RTCL — Real-time Clock counter reload low (bits 14 to 7).

UM10109

P89LPC932A1 User manual

The Real-time clock system timer can be enabled by setting the RTCEN (RTCCON.0) bit. The Real-time Clock is a 23-bit down counter (initialized to all 0’s when RTCEN = 0) that is comprised of a 7-bit prescaler and a 16-bit loadable down counter. When RTCEN is written with logic 1, the counter is first loaded with (RTCH, RTCL, ‘1111111’) and will count down. When it reaches all 0’s, the counter will be reloaded again with (RTCH, RTCL, ‘1111111’) and a flag - RTCF (RTCCON.7) - will be set.

RTCH RTCL RTC RESET

RELOAD ON UNDERFLOW

MSB LSB

23-BIT DOWN COUNTER

wake-up from power-down

Interrupt if enabled (shared with WDT)

ERTC

RTCF

RTC underflow flag

power-on

reset

7-BIT PRESCALER

÷128

RTCEN

RTC enable

XTAL2 XTAL1

LOW FREQUENCY

MEDIUM FREQUENCY

HIGH FREQUENCY

CCLK

internal

oscillators

RTCS1 RTCS2

RTC clk select

002aaa924

Fig 19. Real-time clock/system timer block diagram.

User manual Rev. 02 — 23 May 2005 43 of 133

Philips Semiconductors

8.1 Real-time clock source

RTCS1/RTCS0 (RTCCON[6:5]) are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock. If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock, then the RTC will use CCLK as its clock source.

8.2 Changing RTCS1/RTCS0

RTCS1/RTCS0 cannot be changed if the RTC is currently enabled (RTCCON.0 = 1). Setting RTCEN and updating RTCS1/RTCS0 may be done in a single write to RTCCON. However, if RTCEN = 1, this bit must first be cleared before updating RTCS1/RTCS0.

8.3 Real-time clock interrupt/wake-up

If ERTC (RTCCON.1), EWDRT (IEN1.0.6) and EA (IEN0.7) are set to logic 1, RTCF can be used as an interrupt source. This interrupt vector is shared with the watchdog timer. It can also be a source to wake-up the device.

8.4 Reset sources affecting the Real-time clock

UM10109

P89LPC932A1 User manual

Only power-on reset will reset the Real-time Clock and its associated SFRs to their default state.

Table 25: Real-time Clock/System Timer clock sources

FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source

000 0 00 High frequency crystal High frequency crystal

1 00 High frequency crystal Internal RC oscillator

001 0 00 Medium frequency crystal Medium frequency crystal

1 00 Medium frequency crystal Internal RC oscillator

11 High frequency crystal

/DIVM

11 Internal RC oscillator

11 Medium frequency crystal

/DIVM

11 Internal RC oscillator

/DIVM

User manual Rev. 02 — 23 May 2005 44 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 25: Real-time Clock/System Timer clock sources

FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source

010 0 00 Low frequency crystal Low frequency crystal

11 Low frequency crystal

/DIV

1 00 Low frequency crystal Internal RC oscillator

11 Internal RC oscillator

011 0 00 High frequency crystal Internal RC oscillator

01 Medium frequency crystal

10 Low frequency crystal

11 Internal RC oscillator

/DIVM

1 00 High frequency crystal Internal RC oscillator

01 Medium frequency crystal

10 Low frequency crystal

11 Internal RC oscillator

100 0 00 High frequency crystal Watchdog oscillator

01 Medium frequency crystal

10 Low frequency crystal

11 Watchdog oscillator /DIVM

1 00 High frequency crystal Internal RC oscillator

01 Medium frequency crystal

10 Low frequency crystal

11 Internal RC oscillator

101 x xx undefined undefined

110 x xx undefined undefined

111 0 00 External clock input External clock input

11 External clock input /DIVM

1 00 External clock input Internal RC oscillator

11 Internal RC oscillator

…continued

/DIVM

Table 26: Real-time Clock Control register (RTCCON - address D1h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RTCF RTCS1 RTCS0 - - - ERTC RTCEN

Reset011xxx00

User manual Rev. 02 — 23 May 2005 45 of 133

Philips Semiconductors

Table 27: Real-time Clock Control register (RTCCON - address D1h) bit description

Bit Symbol Description

0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1.

Note that this bit will not power-down the Real-time Clock. The RTCPD bit (PCONA.7) if set, will power-down and disable this block regardless of RTCEN.

1 ERTC Real-time Clock interrupt enable. The Real-time Clock shares the same interrupt

as the watchdog timer. Note that if the user configuration bit WDTE (UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the Real-time Clock caused the interrupt.

2:4 - reserved

5 RTCS0 Real-time Clock source select (see Ta b l e 2 5

6RTCS1

7 RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock

reaches a count of logic 0. It can be cleared in software.

9. Capture/Compare Unit (CCU)

UM10109

P89LPC932A1 User manual

This unit features:

• A 16-bit timer with 16-bit reload on overflow

• Selectable clock (CCUCLK), with a prescaler to divide the clock source by any integer

between 1 and 1024.

• Four Compare / PWM outputs with selectable polarity

• Symmetrical / Asymmetrical PWM selection

• Seven interrupts with common interrupt vector (one Overflow, 2xCapture,

4xCompare), safe 16-bit read/write via shadow registers.

• Two Capture inputs with event counter and digital noise rejection filter

User manual Rev. 02 — 23 May 2005 46 of 133

Philips Semiconductors

16-BIT SHADOW REGISTER

TOR2H TO TOR2L

16-BIT TIMER RELOAD

16-BIT SHADOW REGISTER

OCRxH TO OCRxL

TIMER > COMPARE

UM10109

P89LPC932A1 User manual

16-BIT COMPARE

VALUE

OCD

OCC

OCB

OCA

OVERFLOW/

UNDERFLOW

16-BIT UP/DOWN TIMER

WITH RELOAD

10-BIT DIVIDER

4-BIT

DIVIDER

Fig 20. Capture Compare Unit block diagram.

32 × PLL

9.1 CCU Clock (CCUCLK)

The CCU runs on the CCUCLK, which can be either PCLK in basic timer mode or the output of a PLL (see Figure 20

0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider (PLLDV3:0 bits in the TCR21 register) to help divide PCLK into a frequency between

0.5 MHz and 1 MHz

COMPARE CHANNELS A TO D

16-BIT CAPTURE

EVENT

COUNTER

INTERRUPT FLAG

TICF2x SET

FCOx

ICNFx

NOISE

FILTER

CAPTURE CHANNELS A, B

ICESx

EDGE

SELECT

002aab009

). The PLL is designed to use a clock source between

ICB

ICA

9.2 CCU Clock prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow. Writing a value to the prescaler will cause the prescaler to restart.

9.3 Basic timer operation

The Timer is a free-running up/down counter counting at the pace determined by the prescaler. The timer is started by setting the CCU Mode Select bits TMOD21 and TMOD20 in the CCU Control Register 0 (TCR20) as shown in the table in the TCR20 register description (Ta bl e 3 2

The CCU direction control bit, TDIR2, determines the direction of the count. TDIR2 = 0: Count up, TDIR2 = 1: Count down. If the timer counting direction is changed while the counter is running, the count sequence will be reversed in the CCUCLK cycle following the write of TDIR2. The timer can be written or read at any time and newly-written values will take effect when the prescaler overflows. The timer is accessible through two SFRs, TL2(low byte) and TH2(high byte). A third 16-bit SFR, TOR2H:TOR2L, determines the overflow reload value. TL2, TH2 and TOR2H, TOR2L will be 0 after a reset

User manual Rev. 02 — 23 May 2005 47 of 133

Philips Semiconductors

Up-counting: When the timer contents are FFFFH, the next CCUCLK cycle will set the counter value to the contents of TOR2H:TOR2L.

Down-counting: When the timer contents are 0000H, the next CCUCLK cycle will set the counter value to the contents of TOR2H:TOR2L. During the CCUCLK cycle when the reload is performed, the CCU Timer Overflow Interrupt Flag (TOIF2) in the CCU Interrupt Flag Register (TIFR2) will be set, and, if the EA bit in the IEN0 register and ECCU bit in the IEN1 register (IEN1.4) are set, program execution will vector to the overflow interrupt. The user has to clear the interrupt flag in software by writing a logic 0 to it.

When writing to the reload registers, TOR2H and TOR2L, the values written are stored in two 8-bit shadow registers. In order to latch the contents of the shadow registers into TOR2H and TOR2L, the user must write a logic 1 to the CCU Timer Compare/Overflow Update bit TCOU2, in CCU Timer Control Register 1 (TCR21). The function of this bit depends on whether the timer is running in PWM mode or in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as one and will return to zero when the latching takes place. TCOU2 also controls the latching of the Output Compare registers OCR2A, OCR2B and OCR2C.

UM10109

P89LPC932A1 User manual

When writing to timer high byte, TH2, the value written is stored in a shadow register. When TL2 is written, the contents of TH2’s shadow register is transferred to TH2 at the same time that TL2 gets updated. Thus, TH2 should be written prior to writing to TL2. If a write to TL2 is followed by another write to TL2, without TH2 being written in between, the value of TH2 will be transferred directly to the high byte of the timer.

If the 16-bit CCU Timer is to be used as an 8-bit timer, the user can write FFh (for upcounting) or 00h (for downcounting) to TH2. When TL2 is written, FFh:TH2 (for upcounting) and 00h (for downcounting) will be loaded to CCU Timer. The user will not need to rewrite TH2 again for an 8-bit timer operation unless there is a change in count direction

When reading the timer, TL2 must be read first. When TL2 is read, the contents of the timer high byte are transferred to a shadow register in the same PCLK cycle as the read is performed. When TH2 is read, the contents of the shadow register are read instead. If a read from TL2 is followed by another read from TL2 without TH2 being read in between, the high byte of the timer will be transferred directly to TH2.

Table 28: CCU prescaler control register, high byte (TPCR2H - address CBh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol------TPCR2H.1TPCR2H.0

Resetxxxxxx00

Table 29: CCU prescaler control register, high byte (TPCR2H - address CBh) bit description

Bit Symbol Description

0 TPCR2H.0 Prescaler bit 8

1 TPCR2H.1 Prescaler bit 9

User manual Rev. 02 — 23 May 2005 48 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 30: CCU prescaler control register, low byte (TPCR2L - address CAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0

Reset00000000

Table 31: CCU prescaler control register, low byte (TPCR2L - address CAh) bit description

Bit Symbol Description

0 TPCR2L.0 Prescaler bit 0

1 TPCR2L.1 Prescaler bit 1

2 TPCR2L.2 Prescaler bit 2

3 TPCR2L.3 Prescaler bit 3

4 TPCR2L.4 Prescaler bit 4

5 TPCR2L.5 Prescaler bit 5

6 TPCR2L.6 Prescaler bit 6

7 TPCR2L.7 Prescaler bit 7

UM10109

Table 32: CCU control register 0 (TCR20 - address C8h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20

Reset00000000

Table 33: CCU control register 0 (TCR20 - address C8h) bit description

Bit Symbol Description

1:2 TMOD20/21 CCU Timer mode (TMOD21, TMOD20):

00 — Timer is stopped

01 — Basic timer function

10 — Asymmetrical PWM (uses PLL as clock source)

11 — Symmetrical PWM (uses PLL as clock source)

2 TDIR2 Count direction of the CCU Timer. When logic 0, count up, When logic 1, count down.

3 ALTAB PWM channel A/B alternately output enable. When this bit is set, the output of PWM channel A and B

are alternately gated on every counter cycle.

4 ALTCD PWM channel C/D alternately output enable. When this bit is set, the output of PWM channel C and D

are alternately gated on every counter cycle.

5 HLTEN PWM Halt Enable. When logic 1, a capture event as enabled for Input Capture A pin will immediately

stop all activity on the PWM pins and set them to a predetermined state.

6 HLTRN PWM Halt. When set indicates a halt took place. In order to re-activate the PWM, the user must clear

the HLTRN bit.

7 PLLEN Phase Locked Loop Enable. When set to logic 1, starts PLL operation. After the PLL is in lock this bit it

will read back a one.

9.4 Output compare

The four output compare channels A, B, C and D are controlled through four 16-bit SFRs, OCRAH:OCRAL, OCRBH:OCRBL, OCRCH:OCRCL, OCRDH: OCRDL. Each output compare channel needs to be enabled in order to operate. The channel is enabled by selecting a Compare Output Action by setting the OCMx1:0 bits in the Capture Compare x Control Register – CCCRx (x = A, B, C, D). When a compare channel is enabled, the user

User manual Rev. 02 — 23 May 2005 49 of 133

Philips Semiconductors

P89LPC932A1 User manual

will have to set the associated I/O pin to the desired output mode to connect the pin. (Note: The SFR bits for port pins P2.6, P1.6, P1.7, P2.1 must be set to logic 1 in order for the compare channel outputs to be visible at the port pins.) When the contents of TH2:TL2 match that of OCRxH:OCRxL, the Timer Output Compare Interrupt Flag - TOCFx is set in TIFR2. This happens in the CCUCLK cycle after the compare takes place. If EA and the Timer Output Compare Interrupt Enable bit – TOCIE2x (in TICR2 register), as well as ECCU bit in IEN1 are all set, the program counter will be vectored to the corresponding interrupt. The user must manually clear the bit by writing a logic 0 to it.

Two bits in OCCRx, the Output Compare x Mode bits OCMx1 and OCMx0 select what action is taken when a compare match occurs. Enabled compare actions take place even if the interrupt is disabled.

In order for a Compare Output Action to occur, the compare values must be within the counting range of the CCU timer.

When the compare channel is enabled, the I/O pin (which must be configured as an output) will be connected to an internal latch controlled by the compare logic. The value of this latch is zero from reset and can be changed by invoking a forced compare. A forced compare is generated by writing a logic 1 to the Force Compare x Output bit – FCOx bit in OCCRx. Writing a one to this bit generates a transition on the corresponding I/O pin as set up by OCMx1/OCMx0 without causing an interrupt. In basic timer operating mode the FCOx bits always read zero. (Note: This bit has a different function in PWM mode.) When an output compare pin is enabled and connected to the compare latch, the state of the compare pin remains unchanged until a compare event or forced compare occurs.

Table 34: Capture compare control register (CCRx - address Exh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol ICECx2 ICECx1 ICECx0 ICESx ICNFx FCOx OCMx1 OCMx0

Reset00000000

UM10109

Table 35: Capture compare control register (CCRx - address Exh) bit description

Bit Symbol Description

0 OCMx0 Output Compare x Mode. See Table 37 “

1OCMx1

2 FCOx Force Compare X Output Bit. When set, invoke a force compare.

3 ICNFx Input Capture x Noise Filter Enable Bit. When logic 1, the capture logic needs to see four consecutive

samples of the same value in order to recognize an edge as a capture event. The inputs are sampled every two CCLK periods regardless of the speed of the timer.

4 ICESx Input Capture x Edge Select Bit. When logic 0: Negative edge triggers a capture, When logic 1: Positive

edge triggers a capture.

5 ICECx0 Capture Delay Setting Bit 0. See Ta bl e 3 6

6 ICECx1 Capture Delay Setting Bit 1. See Ta bl e 3 6

7 ICECx2 Capture Delay Setting Bit 2. See Ta bl e 3 6

When the user writes to change the output compare value, the values written to OCRH2x and OCRL2x are transferred to two 8-bit shadow registers. In order to latch the contents of the shadow registers into the capture compare register, the user must write a logic 1 to the CCU Timer Compare/Overflow Update bit TCOU2, in the CCU Control Register 1 TCR21. The function of this bit depends on whether the timer is running in PWM mode or

User manual Rev. 02 — 23 May 2005 50 of 133

Output compare pin behavior”

for details.

Philips Semiconductors

in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as one and will return to zero when the latch takes place. TCOU2 also controls the latching of all the Output Compare registers as well as the Timer Overflow Reload registers - TOR2.

9.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register ICRAH:ICRAL or ICRBH:ICRBL. The capture event is defined by the Input Capture Edge Select – ICESx bit (x being A or B) in the CCCRx register. The user will have to configure the associated I/O pin as an input in order for an external event to trigger a capture.

A simple noise filter can be enabled on the input capture input. When the Input Capture Noise Filter ICNFx bit is set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. The inputs are sampled every two CCLK periods regardless of the speed of the timer.

UM10109

P89LPC932A1 User manual

An event counter can be set to delay a capture by a number of capture events. The three bits ICECx2, ICECx1 and ICECx0 in the CCCRx register determine the number of edges the capture logic has to see before an input capture occurs.

When a capture event is detected, the Timer Input Capture x (x is A or B) Interrupt Flag – TICF2x (TIFR2.1 or TIFR2.0) is set. If EA and the Timer Input Capture x Enable bit – TICIE2x (TICR2.1 or TICR2.0) is set as well as the ECCU (IEN1.4) bit is set, the program counter will be vectored to the corresponding interrupt. The interrupt flag must be cleared manually by writing a logic 0 to it.

When reading the input capture register, ICRxL must be read first. When ICRxL is read, the contents of the capture register high byte are transferred to a shadow register. When ICRxH is read, the contents of the shadow register are read instead. (If a read from ICRxL is followed by another read from ICRxL without ICRxH being read in between, the new value of the capture register high byte (from the last ICRxL read) will be in the shadow register).

Table 36: Event delay counter for input capture

ICECx2 ICECx1 ICECx0 Delay (numbers of edges)

0000

0011

0102

0113

1004

1015

1107

11115

User manual Rev. 02 — 23 May 2005 51 of 133

Philips Semiconductors

9.6 PWM operation

PWM Operation has two main modes, asymmetrical and symmetrical. These modes of timer operation are selected by writing 10H or 11H to TMOD21:TMOD20 as shown in

Section 9.3 “

In asymmetrical PWM operation, the CCU Timer operates in downcounting mode regardless of the setting of TDIR2. In this case, TDIR2 will always read 1.

In symmetrical mode, the timer counts up/down alternately and the value of TDIR2 has no effect. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation. Ta bl e 3 7 behavior of the compare pins in PWM mode.

The user will have to configure the output compare pins as outputs in order to enable the PWM output. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since the bit FCO is used to hold the halt value, only a compare event can change the state of the pin.

UM10109

P89LPC932A1 User manual

Basic timer operation”.

shows the

TOR2

compare value

timer value

0x0000

non-inverted

inverted

Fig 21. Asymmetrical PWM, downcounting.

TOR2

compare value

timer value

non-inverted

inverted

002aaa89

002aaa894

Fig 22. Symmetrical PWM.

The CCU Timer Overflow interrupt flag is set when the counter changes direction at the top. For example, if TOR contains 01FFH, CCU Timer will count: …01FEH, 01FFH, 01FEH,… The flag is set in the counter cycle after the change from TOR to TOR-1.

User manual Rev. 02 — 23 May 2005 52 of 133

Philips Semiconductors

When the timer changes direction at the bottom, in this example, it counts …,0001H, 0000H, 0001H,… The CCU Timer overflow interrupt flag is set in the counter CCUCLK cycle after the transition from 0001H to 0000H.

The status of the TDIR2 bit in TCR20 reflects the current counting direction. Writing to this bit while operating in symmetrical mode has no effect.

9.7 Alternating output mode

In asymmetrical mode, the user can program PWM channels A/B and C/D as alternating pairs for bridge drive control. By setting ALTAB or ALTCD bits in TCR20, the output of these PWM channels are alternately gated on every counter cycle. This is shown in the following figure:

UM10109

P89LPC932A1 User manual

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

TIMER VALUE

PWM OUTPUT A (or C) (P2.6)

Fig 23. Alternate output mode.

Table 37: Output compare pin behavior

OCMx1

0 0 Output compare disabled. On power-on, this is the default state, and pins

0 1 Set when compare in

1 0 invalid configuration

1 1 Toggles on compare

[1]

OCMx0

[1]

Output Compare pin behavior

Basic timer mode Asymmetrical PWM Symmetrical PWM

are configured as inputs.

Non-Inverted PWM. Set operation. Cleared on compare match.

[2]

match

[2]

on compare match.

Cleared on CCU Timer

underflow.

Inverted PWM. Cleared

on compare match. Set

on CCU Timer

underflow.

PWM OUTPUT B (or D) (P1.6)

002aaa895

Non-Inverted PWM. Cleared on compare match, upcounting. Set on compare match, downcounting.

Inverted PWM. Set on compare match,

[2]

upcounting. Cleared on compare match, downcounting.

[2]

[1] x = A, B, C, D

[2] ‘ON’ means in the CCUCLK cycle after the event takes place.

User manual Rev. 02 — 23 May 2005 53 of 133

Philips Semiconductors

9.8 Synchronized PWM register update

When the OCRx registers are written, a built in mechanism ensures that the value is not updated in the middle of a PWM pulse. This could result in an odd-length pulse. When the registers are written, the values are placed in two shadow registers, as is the case in basic timer operation mode. Writing to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. If OCRxH and/or OCRxL are read before the value is updated, the most currently written value is read.

9.9 HALT

Setting the HLTEN bit in TCR20 enables the PWM Halt Function. When halt function is enabled, a capture event as enabled for the Input Capture A pin will immediately stop all activity on the PWM pins and set them to a predetermined state defined by FCOx bit. In PWM Mode, the FCOx bits in the CCCRx register hold the value the pin is forced to during halt. The value of the setting can be read back. The capture function and the interrupt will still operate as normal even if it has this added functionality enabled. When the PWM unit is halted, the timer will still run as normal. The HLTRN bit in TCR20 will be set to indicate that a halt took place. In order to re-activate the PWM, the user must clear the HLTRN bit. The user can force the PWM unit into halt by writing a logic 1 to HLTRN bit.

UM10109

P89LPC932A1 User manual

9.10 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher (The PWM resolution is programmable up to 16 bits by writing to TOR2H:TOR2L). The PLL is fed an input signal of 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as follows:

PLL frequency = PCLK / (N+1)

Where: N is the value of PLLDV3:0.

Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to

Table 38: CCU control register 1 (TCR21 - address F9h) bit allocation

Bit 7 6 5 4 3 2 1 0

SymbolTCOU2---PLLDV.3PLLDV.2PLLDV.1PLLDV.0

Reset0xxx0000

PCLK

⁄16.

User manual Rev. 02 — 23 May 2005 54 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 39: CCU control register 1 (TCR21 - address F9h) bit description

Bit Symbol Description

0:3 PLLDV.3:0 PLL frequency divider.

4:6 - Reserved.

7 TCOU2 In basic timer mode, writing a logic 1 to TCOU2 will cause the values to be latched immediately and the

value of TCOU2 will always read as logic 0. In PWM mode, writing a logic 1 to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as logic 1 and will return to logic 0 when the latching takes place. TCOU2 also controls the latching of the Output Compare registers OCRAx, OCRBx and OCRCx.

Setting the PLLEN bit in TCR20 starts the PLL. When PLLEN is set, it will not read back a one until the PLL is in lock. At this time, the PWM unit is ready to operate and the timer can be enabled. The following start-up sequence is recommended:

1. Set up the PWM module without starting the timer.

2. Calculate the right division factor so that the PLL receives an input clock signal of 500 kHz - 1 MHz. Write this value to PLLDV.

3. Set PLLEN. Wait until the bit reads one

4. Start the timer by writing a value to bits TMOD21, TMOD20

UM10109

When the timer runs from the PLL, the timer operates asynchronously to the rest of the microcontroller. Some restrictions apply:

• The user is discouraged from writing or reading the timer in asynchronous mode. The

results may be unpredictable

• Interrupts and flags are asynchronous. There will be delay as the event may not

actually be recognized until some CCLK cycles later (for interrupts and reads)

9.11 CCU interrupt structure

There are seven independent sources of interrupts in the CCU: timer overflow, captured input events on Input Capture blocks A/B, and compare match events on Output Compare blocks A through D. One common interrupt vector is used for the CCU service routine and interrupts can occur simultaneously in system usage. To resolve this situation, a priority encode function of the seven interrupt bits in TIFR2 SFR is implemented (after each bit is AND-ed with the corresponding interrupt enable bit in the TICR2 register). The order of priority is fixed as follows, from highest to lowest:

• TOIF2

• TICF2A

• TICF2B

• TOCF2A

• TOCF2B

• TOCF2C

• TOCF2D

An interrupt service routine for the CCU can be as follows:

1. Read the priority-encoded value from the TISE2 register to determine the interrupt source to be handled.

User manual Rev. 02 — 23 May 2005 55 of 133

Philips Semiconductors

2. After the current (highest priority) event is serviced, write a logic 0 to the corresponding interrupt flag bit in the TIFR2 register to clear the flag.

3. Read the TISE2 register. If the priority-encoded interrupt source is ‘000’, all CCU interrupts are serviced and a return from interrupt can occur. Otherwise, return to step

for the next interrupt.

EA (IEN0.7)

ECCU (IEN1.4)

TOIE2 (TICR2.7)

TOIF2 (TIFR2.7)

TICIE2A (TICR2.0)

TICF2A (TIFR2.0)

TICIE2B (TICR2.1)

TICF2B (TIFR2.1)

TOCIE2A (TICR2.3)

TOCF2A (TIFR2.3)

TOCIE2B (TICR2.4)

TOCF2B (TIFR2.4)

TOCIE2C (TICR2.5)

TOCF2C (TIFR2.5)

TOCIE2D (TICR2.6)

TOCF2D (TIFR2.6)

other

interrupt

sources

UM10109

P89LPC932A1 User manual

interrupt to CPU

ENCINT.0

PRIORITY

ENCODER

002aaa896

Fig 24. Capture/compare unit interrupts.

Table 40: CCU interrupt status encode register (TISE2 - address DEh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol-----ENCINT.2ENCINT.1ENCINT.0

Resetxxxxx000

ENCINT.1

ENCINT.2

User manual Rev. 02 — 23 May 2005 56 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 41: CCU interrupt status encode register (TISE2 - address DEh) bit description

Bit Symbol Description

2:0 ENCINT.2:0 CCU Interrupt Encode output. When multiple interrupts happen, more than one interrupt flag is set in

CCU Interrupt Flag Register (TIFR2). The encoder output can be read to determine which interrupt is to be serviced. The user must write a logic 0 to clear the corresponding interrupt flag bit in the TIFR2 register after the corresponding interrupt has been serviced. Refer to Ta b le 4 3

000 — No interrupt pending.

001 — Output Compare Event D interrupt (lowest priority)

010 — Output Compare Event C interrupt.

011 — Output Compare Event B interrupt.

100 — Output Compare Event A interrupt.

101 — Input Capture Event B interrupt.

110 — Input Capture Event A interrupt.

111 — CCU Timer Overflow interrupt (highest priority).

3:7 - Reserved.

UM10109

for TIFR2 description.

Table 42: CCU interrupt flag register (TIFR2 - address E9h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A

Reset00000x00

Table 43: CCU interrupt flag register (TIFR2 - address E9h) bit description

Bit Symbol Description

0 TICF2A Input Capture Channel A Interrupt Flag Bit. Set by hardware when an input capture event is detected.

Cleared by software.

1 TICF2B Input Capture Channel B Interrupt Flag Bit. Set by hardware when an input capture event is detected.

Cleared by software.

2 - Reserved for future use. Should not be set to logic 1 by user program.

3 TOCF2A Output Compare Channel A Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHA:OCRLA. Compare channel A must be enabled in order to generate this interrupt. If EA bit in IEN0, ECCU bit in IEN1 and TOCIE2A bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

4 TOCF2B Output Compare Channel B Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHB:OCRLB. Compare channel B must be enabled in order to generate this interrupt. If EA bit in IEN0, ECCU bit in IEN1 and TOCIE2B bit are set, the program counter will vectored to the corresponding interrupt. Cleared by software.

5 TOCF2C Output Compare Channel C Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHC:OCRLC. Compare channel C must be enabled in order to generate this interrupt. If EA bit in IEN0, ECCU bit in IEN1 and TOCIE2C bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

6 TOCF2D Output Compare Channel D Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHD:OCRLD. Compare channel D must be enabled in order to generate this interrupt. If EA bit in IEN0, ECCU bit in IEN1 and TOCIE2D bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

7 TOIF2 CCU Timer Overflow Interrupt Flag bit. Set by hardware on CCU Timer overflow. Cleared by software.

User manual Rev. 02 — 23 May 2005 57 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 44: CCU interrupt control register (TICR2 - address C9h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A - TICIE2B TICIE2A

Reset00000x00

Table 45: CCU interrupt control register (TICR2 - address C9h) bit description

Bit Symbol Description

0 TICIE2A Input Capture Channel A Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is

detected, the program counter will vectored to the corresponding interrupt.

1 TICIE2B Input Capture Channel B Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is

detected, the program counter will vectored to the corresponding interrupt.

2 - Reserved for future use. Should not be set to logic 1 by user program.

3 TOCIE2A Output Compare Channel A Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

is enabled and the contents of TH2:TL2 match that of OCRHA:OCRLA, the program counter will vectored to the corresponding interrupt.

4 TOCIE2B Output Compare Channel B Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

B is enabled and the contents of TH2:TL2 match that of OCRHB:OCRLB, the program counter will vectored to the corresponding interrupt.

5 TOCIE2C Output Compare Channel C Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

C is enabled and the contents of TH2:TL2 match that of OCRHC:OCRLC, the program counter will vectored to the corresponding interrupt.

6 TOCIE2D Output Compare Channel D Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

D is enabled and the contents of TH2:TL2 match that of OCRHD:OCRLD, the program counter will vectored to the corresponding interrupt.

7 TOIE2 CCU Timer Overflow Interrupt Enable bit.

UM10109

10. UART

The P89LPC932A1 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC932A1 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering and several interrupt options.

The UART can be operated in 4 modes, as described in the following sections.

10.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at

10.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see Section 10.6 “

generator and selection” on page 59).

⁄16 of the CPU clock frequency.

Baud Rate

User manual Rev. 02 — 23 May 2005 58 of 133

Philips Semiconductors

10.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved. The baud rate is programmable to either determined by the SMOD1 bit in PCON.

10.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see Section 10.6

“Baud Rate generator and selection” on page 59).

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

UM10109

P89LPC932A1 User manual

⁄16 or 1⁄32 of the CCLK frequency, as

10.5 SFR space

The UART SFRs are at the following locations:

Table 46: UART SFR addresses

PCON Power Control 87H

SCON Serial Port (UART) Control 98H

SBUF Serial Port (UART) Data Buffer 99H

SADDR Serial Port (UART) Address A9H

SADEN Serial Port (UART) Address Enable B9H

SSTAT Serial Port (UART) Status BAH

BRGR1 Baud Rate Generator Rate High Byte BFH

BRGR0 Baud Rate Generator Rate Low Byte BEH

BRGCON Baud Rate Generator Control BDH

10.6 Baud Rate generator and selection

The P89LPC932A1 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON[2:1] (see Figure 25 set. The independent Baud Rate Generator uses CCLK.

). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is

User manual Rev. 02 — 23 May 2005 59 of 133

Philips Semiconductors

10.7 Updating the BRGR1 and BRGR0 SFRs

The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate Generator is disabled (the BRGEN bit in the BRGCON register is logic 0). This avoids the loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0 or

BRGR1 is written when BRGEN = 1, the result is unpredictable.)

Table 47: UART baud rate generation

SCON.7 (SM0)

00XX

0100

100X

1100

SCON.6 (SM1)

PCON.7 (SMOD1)

BRGCON.1 (SBRGS)

UM10109

P89LPC932A1 User manual

Receive/transmit baud rate for UART

CCLK

⁄

CCLK

⁄

(256−TH1)64

CCLK

⁄

(256−TH1)32

CCLK

⁄

((BRGR1, BRGR0)+16)

CCLK

⁄

CCLK

⁄

CCLK

⁄

(256−TH1)64

CCLK

⁄

(256−TH1)32

CCLK

⁄

((BRGR1, BRGR0)+16)

Table 48: Baud Rate Generator Control register (BRGCON - address BDh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol-------SBRGSBRGEN

Resetxxxxxx0 0

Table 49: Baud Rate Generator Control register (BRGCON - address BDh) bit description

Bit Symbol Description

0 BRGEN Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and

BRGR0 can only be written when BRGEN = 0.

1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and

3 (see Ta bl e 4 7

2:7 - reserved

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

Fig 25. Baud rate generation for UART (Modes 1, 3).

for details)

SMOD1 = 1

÷2

SMOD1 = 0

SBRGS = 0

SBRGS = 1

baud rate modes 1 and 3

002aaa897

10.8 Framing error

A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0.

User manual Rev. 02 — 23 May 2005 60 of 133

Philips Semiconductors

10.9 Break detect

A break detect is reported in the status register (SSTAT). A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the UART will go into an idle state and remain in this idle state until a stop bit has been received. The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit (AUXR1.6)

Table 50: Serial Port Control register (SCON - address 98h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SM0/FE SM1 SM2 REN TB8 RB8 TI RI

Resetxxxxxx00

Table 51: Serial Port Control register (SCON - address 98h) bit description

Bit Symbol Description

0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or

1 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or

2 RB8 The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0),

3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software

4 REN Enables serial reception. Set by software to enable reception. Clear by software to

5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or

6 SM1 With SM0 defines the serial port mode, see Ta bl e 5 2

7 SM0/FE The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0,

UM10109

P89LPC932A1 User manual

approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3, if SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is set near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be cleared by software.

at the stop bit (see description of INTLO bit in SSTAT register) in the other modes. Must be cleared by software.

RB8 is the stop bit that was received. In Mode 0, RB8 is undefined.

as desired.

disable reception.

3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 0, SM2 should be 0. In Mode 1, SM2 must be 0.

this bit is read and written as SM0, which with SM1, defines the serial port mode. If SMOD0 = 1, this bit is read and written as FE (Framing Error). FE is set by the receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared by valid frames but is cleared by software. (Note: UART mode bits SM0 and SM1 should be programmed when SMOD0 is logic 0 - default mode on any reset.)

Table 52: Serial Port modes

SM0, SM1 UART mode UART baud rate

CCLK

00 Mode 0: shift register

01 Mode 1: 8-bit UART Variable (see Ta bl e 4 7

10 Mode 2: 9-bit UART

11 Mode 3: 9-bit UART Variable (see Tab l e 4 7)

User manual Rev. 02 — 23 May 2005 61 of 133

⁄16 (default mode on any reset)

)

CCLK

⁄32 or

CCLK

⁄

Philips Semiconductors

Table 53: Serial Port Status register (SSTAT - address BAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol DBMOD INTLO CIDISDBISELFE BR OE STINT

Resetxxxxxx00

Table 54: Serial Port Status register (SSTAT - address BAh) bit description

Bit Symbol Description

0 STINT Status Interrupt Enable. When set = 1, FE, BR, or OE can cause an interrupt. The

1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it

2 BR Break Detect flag. A break is detected when any 11 consecutive bits are sensed

3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end

4 DBISEL Double buffering transmit interrupt select. Used only if double buffering is enabled.

5 CIDIS Combined Interrupt Disable. When set = 1, Rx and Tx interrupts are separate.

6 INTLO Transmit interrupt position. When cleared = 0, the Tx interrupt is issued at the

7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be logic 0 for

UM10109

P89LPC932A1 User manual

interrupt used (vector address 0023h) is shared with RI (CIDIS = 1) or the combined TI/RI (CIDIS = 0). When cleared = 0, FE, BR, OE cannot cause an interrupt. (Note: FE, BR, or OE is often accompanied by a RI, which will generate an interrupt regardless of the state of STINT). Note that BR can cause a break detect reset if EBRR (AUXR1.6) is set to logic 1.

is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while RI in SCON is still set. Cleared by software.

low. Cleared by software.

of the frame. Cleared by software.

This bit controls the number of interrupts that can occur when double buffering is enabled. When set, one transmit interrupt is generated after each character written to SBUF, and there is also one more transmit interrupt generated at the beginning (INTLO = 0) or the end (INTLO = 1) of the STOP bit of the last character sent (i.e., no more data in buffer). This last interrupt can be used to indicate that all transmit operations are over. When cleared = 0, only one transmit interrupt is generated per character written to SBUF. Must be logic 0 when double buffering is disabled. Note that except for the first character written (when buffer is empty), the location of the transmit interrupt is determined by INTLO. When the first character is written, the transmit interrupt is generated immediately after SBUF is written.

When cleared = 0, the UART uses a combined Tx/Rx interrupt (like a conventional 80C51 UART). This bit is reset to logic 0 to select combined interrupts.

beginning of the stop bit. When set = 1, the Tx interrupt is issued at end of the stop bit. Must be logic 0 for mode 0. Note that in the case of single buffering, if the Tx interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit.

UART mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to logic 0 to disable double buffering.

10.10 More about UART Mode 0

In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI (SCON.1) is set, which must be cleared in software. Double buffering must be disabled in this mode.

Reception is initiated by clearing RI (SCON.0). Synchronous serial transfer occurs and RI will be set again at the end of the transfer. When RI is cleared, the reception of the next character will begin. Refer to Figure 26

User manual Rev. 02 — 23 May 2005 62 of 133

Philips Semiconductors

write to

SBUF

shift

RXD (data out)

TXD (shift clock)

WRITE to SCON

(clear RI)

shift

RXD

(data in)

TxD (shift clock)

UM10109

P89LPC932A1 User manual

S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16S1 ... S16S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16S1 ... S16S1 ... S16 S1 ... S16

transmit

D0 D1 D5D2 D6D3 D4 D7

receive

D0 D1 D5D2 D6D3 D4 D7

002aaa925

Fig 26. Serial Port Mode 0 (double buffering must be disabled).

10.11 More about UART Mode 1

Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampled at a rate 16 times the programmed baud rate. When a transition is detected, the divide-by-16 counter is immediately reset. Each bit time is thus divided into 16 counter states. At the 7th, 8th, and 9th counter states, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the receiver goes back to looking for another 1-to-0 transition. This provides rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0 and either SM2 = 0 or the received stop bit = 1. If either of these two conditions is not met, the received frame is lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated.

User manual Rev. 02 — 23 May 2005 63 of 133

Philips Semiconductors

TX clock

write to

SBUF

shift

TxD

clock

RxD

shift

÷16 reset

Fig 27. Serial Port Mode 1 (only single transmit buffering case is shown).

start

bit

D0 D1 D5D2 D6D3 D4 D7

start

D0 D1 D5D2 D6D3 D4 D7

bit

UM10109

P89LPC932A1 User manual

stop bit

INTLO = 0

INTLO = 1

stop bit

transmit

receive

002aaa92

TX clock

write to

SBUF

shift

TxD

clock

RxD

shift

10.12 More about UART Modes 2 and 3

Reception is the same as in Mode 1.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF.

start

÷16 reset

D0 D1 D5D2 D6D3 D4 D7

bit

start

D0 D1 D5D2 D6D3 D4 D7

bit

TB8

stop bit

INTLO = 0 INTLO = 1

RB8

stop bit

SMOD0 = 0 SMOD0 = 1

transmit

receive

002aaa92

Fig 28. Serial Port Mode 2 or 3 (only single transmit buffering case is shown).

10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1

If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table.

User manual Rev. 02 — 23 May 2005 64 of 133

Philips Semiconductors

Table 55: FE and RI when SM2= 1 in Modes 2 and 3

Mode PCON.6

2 0 0 No RI when RB8 = 0 Occurs during STOP

3 1 0 No RI when RB8 = 0 Will NOT occur

10.14 Break detect

A break is detected when 11 consecutive bits are sensed low and is reported in the status register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit times. For Modes 2 and 3, this consists of the start bit, 9 data bits, and one stop bit. The break detect bit is cleared in software or by a reset. The break detect can be used to reset the device and force the device into ISP mode. This occurs if the UART is enabled and the the EBRR bit (AUXR1.6) is set and a break occurs.

(SMOD0)

P89LPC932A1 User manual

RB8 RI FE

bit

1 Similar to Figure 28

occurs during RB8, one bit before FE

[28]

1 Similar to

during STOP bit

, with SMOD0 = 1, RI occurs

, with SMOD0 = 0, RI

Occurs during STOP bit

UM10109

10.15 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out.

10.16 Double buffering in different modes

Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)

Unlike the conventional UART, when double buffering is enabled, the Tx interrupt is generated when the double buffer is ready to receive new data. The following occurs during a transmission (assuming eight data bits):

1. The double buffer is empty initially.

2. The CPU writes to SBUF.

3. The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately.

4. If there is more data, go to 6, else continue.

5. If there is no more data, then:

– If DBISEL is logic 0, no more interrupts will occur.

User manual Rev. 02 — 23 May 2005 65 of 133

Philips Semiconductors

– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

– Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of

6. If there is more data, the CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the

– Go to 3.

TxD

UM10109

P89LPC932A1 User manual

of the STOP bit of the data currently in the shifter (which is also the last data).

STOP bit of the data currently in the shifter (which is also the last data).

the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

beginning of the STOP bit of the data currently in the shifter.

end of the STOP bit of the data currently in the shifter.

write to

SBUF

Tx interrupt

single buffering (DBMOD/SSTAT.7 = 0), early interrupt (INTLO/SSTAT.6 = 0) is shown

TxD

write to

SBUF

Tx interrupt

double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,

no ending Tx interrupt (DBISEL/SSTAT.4 = 0)

TxD

write to

SBUF

Tx interrupt

double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,

with ending Tx interrupt (DBISEL/SSTAT.4 = 1)

Fig 29. Transmission with and without double buffering.

002aaa92

10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)

If double buffering is disabled (DBMOD, i.e. SSTAT.7 = 0), TB8 can be written before or after SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must not be changed again until after TB8 shifting has been completed, as indicated by the Tx interrupt.

User manual Rev. 02 — 23 May 2005 66 of 133

Philips Semiconductors

If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the Section

10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)” on page 65

becomes as follows:

1. The double buffer is empty initially.

2. The CPU writes to TB8.

3. The CPU writes to SBUF.

4. The SBUF/TB8 data is loaded to the shift register and a Tx interrupt is generated immediately.

5. If there is more data, go to 7, else continue on 6.

6. If there is no more data, then:

– If DBISEL is logic 0, no more interrupt will occur.

– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

7. If there is more data, the CPU writes to TB8 again.

8. The CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the

9. Go to 4.

10.Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

UM10109

P89LPC932A1 User manual

of the STOP bit of the data currently in the shifter (which is also the last data).

STOP bit of the data currently in the shifter (which is also the last data).

beginning of the STOP bit of the data currently in the shifter.

end of the STOP bit of the data currently in the shifter.

10.19 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes.

Note that SM2 has no effect in Mode 0, and must be logic 0 in Mode 1.

User manual Rev. 02 — 23 May 2005 67 of 133

Philips Semiconductors

10.20 Automatic address recognition

Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes (mode 2 and mode 3), the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the ‘Given’ address or the ‘Broadcast’ address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the ‘Given’ address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

UM10109

P89LPC932A1 User manual

Table 56: Slave 0/1 examples

Example 1 Example 2

Slave 0 SADDR = 1100 0000 Slave 1 SADDR = 1100 0000

SADEN = 1111 1101 SADEN = 1111 1110

Given = 1100 00X0 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Table 57: Slave 0/1/2 examples

Example 1 Example 2 Example 3

Slave 0 SADDR = 1100 0000 Slave 1 SADDR = 1110 0000 Slave 2 SADDR = 1100 0000

SADEN = 1111 1001 SADEN = 1111 1010 SADEN = 1111 1100

Given = 1100

0XX0

Given = 1110 0X0X Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases,

User manual Rev. 02 — 23 May 2005 68 of 133

Philips Semiconductors

interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares’. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

11. I2C interface

The I2C-bus uses two wires, serial clock (SCL) and serial data (SDA) to transfer information between devices connected to the bus, and has the following features:

• Bidirectional data transfer between masters and slaves

• Multimaster bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I

C-bus may be used for test and diagnostic purposes

UM10109

P89LPC932A1 User manual

A typical I direction bit (R/W), two types of data transfers are possible on the I

C-bus configuration is shown in Figure 30. Depending on the state of the

C-bus:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted

by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave

address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I released.

The P89LPC932A1 device provides a byte-oriented I modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode

C interface. It has four operation

C-bus will not be

User manual Rev. 02 — 23 May 2005 69 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

C-bus

Fig 30. I2C-bus configuration.

The P89LPC932A1 CPU interfaces with the I2C-bus through six Special Function Registers (SFRs): I2CON (I Status Register), I2ADR (I High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).

11.1 I2C data register

I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received data is located at the MSB of I2DAT.

P1.3/SDA P1.2/SCL

P89LPC932A1

C Control Register), I2DAT (I2C Data Register), I2STAT (I2C

C Slave Address Register), I2SCLH (SCL Duty Cycle Register

OTHER DEVICE

WITH I

C-BUS

INTERFACE

SDA

SCL

OTHER DEVICE

C-BUS

WITH I

INTERFACE

002aaa898

Table 58: I2C data register (I2DAT - address DAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0

Reset00000000

11.2 I2C slave address register

I2ADR register is readable and writable, and is only used when the I2C interface is set to slave mode. In master mode, this register has no effect. The LSB of I2ADR is general call bit. When this bit is set, the general call address (00h) is recognized.

Table 59: I2C slave address register (I2ADR - address DBh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC

Reset00000000

Table 60: I

Bit Symbol Description

0 GC General call bit. When set, the general call address (00H) is recognized,

1:7 I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has

C slave address register (I2ADR - address DBh) bit description

otherwise it is ignored.

no effect.

User manual Rev. 02 — 23 May 2005 70 of 133

Philips Semiconductors

11.3 I2C control register

The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

CRSEL determines the SCL source when the I this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master I Timer 1 overflow rate divided by 2 for the I by the user in 8 bit auto-reload mode (Mode 2).

UM10109

P89LPC932A1 User manual

C-bus is in master mode. In slave mode

C device. When CRSEL = 1, the I2C interface uses the

C clock rate. Timer 1 should be programmed

Data rate of I

If f

= 12 MHz, reload value is 0 to 255, so I2C data rate range is 11.72 Kbit/sec to

osc

C-bus = Timer overflow rate / 2 = PCLK / (2*(256-reload value)).

3000 Kbit/sec.

When CRSEL = 0, the I

C interface uses the internal clock generator based on the value

of I2SCLL and I2CSCLH register. The duty cycle does not need to be 50 %.

The STA bit is START flag. Setting this bit causes the I

C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode.

The STO bit is STOP flag. Setting this bit causes the I

C interface to transmit a STOP

condition in master mode, or recovering from an error condition in slave mode.

If the STA and STO are both set, then a STOP condition is transmitted to the I

C-bus if it is in master mode, and transmits a START condition afterwards. If it is in slave mode, an internal STOP condition will be generated, but it is not transmitted to the bus.

Table 61: I2C Control register (I2CON - address D8h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - I2EN STA STO SI AA - CRSEL

Resetx00000x0

Table 62: I

Bit Symbol Description

0 CRSEL SCL clock selection. When set = 1, Timer 1 overflow generates SCL, when cleared

1- reserved

2 AA The Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)

C Control register (I2CON - address D8h) bit description

= 0, the internal SCL generator is used base on values of I2SCLH and I2SCLL.

will be returned during the acknowledge clock pulse on the SCL line on the following situations:

(1)The ‘own slave address’ has been received. (2)The general call address has been received while the general call bit (GC) in I2ADR is set. (3) A data byte has been received while the I byte has been received while the I Mode. When cleared to 0, an not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: (1) A data byte has been received while the I Mode. (2) A data byte has been received while the I Slave Receiver Mode.

C interface is in the Master Receiver Mode. (4)A data

C interface is in the addressed Slave Receiver

C interface is in the Master Receiver

C interface is in the addressed

User manual Rev. 02 — 23 May 2005 71 of 133

Philips Semiconductors

Table 62: I

Bit Symbol Description

3SI I2C Interrupt Flag. This bit is set when one of the 25 possible I2C states is entered.

4 STO STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the

5 STA Start Flag. STA = 1: I

6I2EN I

7- reserved

UM10109

P89LPC932A1 User manual

C Control register (I2CON - address D8h) bit description …continued

When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set. Must be cleared by software by writing 0 to this bit.

C-bus. When the bus detects the STOP condition, it will clear STO bit

I automatically. In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to ‘not addressed’ Slave Receiver Mode. The STO flag is cleared by hardware automatically.

C-bus enters master mode, checks the bus and generates a START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator. When the I already in master mode and some data is transmitted or received, it transmits a repeated START condition. STA may be set at any time, it may also be set when

C interface is in an addressed slave mode. STA = 0: no START condition or

the I repeated START condition will be generated.

C Interface Enable. When set, enables the I2C interface. When clear, the I2C

function is disabled.

C interface is

11.4 I2C Status register

This is a read-only register. It contains the status code of the I2C interface. The least three bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and SI bit is not set. All other 25 status codes correspond to defined I

Ta bl e 6 8

Table 63: I2C Status register (I2STAT - address D9h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0

Reset00000000

Table 64: I

Bit Symbol Description

0:2 - Reserved, are always set to 0.

3:7 STA[0:4] I

C states. When any of these states entered, the SI bit will be set. Refer to

to Ta bl e 7 1 for details.

C Status register (I2STAT - address D9h) bit description

C Status code.

11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL

When the internal SCL generator is selected for the I2C interface by setting CRSEL = 0 in the I2CON register, the user must set values for registers I2SCLL and I2SCLH to select the data rate. I2SCLH defines the number of PCLK cycles for SCL = high, I2SCLL defines the number of PCLK cycles for SCL = low. The frequency is determined by the following formula:

Bit Frequency = f

Where f

User manual Rev. 02 — 23 May 2005 72 of 133

is the frequency of PCLK.

PCLK

/ (2*(I2SCLH + I2SCLL))

PCLK

Philips Semiconductors

The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycles for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended.

Table 65: I2C clock rates selection

I2SCLL+

I2SCLH

6 0 - 307 154 - -

7 0 - 263 132 - -

8 0 - 230 115 - 375

9 0 - 205 102 - 333

10 0 369 184 92 - 300

15 0 246 123 61 400 200

25 0 147 74 37 240 120

30 0 123 61 31 200 100

50 0 74 37 18 120 60

60 0 61 31 15 100 50

100 0 37 18 9 60 30

150 0 25 12 6 40 20

200 0 18 9 5 30 15

- 1 3.6 Kbps to

UM10109

P89LPC932A1 User manual

C data rate range of 0 to 400 kHz. Thus the values of

Bit data rate (Kbit/sec) at f

CRSEL 7.373 MHz 3.6865 MHz 1.8433 MHz 12 MHz 6 MHz

osc

922 Kbps Timer 1 in mode 2

1.8 Kbps to 461 Kbps Timer 1 in mode 2

0.9 Kbps to 230 Kbps Timer 1 in mode 2

5.86 Kbps to 1500 Kbps Timer 1 in mode 2

2.93 Kbps to 750 Kbps Timer 1 in mode 2

11.6 I2C operation modes

11.6.1 Master Transmitter mode

In this mode data is transmitted from master to slave. Before the Master Transmitter mode can be entered, I2CON must be initialized as follows:

Table 66: I2C Control register (I2CON - address D8h)

Bit 7 6 5 4 3 2 1 0

- I2EN STA STO SI AA - CRSEL

value- 1000x- bit rate

CRSEL defines the bit rate. I2EN must be set to 1 to enable the I is 0, it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode. STA, STO, and SI bits must be cleared to 0.

User manual Rev. 02 — 23 May 2005 73 of 133

C function. If the AA bit

Philips Semiconductors

The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

The I

C-bus will enter Master Transmitter Mode by setting the STA bit. The I2C logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT (Data Register) and data direction bit (SLA+W). The SI bit must be cleared before the data transfer can continue.

When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes are 18h, 20h, or 38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled (setting AA = Logic 1). The appropriate action to be taken for each of these status codes is shown in Ta bl e 6 8

UM10109

P89LPC932A1 User manual

S R/W A DATA D ATA

from master to slave from slave to master

Fig 31. Format in the Master Transmitter mode.

11.6.2 Master Receiver mode

In the Master Receiver Mode, data is received from a slave transmitter. The transfer started in the same manner as in the Master Transmitter Mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to I the data transfer can continue.

When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. Refer to Ta bl e 7 0

A A/A Pslave address

logic 0 = write logic 1 = read

C Data Register (I2DAT). The SI bit must be cleared before

data transferred

(n Bytes + acknowledge)

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition

002aaa929

for details.

User manual Rev. 02 — 23 May 2005 74 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

S R Aslave address

logic 0 = write logic 1 = read

from master to slave from slave to master

Fig 32. Format of Master Receiver mode.

DATA DATA

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition

A A P

data transferred

(n Bytes + acknowledge)

After a repeated START condition, I2C-bus may switch to the Master Transmitter Mode.

S R ASLA

logic 0 = write

logic 1 = read

from master to slave from slave to master

Fig 33. A Master Receiver switches to Master Transmitter after sending Repeated Start.

DATA DATA

A W ASLA D ATA A PA RS

data transferred

(n Bytes + acknowledge)

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition SLA = slave address RS = repeat START condition

002aaa93

002aaa931

11.6.3 Slave Receiver mode

In the Slave Receiver Mode, data bytes are received from a master transmitter. To initialize the Slave Receiver Mode, the user should write the slave address to the Slave Address Register (I2ADR) and the I follows:

Table 67: I2C Control register (I2CON - address D8h)

Bit 7 6 5 4 3 2 1 0

- I2EN STA STO SI AA - CRSEL

value- 10001- -

CRSEL is not used for slave mode. I2EN must be set = 1 to enable I must be set = 1 to acknowledge its own slave address or the general call address. STA, STO and SI are cleared to 0.

After I2ADR and I2CON are initialized, the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0(W). If the direction bit is 1(R), it will enter Slave Transmitter Mode. After the address and the direction bit have been received, the SI bit is set and a valid status code can be read from the Status Register(I2STAT). Refer to Ta bl e 7 1

C Control Register (I2CON) should be configured as

C function. AA bit

for the status codes and actions.

User manual Rev. 02 — 23 May 2005 75 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

S W Aslave address

from master to slave from slave to master

Fig 34. Format of Slave Receiver mode.

11.6.4 Slave Transmitter mode

The first byte is received and handled as in the Slave Receiver Mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.3/SDA while the serial clock is input through P1.2/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, the I

C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I slave address in the same serial transfer.

C-bus may operate as a master and as a slave. In the slave mode, the

C-bus switches to the slave mode immediately and can detect its own

logic 0 = write logic 1 = read

DATA DATA

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition RS = repeated START condition

A A/A P/RS

data transferred

(n Bytes + acknowledge)

002aaa932

S R Aslave address

logic 0 = write logic 1 = read

from master to slave from slave to master

Fig 35. Format of Slave Transmitter mode.

DATA DATA

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition

A A P

data transferred

(n Bytes + acknowledge)

002aaa933

User manual Rev. 02 — 23 May 2005 76 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

P1.3/SDA

P1.2/SCL

P1.3

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.2

timer 1

overflow

I2CON I2SCLH I2SCLL

ADDRESS REGISTER

COMPARATOR

SHIFT REGISTER

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

CONTROL

SERIAL CLOCK

GENERATOR

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

I2DAT

TIMING

AND

LOGIC

I2ADR

ACK

CCLK

interrupt

INTERNAL BUS

status bus

I2STAT

STATUS

DECODER

STATUS REGISTER

002aaa899

Fig 36. I2C serial interface block diagram.

User manual Rev. 02 — 23 May 2005 77 of 133

Philips Semiconductors

Table 68: Master Transmitter mode

Status code (I2STAT)

08H A START

10H A repeat START

18h SLA+W has been

20h SLA+W has been

28h Data byte in I2DAT

Status of the I2C hardware

condition has been transmitted

transmitted; ACK has been received

transmitted; NOT-ACK has been received

has been transmitted; ACK has been received

UM10109

P89LPC932A1 User manual

Application software response Next action taken by I2C

to/from I2DAT to I2CON

STA STO SI AA

Load SLA+W x 0 0 x SLA+W will be transmitted;

Load SLA+W or

Load SLA+R

Load data byte or000xData byte will be transmitted;

no I2DAT action or100xRepeated START will be

no I2DAT action or010xSTOP condition will be

no I2DAT action 110xSTOP condition followed by a

Load data byte or000xData byte will be transmitted;

no I2DAT action or100xRepeated START will be

no I2DAT action or010xSTOP condition will be

no I2DAT action 110xSTOP condition followed by a

Load data byte or000xData byte will be transmitted;

no I2DAT action or100xRepeated START will be

no I2DAT action or010xSTOP condition will be

no I2DAT action 110xSTOP condition followed by a

x 0 0 x As above; SLA+W will be

hardware

ACK bit will be received

transmitted; I to Master Receiver Mode

ACK bit will be received

transmitted;

STO flag will be reset

START condition will be transmitted; STO flag will be reset.

ACK bit will be received

transmitted;

transmitted; STO flag will be reset

START condition will be transmitted; STO flag will be reset

ACK bit will be received

transmitted;

transmitted; STO flag will be reset

START condition will be transmitted; STO flag will be reset

C-bus switches

User manual Rev. 02 — 23 May 2005 78 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 68: Master Transmitter mode

Status code (I2STAT)

30h Data byte in I2DAT

38H Arbitration lost in

Table 69: Master Receiver mode

Status code (I2STAT)

08H A START

10H A repeat START

38H Arbitration lost in

40h SLA+R has been

48h SLA+R has been

Status of the I2C hardware

has been transmitted, NOT ACK has been received

SLA+R/W or data bytes

Status of the I2C hardware

condition has been transmitted

NOT ACK bit

transmitted; ACK has been received

transmitted; NOT ACK has been received

…continued

Application software response Next action taken by I2C

to/from I2DAT to I2CON

STA STO SI AA

Load data byte or000xData byte will be transmitted;

no I2DAT action or100xRepeated START will be

no I2DAT action or010xSTOP condition will be

no I2DAT action110xSTOP condition followed by a

No I2DAT action or000xI

No I2DAT action 100xA START condition will be

Application software response Next action taken by I2C hardware

to/from I2DAT to I2CON

Load SLA+R x 0 0 x SLA+R will be transmitted; ACK bit

Load SLA+R or x 0 0 x As above

Load SLA+W SLA+W will be transmitted; I

no I2DAT action or 0 0 0 x I

no I2DAT action 1 0 0 x A START condition will be

no I2DAT action or 0 0 0 0 Data byte will be received; NOT ACK

no I2DAT action or 0 0 0 1 Data byte will be received; ACK bit

No I2DAT action or1 0 0 x Repeated START will be transmitted

no I2DAT action or 0 1 0 x STOP condition will be transmitted;

no I2DAT action or 1 1 0 x STOP condition followed by a START

STA STO SI STA

hardware

ACK bit will be received

transmitted;

transmitted; STO flag will be reset

START condition will be transmitted. STO flag will be reset.

C-bus will be released; not

addressed slave will be entered

transmitted when the bus becomes free.

will be received

C-bus will be switched to Master Transmitter Mode

C-bus will be released; it will enter a

slave mode

transmitted when the bus becomes free

bit will be returned

will be returned

STO flag will be reset

condition will be transmitted; STO flag will be reset

User manual Rev. 02 — 23 May 2005 79 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 69: Master Receiver mode

Status code (I2STAT)

50h Data byte has

58h Data byte has

Table 70: Slave Receiver mode

Status code (I2STAT)

60H Own SLA+W has

68H Arbitration lost in

70H General call

78H Arbitration lost in

80H Previously

Status of the I2C hardware

been received; ACK has been returned

been received; NACK has been returned

Status of the I2C hardware

been received; ACK has been received

SLA+R/Was master; Own SLA+W has been received, ACK returned

address(00H) has been received, ACK has been returned

SLA+R/W as master; General call address has been received, ACK bit has been returned

addressed with own SLA address; Data has been received; ACK has been returned

…continued

Application software response Next action taken by I2C hardware

to/from I2DAT to I2CON

STA STO SI STA

Read data byte 0 0 0 0 Data byte will be received; NOT ACK

bit will be returned

read data byte 0 0 0 1 Data byte will be received; ACK bit

will be returned

Read data byte or 1 0 0 x Repeated START will be transmitted;

read data byte or 0 1 0 x STOP condition will be transmitted;

STO flag will be reset

read data byte 1 1 0 x STOP condition followed by a START

condition will be transmitted; STO flag will be reset

Application software response Next action taken by I2C hardware

to/from I2DAT to I2CON

STA STO SI AA

no I2DAT action orx 000Data byte will be received and NOT

ACK will be returned

no I2DAT action x001Data byte will be received and ACK

No I2DAT action orx000Data byte will be received and NOT

no I2DAT action x001Data byte will be received and ACK

No I2DAT action orx000Data byte will be received and NOT

no I2DAT action x001Data byte will be received and ACK

no I2DAT action orx000Data byte will be received and NOT

no I2DAT action x001Data byte will be received and ACK

Read data byte orx000Data byte will be received and NOT

read data bytex001Data byte will be received; ACK bit

will be returned

ACK will be returned

will be returned

ACK will be returned

will be returned

ACK will be returned

will be returned

ACK will be returned

will be returned

User manual Rev. 02 — 23 May 2005 80 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 70: Slave Receiver mode

Status code (I2STAT)

88H Previously

90H Previously

98H Previously

Status of the I2C hardware

addressed with own SLA address; Data has been received; NACK has been returned

addressed with General call; Data has been received; ACK has been returned

addressed with General call; Data has been received; NACK has been returned

…continued

Application software response Next action taken by I2C hardware

to/from I2DAT to I2CON

STA STO SI AA

Read data byte or0000Switched to not addressed SLA

mode; no recognition of own SLA or general address

read data byte

read data byte1001Switched to not addressed SLA

Read data byte orx000Data byte will be received and NOT

read data bytex001Data byte will be received and ACK

Read data byte0000Switched to not addressed SLA

read data byte0001Switched to not addressed SLA

read data byte1000Switched to not addressed SLA

read data byte1001Switched to not addressed SLA

0001Switched to not addressed SLA

mode; Own SLA will be recognized; general call address will be recognized if I2ADR.0 = 1

1000Switched to not addressed SLA

mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free.

ACK will be returned

will be returned

mode; no recognition of own SLA or General call address

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free.

User manual Rev. 02 — 23 May 2005 81 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 70: Slave Receiver mode

Status code (I2STAT)

A0H A STOP condition

Table 71: Slave Transmitter mode

Status code (I2STAT)

A8h Own SLA+R has

B0h Arbitration lost in

B8H Data byte in

Status of the I2C hardware

or repeated START condition has been received while still addressed as SLA/REC or SLA/TRX

Status of the I2C hardware

been received; ACK has been returned

SLA+R/W as master; Own SLA+R has been received, ACK has been returned

I2DAT has been transmitted; ACK has been received

…continued

Application software response Next action taken by I2C hardware

to/from I2DAT to I2CON

STA STO SI AA

No I2DAT action0000Switched to not addressed SLA

mode; no recognition of own SLA or General call address

no I2DAT action0001Switched to not addressed SLA

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

no I2DAT action1000Switched to not addressed SLA

mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

no I2DAT action1001Switched to not addressed SLA

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free.

Application software response Next action taken by I2C

to/from I2DAT to I2CON

Load data byte orx000Last data byte will be transmitted

load data bytex001Data byte will be transmitted; ACK

Load data byte orx000Last data byte will be transmitted

load data bytex001Data byte will be transmitted; ACK

Load data byte orx000Last data byte will be transmitted

load data bytex001Data byte will be transmitted; ACK

STA STO SI AA

hardware

and ACK bit will be received

will be received

and ACK bit will be received

bit will be received

and ACK bit will be received

will be received

User manual Rev. 02 — 23 May 2005 82 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Table 71: Slave Transmitter mode

Status code (I2STAT)

C0H Data byte in

C8H Last data byte in

Status of the I2C hardware

I2DAT has been transmitted; NACK has been received

I2DAT has been transmitted (AA = 0); ACK has been received

…continued

Application software response Next action taken by I2C

to/from I2DAT to I2CON

STA STO SI AA

No I2DAT action or0000Switched to not addressed SLA

no I2DAT action or0001Switched to not addressed SLA

no I2DAT action or1000Switched to not addressed SLA

no I2DAT action 1001Switched to not addressed SLA

No I2DAT action or0000Switched to not addressed SLA

no I2DAT action or0001Switched to not addressed SLA

no I2DAT action or1000Switched to not addressed SLA

no I2DAT action 1001Switched to not addressed SLA

hardware

mode; no recognition of own SLA or General call address.

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free.

mode; no recognition of own SLA or General call address.

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free.

mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A START condition will be transmitted when the bus becomes free.

12. Serial Peripheral Interface (SPI)

The P89LPC932A1 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.

User manual Rev. 02 — 23 May 2005 83 of 133

Philips Semiconductors

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPR1

SPR0

SPI CONTROL

SPIF

WCOL

SPI STATUS REGISTER

SPI clock (master)

MSTR SPEN

SPI

interrupt

request

8-BIT SHIFT REGISTER

READ DATA BUFFER

CLOCK LOGIC

SSIG

SPEN

DORD

MSTR

SPI CONTROL REGISTER

internal

data

bus

clock

CPHA

CPOL

SPR1

SPR0

UM10109

P89LPC932A1 User manual

S M

M S

CONTROL

LOGIC

S M

SPEN

MSTR

MISO P2.3

MOSI P2.2

SPICLK P2.5

SS P2.4

002aaa900

Fig 37. SPI block diagram.

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

• SS is the optional slave select pin. In a typical configuration, an SPI master asserts

Note that even if the SPI is configured as a master (MSTR = 1), it can still be converted to a slave by driving the SS happen, the SPIF bit (SPSTAT.7) will be set (see Section 12.4 “

devices. Data flows from master to slave on the MOSI (Master Out Slave In) pin and flows from slave to master on the MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS following conditions are true:

– If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value)

– If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P2.4 is

configured as an output (via the P2M1.4 and P2M2.4 SFR bits);

– If the SS

functions.

pin to determine whether it is selected. The SS is ignored if any of the

pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port

pin low (if P2.4 is configured as input and SSIG = 0). Should this

Mode change on SS”)

Typical connections are shown in Figure 38

to Figure 40.

Table 72: SPI Control register (SPCTL - address E2h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0

Reset00000100

User manual Rev. 02 — 23 May 2005 84 of 133

Philips Semiconductors

Table 73: SPI Control register (SPCTL - address E2h) bit description

Bit Symbol Description

0 SPR0 SPI Clock Rate Select

1 SPR1

2 CPHA SPI Clock PHAse select (see Figure 41 to Figure 44):

3 CPOL SPI Clock POLarity (see Figure 41

4 MSTR Master/Slave mode Select (see Tab l e 7 7).

5 DORD SPI Data ORDer.

6 SPEN SPI Enable.

7 SSIG SS IGnore.

UM10109

P89LPC932A1 User manual

SPR1, SPR0:

CCLK

00 —

01 —

10 —

11 —

1 — Data is driven on the leading edge of SPICLK, and is sampled on the trailing

edge.

0 — Data is driven when SS SPICLK, and is sampled on the leading edge. (Note: If SSIG = 1, the operation is not defined.

1 — SPICLK is high when idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge.

0 — SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge.

1 — The LSB of the data word is transmitted first.

0 — The MSB of the data word is transmitted first.

1 — The SPI is enabled.

0 — The SPI is disabled and all SPI pins will be port pins.

1 — MSTR (bit 4) decides whether the device is a master or slave.

0 — The SS

used as a port pin (see Tab l e 7 7

⁄

CCLK

⁄

CCLK

⁄

CCLK

⁄

128

is low (SSIG = 0) and changes on the trailing edge of

to Figure 44):

pin decides whether the device is master or slave. The SS pin can be

Table 74: SPI Status register (SPSTAT - address E1h) bit allocation

Bit 7 6 5 4 3 2 1 0

SymbolSPIFWCOL------

Reset00xxxxxx

Table 75: SPI Status register (SPSTAT - address E1h) bit description

Bit Symbol Description

0:5 - reserved

6 WCOL SPI Write Collision Flag. The WCOL bit is set if the SPI data register, SPDAT, is

written during a data transfer (see Section 12.5 “ is cleared in software by writing a logic 1 to this bit.

7 SPIF SPI Transfer Completion Flag. When a serial transfer finishes, the SPIF bit is set

and an interrupt is generated if both the ESPI (IEN1.3) bit and the EA bit are set. If

is an input and is driven low when SPI is in master mode, and SSIG = 0, this bit

SS will also be set (see Section 12.4 “ in software by writing a logic 1 to this bit.

User manual Rev. 02 — 23 May 2005 85 of 133

Mode change on SS”). The SPIF flag is cleared

Write collision”). The WCOL flag

Philips Semiconductors

Table 76: SPI Data register (SPDAT - address E3h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol MSB LSB

Reset00000000

UM10109

P89LPC932A1 User manual

master slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

PORT

MISO

MOSI

SPICLK

8-BIT SHIFT

002aaa901

Fig 38. SPI single master single slave configuration.

In Figure 38, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave. The SPI master can use any port pin (including P2.4/SS

master slave

8-BIT SHIFT

MISO

MOSI

) to drive the SS pin.

MISO

MOSI

8-BIT SHIFT

SPI CLOCK

GENERATOR

SPICLK

SPI CLOCK

GENERATOR

002aaa90

Fig 39. SPI dual device configuration, where either can be a master or a slave.

Figure 39

shows a case where two devices are connected to each other and either device can be a master or a slave. When no SPI operation is occurring, both can be configured as masters (MSTR = 1) with SSIG cleared to 0 and P2.4 (SS

) configured in quasi-bidirectional mode. When a device initiates a transfer, it can configure P2.4 as an output and drive it low, forcing a mode change in the other device (see Section 12.4 “

Mode

change on SS”) to slave.

User manual Rev. 02 — 23 May 2005 86 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

master slave

MISO

8-BIT SHIFT

SPI CLOCK

GENERATOR

Fig 40. SPI single master multiple slaves configuration.

In Figure 40, SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected by the corresponding SS P2.4/SS

) to drive the SS pins.

MOSI

SPICLK

port

signals. The SPI master can use any port pin (including

MISO

MOSI

SPICLK

MISO

MOSI

SPICLK

8-BIT SHIFT

slave

8-BIT SHIFT

002aaa903

12.1 Configuring the SPI

Ta bl e 7 7 shows configuration for the master/slave modes as well as usages and directions

for the modes.

Table 77: SPI master and slave selection

SPEN SSIG SS Pin MSTR Master

or Slave Mode

[1]

0xP2.4

1 0 0 0 Slave output input input Selected as slave.

1 0 1 0 Slave Hi-Z input input Not selected. MISO is high-impedance to avoid

1 0 0 1 (-> 0)

User manual Rev. 02 — 23 May 2005 87 of 133

x SPI

Disabled

[2]

Slave output input input P2.4/SS is configured as an input or

MISO MOSI SPICLK Remarks

P2.3

[1]

P2.2

[1]

P2.5

[1]

SPI disabled. P2.2, P2.3, P2.4, P2.5 are used as port pins.

bus contention.

quasi-bidirectional pin. SSIG is 0. Selected externally as slave if SS driven low. The MSTR bit will be cleared to logic 0 when SS

is selected and is

becomes low.

Philips Semiconductors

Table 77: SPI master and slave selection …continued

SPEN SSIG SS Pin MSTR Master

or Slave Mode

1011 Master

(idle)

Master

(active)

[1]

11P2.4

[1] Selected as a port function

[2] The MSTR bit changes to logic 0 automatically when SS

0 Slave output input input

[1]

1 Master input output output

MISO MOSI SPICLK Remarks

input Hi-Z Hi-Z MOSI and SPICLK are at high-impedance to

12.2 Additional considerations for a slave

UM10109

P89LPC932A1 User manual

avoid bus contention when the MAster is idle. The application must pull-up or pull-down SPICLK (depending on CPOL - SPCTL.3) to avoid a floating SPICLK.

output output MOSI and SPICLK are push-pull when the

Master is active.

becomes low in input mode and SSIG is logic 0.

When CPHA equals zero, SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte. If the SPDAT register is written while SS is active (low), a write collision error results. The operation is undefined if CPHA is logic 0 and SSIG is logic 1.

When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0, the SS active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line.

12.3 Additional considerations for a master

In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN = 1) and selected as master, writing to the SPI data register by the master starts the SPI clock generator and data transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.

Note that the master can select a slave by driving the SS low. Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave, at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master.

After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt will be created if the SPI interrupt is enabled (ESPI, or IEN1.3 = 1). The two shift registers in the master CPU and slave CPU can be considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged.

pin may remain

pin of the corresponding device

12.4 Mode change on SS

If SPEN = 1, SSIG = 0 and MSTR = 1, the SPI is enabled in master mode. The SS pin can be configured as an input (P2M2.4, P2M1.4 = 00) or quasi-bidirectional (P2M2.4, P2M1.4 = 01). In this case, another master can drive this pin low to select this device as an SPI

User manual Rev. 02 — 23 May 2005 88 of 133

Philips Semiconductors

slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.

The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an SPI interrupt will occur.

User software should always check the MSTR bit. If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will stay in slave mode.

12.5 Write collision

The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for transmission can not be written to the shift register until the previous transaction is complete. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case, the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the collision, will be lost.

UM10109

P89LPC932A1 User manual

While write collision is detected for both a master or a slave, it is uncommon for a master because the master has full control of the transfer in progress. The slave, however, has no control over when the master will initiate a transfer and therefore collision can occur.

For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character. However, the received character must be read from the Data Register before the next character has been completely shifted in. Otherwise. the previous data is lost.

WCOL can be cleared in software by writing a logic 1 to the bit.

12.6 Data mode

Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. Figure 41

Figure 44

show the different settings of Clock Phase bit CPHA.

User manual Rev. 02 — 23 May 2005 89 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

(1) Not defined

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

Fig 41. SPI slave transfer format with CPHA = 0.

LSB

MSB

LSB

MSB

(1)

002aaa934

User manual Rev. 02 — 23 May 2005 90 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

(1) Not defined

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

(1)

MSB

LSB

Fig 42. SPI slave transfer format with CPHA = 1.

LSB

MSB

LSB

MSB

002aaa93

User manual Rev. 02 — 23 May 2005 91 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

(1) Not defined

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

Fig 43. SPI master transfer format with CPHA = 0.

LSB

MSB

LSB

MSB

002aaa93

User manual Rev. 02 — 23 May 2005 92 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

(1) Not defined

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

Fig 44. SPI master transfer format with CPHA = 1.

LSB

MSB

LSB

MSB

002aaa93

12.7 SPI clock prescaler select

The SPI clock prescalar selection uses the SPR1-SPR0 bits in the SPCTL register (see

Ta bl e 7 3

13. Analog comparators

Two analog comparators are provided on the P89LPC932A1. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes.

13.1 Comparator configuration

Each comparator has a control register, CMP1 for comparator 1 and CMP2 for comparator

2. The control registers are identical and are shown in Ta bl e 7 9

The overall connections to both comparators are shown in Figure 45 possible configurations for each comparator, as determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in

Figure 46

. There are eight

User manual Rev. 02 — 23 May 2005 93 of 133

Philips Semiconductors

When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

Table 78: Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit

Bit 7 6 5 4 3 2 1 0

Symbol - - CEn CPn CNn OEn COn CMFn

Resetxx000000

Table 79: Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit

Bit Symbol Description

0 CMFn Comparator interrupt flag. This bit is set by hardware whenever the comparator

1 COn Comparator output, synchronized to the CPU clock to allow reading by software.

2 OEn Output enable. When logic 1, the comparator output is connected to the CMPn pin

3 CNn Comparator negative input select. When logic 0, the comparator reference pin

4 CPn Comparator positive input select. When logic 0, CINnA is selected as the positive

5 CEn Comparator enable. When set, the corresponding comparator function is enabled.

6:7 - reserved

UM10109

P89LPC932A1 User manual

allocation

description

output COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by software.

if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.

CMPREF is selected as the negative comparator input. When logic 1, the internal comparator reference, Vref, is selected as the negative comparator input.

comparator input. When logic 1, CINnB is selected as the positive comparator input.

Comparator output is stable 10 microseconds after CEn is set.

CP1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

REF

CN1

CP2

(P0.2) CIN2A

(P0.1) CIN2B

CN2

Fig 45. Comparator input and output connections.

User manual Rev. 02 — 23 May 2005 94 of 133

comparator 1

comparator 2

CO1

change detect

CO2

OE1

CMP1 (P0.6)

CMF1

interrupt

CMF2

CMP2 (P0.0)

OE2

002aaa904

Philips Semiconductors

13.2 Internal reference voltage

An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the P89LPC932A1 data sheet for specifications

13.3 Comparator input pins

Comparator input and reference pins maybe be used as either digital I/O or as inputs to the comparator. When used as digital I/O these pins are 5 V tolerant. However, when selected as comparator input signals in CMPn lower voltage limits apply. Please refer to the P89LPC932A1 data sheet for specifications.

13.4 Comparator interrupt

Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register. If both comparators enable interrupts, after entering the interrupt service routine, the user will need to read the flags to determine which comparator caused the interrupt.

UM10109

P89LPC932A1 User manual

When a comparator is disabled the comparator’s output, COx, goes high. If the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.

13.5 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down mode or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down mode and Idle mode, as well as in the normal operating mode. This should be taken into consideration when system power consumption is an issue. To minimize power consumption, the user can power-down the comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply putting the device in Total Power-down mode.

User manual Rev. 02 — 23 May 2005 95 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

CINnA

CMPREF

COn

002aaa618

CINnA

CMPREF

a. CPn, CNn, OEn = 0 0 0 b. CPn, CNn, OEn = 0 0 1

REF

CINnA

(1.23 V)

COn

002aaa621

REF

CINnA

(1.23 V)

c. CPn, CNn, OEn = 0 1 0 d. CPn, CNn, OEn = 0 1 1

CINnB

CMPREF

COn

002aaa623

CINnB

CMPREF

e. CPn, CNn, OEn = 1 0 0 f. CPn, CNn, OEn = 1 0 1

REF

CINnB

(1.23V)

COn

002aaa625

REF

CINnB

(1.23 V)

g. CPn, CNn, OEn = 1 1 0 h. CPn, CNn, OEn = 1 1 1

Fig 46. Comparator configurations.

COn

002aaa620

002aaa622

COn

002aaa624

002aaa626

COn

CMPn

13.6 Comparators configuration example

The code shown below is an example of initializing one comparator. Comparator 1 is configured to use the CIN1A and CMPREF inputs, outputs the comparator result to the CMP1 pin, and generates an interrupt when the comparator output changes.

CMPINIT:

MOV PT0AD,#030h ;Disable digital INPUTS on CIN1A, CMPREF.

ANL P0M2,#0CFh ;Disable digital OUTPUTS on pins that are used ORL P0M1,#030h ;for analog functions: CIN1A, CMPREF. MOV CMP1,#024h ;Turn on comparator 1 and set up for:

;Positive input on CIN1A. ;Negative input from CMPREF pin.

;Output to CMP1 pin enabled. CALL delay10us ;The comparator needs at least 10 microseconds before use. ANL CMP1,#0FEh ;Clear comparator 1 interrupt flag. SETB EC ;Enable the comparator interrupt, SETB EA ;Enable the interrupt system (if needed).

RET ;Return to caller.

The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning

User manual Rev. 02 — 23 May 2005 96 of 133

Philips Semiconductors

14. Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

There are three SFRs used for this function. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 are enabled to trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA = 1. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 0 (not equal), then any key connected to Port0 which is enabled by KBMASK register is will cause the hardware to set KBIF = 1 and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use.

UM10109

P89LPC932A1 User manual

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs

Table 80: Keypad Pattern register (KBPATN - address 93h) bit allocation

Bit 7 6 5 4 3 2 1 0

S ym b ol K B PATN .7 K B PATN . 6 K B PAT N. 5 K B PAT N. 4 K B PATN . 3 K BPAT N .2 K B PAT N. 1 K B PAT N. 0

Reset11111111

Table 81: Keypad Pattern register (KBPATN - address 93h) bit description

Bit Symbol Access Description

0:7 KBPATN.7:0 R/W Pattern bit 0 - bit 7

Table 82: Keypad Control register (KBCON - address 94h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol------PATN_SELKBIF

Resetxxxxxx00

Table 83: Keypad Control register (KBCON - address 94h) bit description

Bit Symbol Access Description

0 KBIF R/W Keypad Interrupt Flag. Set when Port 0 matches user defined conditions specified in KBPATN,

KBMASK, and PATN_SEL. Needs to be cleared by software by writing logic 0.

1 PATN_SEL R/W Pattern Matching Polarity selection. When set, Port 0 has to be equal to the user-defined

Pattern in KBPATN to generate the interrupt. When clear, Port 0 has to be not equal to the value of KBPATN register to generate the interrupt.

2:7 - - reserved

User manual Rev. 02 — 23 May 2005 97 of 133

Philips Semiconductors

P89LPC932A1 User manual

Table 84: Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol KBMASK.7 KBMASK.6 KBMASK.5 KBMASK.4 KBMASK.3 KBMASK.2 KBMASK.1 KBMASK.0

Reset00000000

Table 85: Keypad Interrupt Mask register (KBMASK - address 86h) bit description

Bit Symbol Description

0 KBMASK.0 When set, enables P0.0 as a cause of a Keypad Interrupt.

1 KBMASK.1 When set, enables P0.1 as a cause of a Keypad Interrupt.

2 KBMASK.2 When set, enables P0.2 as a cause of a Keypad Interrupt.

3 KBMASK.3 When set, enables P0.3 as a cause of a Keypad Interrupt.

4 KBMASK.4 When set, enables P0.4 as a cause of a Keypad Interrupt.

5 KBMASK.5 When set, enables P0.5 as a cause of a Keypad Interrupt.

6 KBMASK.6 When set, enables P0.6 as a cause of a Keypad Interrupt.

7 KBMASK.7 When set, enables P0.7 as a cause of a Keypad Interrupt.

[1] The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective.

UM10109

15. Watchdog timer (WDT)

The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.

15.1 Watchdog function

The user has the ability using the WDCON and UCFG1 registers to control the run /stop condition of the WDT, the clock source for the WDT, the prescaler value, and whether the WDT is enabled to reset the device on underflow. In addition, there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer.

The WDTE bit (UCFG1.7), if set, enables the WDT to reset the device on underflow. Following reset, the WDT will be running regardless of the state of the WDTE bit.

The WDRUN bit (WDCON.2) can be set to start the WDT and cleared to stop the WDT. Following reset this bit will be set and the WDT will be running. All writes to WDCON need to be followed by a feed sequence (see Section 15.2 user to select the clock source for the WDT and the prescaler.

When the timer is not enabled to reset the device on underflow, the WDT can be used in ‘timer mode’ and be enabled to produce an interrupt (IEN0.6) if desired

). Additional bits in WDCON allow the

The Watchdog Safety Enable bit, WDSE (UCFG1.4) along with WDTE, is designed to force certain operating conditions at power-up. Refer to Tab le 8 6

User manual Rev. 02 — 23 May 2005 98 of 133

for details.

Philips Semiconductors

Figure 49 shows the watchdog timer in watchdog mode. It consists of a programmable

13-bit prescaler, and an 8-bit down counter. The down counter is clocked (decremented) by a tap taken from the prescaler. The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register. (Note that switching of the clock sources will not take effect immediately - see Section 15.3

The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect.

If a watchdog reset occurs, the internal reset is active for at least one watchdog clock cycle (PCLK or the watchdog oscillator clock). If CCLK is still running, code execution will begin immediately after the reset cycle. If the processor was in Power-down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable.

Table 86: Watchdog timer configuration

WDTE WDSE FUNCTION

0 x The watchdog reset is disabled. The timer can be used as an internal timer and

1 0 The watchdog reset is enabled. The user can set WDCLK to choose the clock

1 1 The watchdog reset is enabled, along with additional safety features:

P89LPC932A1 User manual

can be used to generate an interrupt. WDSE has no effect.

source.

1. WDCLK is forced to 1 (using watchdog oscillator)

2. WDCON and WDL register can only be written once

3. WDRUN is forced to 1

UM10109

watchdog

oscillator

PCLK

WDCLK AFTER

A WATCHDOG

FEED SEQUENCE

PRE2

PRE1

PRE0

Fig 47. Watchdog Prescaler.

DECODE

÷32

000 001 010 011 100 101 110 111

15.2 Feed sequence

The watchdog timer control register and the 8-bit down counter (See Figure 48) are not directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control register and the 8-bit down counter. Before the feed sequence, any new values written to

÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2

÷64÷32 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096

to watchdog down counter (after one prescaler count delay)

002aaa938

User manual Rev. 02 — 23 May 2005 99 of 133

Philips Semiconductors

these two SFRs will not take effect. To avoid a watchdog reset, the watchdog timer needs to be fed (via a special sequence of software action called the feed sequence) prior to reaching an underflow.

To feed the watchdog, two write instructions must be sequentially executed successfully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register. An incorrect feed sequence will cause an immediate watchdog reset. The program sequence to feed the watchdog timer is as follows:

CLR EA ;disable interrupt

This sequence assumes that the P89LPC932A1 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset. If it is known that no interrupt could occur during the feed sequence, the instructions to disable and re-enable interrupts may be removed.

UM10109

P89LPC932A1 User manual

MOV WFEED1,#0A5h ;do watchdog feed part 1 MOV WFEED2,#05Ah ;do watchdog feed part 2 SETB EA ;enable interrupt

In watchdog mode (WDTE = 1), writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8-bit down counter, and the WDCON to the shadow register. If writing to the WDCON register is not immediately followed by the feed sequence, a watchdog reset will occur.

For example: setting WDRUN = 1:

MOV ACC,WDCON ;get WDCON SETB ACC.2 ;set WD_RUN=1 MOV WDL,#0FFh ;New count to be loaded to 8-bit down counter CLR EA ;disable interrupt MOV WDCON,ACC ;write back to WDCON (after the watchdog is enabled, a feed

must occur ; immediately)

MOV WFEED1,#0A5h ;do watchdog feed part 1 MOV WFEED2,#05Ah ;do watchdog feed part 2 SETB EA ;enable interrupt

In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle (no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.

The number of watchdog clocks before timing out is calculated by the following equations:

tclks 2

5 PRE+()

()WDL 1+()1+=

(1)

where:

PRE is the value of prescaler (PRE2 to PRE0) which can be the range 0 to 7, and;

WDL is the value of watchdog load register which can be the range of 0 to 255.

The minimum number of tclks is:

50+()

tclks 2

User manual Rev. 02 — 23 May 2005 100 of 133

()01+()133=+=

(2)

Philips UM10109 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Comparison to the P89LPC932 device

1.2 Pin configuration

1.3 Pin description

1.4 Special function registers

1.5 Memory organization

2. Clocks

2.1 Enhanced CPU

2.2 Clock definitions

2.3 Clock output

2.4 On-chip RC oscillator option

2.5 Watchdog oscillator option

2.6 External clock input option

2.7 Oscillator Clock (OSCCLK) wake-up delay

2.8 CPU Clock (CCLK) modification: DIVM register

2.9 Low power select

3. Interrupts

3.1 Interrupt priority structure

3.2 External Interrupt pin glitch suppression

4. I/O ports

4.1 Port configurations

4.2 Quasi-bidirectional output configuration

4.3 Open drain output configuration

4.4 Input-only configuration

4.5 Push-pull output configuration

4.6 Port 0 and Analog Comparator functions

4.7 Additional port features

5. Power monitoring functions

5.1 Brownout detection

5.2 Power-on detection

5.3 Power reduction modes

6. Reset

6.1 Reset vector

7. Timers 0 and 1

7.1 Mode 0

7.2 Mode 1

7.3 Mode 2

7.4 Mode 3

7.5 Mode 6

7.6 Timer overflow toggle output

8. Real-time clock system timer

8.1 Real-time clock source

8.2 Changing RTCS1/RTCS0

8.3 Real-time clock interrupt/wake-up

8.4 Reset sources affecting the Real-time clock

9. Capture/Compare Unit (CCU)

9.1 CCU Clock (CCUCLK)

9.2 CCU Clock prescaling

9.3 Basic timer operation

9.4 Output compare

9.5 Input capture

9.6 PWM operation

9.7 Alternating output mode

9.8 Synchronized PWM register update

9.9 HALT

9.10 PLL operation

9.11 CCU interrupt structure

10. UART

10.1 Mode 0

10.2 Mode 1

10.3 Mode 2

10.4 Mode 3

10.5 SFR space

10.6 Baud Rate generator and selection

10.7 Updating the BRGR1 and BRGR0 SFRs

10.8 Framing error

10.9 Break detect

10.10 More about UART Mode 0

10.11 More about UART Mode 1

10.12 More about UART Modes 2 and 3

10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1

10.14 Break detect

10.15 Double buffering

10.16 Double buffering in different modes

10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)

10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)