Philips UM10109 User Manual

UM10109

P89LPC932A1 8-bit microcontroller with two-clock 80C51 core

Rev. 02 — 23 May 2005 User manual

Document information

Info Content

Keywords P89LPC932, P89LPC932A1

Abstract Technical information for the P89LPC932A1 device.

Philips Semiconductors

Revision history

Rev Date Description

2 20050523

1 20040802 Initial version

• Corrected typographical error in Table 35 “Capture compare control register (CCRx -

address Exh) bit description”.

• Corrected Table 92 “Data EEPROM control register (DEECON address F1h) bit

allocation” and Table 93 “Data EEPROM control register (DEECON address F1h) bit description”.

• Removed “with 8-bit A/D” from title.

• Revised Table 37 “Output compare pin behavior” for OCMx1:0 =10.

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P89LPC932A1 User manual

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual Rev. 02 — 23 May 2005 2 of 133

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1. Introduction

The P89LPC932A1 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC932A1 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC932A1 in order to reduce component count, board space, and system cost.

1.1 Comparison to the P89LPC932 device

The P89LPC932A1 includes several improvements compared to the P89LPC932. These improvements are described below.

1.1.1 Byte-erasability (IAP-Lite)

The original P89LPC932 allowed from 1 byte to 64 bytes of user code memory, in a single page, to be programmed using an IAP function call. The bytes to be programmed needed to have been previously erased using either a page erase, sector erase, or chip erase (in a parallel programmer) command. Thus code memory was erased in 64 byte, 1 kB, or 8 kB groups. The P89LPC932A1 allows from 1 byte to 64 bytes of a page of user code memory to be erased and reprogrammed in a single operation. The bytes to be erased and reprogrammed may be randomly addressed within a single page. Only the bytes so addressed will be affected. See Section 18.4 “

page 109.

1.1.2 Serial in-circuit programming (ICP)

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P89LPC932A1 User manual

Using Flash as data storage: IAP-Lite” on

In-Circuit Programming is a method intended to allow low cost commercial programmers to program and erase these devices without removing the microcontroller from the system. The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC932A1 through a two-wire serial interface. Philips has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins (V be available to interface your application to an external programmer in order to use this feature. This function was not available on the P89LPC932 device.

1.1.3 ‘On-the-fly’ clock selection

The RC Oscillator can be selected as the source for the CPU clock (CCLK) by using the RCCLK bit in the TRIM register (TRIM.7). This bit allows for fast ‘on-the-fly’ switching between the RC Oscillator and the clock source selected by the oscillator type select bits, FOSC[2:0], in UCFG1, without the need to reset the device. This functionality was not available on the P89LPC932. See Table 5 “

address 96h) bit description” on page 22.

, VSS, P0.5, P0.4, and RST). Only a small connector needs to

DD

On-chip RC oscillator trim register (TRIM -

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Philips Semiconductors

1.1.4 Increased ISP/IAP functionality

1.1.4.1 Support for the watchdog timer

The ISP code has been modified to set the WDT prescaler (in WDCON) and WDL register to their maximum values. Other WDCON bits are unchanged and the ISP code does not explicitly enable or disable the WDT. Periodic feeds are provided within the ISP code to support applications that entered the ISP code with an enabled WDT. This functionality was not provided in the ISP code on the P89LPC932.

1.1.4.2 XDATA data buffer option added for programming code memory

The “program user code page” function on the P89LPC932 used IDATA as the 64 byte data buffer. An option is provided to allow the user to specify that XDATA is to be used instead as the buffer source. If the F1 flag (PSW.1) is set, then XDATA is used. If the F1 flag (PSW.1) is cleared, then IDATA is used.

1.1.4.3 Port 0 initialization

On the P89LPC932 the ISP code during initialization programmed all bits of Port 0 to the quasi-bidirectional mode and set these port pins HIGH. This has been changed such that only the TxD and RxD pins have their port mode programmed during ISP initialization. All other Port 0 pins remain in their previous state (for example, input-only mode following a reset).

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P89LPC932A1 User manual

1.1.4.4 Direct load of UART baud rate fix

A bug identified in the “direct load of baud rate” ISP function has been fixed. The baud rate source for this function has been changed from Timer 1 to the BRG.

1.1.4.5 Boot Vector and IAP entry points modified

To protect against errant code execution incrementing into the ISP or IAP routines, software reset instructions have been added to the beginning of these code blocks. This required that the ISP and IAP entry points be changed. The ISP entry point has changed to 1F00H resulting in a default Boot Vector of 1FH. The IAP entry point has changed to FF03H.

1.1.4.6 IAP authorization key

IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call. This authorization key is set by writing 96H to RAM location FFH. See Section 18.13 “

After the function call is processed by the IAP routine, the authorization key will be cleared. Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key. If an IAP routine that requires an authorization key is called without a valid authorization key present, the MCU will perform a reset.

1.1.4.7 Hardware write enable (WE) key

This device has hardware write enable protection. This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes (UCFG1, BOOTVEC, and BOOTSTAT). This protection does not apply to commercial programmer modes. When enabled, user code requesting a write function via IAP or IAP-Lite will need to explicitly set a Write Enable flag prior to requesting the write function. See Section 18.14 “

Flash write enable” on page 119

IAP authorization key” on page 118

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1.1.4.8 Configuration byte protection

A separate write protection bit has been provided for the “configuration bytes”. These bytes include UCFG1, BootStat, Boot Vector, and the sector security bytes. This write protection applies for ISP and IAP modes. It does not apply to commercial programmer modes. See Section 18.15 “

1.1.5 Previous errata fix

Most known errata on the P89LPC932 devices has been fixed on the P89LPC932A1 device. For current errata information on the P89LPC932A1, if any, please see the P89LPC932A1 errata sheet.

1.2 Pin configuration

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P89LPC932A1 User manual

Configuration byte protection” on page 119

V

SS

1

2

3

4

5

6

7

P89LPC932A1FDH

8

9

10

11

12

13

14

ICB/P2.0

OCD/P2.1

KBI0/CMP2/P0.0

OCC/P1.7

OCB/P1.6

RST/P1.5

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

INT1/P1.4

SDA/INT0/P1.3

SCL/T0/P1.2

MOSI/P2.2

MISO/P2.3

Fig 1. P89LPC932A1 TSSOP28 pin configuration.

002aaa886

28

P2.7/ICA

27

P2.6/OCA

26

P0.1/CIN2B/KBI1

25

P0.2/CIN2A/KBI2

24

P0.3/CIN1B/KBI3

23

P0.4/CIN1A/KBI4

22

P0.5/CMPREF/KBI5

21

V

DD

20

P0.6/CMP1/KBI6

19

P0.7/T1/KBI7

18

P1.0/TXD

17

P1.1/RXD

16

P2.5/SPICLK

15

P2.4/SS

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P1.7/OCC

P0.0/CMP2/KBI0

P2.1/OCD

2

4

3

P2.0/ICB

P2.7/ICA

1

28

P2.6/OCA

P0.1/CIN2B/KBI1

26

27

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P89LPC932A1 User manual

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

5

6

7

V

SS

8

P89LPC932A1FA

9

10

11

121314

P1.2/T0/SCL

15

P2.4/SS

P2.2/MOSI

P2.3/MISO

Fig 2. P89LPC932A1 PLCC28 pin configuration.

terminal 1

index area

P1.6/OCB

P1.5/RST

V

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

SS

P1.7/OCC

P2.1/OCD

P2.0/ICB

P0.0/CMP2/KBI0

28272625242322

1 21

2 20

3

4 18

P89LPC932A1FHN

5 17

6 16

7 15

8

9

1011121314

161718

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1

19

25

P0.2/CIN2A/KBI2

24

P0.3/CIN1B/KBI3

23

P0.4/CIN1A/KBI4

22

P0.5/CMPREF/KBI5

21

V

DD

P0.6/CMP1/KBI6

20

P0.7/T1/KBI7

19

002aaa887

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

002aaa889

P2.4/SS

P2.2/MOSI

P2.3/MISO

P1.2/T0/SCL

Transparent top view

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

Fig 3. P89LPC932A1 HVQFN28 pin configuration.

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1.3 Pin description

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P0.0 to P0.7 3, 26, 25,

24, 23, 22, 20, 19

327I/OP0.0 — Port 0 bit 0.

26 22 I/O P0.1 — Port 0 bit 1.

25 21 I/O P0.2 — Port 0 bit 2.

24 20 I/O P0.3 — Port 0 bit 3.

23 19 I/O P0.4 — Port 0 bit 4.

22 18 I/O P0.5 — Port 0 bit 5.

HVQFN28

27, 22, 21, 20, 19, 18, 16, 15

I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.

During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 “Port configurations” and the P89LPC932A1 data sheet, Static characteristics for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

O CMP2 — Comparator 2 output.

I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B.

I KBI1 — Keyboard input 1.

I CIN2A — Comparator 2 positive input A.

I KBI2 — Keyboard input 2.

I CIN1B — Comparator 1 positive input B.

I KBI3 — Keyboard input 3.

I CIN1A — Comparator 1 positive input A.

I KBI4 — Keyboard input 4.

I CMPREF — Comparator reference (negative) input.

I KBI5 — Keyboard input 5.

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Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P0.0 to P0.7 (continued)

20 16 I/O P0.6 — Port 0 bit 6.

19 15 I/O P0.7 — Port 0 bit 7.

…continued

HVQFN28

O CMP1 — Comparator 1 output.

I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overflow output.

I KBI7 — Keyboard input 7.

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P89LPC932A1 User manual

Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P1.0 to P1.7 18, 17, 12,

11, 10, 6, 5, 4

18 14 I/O P1.0 — Port 1 bit 0.

17 13 I/O P1.1 — Port 1 bit 1.

12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

11 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

10 6 I P1.4 — Port 1 bit 4.

62 IP1.5 — Port 1 bit 5 (input only).

51 I/OP1.6 — Port 1 bit 6.

428I/OP1.7 — Port 1 bit 7.

…continued

HVQFN28

14, 13, 8, 7, 6, 2, 1, 28

[1]

I/O, I

O TXD — Transmitter output for the serial port.

I RXD — Receiver input for the serial port.

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain

I/O SCL — I

I INT0

I/O SDA — I

I INT1

I RST

O OCB — Output Compare B

O OCC — Output Compare C

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 4.1 “ and the P89LPC932A1 data sheet, Static characteristics for details.

P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

when used as output).

2

— External interrupt 0 input.

2

— External interrupt 1 input.

— External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until V specified level. When system power is removed V the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

DD

Port configurations”

C serial clock input/output.

C serial data input/output.

has reached its

DD

falls below the minimum specified operating voltage.

will fall below

DD

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Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P2.0 to P2.7 1, 2, 13,

14, 15, 16, 27, 28

125I/OP2.0 — Port 2 bit 0.

226I/OP2.1 — Port 2 bit 1.

13 9 I/O P2.2 — Port 2 bit 2.

14 10 I/O P2.3 — Port 2 bit 3.

15 11 I/O P2.4 — Port 2 bit 4.

16 12 I/O P2.5 — Port 2 bit 5.

27 23 I/O P2.6 — Port 2 bit 6.

28 24 I/O P2.7 — Port 2 bit 7.

…continued

HVQFN28

25, 26, 9, 10, 11, 12, 23, 24

I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.

During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 “ the P89LPC932A1 data sheet, Static characteristics for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

I ICB — Input Capture B

O OCD — Output Compare D

I/O MOSI — SPI master out slave in. When configured as master, this pin is

output; when configured as slave, this pin is input.

I/O MISO — When configured as master, this pin is input, when configured

as slave, this pin is output.

I SS

I/O SPICLK — SPI clock. When configured as master, this pin is output;

O OCA — Output Compare A

I ICA — Input Capture A

— SPI Slave select.

when configured as slave, this pin is input.

Port configurations” and

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Table 1: Pin description

Symbol Pin Type Description

TSSOP28, PLCC28

P3.0 to P3.1 9, 8 5, 4 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.

95 I/OP3.0 — Port 3 bit 0.

84 I/OP3.1 — Port 3 bit 1.

V

SS

V

DD

73 IGround: 0 V reference.

21 17 I Power Supply: This is the power supply voltage for normal operation as

…continued

HVQFN28

During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 4.1 data sheet, Static characteristics for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator

option is selected via the FLASH configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer.

I XTAL1 — Input to the oscillator circuit and internal clock generator

circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer.

well as Idle and Power-down modes.

and the P89LPC932A1

[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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UM10109

P89LPC932A1 User manual

P89LPC932A1

8 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM

512-BYTE

DATA EEPROM

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

ACCELERATED 2-CLOCK 80C51 CPU

internal

bus

UART

I2C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

CCU (CAPTURE/ COMPARE UNIT)

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CRYSTAL

OR

RESONATOR

CONFIGURABLE

OSCILLATOR

Fig 4. P89LPC932A1 block diagram.

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

CPU clock

ON-CHIP

RC

OSCILLATOR

002aaa885

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1.4 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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P89LPC932A1 User manual

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

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Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 0000 0000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0

B* B register F0H 00 0000 0000

BRGR0

BRGR1

BRGCON Baud rate generator

CCCRA Capture compare A control

CCCRB Capture compare B control

CCCRC Capture compare C control

CCCRD Capture compare D control

CMP1 Comparator 1 control

CMP2 Comparator 2 control

DEECON Data EEPROM control

DEEDAT Data EEPROM data

DEEADR Data EEPROM address

DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

[2]

Baud rate generator rate low

[2]

Baud rate generator rate high

control

register

control

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

BEH 00 0000 0000

BFH 00 0000 0000

BDH------SBRGSBRGEN00

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 0000 0000

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 0000 0000

ECH-----FCOCOCMC1OCMC000xxxxx000

EDH-----FCODOCMD1OCMD000xxxxx000

ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

F1H EEIF HVERR ECTL1 ECTL0 - - - EADR8 0E 0000 1110

F2H 00 0000 0000

F3H 00 0000 0000

95H 00 0000 0000

MSB LSB Hex Binary

[2]

[1]

Philips Semiconductors

xxxx xx00

xx00 0000

P89LPC932A1 User manual

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Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

DPH Data pointer high 83H 00 0000 0000

DPL Data pointer low 82H 00 0000 0000

I2ADR I

I2CON* I

I2DAT I

I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

ICRAH Input capture A register

ICRAL Input capture A register

ICRBH Input capture B register

ICRBL Input capture B register

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

IEN1* Interrupt enable 1 E8H EIEE EST - ECCU ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PIEE PST - PCCU PSPI PC PKBI PI2C 00

IP1H Interrupt priority 1 high F7H PIEEH PSTH - PCCUH PSPIH PCH PKBIH PI2CH 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

2

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

Bit address DF DE DD DC DB DA D9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

2

C data register DAH

DDH 00 0000 0000

duty cycle register high

DCH 00 0000 0000

duty cycle register low

2

C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000

ABH 00 0000 0000

high

AAH 00 0000 0000

low

AFH 00 0000 0000

high

AEH 00 0000 0000

low

Bit address AF AE AD AC AB AA A9 A8

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

Bit address FF FE FD FC FB FA F9 F8

MSB LSB Hex Binary

[1]

PT1H PX1H PT0H PX0H 00

PSRH

[1]

00x0 0000

x000 0000

00x0 0000

Philips Semiconductors

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User manual Rev. 02 — 23 May 2005 16 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 1111 1111

OCRAH Output compare A register

OCRAL Output compare A register

OCRBH Output compare B register

OCRBL Output compare B register

OCRCH Output compare C register

OCRCL Output compare C register

OCRDH Output compare D register

OCRDL Output compare D register

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H OCC OCB RST

P2* Port 2 A0H ICA OCA SPICLK SS

P3*Port3 B0H------XTAL1XTAL2

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

86H 00 0000 0000

register

EFH 00 0000 0000

high

EEH 00 0000 0000

low

FBH 00 0000 0000

high

FAH 00 0000 0000

low

FDH 00 0000 0000

high

FCH 00 0000 0000

low

FFH 00 0000 0000

high

FEH 00 0000 0000

low

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address B7 B6 B5 B4 B3 B2 B1 B0

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

CIN1A

/KB4

INT1 INT0/

CIN1B

/KB3

SDA

MISO MOSI OCD ICB

KBIF 00

_SEL

CIN2A

/KB2

T0/SCL RXD TXD

CIN2B

/KB1

CMP2

/KB0

[1]

Philips Semiconductors

xxxx xx00

[1]

P89LPC932A1 User manual

[1]

UM10109

[1]

1111 1111

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User manual Rev. 02 — 23 May 2005 17 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

P3M1Port3 output mode1B1H------(P3M1.1)(P3M1.0)03

P3M2Port3 output mode2B2H------(P3M2.1)(P3M2.0)00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000

PCONA Power control register A B5H RTCPD DEEPD VCPD - I2PD SPPD SPD CCUPD 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register

RTCL Real-time clock register

SADDR Serial port address

SADEN Serial port address enable B9H 00 0000 0000

SBUF Serial Port data buffer

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address D7 D6 D5 D4 D3 D2 D1 D0

D2H 00

high

D3H 00

low

A9H 00 0000 0000

register

99H xx xxxx xxxx

register

MSB LSB Hex Binary

[1]

[1][6]

[6]

Philips Semiconductors

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000

xxxx xx11

xxxx xx00

0000 0000

[3]

011x xx00

0000 0000

P89LPC932A1 User manual

UM10109

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User manual Rev. 02 — 23 May 2005 18 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

SSTAT Serial port extended status

SP Stack pointer 81H 07 0000 0111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

SPSTAT SPI status register E1H SPIF WCOL - - ----0000xxxxxx

SPDAT SPI data register E3H 00 0000 0000

TAMOD Timer 0 and 1 auxiliary

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

TCR20* CCU control register 0 C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000

TCR21 CCU control register 1 F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0 00 0xxx 0000

TH0 Timer 0 high 8CH 00 0000 0000

TH1 Timer 1 high 8DH 00 0000 0000

TH2 CCU timer high CDH 00 0000 0000

TICR2 CCU interrupt control

TIFR2 CCU interrupt flag register E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A 00 0000 0x00

TISE2 CCU interrupt status

TL0 Timer 0 low 8AH 00 0000 0000

TL1 Timer 1 low 8BH 00 0000 0000

TL2 CCU timer low CCH 00 0000 0000

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T

TOR2H CCU reload register high CFH 00 0000 0000

TOR2L CCU reload register low CEH 00 0000 0000

TPCR2H Prescaler control register

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addr.

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000

register

8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0

mode

Bit address 8F 8E 8D 8C 8B 8A 89 88

C9H TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A - TICIE2B TICIE2A 00 0000 0x00

register

DEH-----ENCINT.

encode register

CBH------TPCR2H.

high

…continued

Bit functions and addresses Reset value

MSB LSB Hex Binary

ENCINT.1ENCINT.000 xxxx x000

2

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000

TPCR2H.000 xxxx xx00

1

Philips Semiconductors

P89LPC932A1 User manual

UM10109

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User manual Rev. 02 — 23 May 2005 19 of 133

Table 2: P89LPC932A1 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TPCR2L Prescaler control register

TRIM Internal oscillator trim

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

WDL Watchdog load C1H FF 1111 1111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

[1] All por ts are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

CAH TPCR2L.7TPCR2L.6TPCR2L.5TPCR2L.4TPCR2L.3TPCR2L.2TPCR2L.1TPCR2L.000 0000 0000

low

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

register

xx110000.

Other resets will not affect WDTOF.

…continued

Bit functions and addresses Reset value

MSB LSB Hex Binary

[5] [6]

[4] [6]

Philips Semiconductors

P89LPC932A1 User manual

UM10109

Philips Semiconductors

1.5 Memory organization

FF00h

FFEFh

1FFFh

1E00h

1C00h 1BFFh

1800h 17FFh

1400h 13FFh

1000h

0FFFh

0C00h 0BFFh

0800h 07FFh

0400h 03FFh

0000h

IAP entry-

points

ISP CODE

(512B)*

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

read-protected

IAP calls only

IDATA routines

entry points for:

-51 ASM. code

-C code

ISP serial loader

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.*

flexible choices:

-as supplied (UART)

-Philips libraries*

-user-defined

FFEFh

FF1Fh

FF00h

1FFFh

1E00h

entry points

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

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P89LPC932A1 User manual

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

002aaa948

Fig 5. P89LPC932A1 memory map.

The various P89LPC932A1 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC932A1 has 8 kB of on-chip Code memory.

Table 3: Data RAM arrangement

Type Data RAM Size (bytes)

DATA Directly and indirectly addressable memory 128

IDATA Indirectly addressable memory 256

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Philips Semiconductors

2. Clocks

2.1 Enhanced CPU

The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC932A1 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 6

Section 2.8 “

OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is

P89LPC932A1 User manual

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

⁄2.

UM10109

and

is defined as the

osc

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC932A1 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

2.2.2 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

2.2.3 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.2.4 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this configuration.

2.3 Clock output

The P89LPC932A1 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC932A1. This output is enabled by the ENCLK bit in the TRIM register

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P89LPC932A1 User manual

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

UM10109

2.4 On-chip RC oscillator option

The P89LPC932A1 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ± 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC932A1 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

Table 4: On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

Table 5: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset,

1TRIM.1

2TRIM.2

3TRIM.3

4TRIM.4

5TRIM.5

6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

being used.

fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle. The original P89LPC932 required a reset

cycle in order to switch between clock sources.

⁄2 is output on the XTAL2 pin provided the crystal oscillator is not

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until V

has reached its specified

DD

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Philips Semiconductors

level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low

Fig 6. Using the crystal oscillator.

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P89LPC932A1 User manual

quartz crystal or

ceramic resonator

P89LPC932A1

XTAL1

(1)

XTAL2

002aab008

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

frequency crystals (see text).

XTAL1

XTAL2

(7.3728 MHz ±1 %)

(400 kHz )

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

RC

OSCILLATOR

WATCHDOG

OSCILLATOR

+20 %

−30 %

RCCLK

TIMER 0 AND

TIMER 1

OSCCLK

I2C-BUS

PCLK

DIVM

SPI

CCLK

PCLK

÷2

UART

(P89LPC932A1)

Fig 7. Block diagram of oscillator control.

2.7 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC932A1 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 µs to 100 µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

RTC

CPU

WDT

32 × PLL

CCU

002aaa891

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2.8 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

UM10109

P89LPC932A1 User manual

2.9 Low power select

3. Interrupts

osc

).

/ (2N)

osc

to f

osc

/510.

CCLK frequency = f

Where: f

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f (for N = 0, CCLK = f

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

The P89LPC932A1 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

is the frequency of OSCCLK, N is the value of DIVM.

osc

The P89LPC932A1 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC932A1’s 15 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level. Ta bl e 7 addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake-up the CPU from a Power-down mode.

summarizes the interrupt sources, flag bits, vector

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Philips Semiconductors

3.1 Interrupt priority structure

Table 6: Interrupt priority level

Priority bits

IPxH IPx Interrupt priority level

0 0 Level 0 (lowest priority)

01Level 1

10Level 2

11Level 3

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Tab le 7

The P89LPC932A1 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn triggered. In this mode if consecutive samples of the INTn cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

UM10109

P89LPC932A1 User manual

.

pin. If ITn = 1, external interrupt n is edge

pin show a high level in one

Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC932A1 is put into Power-down mode or Idle mode, the interrupt occurrence will cause the processor to wake-up and resume operation. Refer to Section 5.3 “

reduction modes” for details.

3.2 External Interrupt pin glitch suppression

Most of the P89LPC932A1 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0 suppression circuits. Therefore, INT1

/P1.3 and SCL/T0/P1.2 do not have the glitch

has glitch suppression while INT0 does not.

Power

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P89LPC932A1 User manual

Table 7: Summary of interrupts

Description Interrupt flag

bit(s)

External interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes

Timer 0 interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No

External interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 7 Yes

Timer 1 interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 10 No

Serial port Tx and Rx TI and RI 0023h ES/ESR (IEN0.4) IP0H.4, IP0.4 13 No

Serial port Rx RI

Brownout detect BOF 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes

Watchdog timer/Real-time clock

2

C interrupt SI 0033h EI2C (IEN1.0) IP0H.0, IP0.0 5 No

I

KBI interrupt KBIF 003Bh EKBI (IEN1.1) IP0H.0, IP0.0 8 Yes

Comparators 1 and 2 interrupts

SPI interrupt SPIF 004Bh ESPI (IEN1.3) IP1H.3, IP1.3 14 No

Capture/Compare Unit 005Bh ECCU(IEN1.4) IP1H.4, IP1.4 6 No

Serial port Tx TI 006Bh EST (IEN1.6) IP0H.0, IP0.0 12 No

Data EEPROM ADCI1, BNDI1 0073h EAD (IEN1.7) IP1H.7, IP1.7 15 (lowest) No

WDOVF/RTCF 0053h EWDRT (IEN0.6) IP0H.6, IP0.6 3 Yes

CMF1/CMF2 0043h EC (IEN1.2) IP0H.0, IP0.0 11 Yes

Vector address

Interrupt enable bit(s)

Interrupt priority

UM10109

Arbitration ranking

Powerdown wake-up

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RTCF ERTC

(RTCCON.1)

WDOVF

any CCU interrupt (1)

IE0

EX0

IE1

EX1

BOPD

EBO

KBIF EKBI

EWDRT

CMF2 CMF1

EC

EA (IE0.7)

TF0 ET0

TF1 ET1

TI & RI/RI

ES/ESR

EST

EI2C

SPIF ESPI

ECCU

EEIF EIEE

UM10109

P89LPC932A1 User manual

wake-up (if in power-down)

TI

SI

interrupt to CPU

002aaa892

(1) See Section 9 “

Capture/Compare Unit (CCU)”.

Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources.

4. I/O ports

The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1, and 2 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Ta bl e 8

Table 8: Number of I/O pins available

Clock source Reset option Number of I/O

On-chip oscillator or watchdog oscillator

External clock input No external reset (except during power up) 25

Low/medium/high speed oscillator (external crystal or resonator)

[1] Required for operation above 12 MHz.

No external reset (except during power up) 26

External RST

pin supported 25

pin supported

No external reset (except during power up) 24

External RST

pin supported

).

pins

[1]

24

23

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Philips Semiconductors

4.1 Port configurations

All but three I/O port pins on the P89LPC932A1 may be configured by software to one of four types on a pin-by-pin basis, as shown in Ta b le 9 (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

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P89LPC932A1 User manual

. These are: quasi-bidirectional

P1.5 (RST

P1.2 (SCL/T0) and P1.3 (SDA/INT0 open drain.

Table 9: Port output configuration settings

PxM1.y PxM2.y Port output mode

0 0 Quasi-bidirectional

0 1 Push-pull

1 0 Input only (high-impedance)

1 1 Open drain

) can only be an input and cannot be configured.

) may only be configured to be either input-only or

4.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

The quasi-bidirectional port configuration is shown in Figure 9

Although the P89LPC932A1 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit

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causing extra power consumption. Therefore, applying 5 V to pins

DD

.

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(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

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P89LPC932A1 User manual

V

DD

port latch

data

Fig 9. Quasi-bidirectional output.

4.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

DD

2 CPU

CLOCK DELAY

PP P

input

data

very

weak

weakstrong

glitch rejection

PORT

002aaa914

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open drain port configuration is shown in Figure 10

.

An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications.

PORT

port latch

data

input data

glitch rejection

Fig 10. Open drain output.

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002aaa915

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4.4 Input-only configuration

The input port configuration is shown in Figure 11. It is a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

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P89LPC932A1 User manual

input

data

glitch rejection

Fig 11. Input only.

PORT

002aaa916

4.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 12

A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter specifications).

V

DD

P

.

strong

PORT

port latch

data

input data

Fig 12. Push-pull output.

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N

glitch rejection

002aaa917