Philips UM10107 User Manual

UM10107

P89LPC915/916/917 8-bit microcontrollers with two-clock 80C51 core and 8-bit A/D

Rev. 01 — 15 July 2004 User manual

Document information

Info Content Keywords P89LPC915, P89LPC916, P89LPC917 Abstract Technical information for the P89LPC915, P89LPC916, and P89LPC917

devices.

Philips Semiconductors

Revision history

Rev Date Description

01 20040715 Initial version (9397 750 13316).

UM10107

P89LPC915/916/917 User manual

Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual Rev. 01 — 15 July 2004 2 of 125

Philips Semiconductors

1. Introduction

The P89LPC915/916/917 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC915/916/917 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC915/916/917 in order to reduce component count, board space, and system cost.

1.1 Logic symbols

VDDV

UM10107

P89LPC915/916/917 User manual

SS

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5

DAC1

AD10 AD11 AD12 AD13

CLKIN

Fig 1. P89LPC915 logic symbol.

KBI1 KBI2 KBI3 KBI4 KBI5

DAC1

AD10 AD11 AD12 AD13

CLKIN

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CIN2B CIN2A CIN1B CIN1A

CMPREF

PORT 0

P89LPC915

002aaa828

V

DD

SS

P89LPC916

002aaa829

PORT 1

PORT 2

TxD RxD T0 INT0 INT1 RST

TxD RxD T0 INT0

RST

MOSI MISO SS SPICLK

SCL SDA

Fig 2. P89LPC916 logic symbol.

User manual Rev. 01 — 15 July 2004 3 of 125

Philips Semiconductors

C

1

UM10107

P89LPC915/916/917 User manual

V

DD

SS

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI7

DAC1

AD10 AD11 AD12 AD13

CLKIN

CLKOUT

Fig 3. P89LPC917 logic symbol.

1.2 Product comparison

Table 1 highlights the differences between these devices. For a complete list of device

features, please refer to the P89LPC915/916/917 data sheet.

Table 1: Product comparison

Type number

P89LPC915 X - - - X 6 P89LPC916 - X - - - 5 P89LPC917 X - X X X 7

1.3 Pin Configuration

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

T1

Comp 2 output

PORT 0

P89LPC917

002aaa830

SPI T1 PWM

output

TxD

PORT 1

PORT 2

RxD T0 INT0 INT1 RST

SCL SDA

CLKOUT INT1 KBI

002aaa825

14 13 12 11

P0.5/CMPREF/KBI5/CLKIN

10

DD

9

IN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

KBI0/CMP2/P0.0 P0.3/CIN1B/KBI3/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC

INT1/P1.4 V

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

1 2 3

V

SS

LPC915

4 5 6 7 8

Fig 4. P89LPC915 TSSOP14 pin configuration.

User manual Rev. 01 — 15 July 2004 4 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

CIN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

SS/P2.4 P0.3/CIN1B/KB13/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC1

MISO/P2.3 V

MOSI/P2.2 P2.5/SPICLK

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

1

2

3

V

4

SS

LPC916

5

6

7

8

002aaa826

Fig 5. P89LPC916 TSSOP16 pin configuration.

CIN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

KBI0/CMP2/P0.0 P0.3/CIN1B/KB13/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC1

MOSI/P2.2 V

INT1/P1.4 P0.7/T1/KBI7/CLKOUT

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

1

2

3

V

4

SS

LPC917

5

6

7

8

002aaa827

Fig 6. P89LPC917 TSSOP pin configuration.

16

15

14

13

P0.5/CMPREF/KBI5/CLKIN

12

DD

11

10

9

16

15

14

13

P0.5/CMPREF/KBI5/CLKIN

12

DD

11

10

9

User manual Rev. 01 — 15 July 2004 5 of 125

Philips Semiconductors

Ta ble 2: P89LPC915 pin description

Symbol Pin Type Description

P0.0 to P0.5 1, 2, 11,

12, 13, 14

2 I/O P0.0 — Port 0 bit 0.

1 I/O P0.1 — Port 0 bit 1.

14 I/O P0.2 — Port 0 bit 2.

13 I/O P0.3 — Port 0 bit 3.

12 I/O P0.4 — Port 0 bit 4.

11 I/O P0.5 — Port 0 bit 5.

I/O Port 0: Port 0 is a 6-bit I/O port with user-configurable outputs. During reset Port 0

latches are configured in the input only mode with the internal pull-up disabled. The operation of Port0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock i nput.

UM10107

P89LPC915/916/917 User manual

for details.

User manual Rev. 01 — 15 July 2004 6 of 125

Philips Semiconductors

Ta ble 2: P89LPC915 pin description

Symbol Pin Type Description

P1.0 to P1.5 3, 5, 6, 7,

8, 9

9 I/O P1.0 — Port 1 bit 0

8 I/O P1.1 — Port 1 bit 0

7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

6 I/O P1.3 — Port 1 bit 2. (Open drain when used as an output.)

5 I/O P1.4 — Port 1 bit 2.

3IP1.5 — Port 1 bit 5. (Input only.)

V

SS

V

DD

4IGround: 0 V reference. 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle

I/O (P1.2); I(P1.5)

O TxD — Serial port transmitter data.

I RxD — Serial port receiver dat a .

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output. I/O SCL — I

I/O INT0 I/O SDA — I

I/O INT1

I RST

Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the inputs and outputs depends upon the port configuration selected. Refer to Section 5.1 input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

2

— External interrupt 0 input.

2

— External interrupt 1input.

— External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

UM10107

P89LPC915/916/917 User manual

for details. P1.2 is an o pen drai n whe n used as an outpu t. P1. 5 is

C serial clock input/output.

C serial data input/output.

User manual Rev. 01 — 15 July 2004 7 of 125

Philips Semiconductors

Ta ble 3: P89LPC916 pin description

Symbol Pin Type Description

P0.1 to P0.5 1, 13, 14,

15, 16

1 I/O P0.1 — Port 0 bit 1.

16 I/O P0.2 — Port 0 bit 2.

15 I/O P0.3 — Port 0 bit 3.

14 I/O P0.4 — Port 0 bit 4.

13 I/O P0.5 — Port 0 bit 5.

I/O Port 0: Port 0 is a 5-bit I/O port with user-configurable outputs. During reset Port 0

latches are configured in the input only mode with the internal pull-up disabled. The operation of Port0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock i nput.

UM10107

P89LPC915/916/917 User manual

for details.

User manual Rev. 01 — 15 July 2004 8 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

Ta ble 3: P89LPC916 pin description

Symbol Pin Type Description

P1.0 to P1.3, P1.5

P2.2 to P2.5 2, 5, 6, 11 I/O Port 2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset

V

SS

V

DD

3, 7, 8, 9, 10I/O

(P1.2); I(P1.5)

10 I/O P1.0 — Port 1 bit 0

O TxD — Serial port transmitter data.

9 I/O P1.1 — Port 1 bit 0

I RxD — Serial port receiver dat a .

8 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output. I/O SCL — I

7 I/O P1.3 — Port 1 bit 2. (Open drain when used as an output.)

I/O INT0 I/O SDA — I

3IP1.5 — Port 1 bit 5. (Input only.)

I RST

6 I/O P2.2 — Port 2 bit 2.

O MOSI — SPI master out slave in. When configured as a master this pin is an output.

5 I/O P2.3 — Port 2 bit 3.

I MISO — SPI master in slave out. When configured as a master this pin is an input.

2 I/O P2.4 — Port 2 bit 4.

I/O SS

11 I/O P2.5 — Port 2 bit 5.

I/O SPICLK — When configured as a master this pin is an output. When configured as a

4IGround: 0 V reference. 12 I Power Supply: This is the power supply voltage for normal operation as well as Idle

Port 1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the P1. 2 input and output s de pends upon the port c onf iguration selected. Refer to Section 5.1 input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

2

C serial clock input/output.

— External interrupt 0 input.

2

C serial data input/output.

— External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

Port 1 latches are configured in th e input only mode with the i nternal pull-up disabled. The operation of the P2 input and outputs depends upon the port configuration selected. Refer to Section 5.1

All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:

When configured as a slave, this pin is an input.

When configured as a slave, this pin is an output.

— SPI Slave select.

slave, this pin is an input.

and Power-down modes.

for details. P1.2 is an o pen drai n whe n used as an outpu t. P1. 5 is

for details.

User manual Rev. 01 — 15 July 2004 9 of 125

Philips Semiconductors

Ta ble 4: P89LPC917 pin description

Symbol Pin Type Description

P0.0 to P0.5, P0.7

1, 2, 11, 13, 14, 15, 16

2 I/O P0.0 — Port 0 bit 0.

1 I/O P0.1 — Port 0 bit 1.

16 I/O P0.2 — Port 0 bit 2.

15 I/O P0.3 — Port 0 bit 3.

14 I/O P0.4 — Port 0 bit 4.

13 I/O P0.5 — Port 0 bit 5.

11 I/O P0.7 — Port 0 bit 7.

I/O Port 0: Port 0 is a 7-bit I/O port with user-configurable outputs. During reset Port 0

latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input.

I T1 — Timer/counter 1 external count input, overflow output, or PWM output. I KBI7 — Keyboard input 7. I CLKOUT — Clock output.

UM10107

P89LPC915/916/917 User manual

for details.

User manual Rev. 01 — 15 July 2004 10 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

Ta ble 4: P89LPC917 pin description

Symbol Pin Type Description

P1.0 to P1.5 3, 6, 7, 8,

9, 10

10 I/O P1.0 — Port 1 bit 0.

9 I/O P1.1 — Port 1 bit 1.

8 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

7 I/O P1.3 — Port 1 bit 3. (Open drain when used as an output.)

6 I/O P1.4 — Port 1 bit 4.

3IP1.5 — Port 1 bit 5. (Input only.)

P2.2 5 I/O Port 2: Port 2.2 is a single-bit I/O port with a user-configurable output. During reset

V

SS

V

DD

4IGround: 0 V reference. 12 I Power Supply: This is the power supply v olt age fo r norma l ope ration as w ell as Id le

I/O (P1.0:4); I(P1.5)

O TxD — Serial port transmitter data.

I RxD — Serial port receiver data.

I/O T0 — Timer/counter 0 external count input, overflow, or PWM output. I/O SCL — I

I/O INT0 I/O SDA — I

I/O INT1

I RST

Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the outputs depends upon the port configuration selected. Refer to

Section 5.1

input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

functioning as a reset input a LOW on thi s pin reset s t he mi crocon trolle r, causing I /O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

the Port 2.2 latch is configured in the input only mode with the internal pull-up disabled. The operation of the output depends upon the port configuration selected. Refer to Section 5.1

This pin has a Schmitt triggered i nput.

and Power-down modes.

for details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is

2

C serial clock input/output.

— External interrupt 0 input.

2

C serial data input/output.

— External interrupt 1input.

— External Reset input during power-on or if selected via UCFG1. When

and details.

User manual Rev. 01 — 15 July 2004 11 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

external

clock input

P89LPC915

2 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

UART

I2C

ADC1/DAC1

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

Fig 7. P89LPC915 block diagram.

002aaa822

User manual Rev. 01 — 15 July 2004 12 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

external

clock

input

P89LPC916

2 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

UART

I2C

ADC1/DAC1

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

Fig 8. P89LPC916 block diagram.

002aaa823

User manual Rev. 01 — 15 July 2004 13 of 125

Philips Semiconductors

UM10107

P89LPC915/916/917 User manual

external

clock input

CLKOUT

P89LPC917

2 kB

CODE FLASH

256-BYTE DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET,

BROWNOUT RESET)

UART

I2C

ADC1/DAC1

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

002aaa824

Fig 9. P89LPC917 block diagram.

User manual Rev. 01 — 15 July 2004 14 of 125

Philips Semiconductors

1.4 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specif ied, must be written with ‘0’, but can return any value

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

UM10107

P89LPC915/916/917 User manual

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

User manual Rev. 01 — 15 July 2004 15 of 125

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 16 of 125

Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000 ADMODAA/D mode registerA C0HBNDI1BURST1SCC1SCAN1----0000000000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x0000 AD1BH A/D_1 boundary high register C4H FF 11111111 AD1BL A/D_1 boundary low register BCH 00 00000000 AD1DAT0 A/D_1 data register 0 D5H 00 00000000 AD1DAT1 A/D_1 data register 1 D6H 00 00000000 AD1DAT2 A/D_1 data register 2 D7H 00 00000000 AD1DAT3 A/D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR - ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000 BRGR0 BRGR1 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00 00000000

DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H - - - - - - 00 00000000 FMADRL Program Flash address low E6H 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit addressE7E6E5E4E3E2E1E0

Bit addressF7F6F5F4F3F2F1F0

[2]

Baud rate generator rate low BEH 00 00000000

[2]

Baud rate generator rate high BFH 00 00000000

95H 00 00000000

control

MSB LSB Hex Binary

[2] [1] [1]

xxxxxx00 xx000000 xx000000

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 17 of 125

Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I2C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - - EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00 IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - - PC PKBI PI2C 00 IP1H Interrupt priority 1 high F7H PADH PSTH - - - PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit addressDFDEDDDCDBDAD9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

2

C data register DAH

DDH 00 00000000

duty cycle register high

DCH 00 00000000

duty cycle register low

2

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

register

Bit address8786858483828180

MSB LSB Hex Binary

0

[1]

PT1H PX1H PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 18 of 125

Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - - RST

P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD - SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register high D2H 00 RTCL Real-time clock register low D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111 TAMODTimer0 and 1 auxiliary mode8FH-------T0M200xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000 TH0 Timer 0 high 8CH 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

/KBI5

CIN1A

/KBI4

CIN1B

/KBI3

INT1 INT0/

SDA

CIN2A

/KBI2

CIN2B

/KBI1

CMP2

/KBI0

T0/SCL RXD TXD

[1]

[1][6] [6] [6]

[1]

11111111 00000000 11x1xx11 00x0xx00

00000000

[3]

011xxx00 00000000 00000000

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 19 of 125

Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TH1 Timer 1 high 8DH 00 00000000 TL0 Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

value is xx110000.

resets will not affect WDTOF.

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

Philips Semiconductors

[5] [6] [4] [6]

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 20 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000 ADMODAA/D mode registerA C0HBNDI1BURST1SCC1SCAN1----0000000000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x0000 AD1BH A/D_1 boundary HIGH

AD1BL A/D_1 boundary LOW

AD1DAT0 A/D_1 data register 0 D5H 00 00000000 AD1DAT1 A/D_1 data register 1 D6H 00 00000000 AD1DAT2 A/D_1 data register 2 D7H 00 00000000 AD1DAT3 A/D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR - ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000 BRGR0

BRGR1

BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 xx000000 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H - - - - - - 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

register

[2]

Baud rate generator rate LOW

[2]

Baud rate generator rate HIGH

control

addr.

Bit addressE7E6E5E4E3E2E1E0

C4H FF 11111111

BCH 00 00000000

Bit addressF7F6F5F4F3F2F1F0

BEH 00 00000000

BFH 00 00000000

95H 00 00000000

MSB LSB Hex Binary

[2] [1]

xxxxxx00 xx000000

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 21 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 PX0 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - PSPI PC PKBI PI2C 00 IP1H Interrupt priority 1 HIGH F7H PADH PSTH - - PSPIH PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

2

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit addressDFDEDDDCDBDAD9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

2

C data register DAH

DDH 00 00000000

duty cycle register HIGH

DCH 00 00000000

duty cycle register LOW

2

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

register

MSB LSB Hex Binary

0

[1]

PT1H - PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 22 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - - RST

P2* Port 2 A0H - - SPICLK SS P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) - FF P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) - 00 P1M1 Port 1 output mode 1 91H - - - - (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - - (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 P2M1 Port 2 output mode 1 A4H - - (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) - - FF P2M2 Port 2 output mode 2 A5H - - (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) - - 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address8786858483828180

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

MSB LSB Hex Binary

/KBI5

CIN1A

/KBI4

- INT0/

CIN1B

/KBI3

CIN2A

/KBI2

CIN2B

/KBI1

T0/SCL RXD TXD

SDA

MISO MOSI - -

-

[1]

[1][6] [6] [6]

[1]

11111111 00000000 11x1xx11 00x0xx00 11111111 00000000

00000000

[3]

011xxx00 00000000 00000000

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 23 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

SP Stack pointer 81H 07 00000111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI status register E1H SPIF WCOL - -----0000xxxxxx SPDAT SPI data register E3H 00 00000000 TAMODTimer0 and 1 auxiliary mode8FH-------T0M200xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - - IE0 IT0 00 00000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

[5] [6] [4] [6]

Philips Semiconductors

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 24 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000 ADMODAA/D mode registerA C0HBNDI1BURST1SCC1SCAN1----0000000000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x0000 AD1BH A/D_1 boundary HIGH

AD1BL A/D_1 boundary LOW

AD1DAT0 A/D_1 data register 0 D5H 00 00000000 AD1DAT1 A/D_1 data register 1 D6H 00 00000000 AD1DAT2 A/D_1 data register 2 D7H 00 00000000 AD1DAT3 A/D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000 BRGR0

BRGR1

BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000

FMADRH Program Flash address HIGH E7H - - - - - - 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

register

[2]

Baud rate generator rate LOW

[2]

Baud rate generator rate HIGH

control

addr.

Bit addressE7E6E5E4E3E2E1E0

C4H FF 11111111

BCH 00 00000000

Bit addressF7F6F5F4F3F2F1F0

BEH 00 00000000

BFH 00 00000000

95H 00 00000000

MSB LSB Hex Binary

[2] [1] [1]

xxxxxx00 xx000000 xx000000

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 25 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - - EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - - PC PKBI PI2C 00 IP1H Interrupt priority 1 HIGH F7H PADH PSTH - - - PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

2

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit addressDFDEDDDCDBDAD9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

2

C data register DAH

DDH 00 00000000

duty cycle register HIGH

DCH 00 00000000

duty cycle register LOW

2

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

register

MSB LSB Hex Binary

0

[1]

PT1H PX1H PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

Philips Semiconductors

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 26 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H T1/KBI7/

P1* Port 1 90H - - RST

P0M1 Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD - SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address8786858483828180

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

-CMPREF

CLKOUT

/KBI5

CIN1A

/KBI4

CIN1B

/KBI3

INT1 INT0/

SDA

CIN2A

/KBI2

CIN2B

/KBI1

CMP2

/KBI0

T0/SCL RXD TXD

[1]

[1][6] [6] [6]

Philips Semiconductors

[1]

11111111 00000000 11x1xx11 00x0xx00

00000000

[3]

011xxx00 00000000 00000000

P89LPC915/916/917 User manual

UM10107

xxxxxxxxxxxxxxxx xxxxx xxxxxxx xxxxxxxxxxx xxxxxxxx xxxx xxx x x x xxxxxxxx xxxxxxxxxxxxxx xxxxxxxx xxx xxxxxxxxxxxx xxxx xx xx xxxx x

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 15 July 2004 27 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

value is xx110000.

resets will not affect WDTOF.

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

Philips Semiconductors

[5] [6] [4] [6]

P89LPC915/916/917 User manual

UM10107

Philips Semiconductors

3

1.5 Memory organization

07FFh

0700h

06FFh

0600h

05FFh

0500h

04FFh

0400h

03FFh

0300h

02FFh

0200h

01FFh

0100h

00FFh

000h

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

2 kB Flash code

memory space

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

UM10107

P89LPC915/916/917 User manual

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

FFh

80h

7Fh

00h

002aaa91

Fig 10. P89LPC915/916/917 memory map.

The various P89LPC915/916/917 memory spaces are as follows: DAT A — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or

indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDAT A — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.

Table 8: Data RAM arrangement

Type Data RAM Size (bytes)

DA TA Directly and indirectly addressab le memo ry 128 IDATA Indirectly addressable memory 256

User manual Rev. 01 — 15 July 2004 28 of 125

Philips Semiconductors

2. Clocks

2.1 Enhanced CPU

The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definit ions

The P89LPC915/916/917 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of three clock

sources and can also be optionally divided to a slower frequency (see Figure 11

Section 2.8 “

OSCCLK frequency. CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is

P89LPC915/916/917 User manual

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

e

.

2

UM10107

and

is defined as the

osc

The P89LPC915/916/917 provides user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, or an external clock source.

2.3 Clock output (P89LPC917)

The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin. This allows external devices to synchronize to the P89LPC917. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

1

e

that of the CCLK. If the clock output is not needed

2

2.4 On-chip RC oscillator option

The P89LPC915/916/917 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, r 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC915/916/917 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

User manual Rev. 01 — 15 July 2004 29 of 125

Philips Semiconductors

Table 9: On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

Table 10: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During 1TRIM.1 2TRIM.2 3TRIM.3 4TRIM.4 5TRIM.5 6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK)

UM10107

P89LPC915/916/917 User manual

reset, these bits are loaded wi th a stored factory calibra tion value. When w riting to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

e

is output on the XTAL2 pin provide d the cryst al osci llator is no t

being used.

2

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the P0.5 pin. The rate may be from 0 Hz up to 12 MHz.

RTCS1:0

CLKIN

RC

OSCILLATOR

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

RCCLK

XCLK

OSCCLK

DIVM

PCLK

RCCLK

CCLK

÷2

PCLK

peripheral clock

RTC

CPU

ADC1/DAC1

WDT

CLKOUT

BAUD RATE

GENERATOR

UART

TIMERS 1 AND 0

I2C

SPI

(P89LPC916)

002aaa831

Fig 11. Block diagram of oscillator control.

User manual Rev. 01 — 15 July 2004 30 of 125