Philips UM10107 User Manual

UM10107

P89LPC915/916/917

8-bit microcontrollers with two-clock 80C51 core and 8-bit A/D

Rev. 01 — 15 July 2004	User manual

Document information

Info	Content
Keywords	P89LPC915, P89LPC916, P89LPC917

Abstract	Technical information for the P89LPC915, P89LPC916, and P89LPC917
	devices.

Philips Semiconductors				UM10107
				P89LPC915/916/917 User manual
Revision history

Rev		Date	Description

01	20040715		Initial version (9397 750 13316).

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

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1. Introduction

The P89LPC915/916/917 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC915/916/917 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC915/916/917 in order to reduce component count, board space, and system cost.

1.1 Logic symbols

VDD VSS

		KBI0	CMP2

	AD10	KBI1	CIN2B

	AD11	KBI2	CIN2A

	AD12	KBI3	CIN1B

DAC1	AD13	KBI4	CIN1A

	CLKIN	KBI5	CMPREF

Fig 1. P89LPC915 logic symbol.

PORT 0

P89LPC915

002aaa828

PORT 1

TxD

RxD

T0		SCL

INT0 SDA

INT1

RST

VDD VSS

	AD10	KBI1	CIN2B

	AD11	KBI2	CIN2A

	AD12	KBI3	CIN1B

DAC1	AD13	KBI4	CIN1A

	CLKIN	KBI5	CMPREF

PORT 0

1PORT P89LPC916

2PORT

TxD

RxD

T0 SCL

INT0 SDA

RST

MOSI

MISO

SPICLK

002aaa829

Fig 2. P89LPC916 logic symbol.

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			KBI0	CMP2

		AD10	KBI1	CIN2B

		AD11	KBI2	CIN2A

		AD12	KBI3	CIN1B

DAC1		AD13	KBI4	CIN1A

		CLKIN	KBI5	CMPREF

	CLKOUT		KBI7	T1

Fig 3. P89LPC917 logic symbol.

PORT 0

VDD VSS

P89LPC917

002aaa830

		TxD
		TxD
		RxD	SCL
		RxD
	1	T0
	1	T0
	PORT
	PORT	INT0	SDA
		INT0	SDA
		INT1
		INT1
		RST
		RST
PORT 2

1.2 Product comparison

Table 1 highlights the differences between these devices. For a complete list of device features, please refer to the P89LPC915/916/917 data sheet.

Table 1: Product comparison


Type	Comp 2	SPI	T1 PWM	CLKOUT	INT1	KBI
number	output		output
P89LPC915	X	-	-	-	X	6

P89LPC916	-	X	-	-	-	5

P89LPC917	X	-	X	X	X	7

1.3 Pin Configuration

CIN2B/KBI1/AD10/P0.1			1		14	P0.2/CIN2A/KBI2/AD11

KBI0/CMP2/P0.0			2		13	P0.3/CIN1B/KBI3/AD12

	RST/P1.5		3		12	P0.4/CIN1A/KBI4/AD13/DAC1
				LPC915
		VSS	4	LPC915	11	P0.5/CMPREF/KBI5/CLKIN

INT1/P1.4			5		10	VDD

SDA/INT0/P1.3			6		9	P1.0/TXD
SCL/T0/P1.2						P1.1/RXD
SCL/T0/P1.2			7		8	P1.1/RXD
				002aaa825

Fig 4. P89LPC915 TSSOP14 pin configuration.

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CIN2B/KBI1/AD10/P0.1				1		16	P0.2/CIN2A/KBI2/AD11
							P0.3/CIN1B/KB13/AD12
		SS/P2.4		2		15	P0.3/CIN1B/KB13/AD12

	RST/P1.5			3		14	P0.4/CIN1A/KBI4/AD13/DAC1

			VSS	4	LPC916	13	P0.5/CMPREF/KBI5/CLKIN
MISO/P2.3					LPC916		VDD
MISO/P2.3				5		12	VDD
MOSI/P2.2							P2.5/SPICLK
MOSI/P2.2				6		11	P2.5/SPICLK

SDA/INT0/P1.3				7		10	P1.0/TXD

SCL/T0/P1.2				8		9	P1.1/RXD
					002aaa826

Fig 5. P89LPC916 TSSOP16 pin configuration.

CIN2B/KBI1/AD10/P0.1			1		16	P0.2/CIN2A/KBI2/AD11
KBI0/CMP2/P0.0						P0.3/CIN1B/KB13/AD12
KBI0/CMP2/P0.0			2		15	P0.3/CIN1B/KB13/AD12

	RST/P1.5		3		14	P0.4/CIN1A/KBI4/AD13/DAC1
		VSS
		VSS	4	LPC917	13	P0.5/CMPREF/KBI5/CLKIN
MOSI/P2.2				LPC917		VDD
MOSI/P2.2			5		12	VDD

INT1/P1.4			6		11	P0.7/T1/KBI7/CLKOUT
						P1.0/TXD
SDA/INT0/P1.3			7		10	P1.0/TXD

SCL/T0/P1.2			8		9	P1.1/RXD
				002aaa827

Fig 6. P89LPC917 TSSOP pin configuration.

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Table 2:	P89LPC915 pin description

Symbol		Pin	Type	Description
P0.0 to P0.5 1, 2, 11,			I/O	Port 0: Port 0 is a 6-bit I/O port with user-configurable outputs. During reset Port 0
	12, 13, 14			latches are configured in the input only mode with the internal pull-up disabled. The
				operation of Port 0 pins as inputs and outputs depends upon the port configuration
				selected. Each port pin is configured independently. Refer to Section 5.1 for details.
				The Keypad Interrupt feature operates with Port 0 pins.
				All pins have Schmitt triggered inputs.
				Port 0 also provides various special functions as described below:

	2		I/O	P0.0 — Port 0 bit 0.

			I	CMP2 — Comparator 2 output.

			I	KBI0 — Keyboard input 0.

	1		I/O	P0.1 — Port 0 bit 1.

			I	CIN2B — Comparator 2 positive input B.

			I	KBI1 — Keyboard input 1.

			I	AD10 — A/D channel 1, input 0

	14		I/O	P0.2 — Port 0 bit 2.

			I	CIN2A — Comparator 2 positive input A.

			I	KBI2 — Keyboard input 2.

			I	AD11 — A/D channel 1, input 1

	13		I/O	P0.3 — Port 0 bit 3.

			I	CIN1B — Comparator 1 positive input B.

			I	KBI3 — Keyboard input 3.

			I	AD12 — A/D channel 1, input 2.

	12		I/O	P0.4 — Port 0 bit 4.

			I	CIN1A — Comparator 1 positive input A.

			I	KBI4 — Keyboard input 4.

			I	AD13 — A/D channel 1, input 3.

			O	DAC1 — Digital to analog converter 1 output.

	11		I/O	P0.5 — Port 0 bit 5.

			I	CMPREF — Comparator reference (negative) input.

			I	KBI5 — Keyboard input 5.

			I	CLKIN — External clock input.

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Table 2:	P89LPC915 pin description

Symbol		Pin	Type	Description
P1.0 to P1.5 3, 5, 6, 7,			I/O	Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1
	8, 9		(P1.2);	latches are configured in the input only mode with the internal pull-up disabled. The
			I (P1.5)	operation of the inputs and outputs depends upon the port configuration selected.
				Refer to Section 5.1 for details. P1.2 is an open drain when used as an output. P1.5 is
				input only.
				All pins have Schmitt triggered inputs.
				Port 1 also provides various special functions as described below:

	9		I/O	P1.0 — Port 1 bit 0

			O	TxD — Serial port transmitter data.

	8		I/O	P1.1 — Port 1 bit 0

			I	RxD — Serial port receiver data.

7I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output.

	I/O	SCL — I2C serial clock input/output.
6	I/O	P1.3	— Port 1 bit 2.	(Open drain when used as an output.)

	I/O	INT0 — External interrupt 0 input.

	I/O	SDA — I2C serial data input/output.
5	I/O	P1.4	— Port 1 bit 2.

	I/O	INT1 — External interrupt 1input.

3	I	P1.5	— Port 1 bit 5.	(Input only.)

IRST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

VSS	4	I	Ground: 0 V reference.
VDD	10	I	Power Supply: This is the power supply voltage for normal operation as well as Idle
			and Power-down modes.

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Table 3:	P89LPC916 pin description

Symbol		Pin	Type	Description
P0.1 to P0.5 1, 13, 14,			I/O	Port 0: Port 0 is a 5-bit I/O port with user-configurable outputs. During reset Port 0
	15, 16			latches are configured in the input only mode with the internal pull-up disabled. The
				operation of Port 0 pins as inputs and outputs depends upon the port configuration
				selected. Each port pin is configured independently. Refer to Section 5.1 for details.
				The Keypad Interrupt feature operates with Port 0 pins.
				All pins have Schmitt triggered inputs.
				Port 0 also provides various special functions as described below:

	1		I/O	P0.1 — Port 0 bit 1.

			I	CIN2B — Comparator 2 positive input B.

			I	KBI1 — Keyboard input 1.

			I	AD10 — A/D channel 1, input 0

	16		I/O	P0.2 — Port 0 bit 2.

			I	CIN2A — Comparator 2 positive input A.

			I	KBI2 — Keyboard input 2.

			I	AD11 — A/D channel 1, input 1

	15		I/O	P0.3 — Port 0 bit 3.

			I	CIN1B — Comparator 1 positive input B.

			I	KBI3 — Keyboard input 3.

			I	AD12 — A/D channel 1, input 2.

	14		I/O	P0.4 — Port 0 bit 4.

			I	CIN1A — Comparator 1 positive input A.

			I	KBI4 — Keyboard input 4.

			I	AD13 — A/D channel 1, input 3.

			O	DAC1 — Digital to analog converter 1 output.

	13		I/O	P0.5 — Port 0 bit 5.

			I	CMPREF — Comparator reference (negative) input.

			I	KBI5 — Keyboard input 5.

			I	CLKIN — External clock input.

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Table 3:	P89LPC916 pin description

Symbol		Pin	Type	Description
P1.0 to P1.3, 3, 7, 8, 9,			I/O	Port 1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port 1
P1.5	10		(P1.2);	latches are configured in the input only mode with the internal pull-up disabled. The
			I (P1.5)	operation of the P1.2 input and outputs depends upon the port configuration selected.
				Refer to Section 5.1 for details. P1.2 is an open drain when used as an output. P1.5 is
				input only.
				All pins have Schmitt triggered inputs.
				Port 1 also provides various special functions as described below:

	10		I/O	P1.0 — Port 1 bit 0

			O	TxD — Serial port transmitter data.

	9		I/O	P1.1 — Port 1 bit 0

			I	RxD — Serial port receiver data.

8I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output.

	I/O	SCL — I2C serial clock input/output.
7	I/O	P1.3 — Port 1 bit 2. (Open drain when used as an output.)

	I/O	INT0 — External interrupt 0 input.

	I/O	SDA — I2C serial data input/output.
3	I	P1.5 — Port 1 bit 5. (Input only.)

	I	RST — External Reset input during power-on or if selected via UCFG1. When
		functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
		ports and peripherals to take on their default states, and the processor begins
		execution at address 0. Also used during a power-on sequence to force In-System
		Programming mode.

P2.2 to P2.5 2, 5, 6, 11	I/O	Port 2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset
		Port 1 latches are configured in the input only mode with the internal pull-up disabled.
		The operation of the P2 input and outputs depends upon the port configuration
		selected. Refer to Section 5.1 for details.
		All pins have Schmitt triggered inputs.
		Port 2 also provides various special functions as described below:

6	I/O	P2.2 — Port 2 bit 2.

	O	MOSI — SPI master out slave in. When configured as a master this pin is an output.
		When configured as a slave, this pin is an input.

5	I/O	P2.3 — Port 2 bit 3.

	I	MISO — SPI master in slave out. When configured as a master this pin is an input.
		When configured as a slave, this pin is an output.

2	I/O	P2.4 — Port 2 bit 4.

	I/O	SS — SPI Slave select.

11I/O P2.5 — Port 2 bit 5.

I/O SPICLK — When configured as a master this pin is an output. When configured as a slave, this pin is an input.

VSS	4	I	Ground: 0 V reference.
VDD	12	I	Power Supply: This is the power supply voltage for normal operation as well as Idle
			and Power-down modes.

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Table 4:	P89LPC917 pin description

Symbol		Pin	Type	Description
P0.0 to P0.5, 1, 2, 11,			I/O	Port 0: Port 0 is a 7-bit I/O port with user-configurable outputs. During reset Port 0
P0.7	13, 14, 15,			latches are configured in the input only mode with the internal pull-up disabled. The
	16			operation of Port 0 pins as inputs and outputs depends upon the port configuration
				selected. Each port pin is configured independently. Refer to Section 5.1 for details.
				The Keypad Interrupt feature operates with Port 0 pins.
				All pins have Schmitt triggered inputs.
				Port 0 also provides various special functions as described below:

	2		I/O	P0.0 — Port 0 bit 0.

			I	CMP2 — Comparator 2 output.

			I	KBI0 — Keyboard input 0.

	1		I/O	P0.1 — Port 0 bit 1.

			I	CIN2B — Comparator 2 positive input B.

			I	KBI1 — Keyboard input 1.

			I	AD10 — A/D channel 1, input 0

	16		I/O	P0.2 — Port 0 bit 2.

			I	CIN2A — Comparator 2 positive input A.

			I	KBI2 — Keyboard input 2.

			I	AD11 — A/D channel 1, input 1

	15		I/O	P0.3 — Port 0 bit 3.

			I	CIN1B — Comparator 1 positive input B.

			I	KBI3 — Keyboard input 3.

			I	AD12 — A/D channel 1, input 2.

	14		I/O	P0.4 — Port 0 bit 4.

			I	CIN1A — Comparator 1 positive input A.

			I	KBI4 — Keyboard input 4.

			I	AD13 — A/D channel 1, input 3.

			O	DAC1 — Digital to analog converter 1 output.

	13		I/O	P0.5 — Port 0 bit 5.

			I	CMPREF — Comparator reference (negative) input.

			I	KBI5 — Keyboard input 5.

			I	CLKIN — External clock input.

	11		I/O	P0.7 — Port 0 bit 7.

			I	T1 — Timer/counter 1 external count input, overflow output, or PWM output.

			I	KBI7 — Keyboard input 7.

			I	CLKOUT — Clock output.

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Table 4:	P89LPC917 pin description

Symbol		Pin	Type	Description
P1.0 to P1.5 3, 6, 7, 8,			I/O	Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1
	9, 10		(P1.0:4);	latches are configured in the input only mode with the internal pull-up disabled. The
			I (P1.5)	operation of the outputs depends upon the port configuration selected. Refer to
				Section 5.1 for details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is
				input only.
				All pins have Schmitt triggered inputs.
				Port 1 also provides various special functions as described below:

	10		I/O	P1.0 — Port 1 bit 0.

			O	TxD — Serial port transmitter data.

	9		I/O	P1.1 — Port 1 bit 1.

			I	RxD — Serial port receiver data.

	8		I/O	P1.2 — Port 1 bit 2. (Open drain when used as an output.)

			I/O	T0 — Timer/counter 0 external count input, overflow, or PWM output.

			I/O	SCL — I2C serial clock input/output.
	7		I/O	P1.3 — Port 1 bit 3. (Open drain when used as an output.)

			I/O	INT0 — External interrupt 0 input.

			I/O	SDA — I2C serial data input/output.
	6		I/O	P1.4 — Port 1 bit 4.

			I/O	INT1 — External interrupt 1input.

	3		I	P1.5 — Port 1 bit 5. (Input only.)

P2.2	5	I/O	Port 2: Port 2.2 is a single-bit I/O port with a user-configurable output. During reset
			the Port 2.2 latch is configured in the input only mode with the internal pull-up
			disabled. The operation of the output depends upon the port configuration selected.
			Refer to Section 5.1 and details.
			This pin has a Schmitt triggered input.

VSS	4	I	Ground: 0 V reference.
VDD	12	I	Power Supply: This is the power supply voltage for normal operation as well as Idle
			and Power-down modes.

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P89LPC915
P89LPC915			HIGH PERFORMANCE
			HIGH PERFORMANCE
		ACCELERATED 2-CLOCK 80C51 CPU


	2 kB			UART
	CODE FLASH			UART
	CODE FLASH		INTERNAL

256-BYTE

BUS

I2C

DATA RAM

PORT 1

ADC1/DAC1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

REAL-TIME CLOCK/

SYSTEM TIMER

KEYPAD

TIMER 0

INTERRUPT

TIMER 1

WATCHDOG TIMER

ANALOG

AND OSCILLATOR

COMPARATORS

PROGRAMMABLE

CPU

OSCILLATOR DIVIDER

CLOCK

external

POWER MONITOR

clock

(POWER-ON RESET,

input

BROWNOUT RESET)

ON-CHIP RC

OSCILLATOR

002aaa822

Fig 7. P89LPC915 block diagram.

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P89LPC916
P89LPC916			HIGH PERFORMANCE
			HIGH PERFORMANCE
		ACCELERATED 2-CLOCK 80C51 CPU


	2 kB			UART
	CODE FLASH			UART
	CODE FLASH		INTERNAL

	256-BYTE	BUS
	256-BYTE	I2C
	DATA RAM
	PORT 2	ADC1/DAC1
	CONFIGURABLE I/Os	ADC1/DAC1
	CONFIGURABLE I/Os
	PORT 1	SPI
	CONFIGURABLE I/Os	SPI
	PORT 0	REAL-TIME CLOCK/
	CONFIGURABLE I/Os	SYSTEM TIMER
	KEYPAD	TIMER 0
	KEYPAD	TIMER 1
	INTERRUPT	TIMER 1
	INTERRUPT
	WATCHDOG TIMER	ANALOG
	AND OSCILLATOR	COMPARATORS
	PROGRAMMABLE	CPU
	OSCILLATOR DIVIDER	CPU
	OSCILLATOR DIVIDER	CLOCK
	external	CLOCK
	external	POWER MONITOR
	clock	POWER MONITOR
	clock	(POWER-ON RESET,
	input	(POWER-ON RESET,
	input	BROWNOUT RESET)
	ON-CHIP RC	BROWNOUT RESET)
	ON-CHIP RC
	OSCILLATOR

002aaa823

Fig 8. P89LPC916 block diagram.

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P89LPC917			HIGH PERFORMANCE
			HIGH PERFORMANCE
		ACCELERATED 2-CLOCK 80C51 CPU


	2 kB			UART
	CODE FLASH			UART
	CODE FLASH		INTERNAL

	256-BYTE	BUS
	256-BYTE	I2C
	DATA RAM
	PORT 2	ADC1/DAC1
	CONFIGURABLE I/Os	ADC1/DAC1
	CONFIGURABLE I/Os
	PORT 1	REAL-TIME CLOCK/
	CONFIGURABLE I/Os	REAL-TIME CLOCK/
	CONFIGURABLE I/Os	SYSTEM TIMER
		SYSTEM TIMER
	PORT 0	TIMER 0
	CONFIGURABLE I/Os	TIMER 0
	CONFIGURABLE I/Os	TIMER 1
		TIMER 1
	KEYPAD	ANALOG
	INTERRUPT	ANALOG
	INTERRUPT	COMPARATORS
		COMPARATORS
	WATCHDOG TIMER
	AND OSCILLATOR
	PROGRAMMABLE	CPU
	OSCILLATOR DIVIDER	CPU
	OSCILLATOR DIVIDER	CLOCK
	external	CLOCK
	external	POWER MONITOR
	clock	POWER MONITOR
	clock	(POWER-ON RESET,
	input	(POWER-ON RESET,
	input	BROWNOUT RESET)
	ON-CHIP RC	BROWNOUT RESET)
	ON-CHIP RC
	OSCILLATOR

CLKOUT

002aaa824

Fig 9. P89LPC917 block diagram.

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1.4 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:

•User must not attempt to access any SFR locations not defined.

•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

•SFR bits labeled ‘-’, ‘0’ or ‘1’ canonly be written and read as follows:

–‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

–‘0’ must be written with ‘0’, and will return a ‘0’ when read.

–‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 5:

P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

ADCON1

A/D control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

ADCI1

ENADC1

ADCS11

ADCS10

00000000

ADINS

A/D input select

A3H

ADI13

ADI12

ADI11

ADI10

00000000

ADMODA

A/D mode register A

C0H

BNDI1

BURST1

SCC1

SCAN1

00000000

ADMODB

A/D mode register B

A1H

CLK2

CLK1

CLK0

ENDAC1

BSA1

000x0000

AD1BH

A/D_1 boundary high register

C4H

11111111

AD1BL

A/D_1 boundary low register

BCH

00000000

AD1DAT0

A/D_1 data register 0

D5H

00000000

.Rev

AD1DAT1

A/D_1 data register 1

D6H

00000000

AD1DAT2

A/D_1 data register 2

D7H

00000000

— 01

AD1DAT3

A/D_1 data register 3

F5H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT0

SRST

DPS

000000x0

July

Bit address

2004

B register

F0H

00000000

BRGR0[2]

Baud rate generator rate low

BEH

00000000

BRGR1[2]

Baud rate generator rate high

BFH

00000000

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

00[2]

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CP1

CN1

CO1

CMF1

00[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CP2

CN2

OE2

CO2

CMF2

00[1]

xx000000

Koninklijke

DIVM

CPU clock divide-by-M

95H

00000000

Philips

control

DPTR

Data pointer (2 bytes)

NElectronics

DPL

Data pointer low

82H

00000000

DPH

Data pointer high

83H

00000000

.V.

All.2004

FMADRH

Program Flash address high

E7H

00000000

125 of 16

.reserved rights

FMADRL

Program Flash address low

E6H

00000000

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 5:

P89LPC915 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

FMCON

Program Flash Control

E4H

BUSY

HVA

HVE

01110000

(Read)

Program Flash Control (Write)

FMCMD.

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

Program Flash data

E5H

00000000

I2ADR

I2C slave address register

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

00000000

Bit address

I2CON*

I2C control register

D8H

I2EN

STA

STO

CRSEL

x00000x0

I2DAT

I2C data register

DAH

I2SCLH

Serial clock generator/SCL

DDH

00000000

duty cycle register high

.Rev

I2SCLL

Serial clock generator/SCL

DCH

00000000

— 01

duty cycle register low

I2STAT

I2C status register

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

11111000

Bit address

July

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00000000

2004

Bit address

IEN1*

Interrupt enable 1

E8H

EAD

EST

EKBI

EI2C

00[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

00[1]

x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRT

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

00[1]

x0000000

PSRH

Koninklijke

IP1*

Interrupt priority 1

F8H

PAD

PST

PKBI

PI2C

00[1]

00x00000

Bit address

Philips

IP1H

Interrupt priority 1 high

F7H

PADH

PSTH

PCH

PKBIH

PI2CH

00[1]

00x00000

Electronics

KBCON

Keypad control register

94H

PATN

KBIF

00[1]

xxxxxx00

.V.N

_SEL

KBMASK

Keypad interrupt mask

86H

00000000

.2004

rightsAll

KBPATN

Keypad pattern register

93H

11111111

125of

.reserved

Bit address

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 5:

P89LPC915 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

P0*

Port 0

80H

CMPREF

CIN1A

CIN1B

CIN2A

CIN2B

CMP2

[1]

/KBI5

/KBI4

/KBI3

/KBI2

/KBI1

/KBI0

Bit address

P1*

Port 1

90H

T0/SCL

RXD

TXD

[1]

RST

INT1

INT0/

SDA

P0M1

Port 0 output mode 1

84H

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2) (P0M1.1) (P0M1.0)

FF[1]

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.5)

(P0M2.4)

(P0M2.3)

(P0M2.2) (P0M2.1) (P0M2.0)

00[1]

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.4)

(P1M1.3)

(P1M1.2) (P1M1.1) (P1M1.0)

D3[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.4)

(P1M2.3)

(P1M2.2) (P1M2.1) (P1M2.0)

00[1]

00x0xx00

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

.Rev

PCONA

Power control register A

B5H

RTCPD

VCPD

ADPD

I2PD

SPD

00[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

—

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

xx00000x

July

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

2004

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

60[1][6]

011xxx00

RTCH

Real-time clock register high

D2H

00[6]

00000000

RTCL

Real-time clock register low

D3H

00[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial Port data buffer register

99H

xxxxxxxx

Koninklijke

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

Bit address

Philips

SSTAT

Serial port extended status

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Electronics

Stack pointer

81H

00000111

.V.N

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T0M2

xxx0xxx0

.2004

Bit address

rights All

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

125of

.reserved

TH0

Timer 0 high

8CH

00000000

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manual User

2004 July 15 — 01 .Rev

125 of 19

13316 750 9397

.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©

Table 5:

P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

TH1

Timer 1 high

8DH

00000000

TL0

Timer 0 low

8AH

00000000

TL1

Timer 1 low

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

RCCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

[1]All ports are in input only (high impedance) state after power-up.

[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3]The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000.

[4]After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF.

[5]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]The only reset source that affects these SFRs is power-on reset

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 6:

P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

ADCON1

A/D control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

ADCI1

ENADC1

ADCS11

ADCS10

00000000

ADINS

A/D input select

A3H

ADI13

ADI12

ADI11

ADI10

00000000

ADMODA

A/D mode register A

C0H

BNDI1

BURST1

SCC1

SCAN1

00000000

ADMODB

A/D mode register B

A1H

CLK2

CLK1

CLK0

ENDAC1

BSA1

000x0000

AD1BH

A/D_1 boundary HIGH

C4H

11111111

AD1BL

A/D_1 boundary LOW

BCH

00000000

.Rev

AD1DAT0

A/D_1 data register 0

D5H

00000000

AD1DAT1

A/D_1 data register 1

D6H

00000000

—

AD1DAT2

A/D_1 data register 2

D7H

00000000

July

AD1DAT3

A/D_1 data register 3

F5H

00000000

2004

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT0

SRST

DPS

000000x0

Bit address

B register

F0H

00000000

BRGR0[2]

Baud rate generator rate

BEH

00000000

LOW

BRGR1[2]

Baud rate generator rate

BFH

00000000

HIGH

Koninklijke

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

00[2]

xxxxxx00

Philips

CMP1

Comparator 1 control register

ACH

CE1

CP1

CN1

CO1

CMF1

00[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CP2

CN2

OE2

CO2

CMF2

xx000000

NElectronics

DIVM

control

95H

00000000

CPU clock divide-by-M

.V.

DPTR

Data pointer (2 bytes)

All .2004

DPH

Data pointer HIGH

83H

00000000

rights

DPL

Data pointer LOW

82H

00000000

125of

.reserved

FMADRH

Program Flash address HIGH

E7H

00000000

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 6:

P89LPC916 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control

E4H

BUSY

HVA

HVE

01110000

(Read)

Program Flash Control (Write)

FMCMD.

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

Program Flash data

E5H

00000000

I2ADR

I2C slave address register

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

00000000

Bit address

I2CON*

I2C control register

D8H

I2EN

STA

STO

CRSEL

x00000x0

I2DAT

I2C data register

DAH

.Rev

I2SCLH

Serial clock generator/SCL

DDH

00000000

duty cycle register HIGH

I2SCLL

Serial clock generator/SCL

DCH

00000000

—

duty cycle register LOW

I2STAT

I2C status register

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

11111000

July

Bit address

2004

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

ET0

EX0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EAD

EST

ESPI

EKBI

EI2C

00[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PT0

PX0

00[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PSH/

PT1H

PT0H

PX0H

00[1]

x0000000

Koninklijke

PSRH

Philips

Bit address

IP1*

Interrupt priority 1

F8H

PAD

PST

PSPI

PKBI

PI2C

00[1]

00x00000

NElectronics

KBCON

Keypad control register

94H

PATN

KBIF

00[1]

xxxxxx00

IP1H

Interrupt priority 1 HIGH

F7H

PADH

PSTH

PSPIH

PCH

PKBIH

PI2CH

00[1]

00x00000

.V.

_SEL

All .2004

KBMASK

Keypad interrupt mask

86H

00000000

rights

125of

.reserved

KBPATN

Keypad pattern register

93H

11111111

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 6:

P89LPC916 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

Bit address

P0*

Port 0

80H

CMPREF

CIN1A

CIN1B

CIN2A

CIN2B

[1]

/KBI5

/KBI4

/KBI3

/KBI2

/KBI1

Bit address

P1*

Port 1

90H

T0/SCL

RXD

TXD

[1]

RST

INT0/

SDA

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.1)

FF[1]

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.5)

(P0M2.4)

(P0M2.3)

(P0M2.2)

(P0M2.1)

00[1]

00000000

.Rev

P1M1

Port 1 output mode 1

91H

(P1M1.3)

(P1M1.2)

(P1M1.1)

(P1M1.0)

D3[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.3)

(P1M2.2)

(P1M2.1)

(P1M2.0)

00[1]

00x0xx00

P2M1

Port 2 output mode 1

A4H

(P2M1.5)

(P2M1.4)

(P2M1.3)

(P2M1.2)

FF[1]

11111111

—

P2M2

Port 2 output mode 2

A5H

(P2M2.5)

(P2M2.4)

(P2M2.3)

(P2M2.2)

00[1]

00000000

July

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

2004

PCONA

Power control register A

B5H

RTCPD

VCPD

ADPD

I2PD

SPPD

SPD

00[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

60[1][6]

011xxx00

Koninklijke

RTCL

Real-time clock register LOW

D3H

00[6]

00000000

RTCH

Real-time clock register HIGH

D2H

00[6]

00000000

Philips

SADDR

Serial port address register

A9H

00000000

NElectronics

SBUF

Serial Port data buffer register

99H

xxxxxxxx

SADEN

Serial port address enable

B9H

00000000

.V.

Bit address

All .2004

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

rights

SSTAT

Serial port extended status

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

125of

.reserved

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manual User

2004 July 15 — 01 .Rev

125 of 23

13316 750 9397

.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©

Table 6:

P89LPC916 Special function registers

Philips

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Semiconductors

Stack pointer

81H

00000111

SPCTL

SPI control register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00000100

SPSTAT

SPI status register

E1H

SPIF

WCOL

00xxxxxx

SPDAT

SPI data register

E3H

00000000

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T0M2

xxx0xxx0

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

IE0

IT0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

RCCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

manualUserP89LPC915/916/917

UM10107

[3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

resets will not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 7:

P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

ADCON1

A/D control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

ADCI1

ENADC1

ADCS11

ADCS10

00000000

ADINS

A/D input select

A3H

ADI13

ADI12

ADI11

ADI10

00000000

ADMODA

A/D mode register A

C0H

BNDI1

BURST1

SCC1

SCAN1

00000000

ADMODB

A/D mode register B

A1H

CLK2

CLK1

CLK0

ENDAC1

BSA1

000x0000

AD1BH

A/D_1 boundary HIGH

C4H

11111111

AD1BL

A/D_1 boundary LOW

BCH

00000000

.Rev

AD1DAT0

A/D_1 data register 0

D5H

00000000

AD1DAT1

A/D_1 data register 1

D6H

00000000

—

AD1DAT2

A/D_1 data register 2

D7H

00000000

July

AD1DAT3

A/D_1 data register 3

F5H

00000000

2004

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

DPS

000000x0

Bit address

B register

F0H

00000000

BRGR0[2]

Baud rate generator rate

BEH

00000000

LOW

BRGR1[2]

Baud rate generator rate

BFH

00000000

HIGH

Koninklijke

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

00[2]

xxxxxx00

Philips

CMP1

Comparator 1 control register

ACH

CE1

CP1

CN1

CO1

CMF1

00[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CP2

CN2

OE2

CO2

CMF2

00[1]

xx000000

NElectronics

DIVM

control

95H

00000000

CPU clock divide-by-M

.V.

DPTR

Data pointer (2 bytes)

All .2004

DPH

Data pointer HIGH

83H

00000000

rights

DPL

Data pointer LOW

82H

00000000

125of

.reserved

FMADRH

Program Flash address HIGH

E7H

00000000

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

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manualUser

133167509397

Table 7:

P89LPC917 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control

E4H

BUSY

HVA

HVE

01110000

(Read)

Program Flash Control (Write)

FMCMD.

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

Program Flash data

E5H

00000000

I2ADR

I2C slave address register

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

00000000

Bit address

I2CON*

I2C control register

D8H

I2EN

STA

STO

CRSEL

x00000x0

I2DAT

I2C data register

DAH

.Rev

I2SCLH

Serial clock generator/SCL

DDH

00000000

duty cycle register HIGH

I2SCLL

Serial clock generator/SCL

DCH

00000000

—

duty cycle register LOW

I2STAT

I2C status register

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

11111000

July

Bit address

2004

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EAD

EST

EKBI

EI2C

00[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

00[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

00[1]

x0000000

Koninklijke

PSRH

Philips

Bit address

IP1*

Interrupt priority 1

F8H

PAD

PST

PKBI

PI2C

00[1]

00x00000

NElectronics

KBCON

Keypad control register

94H

PATN

KBIF

00[1]

xxxxxx00

IP1H

Interrupt priority 1 HIGH

F7H

PADH

PSTH

PCH

PKBIH

PI2CH

00[1]

00x00000

.V.

_SEL

All .2004

KBMASK

Keypad interrupt mask

86H

00000000

rights

125of

.reserved

KBPATN

Keypad pattern register

93H

11111111

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

manualUser

133167509397

Table 7:

P89LPC917 Special function registers

LSB

Hex

Binary

* indicates SFRs that are bit addressable.

addr.

MSB

Name

Description

SFR

Bit functions and addresses

Reset value

Bit address

P0*

Port 0

80H

T1/KBI7/

CMPREF

CIN1A

CIN1B

CIN2A

CIN2B

CMP2

[1]

CLKOUT

/KBI5

/KBI4

/KBI3

/KBI2

/KBI1

/KBI0

Bit address

P1*

Port 1

90H

T0/SCL

RXD

TXD

[1]

RST

INT1

INT0/

SDA

P0M1

Port 0 output mode 1

84H

(P0M1.7)

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.1)

(P0M1.0)

FF[1]

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.7)

(P0M2.5)

(P0M2.4)

(P0M2.3)

(P0M2.2)

(P0M2.1)

(P0M2.0)

00[1]

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.4)

(P1M1.3)

(P1M1.2)

(P1M1.1)

(P1M1.0)

D3[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.4)

(P1M2.3)

(P1M2.2)

(P1M2.1)

(P1M2.0)

00[1]

00x0xx00

.Rev

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

ADPD

I2PD

SPD

00[1]

00000000

Bit address

—

PSW*

Program status word

D0H

RS1

RS0

00000000

July

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

xx00000x

2004

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

60[1][6]

011xxx00

RTCH

Real-time clock register HIGH

D2H

00[6]

00000000

RTCL

Real-time clock register LOW

D3H

00[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

Koninklijke

SBUF

Bit address

xxxxxxxx

Serial Port data buffer register

99H

Philips

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

Electronics

SSTAT

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Serial port extended status

.V.N

Stack pointer

81H

00000111

.2004

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T1M2

T0M2

xxx0xxx0

rights All

Bit address

125of

.reserved

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

Semiconductors Philips

manual User P89LPC915/916/917

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2004 July 15 — 01 .Rev

125 of 27

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Table 7:

P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

[1]All ports are in input only (high impedance) state after power-up.

[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3]The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000.

[5]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]The only reset source that affects these SFRs is power-on reset.

Semiconductors Philips

manual User P89LPC915/916/917

UM10107

Philips Semiconductors						UM10107
						P89LPC915/916/917 User manual
	1.5 Memory organization

		07FFh
		07FFh		SECTOR 7
		0700h		SECTOR 7
		0700h
		06FFh
		06FFh		SECTOR 6
		0600h		SECTOR 6
		05FFh		SECTOR 5	SPECIAL FUNCTION	IDATA (incl. DATA)		FFh
		05FFh				IDATA (incl. DATA)
						128 BYTES ON-CHIP
		0500h			REGISTERS	128 BYTES ON-CHIP
		0500h			REGISTERS	DATA MEMORY (STACK
		04FFh		SECTOR 4	(DIRECTLY ADDRESSABLE)	AND INDIR. ADDR.)		80h
						AND INDIR. ADDR.)		80h
		0400h
		0400h				DATA		7Fh
		03FFh		SECTOR 3		128 BYTES ON-CHIP
						128 BYTES ON-CHIP
		0300h				DATA MEMORY (STACK,
		0300h				DATA MEMORY (STACK,
		02FFh		SECTOR 2		DIRECT AND INDIR. ADDR.)
		0200h		SECTOR 2		4 REG. BANKS R[7:0]
		0200h				4 REG. BANKS R[7:0]		00h
		01FFh
		01FFh		SECTOR 1		data memory
		0100h		SECTOR 1		data memory
		0100h				(DATA, IDATA)
		00FFh		SECTOR 0
				SECTOR 0
		000h
		000h	2 kB Flash code
			2 kB Flash code
			memory space				002aaa913
							002aaa913
		Fig 10. P89LPC915/916/917 memory map.

The various P89LPC915/916/917 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.

Table 8:	Data RAM arrangement
Type		Data RAM	Size (bytes)
DATA		Directly and indirectly addressable memory	128

IDATA		Indirectly addressable memory	256

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			P89LPC915/916/917 User manual

2. Clocks

2.1 Enhanced CPU

The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC915/916/917 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of three clock sources and can also be optionally divided to a slower frequency (see Figure 11 and Section 2.8 “CPU Clock (CCLK) modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLKe2.

The P89LPC915/916/917 provides user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, or an external clock source.

2.3 Clock output (P89LPC917)

The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin. This allows external devices to synchronize to the P89LPC917. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1e2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.4 On-chip RC oscillator option

The P89LPC915/916/917 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, r 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC915/916/917 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

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Philips Semiconductors

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P89LPC915/916/917 User manual

Table 9:

On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit

Symbol

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

Reset

Bits 5:0 loaded with factory stored value during reset.

Table 10: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit

Symbol

Description

0	TRIM.0
1	TRIM.1

2	TRIM.2

3	TRIM.3

4	TRIM.4

5	TRIM.5

Trim value. Determines the frequency of the internal RC oscillator. During reset, these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

6	ENCLK	when = 1, CCLKe2 is output on the XTAL2 pin provided the crystal oscillator is not
		being used.

7	RCCLK	when = 1, selects the RC Oscillator output as the CPU clock (CCLK)

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the P0.5 pin. The rate may be from 0 Hz up to 12 MHz.

			RTCS1:0
		XCLK
				RTC
		RCCLK		CLKOUT
CLKIN		OSCCLK
CLKIN				CCLK
		DIVM		CCLK
RCCLK		DIVM		CPU
RCCLK
RC
OSCILLATOR
(7.3728 MHz)				ADC1/DAC1
(7.3728 MHz)
			2
				PCLK
WATCHDOG				WDT
OSCILLATOR		peripheral clock
		peripheral clock
(400 kHz)		PCLK
BAUD RATE	UART	TIMERS 1 AND 0	I2C	SPI
GENERATOR	UART	TIMERS 1 AND 0	I2C	(P89LPC916)
GENERATOR				(P89LPC916)
				002aaa831

Fig 11. Block diagram of oscillator control.

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