Philips UM10107 User Manual

Page 1

UM10107

P89LPC915/916/917 8-bit microcontrollers with two-clock 80C51 core and 8-bit A/D

Rev. 01 — 15 July 2004 User manual

Document information

Info Content Keywords P89LPC915, P89LPC916, P89LPC917 Abstract Technical information for the P89LPC915, P89LPC916, and P89LPC917

devices.

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Philips Semiconductors

Revision history

Rev Date Description

01 20040715 Initial version (9397 750 13316).

UM10107

P89LPC915/916/917 User manual

Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

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Philips Semiconductors

1. Introduction

The P89LPC915/916/917 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC915/916/917 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC915/916/917 in order to reduce component count, board space, and system cost.

1.1 Logic symbols

VDDV

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P89LPC915/916/917 User manual

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5

DAC1

AD10 AD11 AD12 AD13

CLKIN

Fig 1. P89LPC915 logic symbol.

KBI1 KBI2 KBI3 KBI4 KBI5

DAC1

AD10 AD11 AD12 AD13

CLKIN

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CIN2B CIN2A CIN1B CIN1A

CMPREF

PORT 0

P89LPC915

002aaa828

P89LPC916

002aaa829

PORT 1

PORT 2

TxD RxD T0 INT0 INT1 RST

TxD RxD T0 INT0

RST

MOSI MISO SS SPICLK

SCL SDA

Fig 2. P89LPC916 logic symbol.

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KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI7

DAC1

AD10 AD11 AD12 AD13

CLKIN

CLKOUT

Fig 3. P89LPC917 logic symbol.

1.2 Product comparison

Table 1 highlights the differences between these devices. For a complete list of device

features, please refer to the P89LPC915/916/917 data sheet.

Table 1: Product comparison

Type number

P89LPC915 X - - - X 6 P89LPC916 - X - - - 5 P89LPC917 X - X X X 7

1.3 Pin Configuration

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

Comp 2 output

PORT 0

P89LPC917

002aaa830

SPI T1 PWM

output

TxD

PORT 1

PORT 2

RxD T0 INT0 INT1 RST

SCL SDA

CLKOUT INT1 KBI

002aaa825

14 13 12 11

P0.5/CMPREF/KBI5/CLKIN

IN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

KBI0/CMP2/P0.0 P0.3/CIN1B/KBI3/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC

INT1/P1.4 V

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

1 2 3

LPC915

4 5 6 7 8

Fig 4. P89LPC915 TSSOP14 pin configuration.

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CIN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

SS/P2.4 P0.3/CIN1B/KB13/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC1

MISO/P2.3 V

MOSI/P2.2 P2.5/SPICLK

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

LPC916

002aaa826

Fig 5. P89LPC916 TSSOP16 pin configuration.

CIN2B/KBI1/AD10/P0.1 P0.2/CIN2A/KBI2/AD11

KBI0/CMP2/P0.0 P0.3/CIN1B/KB13/AD12

RST/P1.5 P0.4/CIN1A/KBI4/AD13/DAC1

MOSI/P2.2 V

INT1/P1.4 P0.7/T1/KBI7/CLKOUT

SDA/INT0/P1.3 P1.0/TXD

SCL/T0/P1.2 P1.1/RXD

LPC917

002aaa827

Fig 6. P89LPC917 TSSOP pin configuration.

P0.5/CMPREF/KBI5/CLKIN

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Ta ble 2: P89LPC915 pin description

Symbol Pin Type Description

P0.0 to P0.5 1, 2, 11,

12, 13, 14

2 I/O P0.0 — Port 0 bit 0.

1 I/O P0.1 — Port 0 bit 1.

14 I/O P0.2 — Port 0 bit 2.

13 I/O P0.3 — Port 0 bit 3.

12 I/O P0.4 — Port 0 bit 4.

11 I/O P0.5 — Port 0 bit 5.

I/O Port 0: Port 0 is a 6-bit I/O port with user-configurable outputs. During reset Port 0

latches are configured in the input only mode with the internal pull-up disabled. The operation of Port0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock i nput.

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for details.

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Ta ble 2: P89LPC915 pin description

Symbol Pin Type Description

P1.0 to P1.5 3, 5, 6, 7,

8, 9

9 I/O P1.0 — Port 1 bit 0

8 I/O P1.1 — Port 1 bit 0

7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

6 I/O P1.3 — Port 1 bit 2. (Open drain when used as an output.)

5 I/O P1.4 — Port 1 bit 2.

3IP1.5 — Port 1 bit 5. (Input only.)

4IGround: 0 V reference. 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle

I/O (P1.2); I(P1.5)

O TxD — Serial port transmitter data.

I RxD — Serial port receiver dat a .

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output. I/O SCL — I

I/O INT0 I/O SDA — I

I/O INT1

I RST

Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the inputs and outputs depends upon the port configuration selected. Refer to Section 5.1 input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

— External interrupt 0 input.

— External interrupt 1input.

— External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

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for details. P1.2 is an o pen drai n whe n used as an outpu t. P1. 5 is

C serial clock input/output.

C serial data input/output.

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Ta ble 3: P89LPC916 pin description

Symbol Pin Type Description

P0.1 to P0.5 1, 13, 14,

15, 16

1 I/O P0.1 — Port 0 bit 1.

16 I/O P0.2 — Port 0 bit 2.

15 I/O P0.3 — Port 0 bit 3.

14 I/O P0.4 — Port 0 bit 4.

13 I/O P0.5 — Port 0 bit 5.

I/O Port 0: Port 0 is a 5-bit I/O port with user-configurable outputs. During reset Port 0

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock i nput.

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for details.

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Ta ble 3: P89LPC916 pin description

Symbol Pin Type Description

P1.0 to P1.3, P1.5

P2.2 to P2.5 2, 5, 6, 11 I/O Port 2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset

3, 7, 8, 9, 10I/O

(P1.2); I(P1.5)

10 I/O P1.0 — Port 1 bit 0

O TxD — Serial port transmitter data.

9 I/O P1.1 — Port 1 bit 0

I RxD — Serial port receiver dat a .

8 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

I/O T0 — Timer/counter 0 external count input, overflow output, or PWM output. I/O SCL — I

7 I/O P1.3 — Port 1 bit 2. (Open drain when used as an output.)

I/O INT0 I/O SDA — I

3IP1.5 — Port 1 bit 5. (Input only.)

I RST

6 I/O P2.2 — Port 2 bit 2.

O MOSI — SPI master out slave in. When configured as a master this pin is an output.

5 I/O P2.3 — Port 2 bit 3.

I MISO — SPI master in slave out. When configured as a master this pin is an input.

2 I/O P2.4 — Port 2 bit 4.

I/O SS

11 I/O P2.5 — Port 2 bit 5.

I/O SPICLK — When configured as a master this pin is an output. When configured as a

4IGround: 0 V reference. 12 I Power Supply: This is the power supply voltage for normal operation as well as Idle

Port 1: Port 1 is a 5-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the P1. 2 input and output s de pends upon the port c onf iguration selected. Refer to Section 5.1 input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

C serial clock input/output.

— External interrupt 0 input.

C serial data input/output.

— External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

Port 1 latches are configured in th e input only mode with the i nternal pull-up disabled. The operation of the P2 input and outputs depends upon the port configuration selected. Refer to Section 5.1

All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:

When configured as a slave, this pin is an input.

When configured as a slave, this pin is an output.

— SPI Slave select.

slave, this pin is an input.

and Power-down modes.

for details. P1.2 is an o pen drai n whe n used as an outpu t. P1. 5 is

for details.

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Ta ble 4: P89LPC917 pin description

Symbol Pin Type Description

P0.0 to P0.5, P0.7

1, 2, 11, 13, 14, 15, 16

2 I/O P0.0 — Port 0 bit 0.

1 I/O P0.1 — Port 0 bit 1.

16 I/O P0.2 — Port 0 bit 2.

15 I/O P0.3 — Port 0 bit 3.

14 I/O P0.4 — Port 0 bit 4.

13 I/O P0.5 — Port 0 bit 5.

11 I/O P0.7 — Port 0 bit 7.

I/O Port 0: Port 0 is a 7-bit I/O port with user-configurable outputs. During reset Port 0

latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — A/D channel 1, input 0

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — A/D channel 1, input 1

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — A/D channel 1, input 2.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — A/D channel 1, input 3. O DAC1 — Digital to analog converter 1 output.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input.

I T1 — Timer/counter 1 external count input, overflow output, or PWM output. I KBI7 — Keyboard input 7. I CLKOUT — Clock output.

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for details.

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Ta ble 4: P89LPC917 pin description

Symbol Pin Type Description

P1.0 to P1.5 3, 6, 7, 8,

9, 10

10 I/O P1.0 — Port 1 bit 0.

9 I/O P1.1 — Port 1 bit 1.

8 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)

7 I/O P1.3 — Port 1 bit 3. (Open drain when used as an output.)

6 I/O P1.4 — Port 1 bit 4.

3IP1.5 — Port 1 bit 5. (Input only.)

P2.2 5 I/O Port 2: Port 2.2 is a single-bit I/O port with a user-configurable output. During reset

4IGround: 0 V reference. 12 I Power Supply: This is the power supply v olt age fo r norma l ope ration as w ell as Id le

I/O (P1.0:4); I(P1.5)

O TxD — Serial port transmitter data.

I RxD — Serial port receiver data.

I/O T0 — Timer/counter 0 external count input, overflow, or PWM output. I/O SCL — I

I/O INT0 I/O SDA — I

I/O INT1

I RST

Port 1: Port 1 is a 6-bit I/O port with user-configurable outputs. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the outputs depends upon the port configuration selected. Refer to

Section 5.1

input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

functioning as a reset input a LOW on thi s pin reset s t he mi crocon trolle r, causing I /O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

the Port 2.2 latch is configured in the input only mode with the internal pull-up disabled. The operation of the output depends upon the port configuration selected. Refer to Section 5.1

This pin has a Schmitt triggered i nput.

and Power-down modes.

for details. P1.2 and P1.3 are open drain when used as outputs. P1.5 is

C serial clock input/output.

— External interrupt 0 input.

C serial data input/output.

— External interrupt 1input.

— External Reset input during power-on or if selected via UCFG1. When

and details.

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external

clock input

P89LPC915

2 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

UART

I2C

ADC1/DAC1

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

Fig 7. P89LPC915 block diagram.

002aaa822

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external

clock

input

P89LPC916

2 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

UART

I2C

ADC1/DAC1

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

Fig 8. P89LPC916 block diagram.

002aaa823

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external

clock input

CLKOUT

P89LPC917

2 kB

CODE FLASH

256-BYTE DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

POWER MONITOR (POWER-ON RESET,

BROWNOUT RESET)

UART

I2C

ADC1/DAC1

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

002aaa824

Fig 9. P89LPC917 block diagram.

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1.4 Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specif ied, must be written with ‘0’, but can return any value

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

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Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000 ADMODAA/D mode registerA C0HBNDI1BURST1SCC1SCAN1----0000000000 ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 - BSA1 - 00 000x0000 AD1BH A/D_1 boundary high register C4H FF 11111111 AD1BL A/D_1 boundary low register BCH 00 00000000 AD1DAT0 A/D_1 data register 0 D5H 00 00000000 AD1DAT1 A/D_1 data register 1 D6H 00 00000000 AD1DAT2 A/D_1 data register 2 D7H 00 00000000 AD1DAT3 A/D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR - ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000 BRGR0 BRGR1 BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00 00000000

DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H - - - - - - 00 00000000 FMADRL Program Flash address low E6H 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit addressE7E6E5E4E3E2E1E0

Bit addressF7F6F5F4F3F2F1F0

[2]

Baud rate generator rate low BEH 00 00000000

[2]

Baud rate generator rate high BFH 00 00000000

95H 00 00000000

control

MSB LSB Hex Binary

[2] [1] [1]

xxxxxx00 xx000000 xx000000

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Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I2C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - - EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00 IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - - PC PKBI PI2C 00 IP1H Interrupt priority 1 high F7H PADH PSTH - - - PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

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Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit addressDFDEDDDCDBDAD9 D8

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

C data register DAH

DDH 00 00000000

duty cycle register high

DCH 00 00000000

duty cycle register low

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

Bit address8786858483828180

MSB LSB Hex Binary

[1]

PT1H PX1H PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

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Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - - RST

P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD - SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register high D2H 00 RTCL Real-time clock register low D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111 TAMODTimer0 and 1 auxiliary mode8FH-------T0M200xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000 TH0 Timer 0 high 8CH 00 00000000

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Bit functions and addresses Reset value

addr.

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

/KBI5

CIN1A

/KBI4

CIN1B

/KBI3

INT1 INT0/

SDA

CIN2A

/KBI2

CIN2B

/KBI1

CMP2

/KBI0

T0/SCL RXD TXD

[1]

[1][6] [6] [6]

[1]

11111111 00000000 11x1xx11 00x0xx00

00000000

[3]

011xxx00 00000000 00000000

Philips Semiconductors

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User manual Rev. 01 — 15 July 2004 19 of 125

Table 5: P89LPC915 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TH1 Timer 1 high 8DH 00 00000000 TL0 Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset

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Bit functions and addresses Reset value

addr.

value is xx110000.

resets will not affect WDTOF.

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

Philips Semiconductors

[5] [6] [4] [6]

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User manual Rev. 01 — 15 July 2004 20 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

AD1BL A/D_1 boundary LOW

AD1DAT0 A/D_1 data register 0 D5H 00 00000000 AD1DAT1 A/D_1 data register 1 D6H 00 00000000 AD1DAT2 A/D_1 data register 2 D7H 00 00000000 AD1DAT3 A/D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR - ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000 BRGR0

BRGR1

BRGCON Baud rate generator control BDH - - - - - - SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 xx000000 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H - - - - - - 00 00000000

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Bit functions and addresses Reset value

[2]

Baud rate generator rate LOW

[2]

Baud rate generator rate HIGH

control

addr.

Bit addressE7E6E5E4E3E2E1E0

C4H FF 11111111

BCH 00 00000000

Bit addressF7F6F5F4F3F2F1F0

BEH 00 00000000

BFH 00 00000000

95H 00 00000000

MSB LSB Hex Binary

[2] [1]

xxxxxx00 xx000000

Philips Semiconductors

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User manual Rev. 01 — 15 July 2004 21 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 PX0 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - PSPI PC PKBI PI2C 00 IP1H Interrupt priority 1 HIGH F7H PADH PSTH - - PSPIH PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

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Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit addressDFDEDDDCDBDAD9 D8

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

C data register DAH

DDH 00 00000000

duty cycle register HIGH

DCH 00 00000000

duty cycle register LOW

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

MSB LSB Hex Binary

[1]

PT1H - PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

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User manual Rev. 01 — 15 July 2004 22 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - - RST

P2* Port 2 A0H - - SPICLK SS P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) - FF P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) - 00 P1M1 Port 1 output mode 1 91H - - - - (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - - (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 P2M1 Port 2 output mode 1 A4H - - (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) - - FF P2M2 Port 2 output mode 2 A5H - - (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) - - 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

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Bit functions and addresses Reset value

addr.

Bit address8786858483828180

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

MSB LSB Hex Binary

/KBI5

CIN1A

/KBI4

- INT0/

CIN1B

/KBI3

CIN2A

/KBI2

CIN2B

/KBI1

T0/SCL RXD TXD

SDA

MISO MOSI - -

[1]

[1][6] [6] [6]

[1]

11111111 00000000 11x1xx11 00x0xx00 11111111 00000000

00000000

[3]

011xxx00 00000000 00000000

Philips Semiconductors

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User manual Rev. 01 — 15 July 2004 23 of 125

Table 6: P89LPC916 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

SP Stack pointer 81H 07 00000111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI status register E1H SPIF WCOL - -----0000xxxxxx SPDAT SPI data register E3H 00 00000000 TAMODTimer0 and 1 auxiliary mode8FH-------T0M200xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 - - IE0 IT0 00 00000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

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Bit functions and addresses Reset value

addr.

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

[5] [6] [4] [6]

Philips Semiconductors

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

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User manual Rev. 01 — 15 July 2004 24 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

AD1BL A/D_1 boundary LOW

B* B register F0H 00 00000000 BRGR0

BRGR1

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000

FMADRH Program Flash address HIGH E7H - - - - - - 00 00000000

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Bit functions and addresses Reset value

[2]

Baud rate generator rate LOW

[2]

Baud rate generator rate HIGH

control

addr.

Bit addressE7E6E5E4E3E2E1E0

C4H FF 11111111

BCH 00 00000000

Bit addressF7F6F5F4F3F2F1F0

BEH 00 00000000

BFH 00 00000000

95H 00 00000000

MSB LSB Hex Binary

[2] [1] [1]

xxxxxx00 xx000000 xx000000

Philips Semiconductors

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User manual Rev. 01 — 15 July 2004 25 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I

I2CON* I I2DAT I I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - - EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - - PC PKBI PI2C 00 IP1H Interrupt priority 1 HIGH F7H PADH PSTH - - - PCH PKBIH PI2CH 00 KBCON Keypad control register 94H - - - - - - PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

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Bit functions and addresses Reset value

addr.

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control (Write) FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit addressDFDEDDDCDBDAD9 D8

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

C data register DAH

DDH 00 00000000

duty cycle register HIGH

DCH 00 00000000

duty cycle register LOW

C status r egister D 9H ST A.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit addressAFAEADACABAAA9 A8

Bit addressEFEEEDECEBEAE9 E8

Bit addressBFBEBDBCBBBAB9 B8

Bit addressFFFEFDFCFBFAF9F8

86H 00 00000000

MSB LSB Hex Binary

[1]

PT1H PX1H PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

Philips Semiconductors

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User manual Rev. 01 — 15 July 2004 26 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0* Port 0 80H T1/KBI7/

P1* Port 1 90H - - RST

P0M1 Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD - SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000

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Bit functions and addresses Reset value

addr.

Bit address8786858483828180

Bit address9796959493929190

Bit addressD7D6D5D4D3D2D1D0

Bit address9F9E9D9C9B9A99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

Bit address8F8E8D8C8B8A89 88

MSB LSB Hex Binary

-CMPREF

CLKOUT

/KBI5

CIN1A

/KBI4

CIN1B

/KBI3

INT1 INT0/

SDA

CIN2A

/KBI2

CIN2B

/KBI1

CMP2

/KBI0

T0/SCL RXD TXD

[1]

[1][6] [6] [6]

Philips Semiconductors

[1]

11111111 00000000 11x1xx11 00x0xx00

00000000

[3]

011xxx00 00000000 00000000

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User manual Rev. 01 — 15 July 2004 27 of 125

Table 7: P89LPC917 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[4] After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other

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Bit functions and addresses Reset value

addr.

value is xx110000.

resets will not affect WDTOF.

MSB LSB Hex Binary

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

Philips Semiconductors

[5] [6] [4] [6]

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Philips Semiconductors

1.5 Memory organization

07FFh

0700h

06FFh

0600h

05FFh

0500h

04FFh

0400h

03FFh

0300h

02FFh

0200h

01FFh

0100h

00FFh

000h

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

2 kB Flash code

memory space

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

UM10107

P89LPC915/916/917 User manual

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

FFh

80h

7Fh

00h

002aaa91

Fig 10. P89LPC915/916/917 memory map.

The various P89LPC915/916/917 memory spaces are as follows: DAT A — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or

indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDAT A — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC915/916/917 has 2 kB of on-chip Code memory.

Table 8: Data RAM arrangement

Type Data RAM Size (bytes)

DA TA Directly and indirectly addressab le memo ry 128 IDATA Indirectly addressable memory 256

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Page 29

Philips Semiconductors

2. Clocks

2.1 Enhanced CPU

The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definit ions

The P89LPC915/916/917 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of three clock

sources and can also be optionally divided to a slower frequency (see Figure 11

Section 2.8 “

OSCCLK frequency. CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is

P89LPC915/916/917 User manual

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

UM10107

and

is defined as the

osc

The P89LPC915/916/917 provides user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, or an external clock source.

2.3 Clock output (P89LPC917)

The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin. This allows external devices to synchronize to the P89LPC917. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

that of the CCLK. If the clock output is not needed

2.4 On-chip RC oscillator option

The P89LPC915/916/917 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, r 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC915/916/917 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

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Table 9: On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

Table 10: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During 1TRIM.1 2TRIM.2 3TRIM.3 4TRIM.4 5TRIM.5 6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK)

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reset, these bits are loaded wi th a stored factory calibra tion value. When w riting to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

is output on the XTAL2 pin provide d the cryst al osci llator is no t

being used.

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the P0.5 pin. The rate may be from 0 Hz up to 12 MHz.

RTCS1:0

CLKIN

OSCILLATOR

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

RCCLK

XCLK

OSCCLK

DIVM

PCLK

RCCLK

CCLK

÷2

PCLK

peripheral clock

RTC

CPU

ADC1/DAC1

WDT

CLKOUT

BAUD RATE

GENERATOR

UART

TIMERS 1 AND 0

I2C

SPI

(P89LPC916)

002aaa831

Fig 11. Block diagram of oscillator control.

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2.7 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it stabilizes. This delay is 224 OSCCLK cycles plus 60 Ps to 100 Ps.

2.8 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

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Where: f Since N ranges from 0 to 255, the CCLK frequency can be in the range of f

(for N =0, CCLK = f This feature makes it possible to temporarily run the CPU at a lower rate, reducing power

consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. The value of DIVM may be changed by the program at any time without interrupting code execution.

2.9 Low power select

The P89LPC915/916/917 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3. A/D converter

The P89LPC915/916/917 has an 8-bit, 4-channel, multiplexed successive approximation analog-to-digital converter module (ADC1) and one DAC module (DAC1). A block diagram of the A/D converter is shown in Figure 12 multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the successive approximation register (SAR) drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

CCLK frequency = f

is the frequency of OSCCLK, N is the value of DIVM.

osc

/ (2N)

to f

osc

. The A/D consists of a 4-input

osc

/510.

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Fig 12. A/D converter block diagram.

3.1 Features

• An 8-bit, 4-channel, multiplexed input, successive approximation A/D converter.

• Four A/D result registers.

• Six operating modes

– Fixed channel, single conversion mode – Fixed channel, continuous conversion mode – Auto sc an , sing le co nve r si on mode – Auto scan, continuous conversion mode – Dual ch anne l, con t in uou s con ve rsi on mode – Single step mode

• Three conversion start modes

– Timer triggered start – Start immediately – Edge triggered

• 8-bit conversion time of t 3.9 Ps at an ADC clock of 3.3 MHz

• Interrupt or polled operation

• Boundary limits interrupt

• DAC output to a port pin with high output impedance

• Clock divider

• Power-down mode

INPUT

MUX

COMP

–

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SAR

CONTROL

LOGIC

DAC1

CCLK

002aaa783

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3.2 A/D operating modes

3.2.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 11 conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCAN1 bit in the ADMODA register.

Table 11: Input channels and Result registers for fixed channel single, auto scan single,

Result register Input channel Result register Input channel

AD1DAT0 AD10 AD1DAT2 AD12 AD1DAT1 AD11 AD1DAT3 AD13

3.2.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers Table 12 enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCC1 bit in the ADMODA register.

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). An interrupt, if enabled, will be generated after the

and autoscan continuous conversion modes.

. An interr up t, i f

3.2.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 11

). An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. This mode is selected by setting the SCAN1 bit in the ADMODA register.

T able 12: Result registers and conversion results for fixed channel, c ontinuous convers ion

mode.

Result register Contains

AD1DAT0 Selected channel, first conversion result AD1DAT1 Selected channel, second conversion result AD1DAT2 Selected channel, third conversion result AD1DAT3 Selected channel, forth conversion result

3.2.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See

Table 11

converted. The process will repeat starting with the first selected channel. Additional

). An interrupt, if enabled, will be generated after all selected channels have been

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conversion results will again cycle through the result registers of the selected channels, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the BURST1 bit in the ADMODA register.

3.2.5 Dual channel, continuous conversion mode

Any combination of two of the four input channels can be selected for conversion. The result of the conversion of the first channel is placed in the first result register. The result of the conversion of the second channel is placed in the second result register. The first channel is again converted and its result stored in the third result register. The second channel is again converted and its result placed in the fourth result register (See

Table 13

conversions per channel). This mode is selected by setting the SCC1 bit in the ADMODA register.

Table 13: Result registers and conversion results for dual channel, continuous conversion

Result register Contains

AD1DA T 0 First channel, first conversion resul t AD1DAT1 Second channel, first conversion result AD1DAT2 First channel, second conversion resu lt AD1DAT3 Second channel, second conversion result

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). An interrupt is generated, if enabled, after every set of four conversions (two

mode.

3.2.6 Single step

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. The result of each channel is placed in the result register which corresponds to the selected input channel (See Table 11 mode is selected by clearing the BURST1, SCC1, and SCAN1 bits in the ADMODA register.

3.2.7 Conversion mode selection bits

The A/D uses three bits in ADMODA to select the conversion mode. These mode bits are summarized in Table 14 combinations shown, ar e undef ined.

Table 14: Conversion mode bits.

BURST1 SCC1 Scan1 ADC1 conversion

0 0 0 single step 0 0 0 single step 0 0 1 fixed channel,

0 1 0 fixed channel,

1 0 0 auto scan,

, below. Combinations of the three bits, other than the

mode

single auto scan, single auto scan, single

continuous dual channel,

continuous

). May be used with any of the start modes. This

BURST0 SCC0 Scan0 ADC0 conversion

mode

0 0 1 fixed channel,

single

0 1 0 fixed channel,

continuous dual channel,

continuous

1 0 0 auto scan,

continuous

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3.3 T rigger modes

3.3.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes. This mode is selected by the TMM1 bit and the ADCS11 and ADCS10 bits (See Table 16

3.3.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all A/D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 16

3.3.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 16

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3.3.4 Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

3.4 DAC output to a port pin with high impedance

The AD0DAT3 register is used to hold the value fed to the DAC. After a value has been written to AD0DAT3 the DAC output will appear on the DAC0 pin. The DAC output is enabled by the ENDAC0 bit in the ADMODB register (See Table 20

3.5 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose (See Table 20

3.6 I/O pins used with A/D converter functions

The analog input pins used with for the A/D converter have a digital input and output function. In order to give the best analog performance, pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected. Digital outputs are disabled by putting the port pins into the Input-only mode as described in the Port Configurations section (see Table 28

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Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A/D or DAC has been enabled. Pins selected in ADINS will be 3 V tolerant provided that the A/D is enabled and the device is not in power-down, otherwise the pin will remain 5 V tolerant.

3.7 Power-down and idle mode

In idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D.

Table 15: A/D Control register 1 (ADCON1 - address 97h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10

Reset00000000

Table 16: A/D Control register 1 (ADCON1 - address 97h) bit description

Bit Symbol Description

0 ADCS10 A/D start mode bits [11:10]: 1 ADCS11

2 ENADC1 Enable A/D channel 1. When set = 1, enables ADC1. Must also be

3 ADCI1 A/D Conversion complete Interrupt 1. Set when an y c onvers io n or

4 EDGE1 When = 0, an Edge conversion start is triggered by a falling edge

5 TMM1 Timer Trigger mode 1. Selects either stop mode (TMM1= 0) or

6 ENADCI1 Enable A/D Conversion com plete Interrupt 1. When s et, will ca use

7 ENBI1 Enable A/D boundary interrup t 1. Whe n set, will c ause a n inte rrupt

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00 — Timer T r igg er mo de whe n TM M1= 1. Conversions starts on

overflow of Timer 0. Stop mode when TMM1 = 0, no start occurs.

01 — Immediate Start mode. Conversions starts immediately. 10 — Edge Trigger mode. Conversion starts when edge condition

defined by bit EDGE1 occurs.

set for D/A operation of this channel.

set of multiple conversions has completed. Cleared by software.

on P1.4. When = 1, an Edge conversion start is trig gered by a rising edge on P1.4.

timer trigger mode (TMM1= 1) when the ADCS11 and ADCS10 bits = 00.

an interrupt if the ADCI1 flag is set and the A/D interrupt is enabled.

if the boundary i nte rrupt 1 flag, BNDI1, is set a nd the A/D i nterrupt is enabled.

Table 17: A/D Mode Register A (ADMODA - address C0h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol BNBI1 BURST1 SCC1 SCAN1 - - - Reset00000000

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Table 18: A/D Mode Register A (ADMODA - address C0h) bit description

Bit Symbol Description

0:3 - reserved 4 SCAN1 when = 1, selects single conv ers io n mod e (auto scan or fixed

5 SCC1 when = 1, selects fixed channel, continuous conversion mode for

6 BURST1 when = 1, selects auto scan, continuous conv ersion mode for

7 BNBI1 ADC1 boundary interrupt flag. Whe n set, indic ate s that the

Table 19: A/D Mode Register B (ADMODB - address A1h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol CLK2 CLK1 CLK0 - ENDAC1-- BSA1 -

Reset00000000

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channel) for ADC1

ADC1

converted result from ADC1 is ou t si de of the range defin ed by the ADC1 boundary registers

Table 20: A/D Mode Register B (ADMODB - address A1h) bit description

Bit Symbol Description

0 - reserved 1 BSA1 ADC1 Boundary Select All. When = 1, BNDI1 will be set if any

ADC1 input excee ds th e bo undary limits. Whe n= 0, BNDI1 will be

set only if the AD10 input exceeded the boundary limits. 2 - reserved 3 ENDAC1 When = 1 selects DAC mode for ADC1; when = 0 selects ADC

mode. 4 - reserved 5 CLK0 Clock divider to produce the ADC clock. Divides CCLK by the 6CLK1 7CLK2

value indicated be low. The resul ting ADC c lock shou ld be 3.3MHz

or less. A minimum of 0.5 MHz is required to ma intain A/D

accuracy. A/D start mode bits:

CLK2:0 — divisor

000 — 1

001 — 2

010 — 3

011 — 4

100 — 5

101 — 6

110 — 7

111 — 8

Table 21: A/D Input Select register (ADINS - address A3h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol AIN13 AIN12 AIN11 AIN10 - - - Reset00000000

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Table 22: A/D Input Select register (ADINS - address A3h) bit description

Bit Symbol Description

0:3 - reserved 4 AIN10 when set, enables the AD10 pin for sampling and conversion 5 AIN11 when set, enables the AD11 pin for sampling and conversion 6 AIN12 when set, enables the AD12 pin for sampling and conversion 7 AIN13 when set, enables the AD13 pin for sampling and conversion

4. Interrupts

The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC915/916/917’s many interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

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If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level. Table 24

summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the CPU from a Power-down mode.

4.1 Interrupt priority structure

Table 23: I nterrupt priority level

Priority bits IPxH IPx Interrupt priority level

0 0 Level 0 (lowest priority) 01Level 1 10Level 2 11Level 3

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0,1) and can therefore be assigned to one of four levels, as shown in Table 23

The P89LPC915/916/917 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

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These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn triggered. In this mode if consecutive samples of the INTn cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

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pin. If ITn = 1, external interrupt n is edge

pin show a high level in one

If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down or Idle mode, the interrupt occurrence will cause the processor to wake up and resume operation. Refer to Section 6.3 “

Power reduction modes” for details.

4.2 External Interrupt pin glitch suppression

Most of the P89LPC915/916/917 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC915/916/917 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0 the glitch suppression circuits. Therefore, INT1 not.

Table 24: Summary of interrupts - P89LPC915, P89LPC917

Description Interrupt flag

bit(s)

External interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0,IP0.0 1 (highest) Yes Timer 0 interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1,IP0.1 4 No External interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2,IP0.2 7 Yes Timer 1 interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3,IP0.3 10 No Serial port Tx and Rx TI and RI 0023h ES/ESR (IEN0.4) IP0H.4,IP0.4 13 No Serial port Rx RI Brownout detect BOF 002Bh EBO (IEN0.5) IP0H.5,IP0.5 2 Yes Watchdog timer/R e al-t im e

clock

C interrupt SI 0033h EI2C (IEN1.0) IP0H.0,IP0.0 5 No

I KBI interrupt KBIF 003Bh EKBI (IEN1.1) IP0H.0,IP0.0 8 Yes Comparators 1/2 interrupts CMF1/CMF2 0043h EC (IEN1.2) IP0H.0,IP0.0 11 Yes Serial port Tx TI 006Bh EST (IEN1.6) IP0H.0,IP0.0 12 No ADC ADCI1,BNDI1 0073h EAD (IEN1.7) IP1H.7,IP1.7 15 (lowest) No

WDOVF/RTCF 0053h EWDRT (IEN0.6) IP0H.6,IP0.6 3 Yes

Vector address

Interrupt enable bit(s)

/P1.3 and SCL/T0/P1.2 do not have

has glitch suppression while INT0 does

Interrupt priority

Arbitration ranking

Powerdown wake-up

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Table 25: Summary of interrupts - P89LPC916

Description Interrupt flag

bit(s)

External interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0,IP0.0 1 (highest) Yes Timer 0 interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1,IP0.1 4 No Timer 1 interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3,IP0.3 10 No Serial port Tx and Rx TI and RI 0023h ES/ESR (IEN0.4) IP0H.4,IP0.4 13 No Serial port Rx RI Brownout detect BOF 002Bh EBO (IEN0.5) IP0H.5,IP0.5 2 Yes Watchdog timer/R e al-t im e

clock

C interrupt SI 0033h EI2C (IEN1.0) IP0H.0,IP0.0 5 No

I KBI interrupt KBIF 003Bh EKBI (IEN1.1) IP0H.0,IP0.0 8 Yes Comparators 1/2 interrupts CMF1/CMF2 0043h EC (IEN1.2) IP0H.0,IP0.0 11 Yes SPI SPIF 004Bh ESP (IEN1.3) IP1H.3, IP1.3 1 4 No Serial port Tx TI 006Bh EST (IEN1.6) IP0H.0,IP0.0 12 No ADC ADCI1,BNDI1 0073h EAD (IEN1.7) IP1H.7,IP1.7 15 (lowest) No

WDOVF/RTCF 0053h EWDRT (IEN0.6) IP0H.6,IP0.6 3 Yes

Vector address

Interrupt enable bit(s)

Interrupt priority

Arbitration ranking

Powerdown wake-up

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(P89LPC915/917)

RTCF ERTC

(RTCCON.1)

WDOVF

(P89LPC916)

IE0

EX0

IE1

EX1

BOPD

EBO

KBIF EKBI

EWDRT

CMF2 CMF1

EA (IE0.7)

TF0 ET0

TF1 ET1

TI & RI/RI

ES/ESR

EST

EI2C

SPIF ESPI

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WAKE-UP (IF IN POWER-DOWN)

INTERRUPT TO CPU

ENADCI1

ADCI1

ENBI1 BNDI1

EAD

Fig 13. Interrupt sources, interrupt enables, and power-down wake up sources.

002aaa833

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5. I/O ports

The P89LPC915 has two I/O ports: Port 0 and Port 1. Ports 0 and 1 are 6-bit ports. The P89LPC916 has three I/O ports: Port 0, Port 1, and Port 2. Ports 0 is a 5-bit port, Port

1 is a 5-bit port and Port 2 is a 4-bit port. The P89LPC917 has three I/O ports: Port 0, Port 1, and Port 2. Ports 0 is a 7-bit port, Port

1 is a 6-bit port and Port 2 is a 1-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen

(see Table 26

Table 26: Number of I/O pins available - P89LPC915

Clock source Reset option Number of I/O

On-chip oscillator or watchdog oscillator

External clock input No external reset (except during power up) 11

and Table 27).

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pins

No external reset (except during power up) 12 External RST

External RST

pin supported 11

pin supported 10

Table 27: Number of I/O pins available - P89LPC916/917

Clock source Reset option Number of I/O

pins

On-chip oscillator or watchdog oscillator

External clock input No external reset (except during power up) 13

No external reset (except during power up) 14 External RST

External RST

pin supported 13

pin supported 12

5.1 Port configurations

All but three I/O port pins on the P89LPC915/916/917 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 28 quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

P1.5 (RST P1.2 (SCL/T0) and P1.3 (SDA/INT0

) can only be an input and cannot be configured.

) may only be configured to be either input-only or

open drain.

Table 28: Port output configuration settings

PxM1.y PxM2.y Port output mode

0 0 Quasi-bidirectional 01Push-pull 1 0 Input only (high impedance) 1 1 Open drain

. These are:

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5.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

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The quasi-bidirectional port configuration is shown in Figure 14 Although the P89LPC915/916/917 is a 3 V device most of the pins are 5 V-tolerant. If 5 V

is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC915/916/917 data sheet, Dynamic characteristics for glitch filter specifications).

causing extra power consumption. Therefore, applying 5 V to pins

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port latch

data

Fig 14. Quasi-bidirectional output.

5.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

The open drain port configuration is shown in Figure 15

2 CPU

CLOCK DELAY

PP P

input

data

very

weak

weakstrong

glitch rejection

port

002aaa914

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC915/916/917 data sheet, Dynamic characteristics for glitch filter spec ifications)

port

port latch

data

input

data

glitch rejection

002aaa915

Fig 15. Open drain output.

5.4 Input-only configuration

The input port configuration is shown in Figure 16. It is a Schmitt-triggered input that also has a glitch suppression circuit.

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(Please refer to the P89LPC915/916/917 data sheet, Dynamic characteristics for glitch filter specifications).

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input

data

glitch rejection

port

002aaa916

Fig 16. Input only.

5.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 17 A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit. (Please refer to the P89LPC915/916/917 data sheet, Dynamic characteristics for glitch

filter specifications).

strong

port

port latch

data

input

data

glitch rejection

002aaa917

Fig 17. Push-pull output.

5.6 Port 0 analog functions

The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port pins into the Input-only mode as described in the Por t Configur ations section (see Figure 16

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Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively. Setting the corresponding bit in PT0AD disables that pin’s digital input. Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port.

On any reset, PT0AD bits 1 through 5 default to 0’s to enable the digital functions.

5.7 I/O pins used with analog functions

After power-up, all pins are in Input-only mode. Please note that this is different from the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be configured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or

open drain.

Every output on the P89LPC915/916/917 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC915/916/917 data sheet for detailed specifications.

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All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

Table 29: Port output configuration

Port pin Configuration SFR bits

PxM1.y PxM2.y Alternate usage Notes

P0.0 P0M1.0 P0M2.0 KBIO, CMP2 P0.1 P0M1.1 P0M2.1 KBI1, CIN2B, AD10 Refer to Section 5.6 “ P0.2 P0M1.2 P0M2.2 KBI2, CIN2A, AD11 P0.3 P0M1.3 P0M2.3 KBI3, CIN1B, AD12 P0.4 P0M1.4 P0M2.4 KBI4, CIN1A, AD13,

DAC1 P0.5 P0M1.5 P0M2.5 KBI5, CMPREF P0.7 P0M1.7 P0M2.7 KBI7, T1 P1.0 P1M1.0 P1M2.0 TxD P1.1 P1M1.1 P1M2.1 RxD P1.2 P1M1.2 P1M2.2 T0, SCL input-only or open-drain P1.3 P1M1.3 P1M2.3 INTO, SDA input-only or open-drain P1.4 P1M1.4 P1M2.4 INT1 P1.5 P1M1.5 P1M2.5 RST P2.2 P2M1.2 P2M2.2 MOSI P2.3 P2M1.3 P2M2.3 MISO P2.4 P2M1.4 P2M2.4 SS P2.5 P2M1.5 P2M2.5 SPICLK

analog functions” for usage as

analog inputs.

Port 0

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6. Power monitoring functions

The P89LPC915/916/917 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.

6.1 Brownout detection

The Brownout Detect function determines if the power supply voltage drops below a certain level. The default operation for a Brownout Detection is to cause a processor reset. However, it may alternatively be configured to generate an interrupt by setting the BOI (PCON.4) bit and the EBO (IEN0.5) bit.

Enabling and disabling of Brownout Detection is done via the BOPD (PCON.5) bit, bit field PMOD1/0 (PCON[1:0]) and user configuration bit BOE (UCFG1.5). If BOE is in an unprogrammed state, brownout is disabled regardless of PMOD1/0 and BOPD. If BOE is in a programmed state, PMOD1/0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled. PMOD1/0 is used to select the power reduction mode. If PMOD1/0 = ‘11’, the circuitry for the Brownout Detection is disabled for lowest power consumption. BOPD defaults to logic 0, indicating brownout detection is enabled on power-on if BOE is programmed.

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If Brownout Detection is enabled, the operating voltage range for V and the brownout condition occurs when V

falls below the Brownout trip voltage, VBO

(see P89LPC915/916/917 data sheet, Static characteristics), and is negated when V rises above V

. If Brownout Detection is disabled, the operating voltage range for VDD is

is 2.7 V to 3.6 V,

2.4 V to 3.6 V. If the P89LPC915/916/917 device is to operate with a power supply that can be below 2.7 V , BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

If Brownout Detect is enabled (BOE programmed, PMOD1/0 z ‘11’, BOPD = 0), BOF (RSTSRC.5) will be set when a brownout is detected, regardless of whether a reset or an interrupt is enabled, BOF will stay set until it is cleared in software by writing logic 0 to the bit. Note that if BOE is unprogrammed, BOF is meaningless. If BOE is programmed, and a initial power-on occurs, BOF will be set in addition to the power-on flag (POF RSTSRC.4).

For correct activation of Brownout Detect, certain V

rise and fall times must be

observed. Please see the P89LPC915/916/917 data sheet f or specifications

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Ta ble 30: Brownout options

BOE (UCFG1.5)

0 (erased) XX X X X X Brownout disabled. V 1

(programmed)

PMOD1/0 (PCON[1:0])

11 (total power-down)

z11 (any mode other than total power-down

BOPD (PCON.5)

XXXX

1(brownout detect powered down)

0 (brownout detect active)

BOI (PCON.4)

X X X Brownout disabled. V

0 (brownout detect generates reset)

1 (brownout detect generates an interrupt)

EBO (IEN0.5)

X X Brownout reset enabled. V

1 (enable brownout interrupt)

0 X Both brownout reset and X0

EA (IEN0.7) Description

1 (global interrupt enable)

operating range is 2.4 V to

3.6 V.

operating range is 2.4 V to

3.6 V. However, BOPD is default to logic 0 upon power-up.

operating range is 2.7 V to

3.6 V . Upon a br ownout reset, BOF (RSTSRC.5) will be set to indicate the reset source. BOF can be cleared by writing logic 0 to the bit.

Brownout interrupt enabled.

operating range is 2.7 V

to 3.6 V. Upon a brownout interrupt, BOF (RSTSRC.5) will be set. BOF can be cleared by writing logic 0 to the bit.

interrupt disabled. V operating range is 2.4 V to

3.6 V. However, BOF (RSTSRC.5) will be set when

falls to the Brownout

Detection trip point. BOF can be cleared by writing logic 0 to the bit.

6.2 Power-on detection

The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function. The POF flag (RSTSRC.4) is set to indicate an initial power-on condition. The POF flag will remain set until cleared by software by writing logic 0 to the bit. Note that if BOE (UCFG1.5) is programmed, BOF (RSTSRC.5) will be set when POF is set. If BOE is unprogrammed, BOF is meaningless.

6.3 Power reduction modes

The P89LPC915/916/917 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Table 31

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Table 31: Power reduction modes

PMOD1 (PCON.1)

0 0 Normal mode (default) - no power reduction. 0 1 Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the

1 0 Power-down mode:

PMOD0 (PCON.0)

Description

processor when an inte rrupt is generate d. Any en abled in terrupt s ource o r rese t may te rminat e Idle mode.

The P89LPC915/916/917 exits Power-down mod e via any res et, or cert ain interru pts - ex ternal pins

, INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and

INT0 comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabl ed if the corres po ndi ng in terru pt is enabled and the EA SFR bit (IEN0.7) is set.

In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V wake up the processor via Reset in this situation. V before the Power-down mode is exited.

When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin executio n wh en the osc illato r is sta ble. Osci ll ator s tabi lity is d eter mined by cou nti ng 25 6 CPU clocks after start-up for the internal RC or external clock input configurations.

Some chip functions c ontinu e to ope rate and draw po wer du ring Powe r-down mode, i ncreasin g the total power used during power-down. These include:

has been lowered to VRAM, therefore it is recommended to

must be raised to within the operating range

• Brownout Detect

• Watchdog timer if WDCLK (WDCON.0) is logic 1.

• Comparators (Note: Comparators can be powered down separately with PCONA.5 set to

logic 1 and comparators disabled);

• Real-time Clock/System Timer ( unless RTCPD, i.e., PCONA.7 is logic 1).

1 1 Total Power-d own mode: This is the same as Power-down mode except that t he Brownout

Detection circuitry and the voltage comparators are also disabled to conserve additional power. Note that a brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

The following are the wake-up options supported:

• Watchdog timer if WDCLK (W DCON.0) is lo gic 1. Could generate Interrupt or Reset, eit her one

can wake up the device

• External interrupts INTO/INT1

• Keyboard Interrupt

• Real-time Clock/System Timer ( unless RTCPD, i.e., PCONA.7 is logic 1).

Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock is running during power-down.

Table 32: Power Control register (PCON - address 87h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 Reset00000000

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Table 33: Power Control register (PCON - address 87h) bit description

Bit Symbol Description

0 PMOD0 Power Reduction mode (see Section 6.3 1PMOD1 2 GF0 General Purpose Flag 0. May b e read or written by user software , but has no

3 GF1 General Purpose Flag 1. May b e read or written by user software , but has no

4 BOI Brownout Detect Interrupt Enable. When logic 1 , Brownout Detection will

5 BOPD Brownout Detect Power-down. When logic 1, Brownout Detect is powered

6 SMOD0 Framing Error Location:

7 SMOD1 Double Baud Rate bit for the se rial port (UAR T) when T ime r 1 is used as the

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effect on operation

generate a interrupt. When logic 0, Brownout Detection will cause a reset

down and therefore disabled. When logic 0, Brownout Detect is enabled. (Note: BOPD must be logic 0 before any programming or erasing command s can be issued. Otherwise these com m and s wi ll be aborted .)

• When logic 0, bit 7 of SCON is accessed as SM0 for the UART.

• When logic 1, bit 7 of SCON is accessed as the framing error status

(FE) for the UART

baud rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When logic 0, the Ti mer 1 o verflow rate is divi ded by two before bei ng supplied to the UART. (See Section 10

)

Table 34: Power Control register A (PCONA - address B5h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RTCPD - VCPD - I2PD - SPD Reset00000000

Table 35: Power Control register A (PCONA - address B5h) bit description

Bit Symbol Description

0 - reserved 1 SPD Serial Port (UART) Power-down: When logic 1, the internal clock

to the UART is disabled. Note that in either Power-down mode or Total Power-down mode, the UART clock will be disabled regardless of this bit.

2 - reserved

3I2PDI

4 - reserved 5 VCPD Analog Voltage Comparators Power-down: When logic 1, the

6 - reserved 7 RTCPD Real-time Clock Power-down: When logic 1, the internal clock to

C Power-down: When logic1, the internal clock to the I2C-bus is disabled. Note that in either Power-down mode or Total Power-down mode, the I bit.

voltage comparators are powered down. User must disable the voltage compa rato r s prio r to settin g this bit.

the Real-time Clock is disabled .

C clock will be disab led regardless of this

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7. Reset

The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Note: During a power-on sequence, The RPE selection is overridden and this pin will always functions as a reset input. An external circuit connected to this pin should not hold this pin low during a Power-on sequence as this will keep the device in reset. After power-on this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-on reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.

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Note: During a power cycle, V

must fall below V

(see P89LPC915/916/917 data

POR

sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset.

Reset can be triggered from the following sources (see Figure 18

• External reset pin (during power-on or if user configured via UCFG1);

• Power-on Detect;

• Brownout Detect;

• Watchdog timer;

• Software reset;

• UART break detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are

cleared.

• For any other reset, any previously set flag bits that have not been cleared will remain

set.

RPE (UCFG1.6)

RST pin

WDTE (UCFG1.7)

Watchdog timer reset

Software reset SRST (AUXR1.3)

Power-on detect

UART break detect

EBRR (AUXR1.6)

Brownout detect reset

BOPD (PCON.5)

Fig 18. Block diagram of reset.

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Table 36: Reset Sources register (RSTSRC - address DFh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - - BOF POF R_BK R_WD R_SF R_EX

[1]

Reset

[1] The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

Table 37: Reset Sources register (RSTSRC - address DFh) bit description

Bit Symbol Description

0 R_EX external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared

1 R_SF software reset Flag. Cleared by software by writing a logic 0 to the bit or a

2 R_WD Watchdog timer reset flag. Cleared by software by writing a logic 0 to the bit or a

3 R_BK break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1,

4 POF Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to

5 BOF Brownout Detect Flag. When Brownout Detect is activated, this bit is set. It will

6:7 - reserved

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xx110000

by software by writing a logic 0 to the bit or a Power-on reset. If RST asserted after the Power-on reset is over, R_EX will be set.

Power-on reset

Power-on reset. (Note: UCFG1.7 must be = 1)

a system reset will occur. This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a logic0 to the bit or on a Power-on reset.

indicate an initial power-up condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)

remain set until cleared by software by writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag bits are cleared.)

is still

7.1 Reset vector

Following reset, the P89LPC915/916/917 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address =00h. The Boot address will be used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1.

8. Timers 0 and 1

The P89LPC915/916/917 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1. Both timers of the P89LPC917 can be configured to operate either as timers or event counters (see Table 39 P89LPC915 and P89LPC916 can be configured to operate either as a timer or an event counter (see Table 39

). Timer 1 of the P89LPC915 and P89LPC916 devices may only

function as a timer. An option to automatically toggle the Tx pin upon timer overflow has been added. In the ‘Timer’ function, the timer is incremented every PCLK.

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). Timer 0 of the

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In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition on its corresponding external input pin, T0, or T1 (P89LPC917). The external input is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycle s (4 CPU cl ocks) t o recogn ize a 1- to-0 tra nsitio n, the maximum c ount ra te is

of the CPU clock frequency. There are no restrictions on the duty cycle of the external

input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

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The ‘Timer’ or ‘Counter’ function is selected by control bits TnC/T

(x = 0 and 1 for Timers 0 and 1 respectively) in the Special Function Register TMOD. Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6), which are selected by bit-pairs (TnM1, TnM0) in TMOD and TnM2 in TAMOD. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different. The operating modes are described later in this section.

Table 38: Timer/Counter Mode register (TMOD - address 89h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol T1GATE T1C/T Reset00000000

Table 39: Timer/Counter Mode register (TMOD - address 89h) bit description

Bit Symbol Description

0 T0M0 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD 1T0M1 2T0C/T

3 T0GATE Gating control for Timer 0. When set, Timer/Counter is enabled only while the

4 T1M0 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD 5T1M1 6T1C/T

7 T1GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the

register to determine the Timer 0 mode (see Table 41 Timer or Counter selector for Timer 0. Cleared for Timer operation (input from

CCLK). Set for Counter operation (input from T0 input pin).

pin is high and the TR0 control pin is set. When cleared, Timer 0 is enabled

INT0 when the TR0 control bit is set.

register to determine the Timer 1 mode (see Table 41 Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from

CCLK). Set for Counter operation (input from T1 input pin).

pin is high and the TR1 control pin is set. When cleared, Timer 1 is enabled

INT1 when the TR1 control bit is set.

T1M1 T1M0 T0GATE T0C/T T0M1 T0M0

Table 40: Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol---T1M2---T0M2 Resetxxx0xxx0

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Table 41: Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description

Bit Symbol Description

0 T0M2 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD

1:3 - reserved 4 T1M2 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD

5:7 - reserved

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000 — 8048 Timer ‘TLn’ serves as 5-bit prescaler. (Mode 0) 001 — 16-bit Timer/Counter ‘THn’ and ‘TLn’ are cascaded; there is no prescaler.

(Mode 1) 010 — 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into

TLn when it overflows. (Mode 2) 011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit

Timer/Coun ter controll ed by the s tanda rd T imer 0 co ntrol bit s. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text). Timer 1 in this mode is stopped. (Mode 3)

100 — Reserved. User must not configure to this mode. 101 — Reserved. User must not configure to this mode. 110 — PWM mode (see Section8.5 111 — Reserved. User must not configure to this mode.

). P89LPC917.

8.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 19

shows Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either TnGATE = 0 or INTn Timer to be controlled by external input INTn

, to facilitate pulse width measurements).

TRn is a control bit in the Special Function Register TCON (Table 43

= 1. (Setting TnGATE = 1 allows the

). The TnGATE bit is

in the TMOD register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3

bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1. See Figure 19

. There are two

different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

8.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 20

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8.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 21 contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

8.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for

Mode 3 on Timer 0 is shown in Figure 22 T0GATE, TR0, INT0 cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC915/916/917 device can look like it has three Timer/Counters.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

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. Overflow from TLn not only sets TFn, but also reloads TLn with the

. TL0 uses the Timer 0 control bits: T0C/T,

, and TF0. TH0 is locked into a timer function (counting machine

8.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks (see Figure 23

). Its structure is similar to Mode 2, except that:

• TFn (n = 0 and 1 for Timers 0 and 1 respectively) is set and cleared in hardware;

• The low period of the TFn is in THn, and should be between 1 and 254, and;

• The high period of the TFn is always 256THn.

• Loading THn with 00h will force the Tx pin high, loading THn with FFh will force the Tx

pin low.

Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn can still be cleared in software like in any other modes. This mode is available on Timer 0 on the P89LPC915/916/917 devices and Timer 1 on the P89LPC917 device.

Table 42: Timer/Counter Control register (TCON) - address 88h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Reset00000000

Table 43: Timer/Counter Control register (TCON - address 88h) bit description

Bit Symbol Description

0 IT0 Interrupt 0 Ty pe control bit. Set/cleared by software to specify falling edge/low

level triggered external interrupts.

1 IE0 Interrupt 0 Edge flag. Set by hardw ar e w hen e xte rnal in terru pt 0 edge is detected.

Cleared by hardware when the interrupt is processed, or by software.

2 IT1 Interrupt 1 Ty pe control bit. Set/cleared by software to specify falling edge/low

level triggered external interrupts (P89LPC915/917)

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Table 43: Timer/Counter Control register (TCON - address 88h) bit description

Bit Symbol Description

3 IE1 Interrupt 1 Edge flag. Set by hardw ar e w hen e xte rnal in terru pt 1 edge is detected.

4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. 5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by

6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off 7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by

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Cleared by hardware when the interrupt is processed, or by software (P89LPC915/917)

hardware when the processor vectors to the interrupt routine, or by software. (except in Mode 6, where it is cleared in hardware)

hardware when the interrupt is processed, or by software (except in Mode 6, see above, when it is cleared in hardware).

PCLK

Tn pin

TRn

Gate

INTn pin

C/T = 0

C/T = 1

control

Fig 19. Timer/counter 0 or 1 in Mode 0 (13-bit counter).

PCLK

Tn pin

TRn

Gate

INTn pin

C/T = 0

C/T = 1

control

Fig 20. Timer/counter 0 or 1 in Mode 1 (16-bit counter).

TLn

(5-bits)

TLn

(8-bits)

THn

(8-bits)

THn

(8-bits)

overflow

toggle

overflow

toggle

TFn

ENTn

002aaa919

TFn

ENTn

002aaa920

interrupt

Tn pin

interrupt

Tn pin

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PCLK

Tn pin

TRn

Gate

INTn pin

C/T = 0

C/T = 1

control

Fig 21. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload).

PCLK

T0 pin

TR0

Gate

INT0 pin

C/T = 0

C/T = 1

Osc/2

control

(8-bits)

TL0

(8-bits)

TH0

(8-bits)

TLn

THn

reload

overflow

toggle

overflow

toggle

overflow

TFn

ENTn

002aaa921

TF0

ENT0

(AUXR1.4)

TF1

interrupt

Tn pin

interrupt

T0 pin

(P1.2 open drain)

interrupt

TR1

Fig 22. Timer/counter 0 Mode 3 (two 8-bit counters).

C/T = 0

PCLK

control

TRn

Gate

INTn pin

Fig 23. Timer/counter 0 or 1 in Mode 6 (PWM auto-reload).

8.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs and PWM outputs are also used for the timer toggle outputs. This function is enabled by

toggle

TLn

(8-bits)

THn

(8-bits)

overflow

reload THn on falling transition

and (256-THn) on rising transition

toggle

ENT1

(AUXR1.5)

TFn

ENTn

002aaa923

T1 pin (P0.7)

002aaa92

interrupt

Tn pin

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control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting PCLK as the clock source for the timer. Timer 1 toggle output is available only on the P89LPC917 device. Timer 0 toggle output is available on the P89LPC9 15, P89 LPC 9 16, and P89LPC917 devices.

9. Real-time clock system timer

The P89LPC915/916/917 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time Clock can be an interrupt or a wake-up source (see Figure 24

The Real-time Clock is a 23-bit down counter. The clock source for this counter can be either the CPU clock (CCLK) or an external clock input. There are three SFRs used for the RTC:

RTCCON — Real-time Clock control. RTCH — Real-time Clock counter reload high (bits 22 to 15). RTCL — Real-time Clock counter reload low (bits 14 to 7).

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The Real-time clock system timer can be enabled by setting the RTCEN (RTCCON.0) bit. The Real-time Clock is a 23-bit down counter (initialized to all 0’s when RTCEN = 0) that is comprised of a 7-bit prescaler and a 16-bit loadable down counter. When RTCEN is written with logic 1, the counter is first loaded with (RTCH,RTCL,‘1111111’) and will count down. When it reaches all 0’s, the counter will be reloaded again with (RTCH,RTCL,’1111111’) and a flag - RTCF (RTCCON.7) - will be set.

RTCH RTCL RTC Reset

Reload on underflow

MSB LSB

23-bit down counter

Wake-up from power-down

Interrupt if enabled (shared with WDT)

ERTC

RTCF

RTC underflow flag

Power-on

reset

7-bit prescaler

÷128

RTCEN

RTC enable

XTAL2 XTAL1

LOW FREQ. MED. FREQ.

HIGH FREQ.

CCLK

internal

oscillators

RTCS1 RTCS2

RTC clk select

002aaa92

Fig 24. Real-time clock/system timer block diagram.

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9.1 Real-time clock so ur ce

RTCS1/RTCS0 (RTCCON[6:5]) are used to select either the external clock input or CCLK as the clock source for the RTC, if either the Internal RC oscillator or the internal WD oscillator is used as the CCLK. If CCLK is derived from the external clock input on P0.5 then the RTC can use CCLK (external clock input/DIVM) or the external input as its clock source.

9.2 Changing RTCS1/RTCS0

RTCS1/RTCS0 cannot be changed if the RTC is currently enabled (RTCCON.0 = 1). Setting RTCEN and updating RTCS1/RTCS0 may be done in a single write to RTCCON. However, if RTCEN = 1, this bit must first be cleared before updating RTCS1/RTCS0.

9.3 Real-time clock interrupt/ wak e-up

If ERTC (RTCCON.1), EWDRT (IEN1.0.6) and EA (IEN0.7) are set to logic 1 RTCF can be used as an interrupt source. This interrupt vector is shared with the watchdog timer. It can also be a source to wake up the device.

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9.4 Reset sources affecting the Real-time clock

Only power-on reset will reset the Real-time Clock and its associated SFRs to their default state.

Table 44: Real-time Clock/System Timer clock sources

FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source

000 x xx undefined undefined 001 010 011 0 00 External clock input Internal RC oscillator /

01 10 11 I nter nal R C oscil lat or / D IVM

1 00 External clock input Internal RC oscillator

01 10 11 Internal RC oscillator

100 0 00 External clock input Watchdog oscillator

01 10 11 Watchdog oscillator /DIVM

1 00 External clock input Internal RC oscillator

01 10

11 Internal RC oscillator 101 x xx undefined undefined 110

DIVM

/DIVM

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Table 44: Real-time Clock/System Timer clock sources

FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source

111 0 00 External clock input External clock input/DIVM

Table 45: Real-time Clock Control register (RTCCON - address D1h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RTCF RTCS1 RTCS0 - - - ERTC RTCEN Reset011xxx00

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11 External clock input /DIVM

1 00 External clock input Internal RC oscillator

11 Internal RC oscillator

10. UART

Table 46: Real-time Clock Control register (RTCCON - address D1h) bit description

Bit Symbol Description

0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic1.

Note that this bit will not power-down the Real-time Clock. The RTCPD bit (PCONA.7) if set, will power-down and disable this block regardless of RTCEN.

1 ERTC Real-time Clock interrupt enable. The Real-time Clock shares the same interrupt

as the watchdog timer. Note that if the user configuration bit WDTE (UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an interrupt. Users can read the RTCF (RT C CON.7 ) bit to dete rmi ne w he the r the Rea l-ti me Clock ca use d

the interrupt. 2:4 - reserved 5 RTCS0 Real-time Clock source select (see Table 44 6RTCS1 7 RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock

reaches a count of logic 0. It can be cleared in software.

The P89LPC915/916/917 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC915/916/917 does include an independent Baud Rate Generator. The baud rate can be selected from CCLK (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering and several interrupt options.

The UART can be operated in four modes, as described in the following sections.

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10.1 Mode 0

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Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at frequency.

10.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see Section 10.6 “

generator and selection” on page 62.

10.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved. The baud rate is programmable to either determined by the SMOD1 bit in PCON.

10.4 Mode 3

1 1 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see Section 10.6

“Baud Rate generator and selection” on page 62.

of the CPU clock

Baud Rate

of the CCLK frequency, as

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.

10.5 SFR sp ac e

The UART SFRs are at the following locations:

Table 47: UART SFR addresses

PCON Power Control 87H SCON Serial Port (UART) Control 98H SBUF Serial Port (UART) Data Buffer 99H SADDR Serial Port (UART) Address A9H SADEN Serial Port (UART) Address Enable B9H SSTAT Serial Port (UART) Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGR0 Baud Rate Generator Rate Low Byte BEH BRGCON Baud Rate Generator Control BDH

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10.6 Baud Rate generator and selection

The P89LPC915/916/917 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON[2:1] (see Figure 25 (PCON.7) is set. Th e independent Baud Rate Generator uses CCLK .

10.7 Updating the BRGR1 and BRGR0 SFRs

The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate Generator is disabled (the BRGEN bit in the BRGCON register is logic 0). This avoids the loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0 or

BRGR1 is written when BRGEN = 1, the result is unpredictable.)

Table 48: UART baud rate generation.

SCON.7 (SM0)

00XX 0100

100X

1100

SCON.6 (SM1)

). Note that Timer T1 is further divided by 2 if the SMOD1 bit

PCON.7 (SMOD1)

10 X1

BRGCON.1 (SBRGS)

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Receive/transmit baud rate for UART

CCLK

(256TH1)64

CCLK

(256TH1)32

CCLK

((BRGR1, BRGR0)+16)

CCLK

(256TH1)64

CCLK

(256TH1)32

CCLK

((BRGR1, BRGR0)+16)

Table 49: Baud Rate Generator Control register (BRGCON - address BDh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - - - - - - SBRGS BRGEN Resetxxxxxx00

Table 50: Baud Rate Generator Control register (BRGCON - address BDh) bit description

Bit Symbol Description

0 BRGEN Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and

BRGR0 can only be written when BRGEN =0.

1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and

3 (see Table 48

for details)

2:7 - reserved

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

÷2

SMOD1 = 1

SMOD1 = 0

SBRGS = 0

Baud Rate Modes 1 and 3

SBRGS = 1

002aaa419

Fig 25. Baud rate generation for UART (Modes 1, 3).

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10.8 Framing error

A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0.

10.9 Break detect

A break detect is reported in the status register (SSTA T). A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the UART will go into an idle state and remain in this idle state until a stop bit has been received. The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit (AUXR1.6)

Table 51: Serial Port Control register (SCON - address 98h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SM0/FE SM1 SM2 REN TB8 RB8 T I RI Resetxxxxxx00

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Table 52: Serial Port Control register (SCON - address 98h) bit description

Bit Symbol Description

0 RI Receive interrupt flag. Set by hardwa re at t he e nd o f the 8th bit time in Mode 0, or

approximately halfw ay thro ugh the stop b it tim e in Mo de 1. Fo r Mode 2 or Mo de 3,

if SMOD0, it is set near the m iddle of the 9t h dat a bit (bit 8 ). If SMOD0= 1, it is set

near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be

cleared by software. 1 TI Transmit interrupt flag. Set by hardwa re at the e nd of the 8th bit t ime in Mode 0 , or

at the stop bit (see descriptio n of INTLO bi t in SSTAT register) in the other m odes.

Must be cleared by software. 2 RB8 The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0),

RB8 is the stop bit that was received. In Mode 0, RB8 is undefined. 3 TB8 The 9th data bit that will be transmitted in Mo des 2 and 3. Set or clear by so ftware

as desired. 4 REN Enables serial reception. Set by softw are to enab le receptio n. Clear by sof tware to

disable reception. 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2

or 3, if SM2 is set to logic 1, then Rl will not be activated if the received 9th data bit

(RB8) is 0. In Mode 0, SM2 should be 0. In Mode 1, SM2 must be 0. 6 SM1 With SM0 defines the Serial port mode, see Table 53 7 SM0/FE The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0,

this bit is read and written as SM0, which with SM1, defines the Serial port mode.

If SMOD0 = 1, this bit is read and written as FE (Framing Error). FE is set by the

receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared

by valid frames but is cleared by software. (Note: UART mode bits SM0 and SM1

should be programmed when SMOD0 is logic 0 - default mode on any reset.)

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Table 53: Serial Port modes

SM0,SM1 UART mode UART baud rate

00 Mode 0: shift register 01 Mode 1: 8-bit UART Variable (see Table 48 10 Mode 2: 9-bit UART 11 Mode 3: 9-bit UART Variable (see Table 48)

Table 54: Serial Port Status register (SSTAT - address BAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol DBMOD INTLO CIDIS DBISEL FE BR OE STINT Resetxxxxxx00

Table 55: Serial Port Status register (SSTAT - address BAh) bit description

Bit Symbol Description

0 STINT Status Interrupt Enable. When set= 1, FE, BR, or OE can cause an interrupt. The

1 OE Overrun Error fl ag is set if a ne w character is received in the receiver bu ffer wh ile it

2 BR Break Detect flag. A break is detected when any 11 consecutive bits are sensed

3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end

4 DBISEL Double buffering transm it in terrupt selec t. Used only if do uble b uf feri ng is en abled.

5 CIDIS Combined Interrupt Disable. When set = 1, Rx and Tx interrupts are separate.

6 INTLO Transmit interrupt position. When cleared = 0, the Tx interrupt is issued at the

7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be logic 0 for

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CCLK

(default mode on any reset)

)

CCLK

interrupt used (vector address 0023h) is shared with RI (CIDIS = 1) or the

combined TI/RI (CIDIS = 0). When cleared = 0, FE, BR, OE cannot cause an

interrupt. (Note: FE, BR, or OE is often accompanied by a RI, which will generate

an interrupt regardless of the state of STINT). Note that BR can cause a break

detect reset if EBRR (AUXR1.6) is set to logic 1.

is still full (before the software has read the previous character from the buffer),

i.e., when bit 8 of a new byte is received while RI in SCON is still set. Cleared by

software.

low. Cleared by software.

of the frame. Cleared by software.

This bit controls the number of interrupts that can occur when double buffering is

enabled. When set, one transmi t interrupt is generated af ter each charac ter written

to SBUF, and there is also one more transmit interrupt generated at the beginni ng

(INTLO = 0) or the end (INTLO= 1) of the STOP bit of the la st c hara cter s en t (i .e.,

no more data in buffer). This last interrupt can be used to indicate that all transmit

operations are over. When cleared = 0, only one transmit interrupt is generated

per character written to SBUF. Must be logic 0 when double buffering is disabled.

Note that except for the first character written (when buffer is empty), the location

of the transmit interrupt is determined by INTLO. When the first character is

written, the transmit interrupt is generated immediately after SBUF is written.

When cleared = 0, the UART uses a combine d Tx/Rx interru pt (lik e a c onven tional

80C51 UART). This bit is reset to logic 0 to select combined interrupts.

beginning of the stop bit . When set = 1, the Tx interrupt is issued at end of the sto p

bit. Must be logic0 for mode 0. Note that in the case of single buffering, if the Tx

interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit.

UART mode 0. In order to be compatible with existing 80C51 devices, this bit is

reset to logic 0 to disable double buffering.

CCLK

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10.10 More about UART Mode 0

In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI (SCON.1) is set, which must be cleared in software. Double buffering must be disabled in this mode.

Reception is initiated by clearing RI (SCON.0). Synchronous serial transfer occurs and RI will be set again at the end of the transfer. When RI is cleared, the reception of the next character will begin. Refer to Figure 26

write to

SBUF

shift

RXD (data out)

TXD (shift clock)

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S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16S1 ... S16S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16S1 ... S16S1 ... S16 S1 ... S16

transmit

D0 D1 D5D2 D6D3 D4 D7

WRITE to SCON

(clear RI)

shift

RXD

(data in)

TxD (shift clock)

D0 D1 D5D2 D6D3 D4 D7

Fig 26. Serial Port Mode 0 (double buffering must be disabled).

10.11 More about UART Mode 1

Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampled at a rate 16 times the programmed baud rate. When a transition is detected, the divide-by-16 counter is immediately reset. Each bit time is thus divided into 16 counter states. At the 7th, 8th, and 9th counter states, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the receiver goes back to looking for another 1-to-0 transition. This provides rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0 and either SM2=0 or the received stop bit = 1. If either of these two conditions is not met, the received frame is lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated.

receive

002aaa92

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TX clock

write to

SBUF

shift

TxD

clock

RxD

shift

÷16 reset

Fig 27. Serial Port Mode 1 (only single transmit buffering case is shown).

start

bit

D0 D1 D5D2 D6D3 D4 D7

start

D0 D1 D5D2 D6D3 D4 D7

bit

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P89LPC915/916/917 User manual

transmit

stop bit

INTLO = 0

INTLO = 1

stop bit

receive

002aaa92

TX clock

write to

SBUF

shift

TxD

clock

RxD

shift

10.12 More about UART Modes 2 and 3

Reception is the same as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the

following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF.

start

÷16 reset

D0 D1 D5D2 D6D3 D4 D7

bit

start

D0 D1 D5D2 D6D3 D4 D7

bit

TB8

stop bit

INTLO = 0 INTLO = 1

RB8

stop bit

SMOD0 = 0 SMOD0 = 1

transmit

receive

002aaa92

Fig 28. Serial Port Mode 2 or 3 (only single transmit buffering case is shown).

10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1

If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table.

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Table 56: FE and RI when SM2= 1 in Modes 2 and 3.

Mode PCON.6

2 0 0 No RI when RB8 = 0 Occurs during STOP

3 1 0 No RI when RB8 = 0 Will NOT occur

10.14 Break detect

A break is detected when 11 consecutive bits are sensed low and is reported in the status register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit times. For Modes 2 and 3, this consists of the start bit, 9 data bits, and one stop bit. The break detect bit is cleared in software or by a reset. The break detect can be used to force the device to execute code using the Boot vector. This occurs if the UART is enabled and the EBRR bit (AUXR1.6) is set and a break occurs.

(SMOD0)

P89LPC915/916/917 User manual

RB8 RI FE

bit

1 Similar to Figure28

occurs during RB8, one bit before FE

1 Similar to Figure28

occurs during STOP bit

, with SMOD0 = 0, RI

, with SMOD0 = 1, RI

Occurs during STOP bit

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10.15 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out.

10.16 Double buffering in different modes

Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)

Unlike the conventional UART, when double buffering is enabled, the Tx interrupt is generated when the double buffer is ready to receive new data. The following occurs during a transmission (assuming eight data bits):

1. The double buffer is empty initially.

2. The CPU writes to SBUF.

3. The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately.

4. If there is more data, go to 6, else continue.

5. If there is no more data, then: – If DBISEL is logic 0, no more interrupts will occur.

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– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

– Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of

6. If there is more data, the CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the

– Go to 3.

TxD

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P89LPC915/916/917 User manual

of the STOP bit of the data currently in the shifter (which is also the last data).

STOP bit of the data currently in the shifter (which is also the last data).

the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

beginning of the STOP bit of the data currently in the shifter.

end of the STOP bit of the data currently in the shifter.

write to

SBUF

Tx interrupt

Single buffering (DBMOD/SSTAT.7 = 0), early interrupt (INTLO/SSTAT.6 = 0) is shown

TxD

write to

SBUF

Tx interrupt

Double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,

no ending Tx interrupt (DBISEL/SSTAT.4 = 0)

TxD

write to

SBUF

Tx interrupt

Double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,

with ending Tx interrupt (DBISEL/SSTAT.4 = 1)

Fig 29. Transmission with and without double buffering .

002aaa92

10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)

If double buffering is disabled (DBMOD, i.e. SSTAT.7 = 0), TB8 can be written before or after SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must not be changed again until after TB8 shifting has been completed, as indicated by the Tx interrupt.

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If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the Section

10.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)” on page 67

becomes as follows:

1. The double buffer is empty initially.

2. The CPU writes to TB8.

3. The CPU writes to SBUF.

4. The SBUF/TB8 data is loaded to the shift register and a Tx interrupt is generated immediately.

5. If there is more data, go to 7, else continue on 6.

6. If there is no more data, then:

– If DBISEL is logic 0, no more interrupt will occur. – If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

7. If there is more data, the CPU writes to TB8 again.

8. The CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the

9. Go to 4.

10.Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

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P89LPC915/916/917 User manual

of the STOP bit of the data currently in the shifter (which is also the last data).

STOP bit of the data currently in the shifter (which is also the last data).

beginning of the STOP bit of the data currently in the shifter.

end of the STOP bit of the data currently in the shifter.

10.19 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes.

Note that SM2 has no effect in Mode 0, and must be logic 0 in Mode 1.

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10.20 Automatic address recognition

Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes (mode 2 and mode 3), the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the ‘Given’ address or the ‘Broadcast’ address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the ‘Given’ address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatil ity of this scheme:

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Table 57: Slave 0/1 examples

Example 1 Example 2

Slave 0 SADDR = 1100 0000 Slave 1 SADDR = 1100 0000

SADEN = 1111 1101 SADEN = 1111 1110 Given = 1100 00X0 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Ta ble 58: Slave 0/1/2 examples

Example 1 Example 2 Example 3

Slave 0 SADDR = 1100 0000 Slave 1 SADDR = 1110 0000 Slave 2 SADDR = 1100 0000

SADEN = 1111 1001 SADEN = 1111 1010 SADEN = 1111 1100 Given = 1100 0XX0 Given = 1110 0X0X Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon

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reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares’. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

11. I2C interface

The I2C-bus uses two wires, serial clock (SCL) and serial data (SDA) to transfer information between devices connected to the bus, and has the following features:

• Bidirectional data transfer between masters and slaves

• Multimaster bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I

P89LPC915/916/917 User manual

C-bus may be used for test and diagnostic purposes

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A typical I direction bit (R/W), two types of data transfers are possible on the I

C-bus configuration is shown in Figure 30. Depending on the state of the

C-bus:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted

by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave

address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I released.

The P89LPC915/916/917 device provides a byte-oriented I operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode.

The P89LPC915/916/917 CPU interfaces with the I Registers (SFRs): I2CON (I Status Register), I2ADR (I High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).

C Control Register), I2DAT (I2C Data Register), I2STAT (I2C

C Slave Address Register), I2SCLH (SCL Duty Cycle Register

C-bus through six Special Function

C-bus will not be

C interface. It has four

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C-BUS

Fig 30. I2C-bus configuration.

11.1 I2C Data register

I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received data is located at the MSB of I2DAT.

Table 59: I2C Data register (I2DAT - address DAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0 Reset00000000

P1.3/SDA P1.2/SCL

P89LPC915/916/917

OTHER DEVICE

WITH I

INTERFACE

C-BUS

SDA

SCL

OTHER DEVICE

WITH I2C-BUS

INTERFACE

002aaa834

11.2 I2C Slave Address register

I2ADR register is readable and writable, and is only used when the I2C interface is set to slave mode. In master mode, this register has no effect. The LSB of I2ADR is general call bit. When this bit is set, the general call address (00h) is recognized.

Table 60: I2C Slave Address register (I2ADR - address DBh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC Reset00000000

Table 61: I

Bit Symbol Description

0 GC General call bit. When set, the general call address (00H) is recognized,

1:7 I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has

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C Slave Address register (I2ADR - address DBh) bit description

otherwise it is ignored.

no effect.

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Philips Semiconductors

11.3 I2C Control register

The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

CRSEL det ermines the SCL source when the I this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master I Timer1 overflow rate divided by 2 for the I the user in 8 bit auto-reload mode (Mode 2).

Data rate of I

If f

= 12 MHz, reload value is 0 to 255, so I2C data rate range is 11.72 Kbit/sec to

osc

3000 Kbit/sec.

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P89LPC915/916/917 User manual

C-bus is in master mode. In slave mode

C device. When CRSEL = 1, the I2C interface uses the

C = Timer overflow rate / 2 = PCLK / (2*(256-reload value)),

C clock rate . T imer 1 shoul d be pr ogramme d by

When CRSEL = 0, the I

C interface uses the internal clock generator based on the value

of I2SCLL and I2CSCLH register. The duty cycle does not need to be 50 %.

The STA bit is START flag. Setting this bit causes the I

C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode.

The STO bit is STOP flag. Setting this bit causes the I

C interface to transmit a STOP

condition in master mode, or recovering from an error condition in slave mode. If the STA and STO are both set, then a STOP condition is transmitted to the I

C-bus if it is in master mode, and transmits a START condition afterwards. If it is in slave mode, an internal STOP condition will be generated, but it is not transmitted to the bus.

Table 62: I2C Control register (I2CON - address D8h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - I2EN STA STO SI AA - CRSEL Resetx00000x0

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Table 63: I2C Control register (I2CON - address D8h) bit description

Bit Symbol Description

0 CRSEL SCL clock selection. When set = 1, Timer1 overflow generates SCL, when

1 - reserved 2 AA The Assert Acknowledge Flag. When set to logic 1, an acknowledge (low level to

3SI I

4 STO STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the

5 STA S t art Flag. STA = 1: I

6I2EN I

7 - reserved

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P89LPC915/916/917 User manual

cleared = 0, the internal SCL generator is used base on values of I2SCLH and I2SCLL.

SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:

1. The ‘own slave address’ has been received.

2. The general call address has been received while the general call bit (GC) in I2ADR is set.

3. A data byte has been received while the I Receiver Mode.

4. A data byte has been received while the I Slave Receiver Mode.

When cleared to 0, an not ackn owledge (high lev el to SDA) will be retu rned durin g the acknowledge clock pulse on the SCL line on the following situations:

1. A data byte has been received while the I Receiver Mode.

2. A data byte has been received while the I Slave Receiver Mode.

C Interrupt Flag. This bit is set when one of the 25 possible I2C-bus states is entered. When EA bit and EI2C (IE N1 .0) b it a re b oth s et , an inte rrup t is req ues ted when SI is set. Must be cleared by software by writing 0 to this bit.

C-bus. When the bus detects the STOP condition, it will clear STO bit

I automatically. In slave mode, setting this bit can recover from an error conditio n. In this case, no ST OP cond ition is transmi tted to th e bus. T he hardw are beha ves as if a STOP condition has been received and it switches to ‘not addressed’ Slave Receiver Mode. The STO flag is cleared by hardware automatically.

C-bus enters ma ste r m ode , c he ck s the bus a nd generates a START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator. When the I already in master mode and some data is transmitted or received, it transmits a repeated START condition. STA may be set at any time, it may also be set when

C interface is in an addressed slave mode. STA = 0: no START condition or

the I repeated START condition will be generated.

C Interface Enable. When set, enables the I2C interface. When clear, the I2C

function is disabled.

C interface is in the Master

C interface is in the addressed

C interface is in the Master

C interface is in the addressed

C interface is

11.4 I2C Status register

This is a read-only register. It contains the status code of I2C interfac e. Th e leas t thre e bit s are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and SI bit is not set. All other 25 status codes correspond to defined I

Table 69

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C states. When any of these states entered, the SI bit will be set. Refer to

to Table 72 for details.

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Table 64: I2C Status register (I2STAT - address D9h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 Reset00000000

Table 65: I

Bit Symbol Description

0:2 - Reserved, are always set to logic 1. 3:7 STA.0:4 I

11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL

When the internal SCL generator is selected for the I2C interface by setting CRSEL = 0 in the I2CON register, the user must set values for registers I2SCLL and I2SCLH to select the data rate. I2SCLH defines the number of PCLK cycles for SCL = high, I2SCLL defines the number of PCLK cycles for SCL = low. The frequency is determined by the following formula:

P89LPC915/916/917 User manual

C Status register (I2STAT - address D9h) bit description

C Status code.

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Bit Frequency = f

Where f

is the frequency of PCLK.

PCLK

/ (2*(I2SCLH + I2SCLL))

PCLK

The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycle’s for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I

C-bus data rate range of 0 to 400 kHz. Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended. The values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended.

Table 66: I2C clock rates selection

Bit data rate (Kbit/sec) at f I2SCLL+ I2SCLH

60- 307154- 70- 263132- 8 0 - 230 115 - 375 9 0 - 205 102 - 333 10 0 369 184 92 - 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30

CRSEL 7.373 MHz 3.6865 MHz 1.8433 MHz 12 MHz 6 MHz

osc

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Table 66: I

I2SCLL+ I2SCLH

150 0 25 12 6 40 20 200 0 18 9 5 30 15

- 1 3.6 Kbps to

11.6 I2C operation modes

11. 6 .1 Master Transmitt er mode

In this mode data is transmitted from master to slave. Before the Master Transmitter mode can be entered, I2CON must be initialized as follows:

Table 67: I2C Control register (I2CON - address D8h)

Bit 7 6 5 4 3 2 1 0

value- 1000x- bit rate

CRSEL defines the bit rate. I2EN must be set to logic 1 to enable the I AA bit is 0, it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode. STA, STO, and SI bits must be cleared to 0.

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C clock rates selection

Bit data rate (Kbit/sec) at f

CRSEL 7.373 MHz 3.6865 MHz 1.8433 MHz 12 MHz 6 MHz

1.8 Kbps to 922 Kbps Timer 1 in mode 2

-I2ENSTASTOSIAA-CRSEL

461 Kbps Timer 1 in mode 2

osc

0.9 Kbps to 230 Kbps Timer 1 in mode 2

5.86 Kbps to 1500 Kbps Timer 1 in mode 2

C function. If the

2.93 Kbps to 750 Kbps Timer 1 in mode 2

The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

The I

C-bus will enter Master Transmitter Mode by setting the STA bit. The I2C logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT (Data Register) and data direction bit (SLA+W). The SI bit must be cleared before the data transfer can continue.

When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes are 18h, 20h, or 38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled (setting AA = logic 1). The appropriate action to be taken for each of these status codes is shown in Table 69

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S R/W A D ATA DATA

from Master to Slave from Slave to Master

Fig 31. Format in the Master Transmitter mode.

11.6.2 Master Receiver mode

In the Master Receiver mode, data is received from a slave transmitter. The transfer started in the same manner as in the Master Transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to I the data transfer can continue.

When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. Refer to Table 71

A A/A Pslave address

logic 0 = write logic 1 = read

C Data Register (I2DAT). The SI bit must be cleared before

data transferred

(n Bytes + acknowledge)

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition

002aaa929

for details.

Fig 32. Format of Master Receiver mode.

After a repeated START condition, the I mode.

S R ASLA

from Master to Slave from Slave to Master

logic 0 = write logic 1 = read

S R Aslave address

from Master to Slave from Slave to Master

DATA DATA

A W ASLA D ATA A PA RS

data transferred

(n Bytes + acknowledge)

DATA DATA

logic 0 = write logic 1 = read

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition SLA = slave address RS = repeat START condition

(n Bytes + acknowledge)

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition

C-bus may switch to the Master Transmitter

A A P

data transferred

002aaa93

002aaa931

Fig 33. A Master Receiver switches to Master Transmitter after sending Repeated Start.

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11. 6.3 Slave Receiver mode

In the Slave Receiver mode, data bytes are received from a master transmitter. To initialize the Slave Receiver mode, the user should write the slave address to the Slave Address Register (I2ADR) and the I follows:

Table 68: I2C Control register (I2CON - address D8h)

Bit 7 6 5 4 3 2 1 0

value- 10001--

CRSEL is not used for slave mode. I2EN must be set = 1 to enable I must be set = 1 to acknowledge its own slave address or the general call address. STA, STO and SI are cleared to 0.

After I2ADR and I2CON are initialized, the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0(W). If the direction bit is 1(R), it will enter Slave Transmitter mode. After the address and the direction bit have been received, the SI bit is set and a valid status code can be read from the Status Register(I2STAT). Refer to Table 72

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P89LPC915/916/917 User manual

C Control Register (I2CON) should be configured as

- I2EN STA STO SI AA - CRSEL

C function. AA bit

for the status codes and actions.

S W Aslave address

from Master to Slave from Slave to Master

Fig 34. Format of Slave Receiver mode.

11.6.4 Slave Transmitter mode

The first byte is received and handled as in the Slave Receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.3/SDA while the serial clock is input through P1.2/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, the I

C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I slave address in the same serial transfer.

C-bus may operate as a master and as a slave. In the slave mode, the

C-bus switches to the slave mode immediately and can detect its own

logic 0 = write

logic 1 = read

DATA DATA

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition RS = repeated START condition

A A/A P/RS

data transferred

(n Bytes + acknowledge)

002aaa932

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S R Aslave address

logic 0 = write

logic 1 = read

from Master to Slave from Slave to Master

Fig 35. Format of Slave Transmitter mode.

P1.3

INPUT

FILTER

P1.3/SDA

OUTPUT

STAGE

DATA DATA

A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition

ADDRESS REGISTER

A A P

data transferred

(n Bytes + acknowledge)

COMPARATOR

SHIFT REGISTER

I2DAT

002aaa933

I2ADR

INTERNAL BUS

ACK

P1.2/SCL

INPUT

FILTER

OUTPUT

STAGE

P1.2

TIMER 1

OVERFLOW

I2CON I2SCLH I2SCLL

STATUS BUS

I2STAT

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

SERIAL CLOCK

GENERATOR

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

STATUS REGISTER

TIMING

CONTROL

LOGIC

AND

CCLK

INTERRUPT

002aaa421

Fig 36. I2C serial interface block diagram.

User manual Rev. 01 — 15 July 2004 79 of 125

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Philips Semiconductors

Table 69: Master Transmitter mode

Status code (I2STAT)

08H A START

10H A repeat

18h SLA+W has

20h SLA+W has

28h Data byte in

Status of the

C hardware

condition has been transmitted

START condition has been transmitted

been transmitted; ACK has been received

been transmitted; NOT-ACK has been received

I2DAT has been transmitted; ACK has been received

UM10107

P89LPC915/916/917 User manual

Application software response Next action taken by to/from

I2DAT

Load SLA+W x 0 0 x SLA+W will be

Load SLA+W or

Load SLA+R

Load data byte or

no I2DAT action or

no I2DAT action

Load data byte or

no I2DAT action or

no I2DAT action

Load data byte or

no I2DAT action or

no I2DAT action

to I2CON STA STO SI AA

x 0 0 x As above; SLA+W will

0 0 0 x Data byte will be

1 0 0 x Repeated START will be

010xSTOP condition will be

1 1 0 x STOP condition followed

0 0 0 x Data byte will be

1 0 0 x Repeated START will be

010xSTOP condition will be

1 1 0 x STOP condition followed

0 0 0 x Data byte will be

1 0 0 x Repeated START will be

010xSTOP condition will be

1 1 0 x STOP condition followed

C hardware

transmitted; ACK bit will be received

be transmitted; I switches to Mas ter Receiver mode

transmitted; ACK bit will be received

transmitted;

transmitted; STO flag will be r eset

by a START condition will be transmitted; STO flag will be reset.

transmitted; ACK bit will be received

transmitted;

transmitted; STO flag will be reset

by a START condition will be transmitted; STO flag will be reset

transmitted; ACK bit will be received

transmitted;

transmitted; STO flag will be reset

by a START condition will be transmitted; STO flag will be reset

User manual Rev. 01 — 15 July 2004 80 of 125

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Philips Semiconductors

Table 69: Master Transmitter mode

Status code (I2STAT)

30h Data byte in

38H Arbitration lost

Status of the

C hardware

I2DAT has been transmitted, NOT ACK has been received

in SLA+R/W or data bytes

UM10107

P89LPC915/916/917 User manual

Application software response Next action taken by to/from

I2DAT

Load data

to I2CON STA STO SI AA

0 0 0 x Data byte will be

byte or

no I2DAT

1 0 0 x Repeated START will be

action or no I2DAT

010xSTOP condition will be

action or

no I2DAT

1 1 0 x STOP condition followed

action

No I2DAT

000xI

action or

No I2DAT

1 0 0 x A START condition will

action

C hardware

transmitted; ACK bit will be received

transmitted;

transmitted; STO flag will be reset

by a START condition will be transmitted. STO flag will be reset.

C-bus will be releas ed; not addressed slave will be entered

be transmitted when the bus becomes free.

Table 70: Master Receiver mode

Status code (I2STAT)

Status of the

C hardware

Application software response Nex t action taken by I2C to/from

I2DAT

08H A START

Load SLA+R x 0 0 x SLA+R will be transmitted; condition has been transmitted

10H A repeat

Load SLA+R orx00xAs above START condition has been

Load SLA+W SLA+W will be transmitted; transmitted

38H Arbitration lost

in NOT ACK bit

no I2DAT

action or

no I2DAT

action

40h SLA+R has

been transmitted; ACK has been received

no I2DAT

action or

no I2DAT

action or

to I2CON

hardware

STASTOSI ST

ACK bit will be received

C-bus will be switched to

I Master Transmitter mode

000xI

C-bus will be released; it

will enter a slave mode

100xA START condition will be

transmitted when the bus becomes free

0000Data byte will be received;

NOT ACK bit will be returned

0001Data byte will be received;

ACK bit will be returned

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Philips Semiconductors

Table 70: Master Receiver mode

Status code (I2STAT)

48h SLA+R has

50h Data byte has

58h Data byte has

Status of the

C hardware

been transmitted; NOT ACK has been received

been received; ACK has been returned

been received; NACK has been returned

UM10107

P89LPC915/916/917 User manual

Application software response Nex t action taken by I2C

to/from

I2DAT

No I2DAT

action or

no I2DAT

action or

no I2DAT

action or

Read data

byte

read data byte0001Data byte will be received;

Read data

byte or

read data byte or010xSTOP condition will be

read data byte110xSTOP condition followed by

to I2CON STASTOSI ST

100xRepeated START will be

010xSTOP condition will be

110xSTOP condition followed by

0000Data byte will be received;

100xRepeated START will be

hardware

transmitted

transmitted; STO flag will be reset

a START condition will be transmitted; STO flag will be reset

NOT ACK bit will be returned

ACK bit will be returned

transmitted;

transmitted; STO flag will be reset

a START condition will be transmitted; STO flag will be reset

T ab le 71: Slave Receiver mode

Status code (I2STAT)

60H Own SLA+W

68H Arbitration

User manual Rev. 01 — 15 July 2004 82 of 125

Status of the

C hardware

has been received; ACK has been received

lost in SLA+R/Was master; Own SLA+W has been received, ACK returned

Application software response Next action taken by I2C

to/from

I2DAT

no I2DAT

action or

no I2DAT

action

No I2DAT

action or

no I2DAT

action

to I2CON STASTOSI AA

x000Data byte will be received

x001Data byte will be received

x000Data byte will be received

x001Data byte will be received

hardware

and NOT ACK will be returned

and ACK will be returned

and NOT ACK will be returned

and ACK will be returned

Page 83

Philips Semiconductors

T ab le 71: Slave Receiver mode

Status code (I2STAT)

Status of the

C hardware

UM10107

P89LPC915/916/917 User manual

Application software response Next action taken by I2C

to/from

I2DAT

to I2CON STASTOSI AA

hardware

70H General call

address(00H) has been received, ACK has been returned

78H Arbitration

lost in SLA+R/W as master; General call address has been received, ACK bit has been returned

80H Previously

addressed with own SLA address; Data has been received; ACK has been returned

88H Previously

addressed with own SLA address; Data has been received; NACK has been returned

No I2DAT

action or

no I2DAT

action

no I2DAT

action or

no I2DAT

action

Read data

byte or

read data bytex001Data byte will be received;

Read data

byte or

read data byte

read data byte1001Switched to not addressed

x000Data byte will be received

and NOT ACK will be returned

x001Data byte will be received

and ACK will be returned

x000Data byte will be received

and NOT ACK will be returned

x001Data byte will be received

and ACK will be returned

x000Data byte will be received

and NOT ACK will be returned

ACK bit will be returned

0000Switched to not addressed

SLA mode; no recognition of own SLA or general address

0001Switched to not addressed

SLA mode; Own SLA will be recognized; general call address will be recogn ized if I2ADR.0 = 1

1000Switched to not addressed

SLA mode; no recognition of own SLA or General call address. A ST AR T condition will be transmitted when the bus becomes free

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0= 1. A START condition will be transmitted when the bus becomes free.

User manual Rev. 01 — 15 July 2004 83 of 125

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Philips Semiconductors

T ab le 71: Slave Receiver mode

Status code (I2STAT)

Status of the

C hardware

UM10107

P89LPC915/916/917 User manual

Application software response Next action taken by I2C

to/from

I2DAT

to I2CON STASTOSI AA

hardware

90H Previously

addressed with General call; Data has been received; ACK has been returned

98H Previously

addressed with General call; Data has been received; NACK has been returned

Read data

byte or

read data bytex001Data byte will be received

Read data

byte

read data byte0001Switched to not addressed

read data byte1000Switched to not addressed

read data byte1001Switched to not addressed

x000Data byte will be received

and NOT ACK will be returned

and ACK will be returned

0000Switched to not addressed

SLA mode; no recognition of own SLA or General call address

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0= 1.

SLA mode; no recognition of own SLA or General call address. A ST AR T condition will be transmitted when the bus becomes free.

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0= 1. A START condition will be transmitted when the bus becomes free.

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Philips Semiconductors

T ab le 71: Slave Receiver mode

Status code (I2STAT)

Status of the

C hardware

UM10107

P89LPC915/916/917 User manual

Application software response Next action taken by I2C

to/from

I2DAT

to I2CON STASTOSI AA

hardware

A0H A STOP

condition or repeated START condition has been received while still addressed as SLA/REC or SLA/TRX

Table 72: Slave Transmitter mode

Status code (I2STAT)

Status of the

C hardware

No I2DAT

action

no I2DAT

action

no I2DAT

action

no I2DAT

action

Application software respons e Next action taken by I2C

to/from

I2DAT

0000Switched to not addressed

SLA mode; no recognition of own SLA or General call address

0001Switched to not addressed

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0= 1.

1000Switched to not addressed

SLA mode; no recognition of own SLA or General call address. A ST AR T condition will be transmitted when the bus becomes free.

1001Switched to not addressed

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0= 1. A START condition will be transmitted when the bus becomes free.

to I2CON STASTOSI AA

hardware

A8h Own SLA+R

has been received; ACK has been returned

B0h Arbitration

lost in SLA+R/W as master; Own SLA+R has been received, ACK has been returned

User manual Rev. 01 — 15 July 2004 85 of 125

Load data

byte or

load data byte x 0 0 1 Data byte will be

Load data

byte or

load data byte x 0 0 1 Data byte will be

x 0 0 0 Last data byte wi ll be

transmitted and ACK bit will be received

transmitted; ACK will be received

x 0 0 0 Last data byte wi ll be

transmitted and ACK bit will be received

transmitted; ACK bit will be received

Page 86

Philips Semiconductors

Table 72: Slave Transmitter mode

Status code (I2STAT)

Status of the

C hardware

UM10107

P89LPC915/916/917 User manual

Application software respons e Next action taken by I2C

to/from

I2DAT

to I2CON STASTOSI AA

hardware

B8H Data byte in

I2DAT has been transmitted; ACK has been received

C0H Data byte in

I2DAT has been transmitted; NACK has been received

Load data

byte or

load data byte x 0 0 1 Data byte will be

No I2DAT

action or

no I2DAT

action or

no I2DAT

action or

no I2DAT

action

x 0 0 0 Last data byte wi ll be

transmitted and ACK bit will be received

transmitted; ACK will be received

0 0 0 0 Switched to not addressed

SLA mode; no recognition of own SLA or General call address.

0 0 0 1 Switched to not addressed

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

1 0 0 0 Switched to not addressed

SLA mode; no recognition of own SLA or General call address. A ST ART condition will be transmitted when the bus becomes free.

1 0 0 1 Switched to not addressed

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A STA RT condition will be transmitted when the bus becomes free.

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Philips Semiconductors

Table 72: Slave Transmitter mode

Status code (I2STAT)

Status of the

C hardware

UM10107

P89LPC915/916/917 User manual

Application software respons e Next action taken by I2C

to/from

I2DAT

to I2CON STASTOSI AA

hardware

C8H Last data byte

in I2DAT has been transmitted(A A=0; ACK has been received

No I2DAT

action or

no I2DAT

action or

no I2DAT

action or

no I2DAT

action

0 0 0 0 Switched to not addressed

0 0 0 1 Switched to not addressed

1 0 0 0 Switched to not addressed

1 0 0 1 Switched to not addressed

12. Serial Peripheral Interface (SPI - P89LPC916)

SLA mode; no recognition of own SLA or General call address.

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.

SLA mode; no recognition of own SLA or General call address. A ST ART condition will be transmitted when the bus becomes free.

SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A STA RT condition will be transmitted when the bus becomes free.

The P89LPC916 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.

User manual Rev. 01 — 15 July 2004 87 of 125

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Philips Semiconductors

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPR1

SPR0

SPI CONTROL

SPIF

WCOL

SPI STATUS REGISTER

SPI clock (master)

interrupt

request

SPI

MSTR SPEN

8-BIT SHIFT REGISTER

READ DATA BUFFER

CLOCK LOGIC

DORD

SPEN

MSTR

SSIG

SPI CONTROL REGISTER

internal

data

bus

clock

CPHA

CPOL

SPR1

SPR0

UM10107

P89LPC915/916/917 User manual

S M

M S

S M

MSTR

PIN CONTROL LOGIC

SPEN

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

002aaa497

Fig 37. SPI block diagram.

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

• SS is the optional slave select pin. In a typical configuration, an SPI master asserts

Note that even if the SPI is configured as a master (MSTR = 1), it can still be converted to a slave by dr ivi ng th e SS happen, the SPIF bit (SPSTAT.7) will be set (see Section 12.5

devices. Data flows from master to slave on the MOSI (Master Out Slave In) pin and flows from slave to master on the MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions

one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS

pin to deter mine whether it is selected. The SS is ignored if any of the

following conditions are true:

– If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value) – If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P2.4 is

configured as an output (via the P2M1.4 and P2M2.4 SFR bits);

– If the SS

pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port

functions

pin low (if P2.4 is configured as input and SSIG = 0). Should this

Typical connections are shown in Figure 38

to Figure 40.

Table 73: SPI Control register (SPCTL - address E2h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 Reset 0000100

User manual Rev. 01 — 15 July 2004 88 of 125

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Philips Semiconductors

Table 74: SPI Control register (SPCTL - address E2h) bit description

Bit Symbol Description

0 SPR0 SPI clock rate select 1 SPR1

2 CPHA SPI Clock PHAse select (see Figures 41

3 CPOL SPI Clock POLarity ( see Figur es 41

4 MSTR Master/Slave mode Select (see Table 78 5 DORD SPI Data ORDer. When logic 1,the LSB of the data word is tran sm itte d f irs t. Wh en

6 SPEN TSPI Enable. If set = 1, the SPI is enabled. If cleared = 0, the SPI is disabled and

7 SSIG SS

UM10107

P89LPC915/916/917 User manual

SPR1:0 — SPI clock rate

00 — CCLK/4 01 — CCLK/16 10 — CCLK/64 11 — CCLK/128

to 44). When logic 1, data is driven on the

leading edge of SPICLK, and is sampled on the trailing edge. When logic 0, data is driven when SS

trailing edge of SPICLK, and is sampled on the leading edge. (Note: If SSIG = 1, the operation is not defined.)

leading edge of SPICLK is the falling edge and the trailing edge is the rising edge. When logic 0, SPICLK is low when idle. The leading edge of SPICLK is the rising

edge and the trailing edge is the falling edge.

logic 0, the MSB of the data word is transmitted first.

all SPI pins will be port pins.

IGnore. If set = 1, MSTR (bit 4) decides whether the device is a master or

slave. If cleared = 0, the SS

pin can be used as a port pin (see Table 78).

pin decides whether the device is master or slave. T he

is low (SSIG = 0) and changes on the

to 44): When 1, SPICLK is hig h when idl e. The

Table 75: SPI Status register (SPSTAT - address E1h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SPIF WCOL - - - - - Reset00xxxxxx

Table 76: SPI Status register (SPSTAT - address E1h) bit description

Bit Symbol Description

0:5 - Reserved. 6 WCOL SPI Write Collision Flag. The WCOL bit is set if the SPI data register, SPDAT, is

written during a data transfe r (see Section 12.6 software by writing logic 1 to this bit.

7 SPIF SPI Transfer Completion Flag. When a serial transfer finishes, the SPIF bit is set

and an interrupt is generated if bot h the ESPI (IEN1.3) bit and the EA bit are se t. If

is an input and is driven l ow when SPI is in master mode , and SSIG = 0, this bit

SS will also be set (see Section 12.5 logic 1 to this bit.

Table 77: SPI Data register (SPDAT - address E3h) bit allocation

Bit 7 6 5 4 3 2 1 0

SymbolMSB------LSB Reset00000000

). The SPIF flag is cleared in software by writing

). The WCOL flag is cleared in

User manual Rev. 01 — 15 July 2004 89 of 125

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Philips Semiconductors

12.1 Typical SPI configurations

P89LPC915/916/917 User manual

Master Slave

MISO

MOSI

8-BIT SHIFT

MISO

MOSI

UM10107

SPICLK

002aaa435

SPI CLOCK

GENERATOR

SPICLK

PORT

Fig 38. SPI single master single slave configuration.

In Figure 38, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave. The SPI master can use any port pin (including P2.4/SS

Master Slave

MISO

8-BIT SHIFT

SPI CLOCK

GENERATOR

MOSI

SPICLK

port

) to drive the SS pin.

MISO

MOSI

SPICLK

8-BIT SHIFT

Slave

port

MISO

MOSI

SPICLK

8-BIT SHIFT

002aaa437

Fig 39. SPI dual device configuration, where either can be a master or a slave.

User manual Rev. 01 — 15 July 2004 90 of 125

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Philips Semiconductors

Figure 39 shows a case where two devices are connected to each other and either device

can be a master or a slave. When no SPI operation is occurring, both can be configured as masters (MSTR = 1) with SSIG cleared to 0 and P2.4 (SS quasi-bidirectional mode. When a device initiates a transfer, it can configure P2.4 as an output and drive it low, forcing a mode change in the other device (see Section 12.5 slave.

P89LPC915/916/917 User manual

) configured in

Master Slave

8-BIT SHIFT

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

UM10107

) to

SPI CLOCK

GENERATOR

SPICLK

SPI CLOCK

GENERATOR

002aaa49

Fig 40. SPI single master multiple slaves configuration.

In Figure 40 by the corresponding SS P2.4/SS

, SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected

signals. The SPI master can use any port pin (including

) to drive the SS pins.

12.2 Configuring the SPI

Table 78 shows configuration for the master/slave modes as well as usages and

directions for the modes.

Ta ble 78: SPI master and slave selection

SPEN SSIG SS pin MSTR Master or

slave mode

[1]

0x P2.4

x SPI

Disabled 1 0 0 0 Slave output input input Selected as slave. 1 0 1 0 Slave Hi-Z input input Not selected. MISO is high impedance to

1 0 0 1 (->

[2]

Slave output input input P2.4/SS is configured as an input or

MISO MOSI SPICLK Comments

P2.3

[1]

P2.2

[1]

P2.5

[1]

SPI disabled. P2.2, P2.3, P2.4, P2.5 are used as port pins.

avoid bus contention.

quasi-bidirectional pin. SSIG is 0. Selected external ly as slave if SS is selected and is driven low. The MSTR bit will be cleared to logic 0 when SS becomes low.

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Philips Semiconductors

Ta ble 78: SPI master and slave selection

SPEN SSIG SS pin MSTR Master or

slave

mode

10 1 1 Master

(idle)

Master

(active)

[1]

11 P2.4 11 P2.4

[1] Selected as a port function. [2] The MSTR bit changes to logic 0 automatically when SS

0 Slave output input input

[1]

1 Master input output output

MISO MOSI SPICLK Comments

input Hi-Z Hi-Z MOSI and SPICLK are at high impedance to

12.3 Additional considerations for a slave

UM10107

P89LPC915/916/917 User manual

avoid bus conten tio n w h en the MAs ter is idle. The application must pull-up or pull -down SPICLK (depending on CPOL - SPCTL.3) to avoid a floating SPICLK.

output ou tput MOSI and SPICLK are push-pull when the

Master is active.

becomes low in input mode and SSIG is logic 0.

When CPHA equals zero, SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte. If the SPDAT register is written while SS is active (low), a write collision error results. The operation is undefined if CPHA is logic 0 and SSIG is logic 1.

When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0, the SS active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line.

12.4 Additional considerations for a master

In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN = 1) and selected as master, writing to the SPI data register by the master starts the SPI clock generator and data transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.

Note that the master can select a slave by driving the SS low. Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave, at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master.

After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt will be created if the SPI interrupt is enabled (ESPI, or IEN1.3 = 1). The two shift registers in the master CPU and slave CPU can be considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged.

pin may remain

pin of the corresponding device

12.5 Mode change on SS

If SPEN = 1, SSIG = 0 and MSTR = 1, the SPI is enabled in master mode. The SS pin can be configured as an input (P2M2.4, P2M1.4 = 00) or quasi-bidirectional (P2M2.4, P2M1.4 = 01). In this case, another master can drive this pin low to select this device as

User manual Rev. 01 — 15 July 2004 92 of 125

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Philips Semiconductors

an SPI slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.

The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an SPI interrupt will occur.

User software should always check the MSTR bit. If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will stay in slave mode.

12.6 Write collision

The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for transmission can not be written to the shift register until the previous transaction is complete. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case, the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the collision, will be lost.

UM10107

P89LPC915/916/917 User manual

While write collision is detected for both a master or a slave, it is uncommon for a master because the master has full control of the transfer in progress. The slave, however, has no control over when the master will initiate a transfer and therefore collision can occur.

For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character. However, the received character must be read from the Data Register before the next character has been completely shifted in. Otherwise. the previous data is lost.

WCOL can be cleared in software by writing logic 1 to the bit.

12.7 Data mode

Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. Figures 41 show the different settings of Clock Phase bit CPHA.

to 44

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Philips Semiconductors

UM10107

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

(1) Not defined

Fig 41. SPI slave transfer format with CPHA = 0.

LSB

MSB

LSB

MSB

(1)

002aaa93

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P89LPC915/916/917 User manual

Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

(1)

MSB

LSB

(1) Not defined

Fig 42. SPI slave transfer format with CPHA = 1.

LSB

MSB

LSB

MSB

002aaa93

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

(1) Not defined

Fig 43. SPI master transfer format with CPHA = 0.

LSB

MSB

LSB

MSB

002aaa93

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

MOSI (input)

MISO (output)

SS (if SSIG bit = 0)

(1) Not defined

DORD = 0

DORD = 1

DORD = 0

DORD = 1

1 2 3 4 5 6 7 8

MSB

LSB

MSB

LSB

Fig 44. SPI master transfer format with CPHA = 1.

LSB

MSB

LSB

MSB

002aaa93

12.8 SPI clock prescaler select

The SPI clock prescaler selection uses the SPR1-SPR0 bits in the SPCTL register (see

Table 74

13. Analog comparators

Two analog comparators are provided on the P89LPC915/916/917. Input and output options allow use of the comparators in different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes.

13.1 Comparator configuration

Each comparator has a control register, CMP1 for comparator 1 and CMP2 for comparator 2 and are shown in Table 80 P89LPC915/916/917 devices and that the OE2 bit (in CMP2) does not exist on the P89LPC916 device.

. Please note that the OE1 bit (in CMP1) does not exist on the

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The overall connections to both comparators are shown in Figure 45. There are eight possible configurations for comparator 2 and six for comparator 1, as determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in Figure 46 devices.

When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

Table 79: Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit

Bit 7 6 5 4 3 2 1 0

Symbol - - CEn CPn CNn OEn COn CMFn Resetxx000000

Table 80: Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit

Bit Symbol Description

0 CMFn Comparator interrupt flag. This bit is set by hardware whenever the comparator

1 COn Comparator output, synchronized to the CPU clock to allow reading by software. 2 OEn Output enable. When logic 1, the comparator output is connected to the CMPn pi n

3 CNn Comparator negative input select. When logic 0, the comparator reference pin

4 CPn Comparator positive input select. When logic 0, CINnA is selected as the positive

5 CEn Comparator enable. When set, the corresponding comparator function is enabled.

6:7 - reserved

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P89LPC915/916/917 User manual

. Note: Not all combinations are available on all

allocation

description

output COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by software.

if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.

CMPREF is selected as the negative comparator input. When logic 1, the internal comparator reference, Vref, is selected as the negative comparator input.

comparator input. When logic 1, CINnB is selected as the positive comparator input.

Comparator output is stable 10 microseconds after CEn is set.

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(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

(P0.2) CIN2A

(P0.1) CIN2B

CP1

REF

CN1

CP2

CN2

Comparator 1

Comparator 2

Fig 45. Comparator input and output connections.

13.2 Internal reference voltage

An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to the P89LPC915/916/917 data sheet for specifications

CO1

Change Detect

CO2

CMF1

Interrupt

CMF2

CMP2 (P0.0)

(P89LPC915/917)

OE2

13.3 Comparator interrupt

Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register. If both comparators enable interrupts, after entering the interrupt service routine, the user will need to read the flags to determine which comparator caused the interrupt.

When a comparator is disabled the comparator’s output, COx, goes high. If the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.

13.4 Comparators and power reduction modes

Either or both comparators may remain enabled when power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode

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in order to obtain fast switching times while in Power-down mode. The reason is that with the clock stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This should be taken into consideration when system power consumption is an issue. To minimize power consumption, the user can power-down the comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply putting the device in Total Power- down mode

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CINnA

CMPREF

COn

002aaa618

CINnA

CMPREF

a. CPn, CNn, OEn= 0 0 0 b. CPn, CNn, OEn = 0 0 1

REF

CINnA

(1.23V)

COn

002aaa621

REF

CINnA

(1.23 V)

c. CPn, CNn, OEn = 0 1 0 d. CPn, CNn, OEn = 0 1 1

CINnB

CMPREF

COn

002aaa623

CINnB

CMPREF

e. CPn, CNn, OEn= 1 0 0 f. CPn, CNn, OEn = 1 0 1

REF

CINnB

(1.23V)

COn

002aaa625

REF

CINnB

(1.23 V)

g. CPn, CNn, OEn= 1 1 0 h. CPn, CNn, OEn = 1 1 1

Fig 46. Comparator configurations.

COn

002aaa620

002aaa622

COn

002aaa624

002aaa626

COn

CMPn

13.5 Comparators configuration example

The code shown below is an example of initializing one comparator. Comparator 1 is configured to use the CIN1A and CMPREF inputs, outputs the comparator result to the CMP1 pin, and generates an interrupt when the comparator output changes.

CMPINIT:

MOV PT0AD,#030h ;Disable digital INPUTS on pins CIN1A, CMPREF.

ANL P0M2,#0CFh ;Disable digital OUTPUTS on pins that are used ORL P0M1,#030h ;for analog functions: CIN1A, CMPREF. MOV CMP1,#020h ;Turn on comparator 1 and set up for:

; - Positive input on CIN1A.

; - Negative input from CMPREF pin. CALL delay10us ;start up for at least 10 microseconds before use. ANL CMP1,#0FEh ;Clear comparator 1 interrupt flag. SETB EC ;Enable the comparator interrupt. The priority is left at

the current value.

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