1.4Advanced audio configuration
2APPLICATIONS
3GENERAL DESCRIPTION
4ORDERING INFORMATION
5QUICK REFERENCE DATA
6BLOCK DIAGRAM
7PINNING
8FUNCTIONAL DESCRIPTION
8.1System clock
8.2Interpolation filter
8.3Noise shaper
8.4Filter stream DAC
8.5Power-on reset
8.6Feature settings
8.6.1Digital interface format select
8.6.2Mute control
8.6.3De-emphasis control
8.6.4Power control and sampling frequency select
9LIMITING VALUES
10HANDLING
11THERMAL CHARACTERISTICS
12QUALITY SPECIFICATION
13DC CHARACTERISTICS
14AC CHARACTERISTICS
14.12.0 V supply voltage
14.23.0 V supply voltage
14.3Timing
15APPLICATION INFORMATION
16PACKAGE OUTLINE
17SOLDERING
17.1Introduction to soldering surface mount
packages
17.2Reflow soldering
17.3Wave soldering
17.4Manual soldering
17.5Suitability of surface mount IC packages for
wave and reflow soldering methods
18DATA SHEET STATUS
19DEFINITIONS
20DISCLAIMERS
2002 May 222
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
1FEATURES
1.1General
• 1.8 to 3.6 V power supply voltage
• Integrated digital filter plus DAC
• Supports sample frequencies from 8 to 100 kHz
• Automatic system clock versus sample rate detection
• Low power consumption
• No analog post filtering required for DAC
• Slave mode only applications
• Easy application
• SO16 package.
2APPLICATIONS
This audio DAC is excellently suitable for digital audio
portable application, such as portable MD, MP3 and
DVD players.
1.2Multiple format data interface
• I2S-bus and LSB-justified format compatible
• 1fs input data rate.
1.3DAC digital sound processing
• Digital de-emphasis for 44.1 kHz sampling rate
• Mute function.
1.4Advanced audio configuration
• High linearity, wide dynamic range and low distortion
• Standby or Sleep mode in which the DAC is powered
down.
4ORDERING INFORMATION
TYPE
NUMBER
UDA1334BTSO16plastic small outline package; 16 leads; body width 3.9 mmSOT109-1
NAMEDESCRIPTIONVERSION
3GENERAL DESCRIPTION
The UDA1334BT supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
The UDA1334BThas basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.
PACKAGE
2002 May 223
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
5QUICK REFERENCE DATA
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX. UNIT
Supplies
V
DDA
V
DDD
I
DDA
I
DDD
T
amb
Digital-to-analog converter (V
V
o(rms)
(THD + N)/S total harmonic
S/Nsignal-to-noise ratiof
α
cs
Digital-to-analog converter (V
V
o(rms)
(THD + N)/S total harmonic
S/Nsignal-to-noise ratiof
α
cs
Power dissipation (at fs= 44.1 kHz)
DAC analog supply voltage1.82.03.6V
digital supply voltage1.82.03.6V
DAC analog supply currentnormal operating mode−2.3−mA
Sleep mode−125−µA
digital supply currentnormal operating mode−1.4−mA
Sleep mode
clock running−250−µA
no clock running−20−µA
ambient temperature−40−+85°C
DDA=VDDD
= 2.0 V)
output voltage (RMS value)at 0 dB (FS) digital input; note 1−600−mV
= 44.1 kHz; at 0 dB−−80−dB
f
s
distortion-plus-noise to signal
ratio
f
= 44.1 kHz; at −60 dB; A-weighted−−37−dB
s
= 96 kHz; at 0 dB−−75−dB
f
s
f
= 96 kHz; at −60 dB; A-weighted−−35−dB
s
= 44.1 kHz; code = 0; A-weighted−97−dB
s
= 96 kHz; code = 0; A-weighted−95−dB
f
s
channel separation−100−dB
DDA=VDDD
= 3.0 V)
output voltage (RMS value)at 0 dB (FS) digital input; note 1−900−mV
f
= 44.1 kHz; at 0 dB−−90−dB
s
distortion-plus-noise to signal
ratio
f
= 44.1 kHz; at −60 dB; A-weighted−−40−dB
s
f
= 96 kHz; at 0 dB−−85−dB
s
= 96 kHz; at −60 dB; A-weighted−−37−dB
f
s
= 44.1 kHz; code = 0; A-weighted−100−dB
s
f
= 96 kHz; code = 0; A-weighted−98−dB
s
channel separation−100−dB
Ppower dissipationplayback mode
at 2.0 V supply voltage−7.4−mW
at 3.0 V supply voltage−17−mW
Sleep mode; at 2.0 V supply voltage
clock running−0.75−mW
no clock running−0.3−mW
Note
1. The DAC output voltage scales proportionally to the power supply voltage.
2002 May 224
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
6BLOCK DIAGRAM
handbook, full pagewidth
BCK
WS
DATAI
SYSCLK
MUTE
DEEM
PCS
VOUTL
V
DDD
4
1
2
3
UDA1334BT
6
8
9
10
14
1312
V
DDA
DIGITAL INTERFACE
DE-EMPHASIS
INTERPOLATION FILTER
NOISE SHAPER
DAC
15
V
SSA
V
DAC
SSD
5
7
SFOR1
11
SFOR0
16
VOUTR
MGU676
V
ref(DAC)
Fig.1 Block diagram.
2002 May 225
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
7PINNING
SYMBOLPINPAD TYPEDESCRIPTION
BCK15 V tolerant digital input pad; note 1bit clock input
WS25 V tolerant digital input pad; note 1word select input
DATAI35 V tolerant digital input pad; note 1serial data input
V
DDD
V
SSD
SYSCLK65 V tolerant digital input pad; note 1system clock input
SFOR175 V tolerant digital input pad; note 1serial format select 1
MUTE85 V tolerant digital input pad; note 1mute control
DEEM95 V tolerant digital input pad; note 1de-emphasis control
PCS103-level input pad; note 2power control and sampling frequency select
SFOR011digital input pad; note 2serial format select 0
V
ref(DAC)
V
DDA
VOUTL14analog output padDAC output left
V
SSA
VOUTR16analog output padDAC output right
4digital supply paddigital supply voltage
5digital ground paddigital ground
12analog padDAC reference voltage
13analog supply padDAC analog supply voltage
15analog ground padDAC analog ground
Notes
1. 5 V tolerantis only supportedif the powersupply voltage isbetween 2.7 and 3.6 V. Forlower power supplyvoltages
this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.
handbook, halfpage
BCK
WS
DATAI
V
DDD
V
SSD
1
2
3
4
UDA1334BT
5
6
7
8
MGU675
16
15
14
13
12
11
10
9
VOUTR
V
SSA
VOUTL
V
DDA
V
ref(DAC)
SFOR0SYSCLK
PCSSFOR1
DEEMMUTE
Fig.2 Pin configuration.
2002 May 226
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
8FUNCTIONAL DESCRIPTION
8.1System clock
The UDA1334BT operates inslave modeonly; thismeans
that in all applicationsthe systemmust providethe system
clock and the digital audio interface signals
(BCK and WS).
Thesystem clockmustbe lockedin frequency tothe digital
interface signals.
The UDA1334BT automatically detects the ratio between
the SYSCLK and WS frequencies.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: f
≤ 64 × fWS.
BCK
Remarks:
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
The modes which are supported are given in Table 1.
Table 1Supported sampling ranges
CLOCK MODESAMPLING RANGE
768f
512f
384f
256f
192f
128f
s
s
s
s
s
s
8to55kHz
8 to 100 kHz
8 to 100 kHz
8 to 100 kHz
8 to 100 kHz
8 to 100 kHz
(1)(2)
(2)
Notes
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in
192fsmode the sampling frequency should be limited
to 55 kHz.
2. Not supported in the low sampling frequency mode.
Table 2Example using a 12.228 MHz system clock
CLOCK MODESAMPLING FREQUENCY
128f
192f
256f
384f
512f
768f
s
s
s
s
s
s
96 kHz
64 kHz
48 kHz
32 kHz
24 kHz
16 kHz
(1)
Note
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in 192f
mode the sampling frequency should be limited to
55 kHz.
8.2Interpolation filter
The interpolation digital filter interpolates from 1fsto 64f
by cascading FIR filters (see Table 3).
Table 3Interpolation filter characteristics
ITEMCONDITIONVALUE (dB)
Pass-band ripple0 to 0.45f
Stop band>0.55f
Dynamic range0 to 0.45f
s
s
s
±0.02
−50
>114
8.3Noise shaper
The 5th-order noise shaper operates at 64f
. It shifts
s
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
s
s
An example is given in Table 2 for a 12.228 MHz system
clock input.
2002 May 227
Philips SemiconductorsProduct specification
Low power audio DACUDA1334BT
8.4Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivityis achieved. Nopost-filter is needed due to
the inherent filter functionof theDAC. On-boardamplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
handbook, halfpage
3.0 V
V
V
ref(DAC)
DDA
13
50 kΩ
RESET
12
CIRCUIT
8.5Power-on reset
The UDA1334BT has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin V
ref(DAC)
and
ground. The reset time should be at least 1 µs for
V
ref(DAC)
will be reset again for V
< 1.25 V. When V
ref(DAC)
is switched off, the device
DDA
< 0.75 V.
During the reset time the system clock should be running.
3.0
handbook, halfpage
V
DDD
(V)
1.5
V
0
3.0
DDA
(V)
1.5
t
C1 >
10 µF
50 kΩ
UDA1334BT
MGU678
Fig.3 Power-on reset circuit.
2002 May 228
V
ref(DAC)
(V)
1.25
0.75
3.0
1.5
0
0
>1 µs
Fig.4 Power-on reset timing.
t
t
MGL984
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