Philips UBA2070 Technical data

INTEGRATED CIRCUITS

DATA SH EET

UBA2070

600 V CCFL ballast driver IC

Product speciﬁcation Supersedes data of 2001 Sep 27

2002 Oct 24

Philips Semiconductors Product speciﬁcation

600 V CCFL ballast driver IC UBA2070

FEATURES

• Current controlled operation

• Adaptive non-overlap time control

• Integrated high voltage level shift function

• Power-down function

• Protected against lamp failures or lamp removal

• Capacitive mode protection.

APPLICATION

• The circuit topology enables a broad range of backlight inverters.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UBA2070T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 UBA2070P DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1

GENERAL DESCRIPTION

TheUBA2070isahighvoltageintegratedcircuitfordriving electronically ballasted Cold Cathode Fluorescent Lamps (CCFL) at mains voltages up to 277 V (RMS) (nominal value). The circuit is made in a 650 V Bipolar CMOS DMOS (BCD) power logic process. The UBA2070 provides the drive function for the two discrete MOSFETs. Besides the drive function the UBA2070 also includes the level-shift circuit, the oscillator function, a lamp voltage monitor, a current control function, a timer function and protections.

PACKAGE

2002 Oct 24 2

Philips Semiconductors Product speciﬁcation

600 V CCFL ballast driver IC UBA2070

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT

High voltage supply

Start-up state

DD(high)

DD(low)

DD(start)

Reference voltage (pin V

ref

Voltage controlled oscillator

bridge(max)

bridge(min)

Output drivers (pins GH and GL)

source

sink

Lamp voltage sensor (pin LVS)

LVS(fail)

LVS(max)

Average current sensor (pin CS)

offset

Ignition timer (pin CT)

high side supply voltage Ihs<30µA; t < 1 s −−600 V

oscillator start voltage 12.4 13 13.6 V oscillator stop voltage 8.6 9.1 9.6 V start-up current VDD<V

)

REF

DD(high)

− 170 200 µA

reference voltage IL=10µA 2.86 2.95 3.04 V

maximum bridge frequency 90 100 110 kHz minimum bridge frequency 38.9 40.5 42.1 kHz

source current VGH− VSH= 0; VGL= 0 135 180 235 mA sink current VGH− VSH=13V;

265 300 415 mA

VGL=13V

fail voltage level 1.19 1.25 1.31 V maximum voltage level 1.67 1.76 1.85 V

offset voltage VCS= 0 to 2.5 V −2 0 +2 mV transconductance f = 1 kHz 100 200 400 µA/mV

LOW-level output voltage − 1.4 − V HIGH-level output voltage − 3.6 − V

2002 Oct 24 3

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2002 Oct 24 4

REF

book, full pagewidth

BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

600 V CCFL ballast driver IC UBA2070

n.c.

GND

REFERENCE

CURRENT

SUPPLY

IGNITION TIMER

VOLTAGE

CONTROLLED

OSCILLATOR

714

reference

voltages

digital

supply (5 V)

analog

DD(low)

reset

LOGIC

3 V

DD(clamp)

STATE LOGIC

• reset state

• ignition state

• burn state

• hold state

• powerdown state

LAMP

VOLTAGE

SENSOR

LVS(fail)VLVS(max)

BOOTSTRAP

DRIVER

LOGIC

FREQUENCY

CONTROL

LOGIC

LEVEL

SHIFTER

ANT/CMD

HS DRIVER

LS DRIVER

AVERAGE CURRENT

SENSOR

ACM

15 16

CS CS

−

REF

LVS

MGT990

CSW

Fig.1 Block diagram.

Philips Semiconductors Product speciﬁcation

600 V CCFL ballast driver IC UBA2070

PINNING

SYMBOL PIN DESCRIPTION

CT 1 ignition timer output CSW 2 voltage controlled oscillator input CF 3 voltage controlled oscillator output I

REF

GND 5 ground GL 6 gate of the low side switch output V

n.c. 8 not connected FV

GH 10 gate of the high side switch output SH 11 source of the high side switch ACM 12 capacitive mode input LVS 13 lamp voltage sensor input V

REF

CS+ 15 average current sensor positive input CS− 16 average current sensor negative input

4 internal reference current input

7 low voltage supply

9 ﬂoating supply; supply for the high side switch

14 reference voltage output

handbook, halfpage

CSW

REF

GND

n.c.

1 2 3 4

UBA2070T

5 6 7 8

MGT985

−

CS V

REF

LVS

ACM

GH FV

Fig.2 Pin configuration (SO16).

2002 Oct 24 5

handbook, halfpage

CSW

REF

GND

n.c.

1 2 3 4

UBA2070P

5 6 7 8

MGT984

−

CS V

REF

LVS

ACM

GH FV

Fig.3 Pin configuration (DIP16).

Philips Semiconductors Product speciﬁcation

600 V CCFL ballast driver IC UBA2070

FUNCTIONAL DESCRIPTION Start-up state

Initial start-up can be achieved by charging C

VDD

using an externalstart-upresistor.Thestart-upofthecircuitissuch, that the MOSFETs Tls and Ths shall be non-conductive. The circuit will be reset in the start-up state. If the V supply reaches the value of V

the circuit starts

DD(high)

oscillating. A DC reset circuit is incorporated in the high side (hs) driver. Below the lockout voltage at pin FVDDthe output voltage (VGH− VSH) is zero. The voltages at pins CF and CT are zero during the start-up state.

Oscillation

The internal oscillator is a Voltage Controlled Oscillator circuit (VCO) which generates a sawtooth waveform between the high level at pin CF and 0 V (see Fig.4). The frequency of the sawtooth is determined by CCF, R

and the voltage at pin CSW. The minimum and

IREF

maximum frequencies are determined by CCF and R

IREF

The minimum to maximum ratio is fixed internally. The sawtooth frequency is twice the half bridge frequency. The IC brings the MOSFETs Thsand Tls alternately into conduction with a duty factor of 50%.The oscillator starts oscillating at f

. During the first switching cycle the

max

MOSFET Tls is switched on. To charge the bootstrap capacitorthe first conduction time after thestart-upstate is made extra long. In all other cases the duty factor at the start is 50%.

Non-overlap time

The non-overlap time is realized with an Adaptive Non-Overlap circuit (ANT). By using this circuit, the application determines the duration of the non-overlap time (determined by the slope of the half bridge voltage and detected by the signal across R

) and makes the

ACM

non-overlap time optimum for each frequency (see Fig.4). The minimum non-overlap time is internally fixed. The maximum non-overlap time is internally fixed at approximately 25% of the bridge period time.

Ignition state

After the start at f

the frequency will decrease due to

max

charging the capacitor at pin CSW with an internally fixed current. During this continuous decrease in frequency, the circuit approaches the resonant frequency of the lamp. This will cause a high voltage across the lamp, which ignites the lamp. The ignition voltage of the lamp is designedtobeabovethe V

level.Ifthelampvoltage

LVS(fail)

exceeds this voltage level the ignition timer is started (see Fig.5).

Burn state

If the lamp voltage does not exceed the V

LVS(max)

voltage at pin CSW will continue to increase until the clamp level at pin CSW is reached. As a consequence the frequency will decrease until the minimum frequency is reached. When the frequency reaches its minimum level it is assumed that the lamp has ignited, the circuit will enter the burn state and the Average Current Sensor (ACS)

circuit will be enabled (see Fig.5). As soon as the average voltage across R

(measured at pin CS−) reaches the

sense

reference level at pin CS+, the average current sensor circuit will take over the control of the lamp current. The average current through R

is transferred to a voltage

sense

at the voltage controlled oscillator to regulate the frequency and, as a result, the lamp current.

Lamp failure

DURING IGNITION STATE Ifthe lamp fails to ignite, thevoltage level increases. When

the lamp voltage exceeds the V

LVS(max)

level, the voltage will be regulated at that level. The ignition timer is started when the V pin LVS is above the V

level is exceeded. If the voltage at

LVS(fail)

level at the end of the

LVS(fail)

ignition time the circuit stops oscillation and is forced into aPower-downstate(seeFig.6).Thisstateisterminatedby switching off the VDD supply.

DURING BURN STATE

level the

Timing circuit

Atiming circuit is included (a clockgenerator)to determine the maximum ignition time. The ignition time is defined as 1 pulseat pin CT; the lamp has toignite within the duration of this pulse. The timer circuit starts operating when a critical value of the lamp voltage [V

LVS(fail)

] is exceeded. When the timer is not operating the capacitor at pin CT is discharged by 1 mA to 0 V.

2002 Oct 24 6

If the lamp fails during normal operation, the voltage across the lamp will increase and the lamp voltage will exceedthe V

level.This forces the circuit to re-enter

LVS(fail)

the ignition state and results in an attempt to re-ignite the lamp. If during restart the lamp still fails, the voltage remains high until the end of the ignition time. At the end of the ignition time the circuit stops oscillating and enters the Power-down state (see Fig.7).

+ 14 hidden pages