Philips UAA3580 User Guide

查询UAA3580供应商

INTEGRATED CIRCUITS

DATA SH EET

UAA3580

Wideband code division multiple
access frequency division duplex
zero IF receiver

Objective specification
Supersedes data of 2002 Oct 16

2002 Oct 30

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING INFORMATION

7.1 Pinning

7.2 Pin description
8 FUNCTIONAL DESCRIPTION

8.1 RF receiver front-end and RF VCO

8.2 Channel filter and AGC

8.3 RF VCO

8.4 RF LO section

8.5 RF fractional-N synthesizer PLL

8.6 Clock PLL

8.7 Control
9 OPERATING MODES

9.1 Basic operating mode

9.2 AGC gain look-up table

9.3 RF PLL synthesizer

9.4 Clock PLL synthesizer
10 PROGRAMMING

10.1 Serial programming bus

10.2 Data format

10.3 Register contents
11 LIMITING VALUES
12 THERMAL CHARACTERISTICS
13 DC CHARACTERISTICS
14 AC CHARACTERISTICS
15 SERIAL BUS TIMING CHARACTERISTICS
16 APPLICATION INFORMATION

17 PACKAGE OUTLINE
18 SOLDERING

18.1 Introduction to soldering surface mount

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for

19 DATA SHEET STATUS
20 DEFINITIONS
21 DISCLAIMERS

UAA3580

packages

wave and reflow soldering methods

2002 Oct 30 2

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

1 FEATURES

• Low noise wide dynamic range for zero IF receivers

• 79 dB gain control range; in steps of 1 dB

• Channel filters

• 96 dB voltage gain

• Fully integrated fractional-N synthesizer with AFC

control capability

• Fully integrated RF VCO withintegrated supply voltage
regulator

• Fully differential design to minimize crosstalk

• Supply voltage from 2.4 to 3.3 V

• 3-wire serial interface bus

• HVQFN24 package.

2 APPLICATIONS

• WCDM-FDDreceiver for GSM hand-portable equipment

• Dual mode GSM/GPRS/EDGE/UMTS handset.

UAA3580

3 GENERAL DESCRIPTION

The UAA3580 is a BiCMOS integrated circuit receiver
intended for the Third Generation Partnership Project
(3GPP) specification for the Universal Mobile
Telecommunication System (UMTS).

ThecircuitisspeciallydesignedfortheFrequencyDivision
Duplex (FDD) mode of the Wide Code Division Multiple
Access (WCDMA) that operates in the 2110 to 2170 MHz
band.

The UAA3580 contains the whole analog receive chain
from Radio Frequency (RF) Low Noise Amplifier (LNA) to
baseband IQ outputs including a channel filter, a complete
RF Phase-Locked Loop (PLL) with a fully integrated
Voltage Controlled Oscillator (VCO), and a clock PLL that
generates a programmable UMTS system clock from an
external 26 MHz reference signal.

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CCA

V

DDD

T

amb

5 ORDERING INFORMATION

TYPE

NUMBER

UAA3580HN HVQFN24 plastic, heatsink very thin quad flat package; no leads

analog supply voltage 2.6 − 3.3 V
digital supply voltage 1.6 − 2.8 V
ambient temperature −30 − +70 °C

PACKAGE

VERSION

NAME DESCRIPTION

SOT616-1

24 terminals; body 4 × 4 × 0.90 mm

2002 Oct 30 3

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

6 BLOCK DIAGRAM

handbook, full pagewidth

REFIN

V

CCA(SYN)

CPCLKO

V

CCA(CP)

RFCPO

CAPVCOREG

VCOGND

V

CCA(RF)

RFGND

RFIP
RFIN

IFGND

RXCEN

V

CCA(IF)

19

20

21
22
23

24

1
2
3

4
5
6
7
8

SIGMA DELTA

FRACTIONAL-N

RF VCO

VCO

REGULATOR

LNA

RF

DIVIDE-BY-2

MIXER

MIXER

RF

SIGMA DELTA

FRACTIONAL-N

UAA3580HN

DIVIDE-BY-2

VCO

SERIAL INTERFACE

18

17

16

15
14
13

12
11

10

9

REXT

UMTSCLKO

V

DDD

EN
CLK
DATA

QN
QP

IN
IP

FCA236

UAA3580

Fig.1 Block diagram.

2002 Oct 30 4

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

7 PINNING INFORMATION

7.1 Pinning

handbook, full pagewidth

IFGND

RFIN
RFIP

RFGND

V

CCA(RF)

VCOGND

6
5
4
3
2
1

CCA(IF)

V

RXCEN

8

7

UAA3580HN

UAA3580

IP

IN

9

10

QP
11

QN
12

13

DATA

14

CLK

15

EN
V

16

UMTSCLKO

17

REXT

18

DDD

22

23

24

RFCPO

CCA(CP)

V

CAPVCOREG

20

21

CPCLKO

CCA(SYN)

V

Fig.2 Pin configuration.

19

FCA237

REFIN

2002 Oct 30 5

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

7.2 Pin description

Table 1 HVQFN24 package

SYMBOL PIN DESCRIPTION

VCOGND 1 RF VCO ground
V

CCA(RF)

RFGND 3 RF receiver ground
RFIP 4 RF positive input
RFIN 5 RF negative input
IFGND 6 IF section ground
RXCEN 7 receiver chip enable input
V

CCA(IF)

IP 9 differential receive baseband positive in-phase output
IN 10 differential receive baseband negative in-phase output
QP 11 differential receive baseband positive in-quadrature output
QN 12 differential receive baseband negative in-quadrature output
DATA 13 serial bus data input
CLK 14 serial bus clock input
EN 15 serial bus enable input
V

DDD

UMTSCLKO 17 UMTS system clock output
REXT 18 external charge pump biasing resistor connection
REFIN 19 reference clock input
V

CCA(SYN)

CPCLKO 21 charge pump clock output
V

CCA(CP)

RFCPO 23 RF charge pump output
CAPVCOREG 24 decoupling capacitor for the VCO regulator

2 analog supply voltage for the RF receiver

8 analog supply voltage for the IF section

16 digital supply voltage

20 analog supply voltage for the synthesizer

22 analog supply voltage for the charge pump section

die pad ground

UAA3580

2002 Oct 30 6

Philips Semiconductors Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

8 FUNCTIONAL DESCRIPTION

The receiver consists of an RF receiver front-end, an
RF VCO, a channel filter, Automatic Gain Control (AGC),
a RF fractional-N synthesizer PLL, a clock PLL, a
Power-up reset circuit and a 3-wire serial programming
bus.

8.1 RF receiver front-end and RF VCO

The front-end receiver converts the aerial RF signal from
WCMDA (2.11 to 2.17 GHz) band down to a Zero
Intermediate Frequency (ZIF). The first stage is a
differential low noise amplifier matched to 50 Ω using an
external balun. The LNA is followed by an IQ down-mixer
which consists of two mixers in parallel but driven by
quadrature out-of-phase LO signals. The In phase (I) and
Quadrature phase (Q) ZIF signals are then low-pass
filtered, to provide protection from high frequency offset
interference, and fed into the channel filter.

8.2 Channel filter and AGC

The front-end zero IF I and Q outputs are applied to the
integrated low-pass channel filter with a provision for
4 × 8 dB gain steps in front of the filter. The filter is a
self-calibrated fifth-order low-pass filter with a cut-off
frequency around 2.4 MHz. Once filtered the zero IF
I and Q outputs are further amplified with provision for
47 × 1 dB steps and DC offset compensation. The zero IF
output buffer provides close rail-to-rail output signal.

8.3 RF VCO

The RF VCO is fully integrated and self-calibrated on
manufacturing tolerances. It consists of 16 different
frequency ranges that are selected internally, depending
on the frequency programmation. It covers the necessary
bandwidth of 4.22 to 4.34 GHz and is tuned via the RF
charge pump and external loop filter. An internal supply
voltage regulator using the pin CAPVCOREG as external
decoupling capacitor supplies the RF VCO and minimizes
parasitic coupling and pushing. The regulator and the RF
VCO are turned on by the RXCEN signal.

8.4 RF LO section

The RF LO section covering the 4.22 to 4.34 GHz band is
driven by the internal RF VCO module. It includes the LO
buffering for the RF PLL and a divide-by-two circuit to
generate the quadrature LO signals to drive the RX IQ
down-mixer.

UAA3580

8.5 RF fractional-N synthesizer PLL

A high performance RF fractional-N synthesizer PLL is
included on-chip which enables the frequency of the RF
VCOtobesynthesized.Thefrequencyissetviathe3-wire
serial programming bus.

The PLL is based on Sigma-Delta (Σ∆) fractional-N
synthesis that enables the required channel frequency,
including Automatic Frequency Control (AFC) from a free
running external 26 MHz GSM reference frequency, to be
obtained. Very low close in-phase noise is achieved which
allows a wider PLL loop bandwidth and a shorter settling
time. The programmable main dividers are controlled by a
second-order (Σ∆) modulus controller. They divide the RF
VCO signals down to frequencies of 26 MHz (in
programmable 12 Hz steps). Their phase is then
compared in a digital Phase/Frequency Detector (PFD) to
the 26 MHz reference clock signal. The phase error
informationis fed back to the RF VCO viathecharge pump
circuit that ‘sources’ into or ‘sinks’ current from the loop
filter capacitor, thus changing the VCO frequency so that
the loop is finally brought into phase-lock.

The RF synthesizer division range enables an external
reference frequency of 13 to 26 MHz to be used.

8.6 Clock PLL

The clock PLL is based on SD fractional-N synthesis that
allows the UMTS system clock, including AFC from a
non-correctedexternal 26 MHz GSM reference frequency,
to be obtained. The PLL comprises a fully integrated RC
VCO.The PLL output is a low harmonic content waveform,
the frequency of which can be programmed to

15.36, 30.72 or 61.44 MHz. The default value is

30.72 MHz.

8.7 Control

Thecontrolof the chip is done via the 3-wire serial bus and
pin RXCEN. At power-up the clock PLL section is
automatically enabled, the other sections are enabled
when the RXCEN signal is set HIGH (also via the 3-wire
bus). The power-up signal is detected on pin V
the voltage rises. The V
maintained, enables the programming parameters to be
retained in memory.

pin, if the supply voltage is

DDD

DDD

when

2002 Oct 30 7

Philips Semiconductors Objective specification

Wideband code division multiple access

UAA3580

frequency division duplex zero IF receiver

9 OPERATING MODES

9.1 Basic operating modes

The circuit can be powered up into different operating
modes, depending on the control bits RXON and SYNON,
via the 3-wire bus. This defines three main modes called
IDLE, SYN and RX mode.

The voltage level applied to pin RXCEN must be set HIGH
to enable the device. The VCO and the PLL sections are
enabled in SYN mode. In the RX mode every section is
enabled (receive part, VCO and PLL sections).

Table 3 AGC gain look-up table

AGC8 AGC7 AGC6 AGC5 AGC4 AGC3 AGC2 AGC1 AGC0

111111111 0
111111110 1
111111101 2
111111100 3
111111011 4
111111010 5
111111001 6
111111000 7
111110111 8
111110110 9
111110101 10
111110100 11
101111011 12
101111010 13
101111001 14
101111000 15
101110111 16
101110110 17
101110101 18
101110100 19
011111011 20
011111010 21
011111001 22
011111000 23
011110111 24
011110110 25
011110101 26
011110100 27
001111011 28
001111010 29

Table 2 Selection of operating mode

MODE SYNON RXON

IDLE 0 0
SYN 1 0
RX 1 1

9.2 AGC gain look-up table

The AGC gain is set via the AGC[8:0] bits; see Table 3.

ATTENUATION FROM

MAXIMUM GAIN (dB)

2002 Oct 30 8