Philips UAA2067G Datasheet

INTEGRATED CIRCUITS

DATA SH EET

UAA2067G

Image reject 1800 MHz transceiver
for DECT applications

Product specification
Supersedes data of 1995 Sep 18
File under Integrated Circuits, IC17

1996 Oct 22

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver
for DECT applications

FEATURES

• Receiver with:
– low noise amplifier
– dual quadrature mixers for image rejection

(lower sideband)

– I and Q combining networks at a fixed IF

• Both high-frequency and low-frequency VCOs including
buffers with good isolation for low pulling

• Transmitter with:
– dual quadrature mixers for image rejection

(lower sideband)
– amplitude ramping circuit
– amplifier with high output power.

APPLICATIONS

• 1800 MHz transceiver for DECT hand-portable
equipment

• TDMA systems.

GENERAL DESCRIPTION

The UAA2067G is a low-power transceiver intended for
use in portable and base station transceivers complying
with the DECT system. The IC performs in accordance
with specifications in the −30 to +85°C temperature range.

The UAA2067G contains a front-end receiver for the
1800 to 1900 MHz frequency range, a high-frequency
VCO for the 1650 to 1850 MHz range, a low-frequency
VCO for the 100 to 140 MHz frequency range and a
transmitter with a high-output power amplifier driver stage
for the 1800 to 1900 MHz frequency range. Designed in
an advanced BiCMOS process, it combines high
performance with low-power consumption and a high
degree of integration, thus reducing external component
costs and total radio size.

Its first advantage is to provide typically 34 dB of image
rejection in the receiver path. Thus, the image filter
between the LNA and the mixer is redundant and
consequently can be removed. The receive section

UAA2067G

consists of a low-noise amplifier that drives a quadrature
mixer pair. Image rejection is achieved by this RF mixer
pair and the two phase shifters in the I and Q channels that
phase shift the IF by 45° and 135° respectively. The two
phase shifted IFs are recombined and buffered to furnish
the IF output signal.

Signals presented at the RF input at LO − IF frequency are
rejected through this signal processing while signals at
LO + IF frequency can form the IF signal.

Its second advantage is to provide a good buffered
high-frequency VCO signal to the RX and TX mixers and
to the synthesizer-prescaler. Switching the receive or
transmit section on gives a very small change in VCO
frequency.

Its third advantage is to provide a good buffered
low-frequency VCO signal to the TX mixers, to the
synthesizer-prescaler and the second down conversion
mixer in a double conversion receiver. Switching the
transmit section on gives a very small change in
VCO frequency.

The frequency of each VCO is determined by a resonator
network that is external to the IC. Each VCO has a
regulated power supply voltage that has been designed
specifically for minimizing a change in frequency due to
changes in the power supply voltage, which may be
caused for instance by switching on the power amplifier.

Its fourth advantage is to provide typically 33 dBc of image
rejection in the single-sideband up-conversion mixer. Thus
the image filter between the power amplifier and the
antenna is redundant and may consequently be removed.
Image rejection is achieved in the internal architecture by
two RF mixers in quadrature and two phase shifters in the
low-frequency VCO signal that shifts the phase to
0° and 90°. The output signals of the mixers are summed
to form the single-upper-sideband output signal.

The output stage is a high-level output buffer with an
output power of approximately 4 dBm. The output level is
sufficient to drive a three-stage bipolar preamplifier
for DECT.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UAA2067G LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1

1996 Oct 22 2

PACKAGE

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver

UAA2067G

for DECT applications

QUICK REFERENCE DATA

For conditions see Chapters “DC characteristics” and “AC characteristics”.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

I

CC(RX)

I

CC(TX)

I

CC(RFLO)

I

CC(IFLO)

NF

RX

G

CP

IR

RX

f

RFLO

f

IFLO

P

out

IR

TX

T

amb

supply voltage 3.0 3.6 5.5 V
receive supply current − 24 − mA
transmit supply current − 42 − mA
RF oscillator supply current − 15 − mA
IF oscillator supply current − 7 − mA
receive noise figure −−7.0 dB
conversion power gain − 30 − dB
receive image frequency rejection − 34 − dB
RFLO frequency range 1.65 − 1.85 GHz
IFLO frequency range 100 − 140 MHz
output transmit power − 4 − dBm
transmit image frequency rejection − 33 − dBc
operating ambient temperature −30 +25 +85 °C

1996 Oct 22 3

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver
for DECT applications

BLOCK DIAGRAM

CC(IFLO)

IFO

25

∑

IFDEC

V

5

UAA2067

PDIFLO

1

GND2

IFLORES

6

7

IFLO

OSCILLATOR

IFLOREG

2

4

IFLOO

3

GND1

o

ICEN

8

0

UAA2067G

handbook, full pagewidth

MGC867

o

90

GND6

PDRX

CC(MIX)

V

GND7

28

RXA

LNA

29

RXB

o

135

23

18

CC2(RFLO)

CC1(RFLO)

V

V

22

GND5

15

PDRFLO

o

o

0

90

RFLO

OSCILLATOR

21

20

RFLOB

RFLOA

17

24

RFLOO

RFLOREG

19

16

GND4

CC(RFLOO)

V

13

TXA

∑

RAMP

12

TXB

14

11109

GND3

CC(TX)

V

PDTX TXRAMP

Fig.1 Block diagram.

o

45

30 26

32 27 31

1996 Oct 22 4

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver
for DECT applications

PINNING

SYMBOL PIN DESCRIPTION

PDIFLO 1 power-down for IFLO
IFLOREG 2 regulator decoupling for IFLO
GND1 3 ground for IFLO; note 1
IFLOO 4 IFLO output
V

CC(IFLO)

IFLORES 6 IFLO resonator
GND2 7 ground for IFLO resonator; note 1
ICEN 8 IC enable
PDTX 9 power-down for transmitter
TXRAMP 10 power ramping transmitter
V

CC(TX)

TXB 12 transmitter RF output B
TXA 13 transmitter RF output A
GND3 14 ground for transmitter output stage
PDRFLO 15 power-down for RFLO
V

CC(RFLOO)

RFLOO 17 RFLO output
V

CC1(RFLO)

GND4 19 ground for RFLO oscillator; note 4
RFLOA 20 RFLO resonator
RFLOB 21 RFLO resonator
GND5 22 ground for RFLO oscillator; note 4
V

CC2(RFLO)

RFLOREG 24 regulator decoupling for RFLO
IFO 25 receiver IF output
IFDEC 26 IF decoupling
V

CC(MIX)

RXA 28 receiver RF input A
RXB 29 receiver RF input B
GND6 30 ground for receive and transmit mixers
PDRX 31 power-down for receiver
GND7 32 die-pad ground

5 supply voltage for IFLO

11 supply voltage for transmitter output stage; note 2

16 supply voltage for RFLO output

18 supply voltage for RFLO oscillator; note 3

23 supply voltage for RFLO oscillator; note 3

27 supply voltage for receive and transmit mixers; note 2

UAA2067G

Notes

1. Pins 3 and 7 are internally short-circuited.

2. Pins 11 and 27 should be at the same DC voltage.

3. Pins 18 and 23 are internally short-circuited.

4. Pins 19 and 22 are internally short-circuited.

1996 Oct 22 5

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver
for DECT applications

handbook, full pagewidth

PDIFLO

IFLOREG

GND1

IFLOO

V

CC(IFLO)

IFLORES

GND2

ICEN

1
2
3
4
5
6
7
8

GND7
32

PDRX
31

GND6

RXB

30

29

UAA2067

RXA
28

CC(MIX)

V
27

IFDEC
26

IFO
25

24
23
22
21
20
19
18
17

RFLOREG
V

CC2(RFLO)

GND5
RFLOB
RFLOA
GND4
V

CC1(RFLO)

RFLOO

UAA2067G

9

10

11

12

13

TXB

PDTX

CC(TX)

V

TXRAMP

TXA

Fig.2 Pin configuration.

14

GND3

15

16

PDRFLO

CC(RFLOO)

V

MGC865

1996 Oct 22 6

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver
for DECT applications

FUNCTIONAL DESCRIPTION
Receive section

The circuit contains a balanced low-noise amplifier
followed by two high dynamic range mixers. The local
oscillator signals, shifted in phase to 0 and 90° mix the
amplified RF signal to the I and Q channels.These two
channels are buffered, phase shifted by 45° and 135°
respectively, amplified and recombined internally to realize
the image rejection. Signals at the RF input at RFLO − IF
frequencies are rejected through the signal processing
while signals at the RFLO + IF frequencies form the
IF signals.

An image rejection of typically 34 dB is obtained for an IF
between 100 and 120 MHz.

Balanced signals are used for minimizing crosstalk due to
package parasitics. The IF output is single-ended.
The typical load is 50 Ω.

Fast switching, on/off of the receive section is controlled
by the hardware input PDRX.

RFLO section

UAA2067G

Transmit section

The circuit contains two balanced mixers, each of which is
driven by the RFLO and IFLO signals. The output signal of
the two mixers is summed and buffered to obtain the single
upper-sideband signal at frequency RFLO + IFLO.

With the use of an off-chip time constant, the ramping
circuit defines the power ramp-up and ramp-down of the
pre-amplifier output signal.

Balanced signals are used for minimizing crosstalk due to
package parasitics.

Fast switching, on/off, of the transmit section is controlled
by the hardware input PDTX.

The power supply voltage of the transmit mixers, the
adding circuit and ramping circuit is taken from the
V
preamplifier output stage.

OPERATING MODES

To use the IC, all V
supply voltage.

and GND6 for maximum isolation from the

CC(MIX)

pins must be connected to the

CC

The high-frequency oscillator (RFLO oscillator) supplies
the local oscillator signal for the down-conversion (receive)
and up-conversion (transmit) mixers. This VCO uses an
on-chip regulator for a power-supply voltage-independent
output frequency. The buffered VCO signal is fed into a
phase shifter and an off-chip prescaler-synthesizer.
The output signal of the phase-shifter is used for driving
the RX and TX mixers. Due to the good isolation in the
buffer stages, a very small change in VCO frequency is
obtained when switching the RX and TX mixers on.

Fast switching, on/off of the oscillator section is controlled
by the hardware input PDRFLO.

IFLO section

The low-frequency oscillator (IFLO oscillator) internally
supplies the local oscillator signal to the single-sideband
transmit mixer. The buffered VCO signal is fed into a
phase shifter. The output signal of the phase-shifter is
used for driving the TX mixers.

Due to the good isolation in the buffer stages, a very small
change in VCO frequency is obtained when switching the
TX mixer on.

Fast switching on/off of the oscillator section is controlled
by the hardware input PDIFLO input.

For transceiving a DECT signal, the RFLO and IFLO
sections should be powered-on. After a stable frequency
has been reached (mainly determined by the synthesizer
design), the receiver or transmitter can be powered-on.

GMSK data modulation can be supplied in two different
ways: the data is directly modulated on IFLO or RFLO.

The ramping of the power level can be set with a time
constant that is external to the IC.

Table 1 gives the definition of the polarity of the switching
signals on the receive, the RFLO, the IFLO and the
transmit sections.

1996 Oct 22 7

Philips Semiconductors Product specification

Image reject 1800 MHz transceiver

UAA2067G

for DECT applications

Table 1 Switching signals on the receiver

SIGNAL SECTION LEVEL on/off

PDRX receive section powered-on LOW on

receive section powered-off HIGH off

PDRFLO RFLO section powered-on LOW on

RFLO section powered-off HIGH off

PDIFLO IFLO section powered-on LOW on

IFLO section powered-off HIGH off

PDTX transmit section powered-on LOW on

transmit section powered-off HIGH off

ICEN all sections disabled LOW off

all sections enabled HIGH on

Note

1. Active when ICEN is enabled.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

(1)

(1)

(1)

(1)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

∆GND difference in ground supply voltage applied

supply voltage − 6V

note 1 − + 0.3 V

between all grounds

P

l(max)

T

j(max)

P

dis(max)

T

stg

maximum power input − +20 dBm
maximum operating junction temperature − +150 °C
maximum power dissipation in stagnant air at 25°C − 500 mW
storage temperature −65 +150 °C

Note

1. Pins short-circuited internally must be short-circuited externally.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 90 K/W

HANDLING

Every pin withstands the ESD test in accordance with

“MIL-STD-883C class 2 (method 3015.5)”

.

1996 Oct 22 8