Philips UAA1570HL Datasheet

INTEGRATED CIRCUITS

DATA SH EET

UAA1570HL

Global Positioning System (GPS) front-end receiver circuit

Product speciﬁcation File under Integrated Circuits, IC18

1999 May 10

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING INFORMATION 7 FUNCTIONAL DESCRIPTION

7.1 Low noise amplifiers LNA1 and LNA2

7.1.1 LNA1IN

7.1.2 LNA1OUT

7.1.3 LNA2IN

7.1.4 LNA2OUT

7.1.5 MX1IN

7.1.6 General remarks and results

7.2 Correlation of the UAA1570HL data sheet, application and test boards

7.3 RF mixer with preamplifier

7.4 VCO

7.5 First IF filter

7.6 Second IF mixer

7.7 Second IF filter

7.8 Time and amplitude quantization

7.8.1 Clock inputs

7.8.2 CMOS to ECL sample clock squaring circuit

7.8.3 Time quantization (sampler)

7.8.4 TTL output stage

7.8.5 1-bit delays

7.9 Programmable synthesizer

7.9.1 VCO prescaler

7.9.2 Main synthesizer dividers (N-path)

7.9.3 Second local oscillator dividers (L-path)

7.9.4 Reference dividers (R-path)

7.10 Serial interface

7.10.1 p0 and p1

7.10.2 r5

7.10.3 r0, r1, r2, r3 and r4

7.10.4 n7

7.10.5 n0, n1, n2, n3, n4, n5 and n6

7.10.6 l0, l1, l2 and l3

7.11 The serial interface word

7.12 The default frequency plan

7.13 Phase detector, charge pump and loop filter

8 OPERATING MODE SELECTION TABLES

8.1 Manual selection operating modes 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 CHARACTERIZATION TEST CIRCUIT 14 DEFAULT APPLICATION AND

15 INTERNAL CIRCUITRY 16 PACKAGE OUTLINE 17 SOLDERING

17.1 Introduction to soldering surface mount

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS

UAA1570HL

DEMONSTRATION BOARD

packages

wave and reflow soldering methods

1999 May 10 2

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

1 FEATURES

• Complete single-chip programmable

double-superheterodyne C/A-code GPS receiver

• Programmable high IF frequencies supporting

wideband/P-code GPS and Global Navigation Satellite System (GLONASS) applications

• Supports frequency plans with a 2nd IF of

4 × f0(1.023 MHz) = 4.092 MHz

• 48-pin LQFP package

•−40 to +85 °C operating temperature range

• 2.7 V minimum supply voltage

• Low DC power consumption [57 mA typical with both

Low-Noise Amplifiers (LNAs) active]

• Power-down mode (<900 µA)

• Typical receiver noise figure at 1.57542 GHz: 4.5 dB

• Typical phase noise −72 dBc/Hz at 10 kHz offset

• Simple microstrip LNA1/2 and first mixer matching

• Single pin VCO with external varactor and resonator

• Digital Phase Locked Loop (DPLL) synthesizer with

programmable VCO, 2nd Local Oscillator (LO) and reference dividers

• 3-bit synthesizer and power-down control input

• Reference and independent sample clock input with

internal squaring

• 1-bit amplitude quantized and time sampled TTL/CMOS

compatible output driver

• High active gain supporting SAW filter applications

• Configurable for external first LNA applications.

UAA1570HL

2 GENERAL DESCRIPTION

The UAA1570HL is a complete single-chip double-superheterodyne receiver front-end intended for GPS and GLONASS navigation systems. The IC includes a programmable on-chip DPLL synthesizer, VCO with external varactor and resonator, a 1-bit amplitude quantizer and a time sampled TTL/CMOS compatible SIGN output bit driver. It can be used with either an active or passive antenna system by disabling or enabling the on-chip LNAs and is ideally suited for low power GPS receiver applications because of its 3 V supply and the power management features through control pins.

Programmable prescaler controls provide the flexibility of using different frequency schemes.

The UAA1570HL is optimized to provide SIGN bit data to the companion Philips part, the SAA1575HL baseband digital signal processor. The SAA1575HL can provide the sample clock input to the UAA1570HL by dividing a TTL/CMOS level reference clock signal down to a programmable sampling clock output frequency. Both ICs can also be used independently.

The UAA1570HL is supplied in a low profile, 48-pin LQFP package for excellent Radio Frequency (RF) performance and small size.

3 ORDERING INFORMATION

TYPE

NUMBER

UAA1570HL LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

1999 May 10 3

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

4 QUICK REFERENCE DATA

CCA=VDDD

=3V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CCA

DDD

VCCA

+ I

analog supply voltage 2.7 3 5 V digital supply voltage 2.7 3 5 V analog supply current plus digital

VDDD

supply current

G G G G ∆V

RF IF1 IF2 v(lim)

lim(M)

available RF power gain LNAs at 1.57542 GHz − 31 − dB available 1st mixer power gain MX1 at 1.57542 GHz − 17.7 − dB available 2nd mixer power gain MX2 at 41.8 MHz − 21.4 − dB limiter voltage gain to 1st latch limiter at 3.48 MHz − 78 − dBV differential limiter sensitivity

(peak value)

amb

receiver noise ﬁgure f = 1.57542 GHz − 4.5 5.2 dB operating ambient temperature V

=25±2°C; unless otherwise speciﬁed.

amb

V V

f = 3.48 MHz − 100 −µV

V V

CCA CCA

CCA CCA CCA

and V and V

and V and V and V

= 2.7 V − 55.1 62.3 mA

DDD

=5V − 61 69.3 mA

DDD

= 3.3 to 5 V −40 +25 +85 °C

DDD

=3to5V −30 +25 +85 °C

DDD

= 2.7 to 5 V 0 +25 +85 °C

DDD

1999 May 10 4

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

5 BLOCK DIAGRAM

handbook, full pagewidth

CCA(LNA1)

LNA1GND1

P42GND

CCA(LNA2) LNA2GND1

LNA2IN

BIASGND2

LNA2GND2

LNA2OUT

CLOCK

1 2 3

LNA2

4 5 6

to data register

LNA1GND2

BIASGND1

LNA1OUT

48 47 46 45 44 43

LNA1IN

LNA1

UAA1570HL

DIVIDE-BY-1 or 2

P41GND

DIVIDE-BY-1 or 2

COMP

4042 41 39 38

PHASE

FREQUENCY

DETECTOR

DIVIDE-BY-2

DIVIDE-BY-N

(64 to 127)

UAA1570HL

P39GND

PLLGND

(1)

DATA REGISTER

PROGRAMMING

SCLK

SQUARING

CIRCUIT

FOR

CCA(PLL)

DGND

DDD

CCA(LIM)

DATA

9 10 11

SQUARING

CIRCUIT

VCO

13 14 15 16 17 18

MXPGND

REFIN

CCA(VCO)

TANK

VCOGND

P12GND

Shaded blocks are NOT active during synthesizer state. (1) The default values are: L = 10, N = 71 and R = 4.

MX1IN

DIVIDE-BY-R

(4 to 31)

MX1GND

CCA(MX1P)

IF1P

(1)

DIVIDE-BY-2

DIVIDE-BY-L

(4 to 15)

IF1N

to data

STROBE

DIVIDE-BY-3

(1)

DIVIDE-BY-2

19 20 21 22 24

CCA(MX2)

MIXER 2MIXER 1

IF2INN

MX2GND

IF2INP

QUANTIZER

IF2P

34 30 29 28 27 26

MHB269

SIGN BFCP LIMINP LIMINN BFCN LIMGND

IF2N

Fig.1 Block diagram.

1999 May 10 5

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

6 PINNING INFORMATION

PIN VOLTAGE

SYMBOL PIN

CCA(LNA2)

1 2.7 5 LNA2 power supply: DC operation range 2.7 to 5 V; use close

LNA2GND1 2 0 0 LNA2 ground 1: minimize RF ground inductance LNA2IN 3 0.815 0.807 LNA2 input: use external RF AC coupling BIASGND2 4 0 0 LNA2 bias circuit ground: minimize RF ground inductance LNA2GND2 5 0 0 LNA2 ground 2: minimize RF ground inductance LNA2OUT 6 1.48 3.629 LNA2 output: use external RF AC coupling. The DC voltage is

CLOCK 7 CMOS level CMOS level Serial interface clock input: this DC coupled CMOS CLOCK

REFIN 8 1.69 3.99 Reference input: use external AC coupling. The DC voltage is

CCA(VCO)

9 2.7 5 VCO power supply: DC operation range 2.7 to 5 V; use critical

TANK 10 1.92 1.92 VCO negative impedance resonator port: use the absolute

VCOGND 11 0 0 VCO ground: minimize RF ground inductance; use critical

P12GND 12 0 0 this pin provides additional RF shielding and has to be

MXPGND 13 0 0 RF mixer preampliﬁer ground: minimize RF ground inductance MX1IN 14 0.82 0.81 RF mixer preampliﬁer input: use external AC coupling and RF

MX1GND 15 0 0 RF mixer ground: minimize RF ground inductance; use critical

CCA(MX1P)

16 2.7 5 RF preampliﬁer/mixer power supply: DC operation range

IF1P 17 2.7 5 RF mixer IF positive output: DC couple this output pin to the

TYPICAL VALUES (V)

VCC= 2.7 V VCC=5V

DESCRIPTION

proximity RF decoupling to pins 2, 4 and 5

approximately 1.3 V below the V

CCA(LNA2)

supply on pin 1.

input moves 20-bit programming words into the synthesizer DATA input register while the STROBE is LOW. A DC short-circuit to ground is recommended with the default frequency plan.

approximately 1 V below the V

CCA(PLL)

supply on pin 36.

close proximity RF decoupling to pin 11

minimum trace lengths and widths and keep the loop to the VCO ground pin 11 as short as possible, while centring the COMP output voltage at pin 40 within the charge pump output voltage range given in Chapter 1 1 by adjusting the resonator inductance and/or required AC coupling component.

close proximity RF decoupling to VCO supply pin 9

connected to ground

matching

close proximity RF decoupling to V

CCA(MX1P)

supply pin 16

2.7 to 5 V; use critical close proximity RF decoupling to pin 15

CCA(MX1P)

supply through ﬁrst IF ﬁlter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced ﬁrst mixer IF1 outputs are recommended. Prevent externally squared reference harmonics from entering the ﬁrst IF signal path or components.

1999 May 10 6

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

PIN VOLTAGE

SYMBOL PIN

IF1N 18 2.7 5 RF mixer IF negative output: DC couple this output pin to the

CCA(MX2)

19 2.7 5 IF mixer power supply: if present, decouple the common V

MX2GND 20 0 0 IF mixer ground: minimize IF ground inductance; use close

IF2INN 21 0.983 0.98 IF mixer negative input: use external AC coupling. Balanced

IF2INP 22 0.983 0.98 IF mixer positive input: use external AC coupling. Balanced

STROBE 23 CMOS level CMOS level Serial interface strobe input: a LOW level on this DC-coupled

IF2P 24 2.7 5 IF mixer second IF positive output: DC couple this output pin

IF2N 25 2.7 5 IF mixer second IF negative output: DC couple this output pin

LIMGND 26 0 0 Limiter ground: minimize ground inductance BFCN 27 1.696 3.999 Negative limiter input DC feedback loop decoupling:

LIMINN 28 1.696 3.999 Negative limiter input: AC couple this pin to the second IF ﬁlter

TYPICAL VALUES (V)

= 2.7 V VCC=5V

DESCRIPTION

CCA(MX1P)

line sourcing the ﬁrst and second mixer by placing a large decoupling capacitor between the two

proximity IF decoupling to the V

CCA(MX2)

supply pin 19

IF1 second mixer inputs are recommended. Prevent externally squared reference harmonics from entering the ﬁrst IF signal path or components.

CMOS STROBE input enables the CLOCK input to load the 20-bit programming word into the synthesizer input DATA register. A mandatory DC short-circuit to ground is required to ensure that the default frequency plan is invoked on power-up.

to the V

CCA(MX2)

supply through second IF ﬁlter inductors or RF chokes. Capacitively decouple the supply near the output inductors. Balanced second mixer IF2 outputs are optional for many applications. Short the unused IF2P or IF2N output directly to the supply in single-ended applications.

to the V

CCA(MX2)

AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the V

CCA(LIM)

supply

on pin 31. No DC coupling.

output or to ground if unused with single-ended ﬁlter applications. The DC voltage is approximately 1 V below the V

CCA(LIM)

supply on pin 31. No DC coupling.

1999 May 10 7

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

PIN VOLTAGE

SYMBOL PIN

LIMINP 29 1.696 3.999 Positive limiter input: AC couple this pin to the second IF ﬁlter

BFCP 30 1.696 3.999 Positive limiter input DC feedback loop decoupling:

CCA(LIM)

31 2.7 5 Limiter, sample clock squaring and sampler Emitter

DATA 32 CMOS level CMOS level Serial interface data input: this DC-coupled CMOSDATA input

DDD

33 2.7

SIGN 34 TTL output TTL output Amplitude and time quantized second IF output signal:

DGND 35 0 0 SIGN bit TTL output driver sink ground: critically isolate this

CCA(PLL)

36 2.7 5 Synthesizer power supply: decouple in close proximity to

SCLK 37 1.34 2.5 Sample clock squaring input: accepts LOW-level AC coupled

PLLGND 38 0 0 PLL ground: minimize ground inductance; use close proximity

P39GND 39 0 0 this pin provides additional RF/IF shielding and has to be

TYPICAL VALUES (V)

VCC= 2.7 V VCC=5V

5 (independent of VCClevel)

(independent

of VCClevel)

DESCRIPTION

output or to ground if unused with single-ended ﬁlter applications. The DC voltage is approximately 1 V below the V

CCA(LIM)

supply on pin 31. No DC coupling.

AC couple this pin to ground in close proximity to the pin. The DC voltage is approximately 1 V below the V

CCA(LIM)

supply

on pin 31. No DC coupling.

Coupled Logic (ECL) circuits power supply: decouple in close proximity to pins 26 and 31. If present, isolate from the common VCC line sourcing the ﬁrst and second mixer by placing a large decoupling capacitor between this block and the mixers.

accepts 20-bit programming words into the synthesizer data input register, while the STROBE is LOW, on the rising edge of the CLOCK input. A DC short-circuit to ground is recommended with the default frequency plan.

SIGN bit TTL output driver power supply: critically isolate and separately decouple this digital V analog (V

) supplies. Maintain minimum trace lengths to

CCA

supply from all other

DDD

decoupling components. Particular attention should be applied to prevent coupling into V

CCA(LIM)

pin 31. If SAA1575HL is used,

use the digital supply from the back-end.

extreme care should be taken to isolate this sampled TTL output signal from all analog traces and components, particularly the second IF ﬁlter components at the limiter input. Avoid coupling into the reference oscillator signal trace.

digital supply ground from all other analog supplies and grounds. Maintain minimum trace lengths to decoupling components.

pin 38

sample clock inputs directly from the PLL reference oscillator or DC-coupled externally squared digital clocks derived from the PLL reference oscillator after external frequency division. The maximum DC-coupled input level at pin 37 should not exceed 75% of the V

CCA(LIM)

half the supply value on V

decoupling to the V

supply value. The threshold level is set at

CCA(LIM)

CCA(PLL)

pin 31.

supply pin 36

connected to ground

1999 May 10 8

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

PIN VOLTAGE

SYMBOL PIN

COMP 40 depends on

P41GND 41 0 0 this pin provides additional RF/IF shielding and has to be

P42GND 42 0 0 this pin provides additional RF/IF shielding and has to be

CCA(LNA1)

LNA1GND1 44 0 0 LNA1 ground 1: minimize RF ground inductance LNA1IN 45 0.815 0.807 LNA1 input: use external RF AC coupling BIASGND1 46 0 0 LNA1 bias circuit ground: minimize RF ground inductance LNA1GND2 47 0 0 LNA1 ground 2: minimize RF ground inductance LNA1OUT 48 1.48 3.629 LNA1 output: use external RF AC coupling. The DC voltage is

43 2.7 5 LNA1 power supply: DC operation range 2.7 to 5 V; use close

TYPICAL VALUES (V)

= 2.7 V VCC=5V

depends on VCO application

VCO

application

DESCRIPTION

Charge pump phase frequency detector output: the PLL loop

ﬁlter is connected in shunt and close proximity to this pin. The PLL loop ﬁlter tuning control voltage should be routed to the external VCO varactor circuit using minimal trace lengths in complete isolation from all potential coupling sources.

connected to ground

proximity RF decoupling to pins 44, 46 and 47.

approximately 1.3 V below the V

CCA(LNA1)

supply on pin 43.

1999 May 10 9

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

handbook, full pagewidth

LNA1IN

LNA1GND1

UAA1570HL

CCA(LNA1)

CCA(LNA2) LNA2GND1

LNA2IN

BIASGND2

LNA2GND2

LNA2OUT

CLOCK

REFIN

CCA(VCO)

TANK

VCOGND

P12GND

BIASGND1

LNA1OUT

LNA1GND2

1 2 3 4 5 6 7 8 9

10 11 12

P41GND

P42GND 42

COMP 40

PLLGND

P39GND 39

SCLK

36 35 34 33 32 31 30 29 28 27 26 25

CCA(PLL)

DGND SIGN V

DDD

DATA V

CCA(LIM)

BFCP LIMINP LIMINN BFCN LIMGND IF2N

UAA1570HL

MX1GND

CCA(MX1P)

IF1P

MX1IN

MXPGND

Fig.2 Pin configuration.

1999 May 10 10

IF1N

MX2GND

CCA(MX2)

IF2INN

IF2INP

24 37

IF2P

STROBE

MHB270

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

7 FUNCTIONAL DESCRIPTION

The programmability of the UAA1570HL and flexible interface definitions allow the device to be configured for a wide range of applications. To restrict the content of this document the functional description of the device will generally concentrate on the C/A-code application circuit based on the default frequency plan.

The application circuit does not allow easy measurement, calibration and documentation of the many sub-block characteristics which ensure good system performance. Therefore, test boards have been developed which allow direct measurement of the sub-block characteristics.

The tables and graphs reflect the UAA1570HL specification as derived from simulation and measured results in these characterization board environments. The tables and graphs do not directly specify application board expectations. The functional description however, focuses on the default application.

The RF system diagram (see Fig.3) illustrates the default application of the UAA1570HL in the Philips GPS demonstration board. In this application the UAA1570HL is intended to be operated directly from a passive GPS antenna through a very short antenna cable. Any cable loss in this demonstrator adds directly to the system noise figure and should therefore be minimized.

UAA1570HL

LNA1 can be powered down in the UAA1570HL to accommodate applications built around external LNAs, typically where long antenna cable runs are required.

The first LNA is assumed to be matched with a 2nd-order band-pass structure to provide some input selectivity, since no dielectric or SAW filter has been used in the demonstration board. It should be noted that low loss RF SAW filters now make it possible to significantly improve the jam immunity of this amplifier, by placing a SAW filter at the output of the antenna.

On the demonstration board the first LNA is followed by a low loss RF SAW filter (<2.4 dB).

On the demonstration board the second LNA has been matched to 50 Ω using a simple transmission line structure.

Finally, another identical RF SAW filter follows the second LNA into the first mixer.

1999 May 10 11

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

handbook, full pagewidth

L = 1020 mils W = 8.8 mils

C326

ISOLATE THE REFERENCE INPUT AND ITS HARMONICS FROM THE FIRST IF AND ITS FILTERING COMPONENTS

REFIN

C307

J301

BPF301

SAW

C306 C320

VRF

R314

C339

tune

L = 217 mils W = 33 mils

50 Ω

line stretcher

analog ground

digital ground

C327 C328

L = 900 mils W = 8.8 mils

L = 286 mils

W = 6 mils

100 Ω

C323

L = 412 mils

W = 6 mils

100 Ω

C331

D301

BPF302

SAW

CLOCK

REFIN

C338

R316

R307

L = 355 mils

W = 6 mils

C334

L305

100 Ω

VRF

C322

VRF

line stretcher

C321

L = 386 mils

W = 6 mils

100 Ω

L = 376 mils W = 33 mils

50 Ω

C324

L = 315 mils W = 6 mils 100 Ω

C330

R311

C325

VRF

C335

C313

R322

VRF

C346

UAA1570HL

C332

R310

L307L306

tune

C316

C315

R315

C305

C341

C340

C319

R306 L304

L303

C314

R319

STROBE

C317C318

3848 47 46 45 44 43 42 41 40 39 37

2313 14 15 16 17 18 19 20 21 22 24

OPTIMUM PERFORMANCE REQUIRES THAT THE GPS DIGITAL BASEBAND, SUPPLY REGULATORS, AND OTHER SOURCES OF DIGITAL NOISE BE PLACED IN THIS RELATIVE ORIENTATION TO THE UAA1570HL.

SCLK

C337

C311

C312

C336

DATA

C310

SIGN

R305

UAA1570HL

ISOLATE THESE DIGITAL SIGNALS,

SUPPLIES, AND GROUNDS FROM ALL ANALOG RF FUNCTIONS.

C329

DDD

C347

C303

L302

L301

R301/C301

C301

C309

C304 C302

R323

C308

L309

L308

C345

MHB271

Fig.3 UAA1570HL RF system diagram (default application).

1999 May 10 12

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

7.1 Low noise ampliﬁers LNA1 and LNA2

Two identical LNAs are provided on the IC although LNA1 need not be biased, if sufficient external gain is provided by an external LNA. The input stage of each amplifier consists of an unbalanced common emitter and a cascode stage. The AC-coupled output stage is a compound feedback bootstrap amplifier. Each stage is independently biased and regulated. LNA1 can be disabled by connecting the respective supply (pin 43) to ground. LNA2 has to be powered-up even if not used.

Each LNA can supply a power matched gain of approximately 15.5 dB with an associated noise figure of

3.7 dB. Both LNAs have −1 dB input compression points of

approximately −22 dBm from a 3 V supply. The 2nd and 3rd-order input intercepts are approximately

−7.9 and −13 dBm, respectively, in a power matched environment.

The RF match impedances at L1 (1.57542 GHz) are provided in Table 1 for all RF inputs and outputs.

Table 1 RF matching impedances

REAL PART

(Ω)

45 31 −j32 LNA1 input 48 77.5 +j6 LNA1 output

324 −j25 LNA2 input 6 74.5 −j0.5 LNA2 output

14 33.5 −j25.5 1st mixer input

IMAGINARY

PART (Ω)

FUNCTION

UAA1570HL

These RF port impedances are marked on the following Smith charts (see Figs 4 to 8; normalized to 50 Ω) and suggested matching structure netlists are provided. They contain transmission lines defined by their characteristic impedance Z (in ohms), their electrical length E (in degrees) and the operating frequency f (in GHz). Capacitors C are given in pF. TLIN is a series transmission line and TLOC is an open-circuit stub transmission line. Node 1 is the UAA1570HL RF port being matched and Node 0 is ground. These matching networks are structurally identical to those illustrated on the GPS application block diagram, however, the component values in the application diagram are somewhat different to account for stray capacitances and other real world influences. The netlists are derived from EEZMATCH software (Besser Associates, Los Altos, CA, USA).

Generally, we assume a minimum shunt capacitance, due to the IC pin pad and adjacent pin strays, of approximately

0.25 pF as an initial stray element in the netlist below, that will always be present in the matching structure design. This value should be re-estimated and matched if the layout introduces significant additional strays at the pin pads.

1999 May 10 13

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

7.1.1 LNA1IN CAP10C=0.25 ! C1 C = PF TLIN12Z=97.0 E = 34.5 F = 1.57542 ! TL1 Z = OH, E = DEG, F = GHZ CAP 2 0 C = 2.0 ! C3 C = PF Alternatively the 2 pF shunt capacitance at the input of the 97 Ω matching line above might be replaced with a 25 Ω

microstrip open stub if space permits. TLOC20Z=25.0 E = 26.1 F = 1.57542

handbook, full pagewidth

0.5

0.2

+ j

− j

0.2

0.5

0.5 1

Fig.4 LNA1 input impedance and matching network.

∞

MHB318

1999 May 10 14

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

7.1.2 LNA1OUT To facilitate matching of both LNA outputs, a small shunt capacitance should be placed as close as possible to the output

pin pad increasing the assumed 0.25 pF lumped pin capacitance by approximately 0.5 pF to 0.75 pF. This ensures that a simple, short, high impedance transmission line will provide a good 50 Ω match at high gain. A via to the opposite side of the board right at this output pin allows a stub or chip capacitance to be added without comprising the characteristics of the 97 Ω matching line.

CAP10C=0.25 ! C22 C = PF IND128L=0.7!L7=NH CAP280C=7.1658792e−1 ! C23 C = PF TLIN 28 29 Z = 97.0 E = 26.239010 F = 1.57542 ! TL15 If an open line stub is used, the latter components have to be replaced by: TLOC 280Z=20.0 E = 8.0 F = 1.57542 ! OTL7 Z = OH, E = DEG, F = GHZ TLIN 28 30 Z = 97.0 E = 26.2 F = 1.57542 ! TL16 Z = OH, E = DEG, F = GHZ

handbook, full pagewidth

0.5

0.2

+ j

− j

0.2

0.5

0.5 1

Fig.5 LNA1 output impedance and matching network.

∞

MHB319

1999 May 10 15

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

7.1.3 LNA2IN CAP10C=0.25 ! C13 C = PF TLIN 1 14 Z = 97.0 E = 30.0 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP140C=2.3309277 ! C14 C = PF

handbook, full pagewidth

+ j

− j

0.5

0.2

0.5

UAA1570HL

∞

0.2

0.5

Fig.6 LNA2 input impedance and matching network.

MHB320

1999 May 10 16

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

7.1.4 LNA2OUT CAP10C=0.25 ! C22 C = PF IND131L=0.1!L8 L=NH CAP310C=0.5!C24C=PF TLIN 31 32 Z = 97.0 E = 25.077020 F = 1.57542 ! TL17 Z = OH, E = DEG, F = GHZ In the event that the second capacitor is replaced by an open line stub, the last two components have to be changed: TLOC 310Z=20.0 E = 5.5 F = 1.57542 ! OTL8 Z = OH, E = DEG, F = GHZ TLIN 31 33 Z = 97.0 E = 24.460094 F = 1.57542 ! TL = 18 Z = OH, E = DEG, F = GHZ

handbook, full pagewidth

0.5

0.2

+ j

− j

0.2

0.5

0.5 1

Fig.7 LNA2 output impedance and matching network.

∞

MHB321

1999 May 10 17

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

7.1.5 MX1IN CAP10C=0.25!C5C=PF TLIN 1 13 Z = 100.0 E = 31.083933 F = 1.57542 ! TL9 Z = OH, E = DEG, F = GHZ CAP130C=1.673902 ! C6 C = PF Again an alternative open stub line is suggested which could be used to replace the 1.67 pF capacitance at this end of

the previous netlist. TLOC 130Z=25.0 E = 23.0 F = 1.57542 ! OTL5 Z = OH, E = DEG, F = GHZ

handbook, full pagewidth

0.5

0.2

+ j

− j

0.2

0.5

Fig.8 MX1 input impedance and matching network.

∞

MHB322

1999 May 10 18

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end

UAA1570HL

receiver circuit

7.1.6 GENERAL REMARKS AND RESULTS The RF match has an important effect on the gains, noise figure, and dynamic characteristics of the RF system blocks.

Reflection coefficients better than −15 dB are easily attainable and can be improved to better than −25 dB with attention to details.

handbook, halfpage

output

(dBm)

−20

−40

−60

−80

(1)

MHB272

(2)

(3)

(1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output.

−100

−90 −70 −50 −10

−30

input (dBm)

Fig.9 Typical LNA fundamental, 2nd and 3rd-order product output levels as a function of input level.

In the following graph (see Fig.10) the solid trace G

(dB) represents the measured frequency response of the

LNA

UAA1570HL LNAs as measured on a spectrum analyzer, while the dotted and dashed results were obtained using a noise figure meter over a more restricted frequency range.

handbook, halfpage

LNA

(dB)

1575.42

(2)

(1)

(3)

MHB273

15.3

3.68

(1) LNA gain (dB). (2) Power gain. (3) Noise figure.

−10 0 1000 2000 3000

f (MHz)

Fig.10 Typical LNA gain and noise figure as a function of frequency (50 Ω power matched on the input and

output).

1999 May 10 19

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

7.2 Correlation of the UAA1570HL data sheet, application and test boards

These boards use a 1 : 16 Ω ratio RF transformer to transform 50 Ω to the more appropriate value of 800 Ω at IF frequencies. The high-impedance side of these transformers is terminated with a physical resistor to adjust the UAA1570HL impedance at the port being measured, to approximately 800 Ω. This ensures that a calibrated signal is applied or received in the 50 Ω test environment. The transformer provides marginal performance at

41.8 MHz, so calibration results for this transformer are

also included in this document. The 800 Ω impedance environment is somewhat less than

that used in the application board. The UAA1570HL Characteristic tables provided in this document are calibrated to this 800 Ω environment as quantified in the notes at the end of the table. The effects of the transformer and associated termination losses have also been removed to some extent, so that specifications reflect the performance of the IC. The measured graph results were all derived from the test boards and corrected to again reflect part performance as much as possible.

However, this was not always possible, so some discussion concerning the measurement limitations is provided where appropriate. Where possible, fundamental design relationships and limitations are indicated.

UAA1570HL

In addition to the direct effects of power losses introduced by the transformer (approximately −1.3 dB at 41.82 MHz), which are reflected in the measured S21 results, the test board results may also be impacted by deficiencies in the transformer 1 : 4 voltage step-up ratio at 41.8 MHz; however, this has not been quantified.

An additional correction must be made to the current test results to compensate for internal 4 pF shunt capacitors on each collector output of the first mixer, which have not been resonated out in the testing.

The first mixer measurements also include a 3 dB loss due to the 800 Ω transformer termination. This loss is also removed from the specification result. The second mixer has similar 2.1 dB input and 3 dB output transformer termination losses removed from the specification.

For measurements made at 3.48 MHz in the second IF,

0.4 dB must be added to the measured results to reflect transformer losses at IF2, also.

In summary the measured gain of the first mixer has been increased by 1.3 dB (transformer IL) + 1.4 dB (capacitive roll-off effects) + 0.2 dB (gain match) + 3 dB (output transformer termination loss) or 5.9 dB to calibrate out these losses in the specification.

The measured gain of the second mixer has been increased by 1.3 dB (input transformer IL) + 1.7 dB (input term loss) + 0.4 dB (output transformer IL) and + 3 dB (output term loss) or 6.4 dB to calibrate out these losses in the specification.

The following two graphs (Figs 11 and 12) reflect the measured performance of the 1 : 16 Ω ratio RF transformer used to test the IF functions. Two transformers were placed back-to-back to make these measurements. Figure 11 represents the transmission function of just one of these transformers over frequency. Figure 12 represents the associated return loss at one input with the second transformer terminated into 50 Ω. In the actual UAA1570HL test board a single transformer is terminated in 800 Ω.

1999 May 10 20

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

handbook, halfpage

(dB)

−1

−2

−3

−4

−5

0 100

20 40 60 80

UAA1570HL

MHB274

(2)

(1)

(3)

f (MHz)

(1) S21; T (2) S21; T (3) S21; T

amb amb amb

= −40 °C. = +25 °C. = +85 °C.

Fig.11 S21 for the test measurement transformer.

handbook, halfpage

(dB)

−10

−20

−30

0 100

(1) (2) (3)

20 40 60 80

MHB275

f (MHz)

(1) S11; T (2) S11; T (3) S11; T

amb amb amb

= −40 °C. = +25 °C. = +85 °C.

Fig.12 S11 for the test measurement transformer.

1999 May 10 21

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

7.3 RF mixer with preampliﬁer

The 1st mixer (the RF mixer) consists of an RF preamplifier followed by a Gilbert cell mixer. The RF preamplifier consists of the same unbalanced common emitter and cascode stage as used in the LNAs, but without the compound feedback bootstrap output stage.

The cascode output is AC-coupled into one side of the lower tree of the Gilbert cell mixer. The other side is internally AC-coupled to mixer ground via a 20 pF decoupling capacitor. The Gilbert mixer RF input is degenerated with low loss inductive emitter feedback to increase the effective −1 dB compression point and intercept points. Referenced to the preamplifier input, the

−1 dB compression point and 3rd-order intercept point are

−25.4 dBm and −16.3 dBm, respectively. Another

important first mixer parameter is its 2nd-order input intercept point, which will extrapolate to approximately

1.38 V (peak value) differential or +12.8 dBm in the 50 Ω

mixer input environment. The differential output of the Gilbert cell mixer is

open-collector to allow optimization of conversion gain and matching to the first IF filter over a wide range of frequencies and filter options. The total conversion gain is therefore determined by the real part of the effective output load, which is given by the IF filter input impedance and loss and/or fixed filter input matching networks, if present.

The voltage conversion gain can be estimated by multiplying the effective single-ended to differential transconductance value for the first mixer (0.0531 A/V) by the total effective differential output resistance. The total power conversion gain to a differential load can be estimated from the voltage conversion gain by subtracting

diff_load

----------------------log 50 Ω

the output resistance is distributed between the fixed output termination, the IF filter input impedance, as well as equivalent loss impedances associated with the finite Q of filter components. The assumption has also been made that the output impedance which the mixer sees is real, at least in the IF band.

. The total power delivered by the mixer to

UAA1570HL

Therefore, the test circuit voltage conversion gain is estimated at 0.0531 A/V times the effective differential loading of approximately 440 Ω. This results in a voltage conversion gain of approximately 27.4 dBV. Subtracting

9.4 dB to convert from power in a 50 Ω environment to power into 440 Ω, we see that the first mixer delivers a total power conversion gain of approximately 18.0 dB in the test circuit. It is important to note that approximately 3 dB of this available power gain is lost in the test circuit output transformer termination and that much of this power can be recovered in application circuits.

The peak differential output voltage swing of the mixer should be limited to less than approximately 1 V (peak value) or 2 V (p-p) differential or

0.5 V (peak value) single-ended to prevent clipping by the internal output ESD protection diodes and to prevent mixer output saturation. This implies that effective differential output loads of approximately 2.5 kΩ could result in clipping at the output of the mixer.

The first mixer output structure also supports single-ended first IF filter applications. By taking one of the mixer outputs to the supply rail, the other can drive a single-ended first IF filter, thereby reducing external component cost in some applications. Maintaining the same single-ended loading impedance, as in the differential case (i.e. double the effective single-ended load) results in the same peak voltage across the same load, even with only half the

transconductance same power is delivered to the same filter load and the conversion gain remains the same. However, an effective load of 1.25 kΩ would also bring this single-ended mixer output to the same clipping point as the full differential equivalent load of 2.5 kΩ. The maximum recommended first mixer single-sided voltage conversion gain (input to one output) is therefore approximately 32 for both single-ended and differential output applications.

The power matched Double-Side Band (DSB) noise figure of the RF mixer with preamplifier is approximately 12 dB at

1.57542 GHz from a 3 V supply.

⁄2(0.0531 A/V) available. Therefore the

Note: The open-collector outputs of the first mixer each include internal 4 pF capacitors to ground. These capacitors should be included in the design of the first IF filter by removing 2 pF from the differential input capacitance for balanced filters and 4 pF from single-ended designs.

1999 May 10 22

Philips Semiconductors Product speciﬁcation

Global Positioning System (GPS) front-end receiver circuit

handbook, halfpage

output

(dBm)

(1) Fundamental output. (2) 3rd-order product output. (3) 2nd-order product output.

−20

−40

−60

−80

−100

−90 −70 −50 −10

(1)

(2)

−30 input (dBm)

UAA1570HL

MHB276

(3)

Fig.13 Typical first mixer fundamental, 2nd and 3rd-order product output levels as a function of input level.

MHB277

VCC (V)

(1) F (2) F (3) F

DSB DSB DSB

; T ; T ; T

amb amb amb

= −40 °C. = +25 °C. = +85 °C.

handbook, halfpage

DSB

(dB)

2345

(3)

(2)

(1)

Fig.14 Typical RF mixer noise figure as a function of temperature and supply voltage (test board).

1999 May 10 23

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