Philips TEA1202TS Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TEA1202TS

Battery power unit

Objective speciﬁcation File under Integrated Circuits, IC03

2000 Jun 08

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

FEATURES

• Fully integrated battery power unit, including complete DC/DC converter circuit, two Low DropOut voltage regulators (LDOs) and a battery low detector

• Configurable for 1, 2 or 3-cell Nickel-Cadmium (NiCd) or Nickel Metal Hybrid (NiMH) batteries and 1 Lithium Ion (Li-Ion) battery

• Guaranteed DC/DC converter start-up from 1-cell NiCd or NiMH battery, even with an load current

• Upconversion or downconversion

• Internal power MOSFETs featuring a low R approximately 0.1 Ω

• Synchronous rectification for high efficiency

• Soft start

• PWM-only operating option

• Dropout voltage of 75 mV at 50 mA

• Both LDOs are also applicable as low-ohmic power

switches

• Stable LDO performance with ceramic capacitors

• Stand-alone low battery detector requires no additional

supply voltage

• Low battery detection level at 0.90 V, externally adjustable to a higher level

• Adjustable output voltages

• Shut-down function

• Small outline package

• Advanced 0.6 µm BICMOS process.

APPLICATIONS

• Cellular phones

• Cordless phones

• Personal Digital Assistants (PDAs)

• Portable Audio Players

• Pagers

• Mobile equipment.

DSon

GENERAL DESCRIPTION

The TEA1202TS is a fully integrated battery power unit including a high-efficiency DC/DC converter which runs from a 1-cell NiCd or NiMH battery, two low dropout voltage regulators and a low battery detector. The circuit can be arrangedinmany ways to optimize the application circuit of a power supply system. Therefore, most inputs and outputs are separated, the DC/DC converter can be arranged for upconversion or downconversion and the regulators can also be used as power switches. One regulator can be used completely independent of the rest of the system, and the low battery detector can be configured for several types of batteries. Accurate low battery detection is possible while all other blocks are switched off.

The DC/DC converter features efficient, compact and dynamic power conversion using a digital control concept comparable with Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), integrated CMOS power switches with a very low R synchronous rectification.

The device operates at a switching frequency of 600 kHz which enables the use of external components with minimum size. The switching frequency can be synchronized to an external high frequency clock signal. Optionally, the device can be kept in PWM control mode only. Deadlock is prevented by an on-chip undervoltage lockout circuit.

Active current limiting enables efficient conversion in pulsed-load systems such as Global System for Mobile communication (GSM) and Digital Enhanced Cordless Telecommunications (DECT).

Both LDOs show a low dropout voltage and are inherently stable, even when ceramic capacitors with a low ESR value are applied at the outputs. Usage of the LDOs as low-ohmic switches is also possible.

The low battery detector has a built-in detection level which is optimum for a 1-cell NiCd or NiMH battery.Higher battery voltages can be translated to this 1-cell level by an additional built-in LDO circuit.

DSon

and fully

ORDERING INFORMATION

TYPE

NUMBER

TEA1202TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

2000 Jun 08 2

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC/DC converter

UPCONVERSION V

I(up)

O(up)

I(start)

DOWNCONVERSION V

I(dwn)

O(dwn)

CURRENT LEVELS I

shdwn

LX(max)

∆I

lim

OWER MOSFETS

DSon(N)

DSon(P)

EFFICIENCY η efﬁciency upconversion VI= 1.2 V; VOup to 3.3 V

TIMING f

i(sync)

start

Low dropout voltage regulators

LDO

dropout

LDO(max)

DSon

General characteristics

ref

input voltage V output voltage V

I(start) O(uvlo)

− 5.50 V

start-up input voltage IL< 10 mA 0.93 0.96 1.00 V

input voltage V

O(uvlo)

− 5.50 V

output voltage 1.30 − 5.50 V

quiescent current − 110 −µA current in shut-down mode 0 2 10 µA maximum continuous current at

=80°C −−1.0 A

amb

pins LX1 and LX2 current limit deviation I

set to 1.0 A

lim

upconversion −12 − +12 % downconversion −12 − +12 %

drain-to-source on-state

Tj=27°C − 110 − mΩ

resistance NFET drain-to-source on-state

Tj=27°C − 125 − mΩ

resistance PFET

=1mA − 66 − %

=10mA − 81 − %

= 100 mA − 85 − %

switching frequency PWM mode 480 600 720 kHz synchronization clock input

6 1320MHz

frequency start-up time − 10 − ms

output voltage range V dropout voltage I

LDO<V4

LDO

+ 0.4 V 1.30 − 5.50 V

=50mA −−75 mV maximum output current in regulation − 50 − mA drain-to-source on-state

>2V; Tj=27°C − 200 − mΩ

FB1,2

resistance

reference voltage 1.165 1.190 1.215 V

2000 Jun 08 3

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

2000 Jun 08 4

SHDWN2

LBI2

LBI1

TEA1202TS

ref

LDO2

IN2

OUT2

FB2

BLOCK DIAGRAM

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

LBO

LX1

LX2

ILIM

N-type

POWER

FET

LOW BATTERY

DETECTOR

sense

FET

ref

TEMPERATURE

PROTECTION

OSCILLATOR

CURRENT LIMIT

COMPARATOR

13 MHz

P-type POWER FET

sense FET

SYNC GATE

START-UP

CIRCUIT

CONTROL LOGIC

AND

MODE GEARBOX

TIME

COUNTER

DIGITAL CONTROLLER

ref

SHDWN0

INTERNAL

LDO1

SUPPLY

REFERENCE

VOLT AGE

OUT1

FB1

UPOUT/DNIN

GND

FB0

ref

GND0

1817 2 19

SYNC/PWM U/D

SHDWN0

Fig.1 Block diagram.

handbook, full pagewidth

MGU062

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

PINNING

SYMBOL PIN DESCRIPTION

LX1 1 inductor connection 1 SHDWN0 2 DC/DC shut-down input SHDWN2 3 LDO2 shut-down input UPOUT/DNIN 4 up mode: DC/DC output;

down mode DC/DC input

ILIM 5 current limiting resistor

connection OUT1 6 LDO1 output FB1 7 LDO1 feedback input GND 8 internal supply ground FB2 9 LDO2 feedback input OUT2 10 LDO2 output IN2 11 LDO2 input LBI2 12 low battery detector input 2 LBI1 13 low battery detector input 1 LBO 14 low battery detector output V

ref

15 reference voltage FB0 16 DC/DC feedback input GND0 17 DC/DC converter ground SYNC/PWM 18 synchronization clock input or

PWM-only selection input U/D 19 conversion mode selection input LX2 20 inductor connection 2

handbook, halfpage

UPOUT/DNIN

LX1

ILIM

OUT1

FB1

GND

FB2

OUT2

2 3 4 5

TEA1202TS

6 7 8 9

SHDWN0 SHDWN2

Fig.2 Pin configuration.

MGU060

LX2

U/D

SYNC/PWM

GND0

FB0

LBO

LBI1

LBI2

IN2

ref

FUNCTIONAL DESCRIPTION Control mechanism

The TEA1202TS DC/DC converter is able to operate in PFM (discontinuous conduction) or PWM (continuous conduction) operating mode. All switching actions are completely determined by a digital control circuit which usestheoutput voltage level as its control input. Thisnovel digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete range of operation of the converter.

When high output power is requested, the device will operate in PWM (continuous conduction) operating mode. This results in minimum AC currents in the circuit components and hence optimum efficiency, minimum costs and low EMC. In this operating mode, the output voltage is allowed to vary between two predefined voltage levels. As long as the output voltage stays within this so-called window, switching continues in a fixed pattern.

2000 Jun 08 5

When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the pulse width and inserting a current step in such a way that the output voltagestays within thewindow with higher or lower current capability. This approach enables very fast reaction to load variations. Figure 3 shows the response of the converter to a sudden load increase. The upper trace shows the output voltage.

The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, times the internal Equivalent Series Resistance (ESR) of the capacitor. After each ramp-down of the inductor current, i.e. when the ESR effect increases the output voltage, the converter determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay.

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

handbook, full pagewidth

load increase

start corrective action

time

high window limit

low window limit

MGK925

Fig.3 Response to load increase.

handbook, full pagewidth

typical

situation

+2%

maximum

positive spread

Fig.4 Output voltage window spread.

2000 Jun 08 6

−2%

maximum

negative spread

MGU061

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

When the output voltage becomes lower than the low limit of the window, a corrective action is taken by a ramp-up of theinductor current during amuchlonger time. As aresult, the DC current level is increased and normal PWM control can continue. The output voltage (including ESR effect) is again within the predefined window.

Figure 4 shows the spread of the output voltage window. The absolute value is mostly dependent on spread, while the actual window size (Vh− Vl) is not affected. For one specific device, the output voltage will not vary more than 2% (typical value).

In low output power situations, the TEA1202TS will switch over to PFM (discontinuous conduction) operating mode. In this mode, regulation information from an earlier PWM operating mode is used. This results in optimum inductor peak current levels in the PFM mode, which are slightly larger than the inductor ripple current in the PWM mode. As a result, the transition between PFMand PWM modeis optimum under all circumstances. In the PFM mode the TEA1202TS regulates the output voltage to the high window limit as shown in Fig.3.

Synchronous rectiﬁcation

For optimum efficiency over the whole load range, synchronous rectifiers inside the TEA1202TS ensure that during the whole second switching phase, all inductor current will flow through the low-ohmic power MOSFETs. Special circuitry is included which detects when the inductorcurrentreacheszero.Following this detection, the digital controller switches off the power MOSFET and proceeds with regulation.

Undervoltage lockout

As a result of too high a load or disconnection of the input power source, the output voltage can drop so low that normal regulation cannot be guaranteed. In this event, the device switches back to start-up mode. If the output voltage drops even further, switching is stopped completely.

Shut-down

When the shut-down input is set HIGH, the DC/DC converter disables both switches and power consumption is reduced to a few microamperes.

Power switches

The power switches in the IC are one N-type and one P-type power MOSFET, both having a typical drain-to-source resistance of 100 mΩ. The maximum average current in the power switches is 1.0 A at T

=80°C.

amb

Temperature protection

When the DC/DC converter operates in the PWM mode, and the die temperature gets too high (typical value is 160 °C), the converter and both LDOs stop operating. They resume operation when the die temperature falls below 90 °C again. As a result, low frequent cycling between the on and off state will occur. It should be noted that in the event of device temperatures at the cut-off limit, the application differs strongly from maximum specifications.

Start-up

Start-up from low input voltage in the boost mode is realized by an independentstart-up oscillator, which starts switching the N-type power MOSFET as soon as the low-battery detector detects a sufficiently high voltage. The inductor current is limited internally to ensure soft-starting. The switch actions of the start-up oscillator will increase the output voltage. As soon as the output voltage is high enough for normal regulation, the digital control system takes control over the power MOSFETs.

2000 Jun 08 7

Current limiters

If the current in one of the power switches exceeds the programmed limit in the PWM mode, the current ramp is stopped immediately and the next switching phase is entered. Current limiting is required to keep power conversion efficient during temporary high loads. Furthermore, current limiting protects the IC against overload conditions, inductor saturation, etc.

The current limiting level is set by an external resistor whichmustbe connected between pin ILIM and ground for downconversion, or between pins ILIM and UPOUT/DNIN for upconversion.

Philips Semiconductors Objective speciﬁcation

Battery power unit TEA1202TS

External synchronization and PWM-only mode

If an external high-frequency clock or a HIGH level is applied to pin SYNC/PWM, the TEA1202TS will use PWM regulation independent of the load applied.

In the event a high-frequency clock is applied, the switching frequency in the PWM mode will be exactly that frequency divided by 22. In the PWM mode the quiescent current of the device increases.

In the event that no external synchronization or PWM mode selection is necessary, pin SYNC/PWM must be connected to ground.

Behaviour at input voltage exceeding the speciﬁed range

In general, an input voltage exceeding the specified range isnot recommended since instabilitymay occur. There are two exceptions:

1. Upconversion: at an input voltage higher than the targetoutput voltage, but up to 5.5 V,theconverter will stop switching and the external Schottky diode will take over. The output voltage will equal the input voltageminus the diodevoltage drop. Since allcurrent flows through the external diode in this situation, the current limiting function is not active.

In the PWM mode, the P-type power MOSFET is always on when the input voltage exceeds the target output voltage. The internal synchronous rectifier ensures that the inductor current does not fall below zero. As a result, the achieved efficiency is higher in this situation than standard PWM-controlled converters achieve.

2. Downconversion: when the input voltage is lower than the target output voltage, but higher than 2.2 V, the P-type power MOSFET will stay conducting resulting in an output voltage being equal to the input voltage minussomeresistivevoltagedrop.Thecurrentlimiting function remains active.

Both LDOs are protected from overload conditions by a current limiting circuit and high temperature (see Section “Temperature protection”).

Next to normal LDO functions, both regulators can be switched off or can be used as switches. Each regulator will act as a low-ohmic switch in the on-state when its feedback input is connected to ground. When the feedback input is higher than 2 V, the regulator will make its power FET high-ohmic. So the feedback inputs of the regulators can be used as digital inputs which make the LDOs behave as switches.

Low battery detector

The low battery detector is an autonomous circuit which can work at an input voltage down to 0.90 V. It is always on, even when all other blocks are in the shut-down mode.

The detector has two inputs: the input on pin LBI1 is tuned to accept a 1-cell NiCd or NiMH battery voltage directly, while the input on pin LBI2 can detect a 2-cell NiCd or NiMHbatteryvoltageorhighervoltage.Thedetectionlevel of the input on pin LBI2 can be set by using a voltage divider between the battery voltage, pin LBI2 and ground. Hysteresisisincludedforproper operating. Furthermore, a capacitor of 10 µF (typical value) must be connected between pin LBI1 and ground when the input on pin LBI2 is used.

The output of the low battery detector on pin LBO is an open-collector output. The output is high (i.e. no current is sunk by the collector) when the input voltage of the detector is below the lower detection level.

Low dropout voltage regulators

The low dropout voltage regulators are functionally equal apart from the shut-down mechanism: LDO2 can be controlled separately by pin SHDWN2, while LDO1 is controlled by pin SHDWN0 like the DC/DC converter.

The input voltage of each LDO must be 250 mV higher than its output voltage to achieve full specification on e.g. ripple rejection. However, the parts will function like an LDOdown to a margin of 75 mVbetweeninput and output: the so-called dropout voltage. At a lower margin between input and output, the LDOs will behave like a resistor.

2000 Jun 08 8

+ 16 hidden pages