Philips TDA9851T-V1 Datasheet

DATA SH EET
Product specification File under Integrated Circuits, IC02
1997 Nov 12
INTEGRATED CIRCUITS
TDA9851
I
C-bus controlled economic BTSC
stereo decoder
1997 Nov 12 2
Philips Semiconductors Product specification
I2C-bus controlled economic BTSC stereo decoder
TDA9851
FEATURES
Voltage Controlled Amplifier (VCA) noise reduction circuit
Stereo or mono selectable at the AF outputs
Stereo pilot PLL circuit with ceramic resonator
Automatic pilot cancellation
Automatic Volume Level (AVL) control (+6 to 15 dB)
I2C-bus transceiver.
GENERAL DESCRIPTION
The TDA9851 is a bipolar-integrated BTSC stereo decoder for application in TV sets, VCRs and multimedia PCs.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CC
supply voltage 8 9 9.5 V
I
CC
supply current 30 40 mA
V
o(rms)
output voltage (RMS value) composite input voltage
250 mV (RMS) for 100% modulation L + R (25 kHz deviation); f
mod
= 300 Hz
500 mV
α
csL,R
stereo channel separation L and R
14% modulation; fL= 300 Hz; f
R
= 3 kHz
20 dB
THD
L,R
total harmonic distortion L and R 100% modulation L or R;
f
mod
= 1 kHz
0.2 1.0 %
S/N signal-to-noise ratio mono mode; referenced to 500 mV
output signal
CCIR 468-2 weighted; quasi peak
50 60 dB
DIN noise weighting filter (RMS value)
73 dBA
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TDA9851 SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 TDA9851T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
1997 Nov 12 3
Philips Semiconductors Product specification
I2C-bus controlled economic BTSC stereo decoder
TDA9851
BLOCK DIAGRAM
ook, full pagewidth
MHA969
STEREO DECODER
DEMATRIX
AND
MODE SELECT
AUTOMATIC
VOLUME
LEVEL
DETECTOR
AND
VOLTAGE
CONTROLLED
AMPLIFIER
SUPPLY
FILTER
AND
REFERENCE
I
2
C-BUS
TRANSCEIVER
TDA9851
L − R
L + R
89
C5
Q1
C6
C10 C11 C13
C
MO
3
C4
C3
C2
R1
C
PH
4
CER
5
C
P1
6
C
P2
C
SS
1611
n.c.
C7
C
AV
12
13
24
1
SDA
SCL
OUTL
OUTR
C1
composite
baseband
input
7COMP
21FDI
20FDO
R3
C9
R2
19 18 17
BPU C
W
TW
C14
21522
C15
14
V
CC
V
CAP
AGND V
ref
23
DGND
R4
10
R
FR
Fig.1 Block diagram.
1997 Nov 12 4
Philips Semiconductors Product specification
I2C-bus controlled economic BTSC stereo decoder
TDA9851
Component list
Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENT VALUE TYPE REMARK
C1 2.2 µF electrolytic 63 V C2 220 nF foil
C3 2.2 µF electrolytic 63 V C4 220 nF foil C5 2.2 µF electrolytic 63 V C6 2.2 µF electrolytic 63 V C7 4.7 µF electrolytic 63 V ±10% C9 22 nF foil C10 4.7 nF foil C11 1 µF electrolytic 63 V C13 10 µF electrolytic 63 V C14 100 µF electrolytic 16 V C15 100 µF electrolytic 16 V R1 3.3 k R2 15 k R3 1.3 k R4 100 k Q1 CSB503F58 radial leads
CSB503JF958 alternative as SMD
1997 Nov 12 5
Philips Semiconductors Product specification
I2C-bus controlled economic BTSC stereo decoder
TDA9851
PINNING
SYMBOL PIN DESCRIPTION
SCL 1 serial clock input (I
2
C-bus)
V
CC
2 supply voltage
C
PH
3 capacitor for phase detector CER 4 ceramic resonator C
P1
5 capacitor for pilot detector C
P2
6 capacitor for pilot detector COMP 7 composite input signal C
MO
8 capacitor DC-decoupling mono C
SS
9 capacitor DC-decoupling stereo R
FR
10 resistor for filter reference n.c. 11 not connected OUTL 12 output, left channel OUTR 13 output, right channel V
ref
14 reference voltage 0.5V
CC
V
CAP
15
capacitor for electronic filtering of supply
C
AV
16 automatic volume control capacitor TW 17 capacitor timing C
W
18
capacitor for VCA and band-pass filter lower corner frequency
BPU
19
band-pass filter upper corner
frequency FDO 20 fixed de-emphasis output FDI 21 fixed de-emphasis input AGND 22 analog ground DGND 23 digital ground SDA 24 serial data input/output (I
2
C-bus)
Fig.2 Pin configuration.
handbook, halfpage
SCL
V
CC
C
PH
CER
C
P1
C
P2
COMP
C
MO
C
SS
R
FR
n.c.
OUTL
SDA DGND AGND FDI
BPU C
W
FDO
TW C
AV
V
CAP
V
ref
OUTR
1 2 3 4 5 6 7 8
9 10 11 12
24 23 22 21 20 19 18 17
16 15 14 13
TDA9851
MHA968
1997 Nov 12 6
Philips Semiconductors Product specification
I2C-bus controlled economic BTSC stereo decoder
TDA9851
FUNCTIONAL DESCRIPTION Stereo decoder
The composite signal is fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L R is sent to the VCA circuit. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator.
Mode selection
The L R signal is fed via the internal VCA circuit to the dematrix/switching circuit. Mode selection is achieved via the I
2
C-bus.
Automatic volume level control
The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from
an input voltage range between 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and because of changes in the programme material. The function can be switched off. To avoid audible plops during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin C
AV
determines the attack and decay time constants. In addition the ratio of attack and decay times can be changed via the I2C-bus.
Integrated filters
The filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. The filter frequencies are controlled by the filter reference circuit via the external resistor R4.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Machine model class B.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
supply voltage 0 9.9 V
V
SDA
, V
SCL
voltage of SDA and SCL to GND VCC<9V 0 V
CC
V
V
CC
9V09V
V
n
voltage of all other pins to GND 0 V
CC
V
T
amb
operating ambient temperature Tj< 125 °C 20 +70 °C
T
stg
storage temperature 65 +150 °C
V
es
electrostatic handling note 1 −−V
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air
TDA9851 (SOT234-1; SDIP24) 55 K/W TDA9851T (SOT137-1; SO24) 90 K/W
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