Philips TDA9851T, TDA9851 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9851

C-bus controlled economic BTSC

stereo decoder

Product speciﬁcation File under Integrated Circuits, IC02

1997 Nov 12

Philips Semiconductors Product speciﬁcation

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

FEATURES

• Voltage Controlled Amplifier (VCA) noise reduction circuit

• Stereo or mono selectable at the AF outputs

• Stereo pilot PLL circuit with ceramic resonator

• Automatic pilot cancellation

• Automatic Volume Level (AVL) control (+6 to −15 dB)

• I2C-bus transceiver.

GENERAL DESCRIPTION

The TDA9851 is a bipolar-integrated BTSC stereo decoder for application in TV sets, VCRs and multimedia PCs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

o(rms)

csL,R

THD

S/N signal-to-noise ratio mono mode; referenced to 500 mV

supply voltage 8 9 9.5 V supply current − 30 40 mA output voltage (RMS value) composite input voltage

− 500 − mV 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); f

stereo channel separation L and R

total harmonic distortion L and R 100% modulation L or R;

L,R

14% modulation; fL= 300 Hz;

= 3 kHz

= 1 kHz

mod

= 300 Hz

− 20 − dB

− 0.2 1.0 %

output signal

CCIR 468-2 weighted;

50 60 − dB

quasi peak DIN noise weighting filter

− 73 − dBA

(RMS value)

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9851 SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 TDA9851T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1997 Nov 12 2

Philips Semiconductors Product speciﬁcation

I2C-bus controlled economic BTSC stereo decoder

BLOCK DIAGRAM

OUTL

OUTR

n.c.

1611

LEVEL

VOLUME

AUTOMATIC

SDA

C-BUS

AND

FILTER

SCL

TRANSCEIVER

REFERENCE

DGND

TDA9851

MHA969

ook, full pagewidth

CER

AND

DEMATRIX

MODE SELECT

L + R

STEREO DECODER

7COMP

TDA9851

L − R

21FDI

SUPPLY

AND

VOLTAGE

DETECTOR

20FDO

21522

AMPLIFIER

CONTROLLED

19 18 17

ref

AGND V

CAP

BPU C

C15

C14

C10 C11 C13

Fig.1 Block diagram.

composite

baseband

input

1997 Nov 12 3

Philips Semiconductors Product speciﬁcation

I2C-bus controlled economic BTSC stereo decoder

Component list

Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise speciﬁed; see Fig.1.

COMPONENT VALUE TYPE REMARK

C1 2.2 µF electrolytic 63 V C2 220 nF foil

C3 2.2 µF electrolytic 63 V C4 220 nF foil C5 2.2 µF electrolytic 63 V C6 2.2 µF electrolytic 63 V C7 4.7 µF electrolytic 63 V ±10% C9 22 nF foil C10 4.7 nF foil C11 1 µF electrolytic 63 V C13 10 µF electrolytic 63 V C14 100 µF electrolytic 16 V C15 100 µF electrolytic 16 V R1 3.3 kΩ R2 15 kΩ R3 1.3 kΩ R4 100 kΩ Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

TDA9851

1997 Nov 12 4

Philips Semiconductors Product speciﬁcation

I2C-bus controlled economic BTSC stereo decoder

PINNING

SYMBOL PIN DESCRIPTION

SCL 1 serial clock input (I V

2 supply voltage

3 capacitor for phase detector CER 4 ceramic resonator C

5 capacitor for pilot detector

6 capacitor for pilot detector COMP 7 composite input signal C

8 capacitor DC-decoupling mono

9 capacitor DC-decoupling stereo

10 resistor for ﬁlter reference n.c. 11 not connected OUTL 12 output, left channel OUTR 13 output, right channel V V

ref CAP

14 reference voltage 0.5V

capacitor for electronic ﬁltering of

supply

16 automatic volume control capacitor TW 17 capacitor timing C

BPU

capacitor for VCA and band-pass ﬁlter

lower corner frequency band-pass ﬁlter upper corner

frequency FDO 20 ﬁxed de-emphasis output FDI 21 ﬁxed de-emphasis input AGND 22 analog ground DGND 23 digital ground SDA 24 serial data input/output (I

C-bus)

handbook, halfpage

SCL

CER

COMP

n.c.

OUTL

7 8

9 10 11 12

TDA9851

MHA968

Fig.2 Pin configuration.

TDA9851

SDA

DGND

AGND

FDI

FDO

20 19

BPU C

CAP

ref

OUTR

1997 Nov 12 5

Philips Semiconductors Product speciﬁcation

I2C-bus controlled economic BTSC stereo decoder

FUNCTIONAL DESCRIPTION Stereo decoder

The composite signal is fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the VCA circuit. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator.

Mode selection

The L − R signal is fed via the internal VCA circuit to the dematrix/switching circuit. Mode selection is achieved via

C-bus.

the I

Automatic volume level control

The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from

TDA9851

an input voltage range between 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and because of changes in the programme material. The function can be switched off. To avoid audible plops during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin C determines the attack and decay time constants. In addition the ratio of attack and decay times can be changed via the I2C-bus.

Integrated ﬁlters

The filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. The filter frequencies are controlled by the filter reference circuit via the external resistor R4.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

, V

SDA

SCL

amb

stg

supply voltage 0 9.9 V voltage of SDA and SCL to GND VCC<9V 0 V

≥ 9V09V

voltage of all other pins to GND 0 V

operating ambient temperature Tj< 125 °C −20 +70 °C storage temperature −65 +150 °C electrostatic handling note 1 −−V

Note

1. Machine model class B.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air

TDA9851 (SOT234-1; SDIP24) 55 K/W TDA9851T (SOT137-1; SO24) 90 K/W

1997 Nov 12 6

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