Philips TDA9850T-V1 Datasheet

DATA SH EET

Preliminary specification
File under Integrated Circuits, IC02

1995 Jun 19

INTEGRATED CIRCUITS

TDA9850

I

2

C-bus controlled BTSC

stereo/SAP decoder

1995 Jun 19 2

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

FEATURES

• Quasi alignment-free application due to automatic
adjustment of channel separation via I2C-bus

• Dbx noise reduction circuit

• Dbx decoded stereo, Second Audio Program (SAP) or

mono selectable at the AF outputs

• Additional SAP output without dbx, including
de-emphasis

• High integration level with automatically tuned
integrated filters

• Input level adjustment I

2

C-bus controlled

• Alignment-free SAP processing

• Stereo pilot PLL circuit with ceramic resonator,

automatic adjustment procedure for stereo channel
separation, two pilot thresholds selectable via I2C-bus

• Automatic pilot cancellation

• Composite input noise detector with I2C-bus selectable

thresholds for stereo and SAP off

• I2C-bus transceiver.

GENERAL DESCRIPTION

The TDA9850 is a bipolar-integrated BTSC stereo/SAP
decoder (I

2

C-bus controlled) for application in TV sets,

VCRs and multimedia.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 8.5 9 9.5 V

I

CC

supply current − 58 75 mA

V

comp(rms)

input signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 250 − mV

V

oR(rms)

;

V

oL(rms)

output signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 500 − mV

G

LA

input level adjustment control −3.5 − +4.0 dB

α

cs

stereo channel separation fL= 300 Hz; fR= 3 kHz 25 35 − dB

THD

L,R

total harmonic distortion L + R fi= 1 kHz − 0.2 − %

S/N signal-to-noise ratio 500 mV (RMS) mono output signal

CCIR noise weighting filter
(peak value)

− 60 − dB

DIN noise weighting filter
(RMS value)

− 73 − dBA

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA9850 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1
TDA9850T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

1995 Jun 19 3

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

License information

A license is required for the use of this product. For further information, please contact:

COMPANY BRANCH ADDRESS

THAT Corporation Licensing Operations 734 Forest St.

Marlborough, MA 01752
USA
Tel.: [phone]
Fax: [phone]

Tokyo Office 405 Palm House, 1-20-2 Honmachi

Shibuya-ku, Tokyo 151
Japan
Tel.: [phone]
Fax: [phone]

1995 Jun 19 4

Philips Semiconductors Preliminary specification

I

2

C-bus controlled BTSC stereo/SAP decoder

TDA9850

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

BLOCK DIAGRAM

o

ok, full pagewidth

composite
baseband
input

+

+

C2

13

14

15

C5

16

Q1

ceramic
resonator

17

DEMATRIX

+

MODE

SELECT

+

C6

18

+

C7

19

DE-EMPHASIS

L+R

L−R/SAP

OUTL

OUTR

27

21

STEREO DECODER

SAP without DBX

23

C8

22

R1

C3

C4

LOGIC, I2C-

TRANSCEIVER

MAD

28

7

stereo
mono
SAP
to
audio
processing

98

SDA SCL

SUPPLY

+

C18

24

6

+

C19

12

10

V

ref

V

CAP

V

CC

SAP

DEMODULATOR

+

C16

5

C15

4

INPUT

LEVEL

ADJUST

+

11

C1

NOISE

DETECTOR

STEREO/SAP

SWITCH

C17

26

TDA9850

STEREO
ADJUST

DBX

+

C14

3

C13

R3

R2

1

2

+

32

+

31

+

30

+

29

C12

C11

C10

C9

+

25

+

20

C

L

C

R

only during
adjustment

MHA010

Fig.1 Block, application and test diagram.

1995 Jun 19 5

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

COMPONENT LIST

Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.

COMPONENT VALUE TYPE REMARK

C1 10 µF electrolytic 63 V
C2 470 nF foil
C3 4.7 µF electrolytic 63 V
C4 220 nF foil
C5 10 µF electrolytic 63 V; I

leak

< 1.5 µA
C6 4.7 µF electrolytic 63 V
C7 4.7 µF electrolytic 63 V
C8 15 nF foil
C9 10 µF electrolytic 63 V ±10%
C10 10 µF electrolytic 63 V ±10%
C11 1 µF electrolytic 63 V
C12 1 µF electrolytic 63 V
C13 47 nF foil ±5%
C14 10 µF electrolytic 63 V
C15 100 nF foil
C16 4.7 µF electrolytic 63 V

C17 100 nF foil
C18 100 µF electrolytic 16 V
C19 100 µF electrolytic 16 V
CR 2.2 µF electrolytic 63 V
CL 2.2 µF electrolytic 63 V
R1 2.2 kΩ
R2 8.2 kΩ±2%
R3 160 Ω±2%
Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

1995 Jun 19 6

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

PINNING

SYMBOL PIN DESCRIPTION

VEO 1 variable emphasis output for dbx
VEI 2 variable emphasis input for dbx
C

NR

3 capacitor noise reduction for dbx

C

M

4 capacitor mute for SAP

C

DEC

5 capacitor DC-decoupling for SAP
AGND 6 analog ground
DGND 7 digital ground
SDA 8 serial data input/output
SCL 9 serial clock input
V

CC

10 supply voltage (+9 V)
COMP 11 composite input signal
V

CAP

12 capacitor for electronic filtering of supply
C

P1

13 capacitor for pilot detector
C

P2

14 capacitor for pilot detector
C

PH

15 capacitor for phase detector
C

ADJ

16 capacitor for filter adjustment
CER 17 ceramic resonator
C

MO

18 capacitor DC-decoupling mono
C

SS

19 capacitor DC-decoupling stereo/SAP
C

R

20 adjustment capacitor, right channel
OUTR 21 output, right channel
C

SDE

22 capacitor SAP de-emphasis
SAP 23 SAP output
V

ref

24 reference voltage 0.5 × (VCC− 1.5 V)
C

L

25 adjustment capacitor, left channel
C

ND

26 noise detector capacitor
OUTL 27 output, left channel
MAD 28 programmable address bit
C

TW

29 capacitor timing wideband for dbx
C

TS

30 capacitor timing spectral for dbx
C

W

31 capacitor wideband for dbx
C

S

32 capacitor spectral for dbx

Fig.2 Pin configuration.

page

TDA9850

MHA012

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VEO

C

S

C

W

C

TS

C

TW

C

ND

C

SDE

C

L

C

R

C

SS

C

MO

V

ref

VEI

C

NR

C

M

C

DEC

AGND OUTL

SAP

OUTR

CER

MAD

DGND

SDA

SCL

V

CC

COMP

V

CAP

C

P1

C

P2

C

PH

C

ADJ

1995 Jun 19 7

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

FUNCTIONAL DESCRIPTION
Input level adjustment

The composite input signal is fed to the input level
adjustment stage. The control range is from

−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress
control 4 of Tables 5 and 6 and the level adjust setting of
Table 10 allows an optimum signal adjustment during the
set alignment. The maximum input signal voltage is
2 V (RMS).

Stereo decoder

The output signal of the level adjustment stage is coupled
to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit. The
decoded sub-signal L − R is sent to the stereo/SAP switch.
To generate the pilot signal the stereo demodulator uses a
PLL circuit including a ceramic resonator. The stereo
channel separation is adjusted by an automatic procedure
to be performed during set production. For a detailed
description see Section “Adjustment procedure”. The
stereo identification can be read by the I

2

C-bus
(see Table 2). Two different pilot thresholds (data
STS = 1; STS = 0) can be selected via the I2C-bus
(see Table 14).

SAP demodulator

The composite signal is fed from the output of the input
level adjustment stage to the SAP demodulator circuit
through a 5f

H

band-pass filter. The demodulator level is
automatically controlled. The SAP demodulator includes
an internal field strength detector that mutes the SAP
output in the event of insufficient signal conditions. The
SAP identification signal can be read by the I2C-bus
(see Table 2).

Noise detector

The composite input noise increases with decreasing
antenna signal. This makes it necessary to switch stereo
or SAP off at certain thresholds. These thresholds can be
set via the I

2

C-bus. With ST0 to ST3 (see Table 6) the
stereo threshold can be selected and with SP0 to SP3 the
SAP threshold. A hysteresis can be achieved via software
by making the threshold dependent of the identification
bits STP and SAPP (see Table 2).

Mode selection

The stereo/SAP switch feeds either the L − R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/switching circuit. Table 8
shows the different switch modes provided at the output
pins OUTR and OUTL.

dbx decoder

The dbx circuit includes all blocks required for the noise
reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.

SAP output

Independent of the stereo/SAP switch, the SAP signal is
also available at pin SAP. At SAP, the SAP signal is not
dbx decoded. The capacitor at SDE provides a
recommended de-emphasis (150 µs) at SAP.

Integrated filters

The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.

1995 Jun 19 8

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

Adjustment procedure

C

OMPOSITE INPUT LEVEL ADJUSTMENT

Feed in from FM demodulator the composite signal with
100% modulation (25 kHz deviation) L + R; fi= 300 Hz.
Set input level control via I2C-bus monitoring OUTL or
OUTR (500 mV ±20 mV). Store the setting in a
non-volatile memory.

A

UTOMATIC ADJUSTMENT PROCEDURE

• Connect 2.2 µF capacitors from ACR and ACL to
ground.

• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel.

• Mode selection setting bits: STEREO = 1, SAP = 0
(see Table 8).

• Start adjustment by transmission ADJ = 1 in register
ALI3. The decoder will align itself.

• After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an
I2C-bus read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory. The alignment procedure
overwrites the previous data stored in ALI1 and ALI2.

• The capacitors from ACR and ACL may be
disconnected after alignment.

M

ANUAL ADJUSTMENT

Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).

• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)

• Composite input L = 300 Hz; 14% modulation

• Adjust channel separation by varying wideband data

• Composite input L = 3 kHz; 14% modulation

• Adjust channel separation by varying spectral data

• Iterative spectral/wideband operation for optimum

adjustment

• Store data in non-volatile memory.

After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.

T

IMING CURRENT FOR RELEASE RATE

Due to possible internal and external spreading, the timing
current can be adjusted via I2C-bus, see Table 9, as
recommended by dbx.

1995 Jun 19 9

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ; V = 2 kV; charge device model: C = 200 pF; R = 0 Ω;
V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage 0 10 V

V

VCAP

voltage of V

CAP

to GND 0 V

CC

V

V

VEO

voltage of VEO to GND 0

1

⁄2V

CC

V

V

SDA

voltage of SDA to GND 0 8.5 V

V

SCL

voltage of SCL to GND 0 8.5 V

V

n

voltage of all other pins to GND VCC≥ 8.5 V 0 8.5 V

V

CC

< 8.5 V 0 V

CC

V

T

amb

operating ambient temperature Tj< 125 °C −20 +70 °C

T

stg

storage temperature −65 +150 °C

V

es

electrostatic handling HBM; note 1

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

SOT232-1 55 K/W
SOT287-1 68 K/W

1995 Jun 19 10

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP decoder

TDA9850

REQUIREMENTS FOR THE COMPOSITE INPUT SIGNAL TO ENSURE CORRECT SYSTEM PERFORMANCE

Notes

1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Z

O

and the composite input

impedance (see Chapter “Characteristics”; row head “Input level adjustment control”) must be taken into account.

2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is
73 kHz).

3. For example colour bar or flat field white; 100% video modulation.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

COMP

L+R(rms)

composite input level for 100%
modulation L + R (25 kHz
deviation); RMS value;
fi= 300 Hz

measured at COMP 162 250 363 mV

∆COMP composite input level

spreading under operating
conditions

T

amb

= −20 to +70 °C; aging;

power supply influence

−0.5 − +0.5 dB

Z

source

source impedance note 1 − low-ohmic 5 kΩ

f

lf

low frequency roll-off 25 kHz deviation L + R; −2dB −− 5Hz

f

hf

high frequency roll-off 25 kHz deviation L + R; −2 dB 100 −−kHz

THD

L,R

total harmonic distortion L + R fi= 1 kHz; 25 kHz deviation −− 0.5 %

f

i

= 1 kHz; 125 kHz deviation;

note 2

−− 1.5 %

S/N signal-to-noise ratio

L + R/noise

CCIR 468-2 weighted quasi
peak; L + R; 25 kHz deviation;
f

i

= 1 kHz; 75 µs de-emphasis

critical picture modulation;
note 3

44 −−dB

with sync only 54 −−dB

α

SB

side band suppression mono
into unmodulated SAP carrier;
SAP carrier/side band

mono signal: 25 kHz deviation,
fi= 1 kHz; side band: SAP
carrier frequency ±1 kHz

40 −−dB

α

SP

spectral spurious attenuation
L + R/spurious

50 Hz to 100 kHz;
mainly n × fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference

n = 1, 4, 5, 6 35 −−dB
n = 2, 3 26 −−dB