Philips TDA9819 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA9819

Multistandard vision and sound-IF PLL with DVB-IF processing

Preliminary specification			1996 Aug 02
File under Integrated Circuits, IC02

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

FEATURES

∙5 V supply voltage

∙Applicable for IF frequencies of 38.9 MHz and 45.75 MHz

∙Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled)

∙True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response)

∙VCO frequency switchable between TV (M or BG/L) IF-picture carrier and Digital Video Broadcast (DVB) frequency

∙Separate video amplifier for sound trap buffering with high video bandwidth

∙VIF AGC detector for gain control, operating as peak sync detector for M and B/G and peak white detector for L; controlled reaction time for L

∙Tuner AGC with adjustable takeover point (TOP)

∙AFC detector without extra reference circuit

∙SIF input for single reference QSS mode

(PLL controlled); SIF AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode

∙AC-coupled limiter amplifier for sound intercarrier signal

∙Alignment-free FM-PLL demodulator with high linearity

∙AM demodulator without extra reference circuit

∙Stabilizer circuit for ripple rejection and to achieve constant output signals.

DVB functions

∙Gain controlled IF-amplifier

∙Mixer for DVB-IF

∙VCO for QAM carrier recovery

∙External VCO control for DVB

∙Internal and external AGC for DVB

∙DVB output level adjust via AGC adjust

∙High level DVB operational output amplifier.

GENERAL DESCRIPTION

The TDA9819 is an integrated circuit for multistandard vision and sound-IF signal processing with single reference PLL demodulator combined with the signal stages for DVB-IF processing.

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	TDA9819	SDIP32	plastic shrink dual in-line package; 32 leads (400 mil)	SOT232-1

1996 Aug 02

2

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VP	supply voltage		4.5	5.0	5.5	V
IP	supply current		81	100	121	mA
Vi VIF(rms)	vision IF input signal voltage	−1 dB video at output	−	60	100	μV
	sensitivity (RMS value)
Vo CVBS(p-p)	CVBS output signal voltage		1.7	2.0	2.3	V
	(peak-to-peak value)
B (M,	−3 dB video bandwidth on pin 10	M, B/G and L standard;	7	8	−	MHz
BG/L)		CL < 20 pF; RL > 1 kΩ;
		AC load
S/N (W)	weighted signal-to-noise ratio for		56	60	−	dB
	video
α1.1	intermodulation attenuation at ‘blue’	f = 1.1 MHz	58	64	−	dB
α3.3	intermodulation attenuation at ‘blue’	f = 3.3 MHz	58	64	−	dB
αH	suppression of harmonics in video		35	40	−	dB
	signal
Vi SIF(rms)	sound-IF input signal voltage	−3 dB at intercarrier output	−	70	100	μV
	sensitivity (RMS value)
Vo(rms)	audio output signal voltage for FM	M and B/G standard;	−	0.5	−	V
	(RMS value)	25 kHz frequency deviation
	audio output signal voltage for AM	L standard;	−	0.5	−	V
	(RMS value)	54% modulation
THD	total harmonic distortion
	FM	25 kHz frequency deviation	−	0.15	0.5	%
	AM	54% modulation	−	0.5	1.0	%
S/N (W)	weighted signal-to-noise ratio
	FM	25 kHz frequency deviation	−	60	−	dB
	AM	54% modulation	47	53	−	dB

1996 Aug 02

3

Aug 1996

2fPC

02

TOP

DVB

DVB

DVB

CVAGC CBL AGC

AGC

loop

external

VCO

tuner

adjust

external

AFC

filter

VCO

adjust

AGC

control

6

19

28

3

15

13

23

7

16

25

24

11

TUNER

VIF-AGC

DVB

AFC

VCO

AGC

AGC

DETECTOR

TWD

TDA9819

21

(1)

FPLL

input/DVB

30

switch

VIF

1

DEMODULATOR/

18

DVB MIXER

VIF

A

2

4

VIF

SWITCH

DVB

B

5

4

LOGIC

31

AM

SIF

10

SIF

32

DEMODULATOR

MIXER

22

IF-filter

INTERNAL			SIF-AGC				12
VOLTAGE
STABILIZER							FM DETECTOR
							(PLL)
29	27	26	8	9	20	17	14
		1/2 VP	CSAGC				MBH352
						4.5/5.5	CAF
VP				standard (1)
(+5 V)				switch

	QSS	AF
	intercarrier
		mute
	output

(1) See switch logic Table 2.

Fig.1 Block diagram.

video

1 V (p-p)

DVB

2 V (p-p)

CVBS

2 V (p-p)

video buffer

AF

DIAGRAM BLOCK	vision Multistandard processing IF-DVB
	with PLL IF-sound and

TDA9819

Semiconductors Philips

specification Preliminary

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

PINNING

SYMBOL	PIN	DESCRIPTION
Vi VIF1	1	VIF differential input signal voltage 1
Vi VIF2	2	VIF differential input signal voltage 2
CBL	3	black level detector
Vi VIF3	4	VIF differential input signal voltage 3
Vi VIF4	5	VIF differential input signal voltage 4
TADJ	6	tuner AGC takeover adjust (TOP)
TPLL	7	PLL loop filter
CSAGC	8	SIF AGC capacitor
STD	9	standard switch input
Vo CVBS	10	2 V CVBS output signal voltage
VCOADJ	11	VCO adjust BG/L/M
Vo AF	12	audio voltage frequency output
VAGC(ext)	13	external AGC voltage (DVB)
CAF	14	AF decoupling capacitor
AGCADJ	15	AGC adjust (DVB)
VVCO(ext)	16	external VCO control voltage (DVB)
Vi FM	17	sound intercarrier input
DVB	18	DVB output
TAGC	19	tuner AGC output
Vo QSS	20	single reference QSS output voltage
Vo(vid)	21	composite video output voltage
Vi(vid)	22	video buffer input voltage
AFC	23	AFC output
VCO1	24	VCO1 reference circuit for 2fPC
VCO2	25	VCO2 reference circuit for 2fPC
Cref	26	1¤2VP reference capacitor
GND	27	ground
CVAGC	28	VIF AGC capacitor
VP	29	supply voltage (+5 V)
INSWI	30	VIF input switch
Vi SIF1	31	SIF differential input signal voltage 1
Vi SIF2	32	SIF differential input signal voltage 2

handbook, halfpage				Vi SIF2
Vi VIF1	1		32
Vi VIF2				Vi SIF1
	2		31
CBL				INSWI
	3		30
Vi VIF3				VP
	4		29
Vi VIF4				CVAGC
	5		28
TADJ
	6		27	GND
TPLL				Cref
	7		26
CSAGC
	8	TDA9819	25	VCO2
STD
	9		24	VCO1
Vo CVBS
	10		23	AFC
VCOADJ				Vi(vid)
	11		22
Vo AF				Vo(vid)
	12		21
VAGC(ext)				Vo QSS
	13		20
CAF
	14		19	TAGC
AGCADJ				DVB
	15		18
VVCO(ext)				Vi FM
	16		17
		MBH354

Fig.2 Pin configuration.

1996 Aug 02

5

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

FUNCTIONAL DESCRIPTION

Vision IF amplifier and input switch

The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration to control the IF gain. The first differential stage is extended by two pairs of emitter followers to provide two IF input channels. The VIF input can be selected by pin 30.

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (open-collector output).

The tuner AGC takeover point can be adjusted.

This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitor to the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level.

Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected. In order to reduce the reaction time for positive modulation, where a very large time constant is needed, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step.

The additional level information is given by the black-level detector voltage.

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency. In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals.

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the PC frequency. The VCO is controlled by two integrated variable capacitors.

The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the frequency-phase detector and fed via the loop filter to the first variable capacitor (FPLL). This control voltage is amplified and converted into a current which represents the AFC output signal. The VCO centre frequency can be decreased by activating an additional internal capacitor. With a variable resistor at VCOADJ (pin 11) the frequency for the M, B/G and L mode can be tuned to the picture carrier frequency. At centre frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency.

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the travelling wave divider output. In the demodulator stage the video signal polarity can be switched in accordance with the TV standard.

The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics for M, B/G and

L standard. The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation. The video output signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of M, B/G and L standard. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted for operating in combination with ceramic sound traps. The output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.

1996 Aug 02

6

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

SIF amplifier and AGC

The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration.

The SIF AGC detector is related to the SIF input signals (average level of AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to ‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is also set to ‘fast’ controlled by the standard switch.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO).

The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 20. With this system a high performance hi-fi stereo sound processing can be achieved.

For a simplified application without a sound-IF SAW filter the single reference QSS mixer can be switched to the intercarrier mode by connecting pins 31 and 32 to ground (see note 18 of Chapter “Characteristics”).

In this mode the sound-IF passes the VIF SAW filter and the composite IF signal is fed to the single reference QSS mixer. This IF signal is multiplied by the 90° TWD output signal for converting the sound-IF to intercarrier frequency. By using this quadrature detection, the low frequency video signals are removed.

Due to the sound-IF attenuation in the VIF filter (sound shelf), the audio signal-to-noise (S/N) figure decreases.

AM demodulator

The AM demodulator (French L standard) is realized by a multiplier. The modulated SIF amplifier output signal is multiplied in phase with the limited (AM is removed)

SIF amplifier output signal. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the AF amplifier.

FM detector

The FM detector consists of a limiter, an FM-PLL and an AF amplifier. The limiter provides the amplification and limitation of the FM sound intercarrier signal before demodulation. The result is high sensitivity and AM suppression. The amplifier consists of 7 stages which are internally AC-coupled in order to minimize the DC offset and to save pins for DC decoupling.

The FM-PLL consists of an integrated relaxation oscillator, an integrated loop filter and a phase detector.

The oscillator is locked to the FM intercarrier signal, output from the limiter. As a result of locking, the oscillator frequency tracks with the modulation of the input signal and the oscillator control voltage is superimposed by the AF voltage. The FM-PLL operates as an FM-demodulator.

The AF amplifier consists of two parts:

1.The AF preamplifier for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator, by principle a small output signal, is amplified by approximately 30 dB. The low-pass characteristic of the amplifier reduces the harmonics of the intercarrier signal at the sound output terminal. An additional DC control circuit is implemented to keep the DC level constant, independent of process spread.

2.The AF output amplifier (10 dB) provides the required output level by a rail-to-rail output stage. This amplifier makes use of an input selector for switching to AM/FM or mute state, controlled by the standard switching voltage and the mute switching voltage.

Internal voltage stabilizer and 1¤2VP reference

The band-gap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage.

For all audio output signals the constant reference voltage cannot be used because large output signals are required. Therefore these signals refer to half the supply voltage to achieve a symmetrical headroom, especially for the rail-to-rail output stage. For ripple and noise attenuation the 1¤2VP voltage has to be filtered via a low-pass filter by using an external capacitor together with an integrated resistor (fg = 5 Hz). For a fast setting to 1¤2VP an internal start-up circuit is added.

1996 Aug 02

7

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

DVB mixer

The VCO can be controlled by an external DC signal to provide a carrier for the down-conversion of the DVB-IF signal. The VCO frequency as a function of the voltage at pin 16 is given in Figs 10 and 11.

DVB AGC

For the DVB operation a peak AGC detector is activated. The peak value of (digital) QAM signal is detected and controlled to a constant value by the variable VIF amplifier. The detector bandwidth is adapted to the signal frequency (3 to 11 MHz). The external AGC time constant is given by the VIF AGC capacitor at pin 28.

LIMITING VALUES

The DVB output signal VO DVB can be adjusted in a range of ±3 dB by a control voltage Vadj at pin 15. The internal AGC can be switched off (see Table 2) and the IF gain can

be controlled by an external voltage at pin 13. The tuner AGC is active in both instances.

DVB output buffer

The output buffer for the DVB signal has a high bandwidth and 0 dB gain. An inverting configuration was chosen to obtain minimum distortion. For non-DVB standards the buffer is switched to a mute to reduce the output signal level.

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VP	supply voltage (pin 29)	maximum chip temperature of 125 °C;	0	7.0	V
		note 1
Vn	voltage at pins 1 to 9, 11 to 13,		0	VP	V
	15, 16, 19, 22, 23 and 28 to 32
tsc(max)	maximum short-circuit time		−	10	s
V19	tuner AGC output voltage		0	13.2	V
Tstg	storage temperature		−25	+150	°C
Tamb	operating ambient temperature		−20	+70	°C
Ves	electrostatic handling voltage	note 2	−300	+300	V

Notes

1.IP = 125 mA; Tamb = 70 °C; Rth j-a = 60 K/W.

2.Machine model class B.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient in free air	60	K/W

1996 Aug 02

8

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

CHARACTERISTICS

VP = 5 V; Tamb = 25 °C; see Table 1 for input frequencies and level; input level Vi IF1-2, 4-5 = 10 mV RMS value (sync-level for M and B/G, peak white level for L); video modulation DSB; residual carrier M and B/G: 10%; L = 3%;

video signal in accordance with “CCIR, line 17”; measurements taken in Fig.12; unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply (pin 29)
VP	supply voltage	note 1	4.5	5.0	5.5	V
IP	supply current	M, B/G and L standard	89	105	121	mA
		DVB	81	96	111	mA
Vision IF amplifier (pins 1, 2, 4 and 5)
Vi VIF(rms)	input signal voltage sensitivity	M, B/G and L standard;	−	60	90	μV
	(RMS value)	−1 dB video at output
Vi max(rms)	maximum input signal voltage	M, B/G and L standard;	140	200	−	mV
	(RMS value)	+1 dB video at output
Vo(int)	internal IF amplitude difference	within AGC range;	−	0.7	1	dB
	between picture and sound	f = 5 MHz
	carrier
GIF	IF gain control range	see Fig.3	65	70	−	dB
Ri(diff)	differential input resistance	note 2; input activated	1.7	2.2	2.7	kΩ
Ci(diff)	differential input capacitance	note 2; input activated	1.2	1.7	2.5	pF
V1, 2, 4, 5	DC input voltage	note 2; input activated	−	3.3	−	V
Ri	input resistance to ground	note 2; input not activated	−	1.1	−	kΩ
V1, 2, 4, 5	DC input voltage	note 2; input not activated	−	0.2	−	V
αi IF	crosstalk attenuation of IF input	notes 2 and 3	55	60	−	dB
	switch at pins 1, 2, 4 and 5
True synchronous video demodulator; note 4
fVCO(max)	maximum oscillator frequency for	f = 2fPC	125	130	−	MHz
	carrier regeneration
fosc	oscillator drift as a function of	free-running oscillator;	−	−	±20	ppm/K
------------	temperature	IAFC = 0; note 5
T
V0 ref(rms)	oscillator voltage swing between		−	60	−	mV
	pins 24 and 25 (RMS value)
fPC CR	vision carrier capture range	M standard	±1.0	±1.25	−	MHz
		B/G and L standard	±1.35	±1.6	−	MHz
fPC(fr)	vision carrier frequency accuracy	M standard	−	±150	±300	kHz
	(free-running)	B/G and L standard	−	±200	±400	kHz
fPC(alg)	frequency alignment range	IAFC = 0; M standard	±300	±400	−	kHz
		IAFC = 0; B/G and	±400	±600	−	kHz
		L standard
tacq	acquisition time	BL = 70 kHz; note 6	−	−	30	ms
Vi VIF(rms)	VIF input signal voltage	maximum IF gain; note 7	−	60	90	μV
	sensitivity for PLL to be locked
	(RMS value; pins 1, 2, 4 and 5)
IFPLL(offset)	FPLL offset current at pin 7	note 8	−	−	±4.5	μA

1996 Aug 02

9

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Composite video amplifier (pin 21; sound carrier off)
Vo video(p-p)	output signal voltage	see Fig.8	0.88	1.0	1.12	V
	(peak-to-peak value)
V21(sync)	sync voltage level		−	1.5	−	V
V21(clu)	upper video clipping voltage level		VP − 1.1	VP − 1	−	V
V21(cll)	lower video clipping voltage level		−	0.7	0.9	V
Ro,21	output resistance	note 2	−	−	10	Ω
Iint 21	internal DC bias current for		1.6	2.0	−	mA
	emitter-follower
I21 max(sink)	maximum AC and DC output		1.0	−	−	mA
	sink current
I21 max(source)	maximum AC and DC output		2.0	−	−	mA
	source current
B−1	−1 dB video bandwidth	CL < 50 pF; RL > 1 kΩ;	5	6	−	MHz
		AC load
B−3	−3 dB video bandwidth	CL < 50 pF; RL > 1 kΩ;	7	8	−	MHz
		AC load
αH	suppression of video signal	CL < 50 pF; RL > 1 kΩ;	35	40	−	dB
	harmonics	AC load; note 9
PSRR	power supply ripple rejection at	video signal; grey level; see
	pin 21	Fig.9
		M and B/G standard	32	35	−	dB
		L standard	26	30	−	dB
CVBS buffer amplifier (only) and noise clipper (pins 10 and 22)
Ri,22	input resistance	note 2	2.6	3.3	4.0	kΩ
Ci,22	input capacitance	note 2	1.4	2	3.0	pF
VI,22	DC input voltage		1.5	1.8	2.1	V
Gv	voltage gain	M, B/G and L standard;	6.5	7	7.5	dB
		note 10
V10(clu)	upper video clipping voltage level		3.9	4.0	−	V
V10(cll)	lower video clipping voltage level		−	1.0	1.1	V
Ro,10	output resistance	note 2	−	−	10	Ω
Iint 10	DC internal bias current for		2.0	2.5	−	mA
	emitter-follower
Io,10 max(sink)	maximum AC and DC output		1.4	−	−	mA
	sink current
Io,10 max(source)	maximum AC and DC output		2.4	−	−	mA
	source current
B−1	−1 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	8.4	11	−	MHz
		AC load
B−3	−3 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	11	14	−	MHz
		AC load

1996 Aug 02

10

Philips Semiconductors	Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.		UNIT
Measurements from IF input to CVBS output (pin 10; 330 Ω between pins 21 and 22, sound carrier off)
Vo CVBS(p-p)	CVBS output signal voltage on	note 10	1.7	2.0	2.3		V
	pin 10 (peak-to-peak value)
Vo CVBS(sync)	sync voltage level	M and B/G standard	−	1.35	−		V
		L standard	−	1.35	−		V
Vo	deviation of CVBS output signal	50 dB gain control	−	−	0.5		dB
	voltage at M and B/G standard	30 dB gain control	−	−	0.1		dB
Vo(blBG)	black level tilt in M and	gain variation; note 11	−	−	1		%
	B/G standard
Vo(blL)	black level tilt for worst case in	vision carrier modulated by	−	−	1.9		%
	L standard	test line (VITS) only; gain
		variation; note 11
Gdiff	differential gain	“CCIR, line 330”	−	2	5		%
ϕdiff	differential phase	“CCIR, line 330”	−	1	2		deg
B−1	−1 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	5	6	−		MHz
		AC load; M, B/G and
		L standard
B−3	−3 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	7	8	−		MHz
		AC load; M, B/G and
		L standard
S/N (W)	weighted signal-to-noise ratio	see Fig.5 and note 12	56	60	−		dB
S/N	unweighted signal-to-noise ratio	see Fig.5 and note 12	49	53	−		dB
IMα1.1	intermodulation attenuation at	f = 1.1 MHz; see Fig.6 and	58	64	−		dB
	‘blue’	note 13
	intermodulation attenuation at	f = 1.1 MHz; see Fig.6 and	60	66	−		dB
	‘yellow’	note 13
IMα3.3	intermodulation attenuation at	f = 3.3 MHz; see Fig.6 and	58	64	−		dB
	‘blue’	note 13
	intermodulation attenuation at	f = 3.3 MHz; see Fig.6 and	59	65	−		dB
	‘yellow’	note 13
αc(rms)	residual vision carrier	fundamental wave and	−	2	10		mV
	(RMS value)	harmonics; M, B/G and
		L standard
αH(sup)	suppression of video signal	note 9	35	40	−		dB
	harmonics
αH(spur)	spurious elements	note 14	40	−	−		dB
PSRR	power supply ripple rejection at	video signal; grey level;
	pin 10	see Fig.9
		M and B/G standard	25	28	−		dB
		L standard	20	23	−		dB

1996 Aug 02

11