Philips TDA9819 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9819

Multistandard vision and sound-IF
PLL with DVB-IF processing

Preliminary specification
File under Integrated Circuits, IC02

1996 Aug 02

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with
DVB-IF processing

FEATURES

• 5 V supply voltage

• Applicable for IF frequencies of 38.9 MHz and

45.75 MHz

• Two switched VIF inputs, gain controlled wide band
VIF-amplifier (AC-coupled)

• True synchronous demodulation with active carrier
regeneration (very linear demodulation, good
intermodulation figures, reduced harmonics and
excellent pulse response)

• VCO frequency switchable between TV (M or BG/L)
IF-picture carrier and Digital Video Broadcast (DVB)
frequency

• Separate video amplifier for sound trap buffering with
high video bandwidth

• VIF AGC detector for gain control, operating as peak
sync detector for M and B/G and peak white detector for
L; controlled reaction time for L

• Tuner AGC with adjustable takeover point (TOP)

• AFC detector without extra reference circuit

• SIF input for single reference QSS mode

(PLL controlled); SIF AGC detector for gain controlled
SIF amplifier; single reference QSS mixer able to
operate in high performance single reference QSS
mode

• AC-coupled limiter amplifier for sound intercarrier signal

• Alignment-free FM-PLL demodulator with high linearity

• AM demodulator without extra reference circuit

• Stabilizer circuit for ripple rejection and to achieve

constant output signals.

DVB functions

• Gain controlled IF-amplifier

• Mixer for DVB-IF

• VCO for QAM carrier recovery

• External VCO control for DVB

• Internal and external AGC for DVB

• DVB output level adjust via AGC adjust

• High level DVB operational output amplifier.

GENERAL DESCRIPTION

The TDA9819 is an integrated circuit for multistandard
vision and sound-IF signal processing with single
reference PLL demodulator combined with the signal
stages for DVB-IF processing.

TDA9819

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9819 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

1996 Aug 02 2

PACKAGE

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

V

i VIF(rms)

V

o CVBS(p-p)

B (M,
BG/L)

S/N (W) weighted signal-to-noise ratio for

α

1.1

α

3.3

α

H

V

i SIF(rms)

V

o(rms)

THD total harmonic distortion

S/N (W) weighted signal-to-noise ratio

supply voltage 4.5 5.0 5.5 V
supply current 81 100 121 mA
vision IF input signal voltage

−1 dB video at output − 60 100 µV

sensitivity (RMS value)
CVBS output signal voltage

1.7 2.0 2.3 V

(peak-to-peak value)

−3 dB video bandwidth on pin 10 M, B/G and L standard;
< 20 pF; RL> 1kΩ;

C

L

78−MHz

AC load

56 60 − dB

video
intermodulation attenuation at ‘blue’ f = 1.1 MHz 58 64 − dB
intermodulation attenuation at ‘blue’ f = 3.3 MHz 58 64 − dB
suppression of harmonics in video

35 40 − dB

signal
sound-IF input signal voltage

−3 dB at intercarrier output − 70 100 µV

sensitivity (RMS value)
audio output signal voltage for FM

(RMS value)
audio output signal voltage for AM

(RMS value)

M and B/G standard;
25 kHz frequency deviation

L standard;
54% modulation

− 0.5 − V

− 0.5 − V

FM 25 kHz frequency deviation − 0.15 0.5 %
AM 54% modulation − 0.5 1.0 %

FM 25 kHz frequency deviation − 60 − dB
AM 54% modulation 47 53 − dB

1996 Aug 02 3

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with
DVB-IF processing

BLOCK DIAGRAM

video

1 V (p-p)

21

VCO

adjust

24 1116

VCO

PC

2f

DVB

VCO

control

external

TWD

DVB

2 V (p-p)

18

CVBS

10

SIF

video

2 V (p-p)

22

MIXER

TDA9819

AF

buffer

12

(PLL)

FM DETECTOR

MBH352

AF

C

1417

AF

mute

loop

filter

AFC

DVB

AGC

external

DVB

AGC

adjust

BL

C

VAGC

C

tuner

TOP

handbook, full pagewidth

3 15 13 23 7 25

19 28

AGC

6

AFC

DETECTOR

DVB

AGC

VIF-AGC

AGC

TUNER

VIF

FPLL

TDA9819

(1)

switch

input/DVB

DVB MIXER

DEMODULA T OR/

1302

A

VIF

VIF

SWITCH
4

5

B

DVB

LOGIC

31

AM

32

SIF

DEMODULA T OR

SIF-AGC

VOLT AGE

INTERNAL

IF-filter

STABILIZER

4.5/5.5

20

QSS

output

intercarrier

(1)

Fig.1 Block diagram.

switch

standard

SAGC

8262729 9

C

P

1/2 V

P

V

(+5 V)

1996 Aug 02 4

(1) See switch logic Table 2.

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with
DVB-IF processing

PINNING

SYMBOL PIN DESCRIPTION

V

i VIF1

V

i VIF2

C

BL

V

i VIF3

V

i VIF4

TADJ 6 tuner AGC takeover adjust (TOP)
T

PLL

C

SAGC

STD 9 standard switch input
V

o CVBS

VCOADJ 11 VCO adjust BG/L/M
V

oAF

V

AGC(ext)

C

AF

AGCADJ 15 AGC adjust (DVB)
V

VCO(ext)

V

iFM

DVB 18 DVB output
TAGC 19 tuner AGC output
V

o QSS

V

o(vid)

V

i(vid)

AFC 23 AFC output
VCO1 24 VCO1 reference circuit for 2f
VCO2 25 VCO2 reference circuit for 2f
C

ref

GND 27 ground
C

VAGC

V

P

INSWI 30 VIF input switch
V

i SIF1

V

i SIF2

1 VIF differential input signal voltage 1
2 VIF differential input signal voltage 2
3 black level detector
4 VIF differential input signal voltage 3
5 VIF differential input signal voltage 4

7 PLL loop filter
8 SIF AGC capacitor

10 2 V CVBS output signal voltage

12 audio voltage frequency output
13 external AGC voltage (DVB)
14 AF decoupling capacitor

16 external VCO control voltage (DVB)
17 sound intercarrier input

20 single reference QSS output voltage
21 composite video output voltage
22 video buffer input voltage

PC
PC

261⁄2VP reference capacitor

28 VIF AGC capacitor
29 supply voltage (+5 V)

31 SIF differential input signal voltage 1
32 SIF differential input signal voltage 2

handbook, halfpage

V

V

V

1

i VIF1

V

2

i VIF2

C

3

BL

V

4

i VIF3

V

5

i VIF4

TADJ

6

T

7

PLL

C

V

o CVBS

VCOADJ

AGC(ext)

AGCADJ

VCO(ext)

SAGC

STD

V

o AF

C

AF

8

9
10
11
12
13
14
15
16

TDA9819

Fig.2 Pin configuration.

MBH354

TDA9819

V

32

i SIF2

V

31

i SIF1

INSWI

30

V

29

P

C

28

VAGC

27

GND
C

26

ref

25

VCO2

24

VCO1

23

AFC
V

22

i(vid)

V

21

o(vid)

V

20

o QSS

19

TAGC
DVB

18

V

17

i FM

1996 Aug 02 5

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with
DVB-IF processing

FUNCTIONAL DESCRIPTION
Vision IF amplifier and input switch

The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage
comprises a feedback network controlled by emitter
degeneration to control the IF gain. The first differential
stage is extended by two pairs of emitter followers to
provide two IF input channels. The VIF input can be
selected by pin 30.

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF
control signal, and is fed to the tuner AGC to generate the
tuner AGC output current (open-collector output).
The tuner AGC takeover point can be adjusted.
This allows the tuner and the SWIF filter to be matched to
achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitor
to the required voltage for setting of VIF and tuner gain in
order to keep the video signal at a constant level.
Therefore for negative video modulation the sync level and
for positive video modulation the peak white level of the
video signal is detected. In order to reduce the reaction
time for positive modulation, where a very large time
constant is needed, an additional level detector increases
the discharging current of the AGC capacitor (fast mode)
in the event of a decreasing VIF amplitude step.
The additional level information is given by the black-level
detector voltage.

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency
detector and into a phase detector via a limiting amplifier.
During acquisition the frequency detector produces a DC
current proportional to the frequency difference between
the input and the VCO signal. After frequency lock-in the
phase detector produces a DC current proportional to the
phase difference between the VCO and the input signal.
The DC current of either frequency detector or phase
detector is converted into a DC voltage via the loop filter,
which controls the VCO frequency. In the event of positive
modulated signals the phase detector is gated by
composite sync in order to avoid signal distortion for
overmodulated VIF signals.

TDA9819

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C
in parallel) at double the PC frequency. The VCO is
controlled by two integrated variable capacitors.
The control voltage required to tune the VCO from its
free-running frequency to actually double the PC
frequency is generated by the frequency-phase detector
and fed via the loop filter to the first variable capacitor
(FPLL). This control voltage is amplified and converted
into a current which represents the AFC output signal.
The VCO centre frequency can be decreased by activating
an additional internal capacitor. With a variable resistor at
VCOADJ (pin 11) the frequency for the M, B/G and L mode
can be tuned to the picture carrier frequency. At centre
frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which
generates two differential output signals with a 90 degree
phase difference independent of the frequency.

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The vision
IF input signal is multiplied with the ‘in phase’ signal of the
travelling wave divider output. In the demodulator stage
the video signal polarity can be switched in accordance
with the TV standard.

The demodulator output signal is fed via an integrated
low-pass filter for attenuation of the carrier harmonics to
the video amplifier. The video amplifier is realized by an
operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an
attenuation of the carrier harmonics for M, B/G and
L standard. The standard dependent level shift in this
stage delivers the same sync level for positive and
negative modulation. The video output signal is 1 V (p-p)
for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational
amplifier with internal feedback is used in the event of M,
B/G and L standard. This amplifier is featured with a high
bandwidth and 7 dB gain. The input impedance is adapted
for operating in combination with ceramic sound traps.
The output stage delivers a nominal 2 V (p-p) positive
video signal. Noise clipping is provided.

1996 Aug 02 6

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with
DVB-IF processing

SIF amplifier and AGC

The sound IF amplifier consists of two AC-coupled
differential amplifier stages. Each differential stage
comprises a controlled feedback network provided by
emitter degeneration.

The SIF AGC detector is related to the SIF input signals
(average level of AM or FM carriers) and controls the SIF
amplifier to provide a constant SIF signal to the AM
demodulator and single reference QSS mixer. The SIF
AGC reaction time is set to ‘slow’ for nominal video
conditions. But with a decreasing VIF amplitude step the
SIF AGC is set to ‘fast’ mode controlled by the VIF AGC
detector. In FM mode this reaction time is also set to ‘fast’
controlled by the standard switch.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier.
The SIF amplifier output signal is fed to the single
reference QSS mixer and converted to intercarrier
frequency by the regenerated picture carrier (VCO).
The mixer output signal is fed via a high-pass for
attenuation of the video signal components to the output
pin 20. With this system a high performance hi-fi stereo
sound processing can be achieved.

For a simplified application without a sound-IF SAW filter
the single reference QSS mixer can be switched to the
intercarrier mode by connecting pins 31 and 32 to ground
(see note 18 of Chapter “Characteristics”).

In this mode the sound-IF passes the VIF SAW filter and
the composite IF signal is fed to the single reference QSS
mixer. This IF signal is multiplied by the 90° TWD output
signal for converting the sound-IF to intercarrier frequency.
By using this quadrature detection, the low frequency
video signals are removed.

Due to the sound-IF attenuation in the VIF filter (sound
shelf), the audio signal-to-noise (S/N) figure decreases.

AM demodulator

The AM demodulator (French L standard) is realized by a
multiplier. The modulated SIF amplifier output signal is
multiplied in phase with the limited (AM is removed)
SIF amplifier output signal. The demodulator output signal
is fed via an integrated low-pass filter for attenuation of the
carrier harmonics to the AF amplifier.

TDA9819

FM detector

The FM detector consists of a limiter, an FM-PLL and an
AF amplifier. The limiter provides the amplification and
limitation of the FM sound intercarrier signal before
demodulation. The result is high sensitivity and AM
suppression. The amplifier consists of 7 stages which are
internally AC-coupled in order to minimize the DC offset
and to save pins for DC decoupling.

The FM-PLL consists of an integrated relaxation oscillator,
an integrated loop filter and a phase detector.
The oscillator is locked to the FM intercarrier signal, output
from the limiter. As a result of locking, the oscillator
frequency tracks with the modulation of the input signal
and the oscillator control voltage is superimposed by the
AF voltage. The FM-PLL operates as an FM-demodulator.

The AF amplifier consists of two parts:

1. The AF preamplifier for FM sound is an operational
amplifier with internal feedback, high gain and high
common mode rejection. The AF voltage from the PLL
demodulator, by principle a small output signal, is
amplified by approximately 30 dB. The low-pass
characteristic of the amplifier reduces the harmonics of
the intercarrier signal at the sound output terminal.
An additional DC control circuit is implemented to keep
the DC level constant, independent of process spread.

2. The AF output amplifier (10 dB) provides the required
output level by a rail-to-rail output stage. This amplifier
makes use of an input selector for switching to AM/FM
or mute state, controlled by the standard switching
voltage and the mute switching voltage.

Internal voltage stabilizer and

The band-gap circuit internally generates a voltage of
approximately 1.25 V, independent of supply voltage and
temperature. A voltage regulator circuit, connected to this
voltage, produces a constant voltage of 3.6 V which is
used as an internal reference voltage.

For all audio output signals the constant reference voltage
cannot be used because large output signals are required.
Therefore these signals refer to half the supply voltage to
achieve a symmetrical headroom, especially for the
rail-to-rail output stage. For ripple and noise attenuation

1

the

⁄2VP voltage has to be filtered via a low-pass filter by

using an external capacitor together with an integrated
resistor (fg= 5 Hz). For a fast setting to 1⁄2VP an internal
start-up circuit is added.

1

⁄2VP reference

1996 Aug 02 7

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

DVB mixer

The VCO can be controlled by an external DC signal to
provide a carrier for the down-conversion of the DVB-IF
signal. The VCO frequency as a function of the voltage at
pin 16 is given in Figs 10 and 11.

DVB AGC

For the DVB operation a peak AGC detector is activated.
The peak value of (digital) QAM signal is detected and
controlled to a constant value by the variable VIF amplifier.
The detector bandwidth is adapted to the signal frequency
(3 to 11 MHz). The external AGC time constant is given by

The DVB output signal V
of ±3 dB by a control voltage ∆V
AGC can be switched off (see Table 2) and the IF gain can
be controlled by an external voltage at pin 13. The tuner
AGC is active in both instances.

DVB output buffer

The output buffer for the DVB signal has a high bandwidth
and 0 dB gain. An inverting configuration was chosen to
obtain minimum distortion. For non-DVB standards the
buffer is switched to a mute to reduce the output signal
level.

the VIF AGC capacitor at pin 28.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

supply voltage (pin 29) maximum chip temperature of 125 °C;

note 1

V

n

voltage at pins 1 to 9, 11 to 13,
15, 16, 19, 22, 23 and 28 to 32

t

sc(max)

V

19

T

stg

T

amb

V

es

maximum short-circuit time − 10 s
tuner AGC output voltage 0 13.2 V
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
electrostatic handling voltage note 2 −300 +300 V

can be adjusted in a range

O DVB

at pin 15. The internal

adj

0 7.0 V

0V

P

V

Notes

1. IP= 125 mA; T

=70°C; R

amb

th j-a

= 60 K/W.

2. Machine model class B.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 60 K/W

1996 Aug 02 8

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

CHARACTERISTICS

VP=5V; T
(sync-level for M and B/G, peak white level for L); video modulation DSB; residual carrier M and B/G: 10%; L = 3%;
video signal in accordance with “

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin 29)

V

P

I

P

Vision IF amplifier (pins 1, 2, 4 and 5)

V

i VIF(rms)

V

i max(rms)

∆V

o(int)

G

IF

R

i(diff)

C

i(diff)

V

1, 2,4, 5

R

i

V

1, 2,4, 5

α

iIF

=25°C; see Table 1 for input frequencies and level; input level V

amb

CCIR, line 17”

; measurements taken in Fig.12; unless otherwise specified.

i IF1-2,4-5

= 10 mV RMS value

supply voltage note 1 4.5 5.0 5.5 V
supply current M, B/G and L standard 89 105 121 mA

DVB 81 96 111 mA

input signal voltage sensitivity
(RMS value)

maximum input signal voltage
(RMS value)

internal IF amplitude difference
between picture and sound

M, B/G and L standard;

−1 dB video at output
M, B/G and L standard;

+1 dB video at output
within AGC range;

∆f=5MHz

− 60 90 µV

140 200 − mV

− 0.7 1 dB

carrier
IF gain control range see Fig.3 65 70 − dB
differential input resistance note 2; input activated 1.7 2.2 2.7 kΩ
differential input capacitance note 2; input activated 1.2 1.7 2.5 pF
DC input voltage note 2; input activated − 3.3 − V
input resistance to ground note 2; input not activated − 1.1 − kΩ
DC input voltage note 2; input not activated − 0.2 − V
crosstalk attenuation of IF input

notes 2 and 3 55 60 − dB

switch at pins 1, 2, 4 and 5
True synchronous video demodulator; note 4
f

VCO(max)

maximum oscillator frequency for

f=2f

PC

carrier regeneration

f∆

osc

------------ ­T∆

V

0 ref(rms)

oscillator drift as a function of
temperature

oscillator voltage swing between

free-running oscillator;
I

= 0; note 5

AFC

pins 24 and 25 (RMS value)

f

PC CR

vision carrier capture range M standard ±1.0 ±1.25 − MHz

B/G and L standard ±1.35 ±1.6 − MHz

∆f

∆f

PC(fr)

PC(alg)

vision carrier frequency accuracy
(free-running)

frequency alignment range I

M standard −±150 ±300 kHz
B/G and L standard −±200 ±400 kHz

= 0; M standard ±300 ±400 − kHz

AFC

I

= 0; B/G and

AFC

L standard

t

acq

V

i VIF(rms)

acquisition time BL = 70 kHz; note 6 −−30 ms
VIF input signal voltage

maximum IF gain; note 7 − 60 90 µV
sensitivity for PLL to be locked
(RMS value; pins 1, 2, 4 and 5)

I

FPLL(offset)

FPLL offset current at pin 7 note 8 −−±4.5 µA

1996 Aug 02 9

125 130 − MHz

−−±20 ppm/K

− 60 − mV

±400 ±600 − kHz

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Composite video amplifier (pin 21; sound carrier off)

V

o video(p-p)

output signal voltage
(peak-to-peak value)

V

21(sync)

V

21(clu)

V

21(cll)

R

o,21

I

int 21

sync voltage level − 1.5 − V
upper video clipping voltage level VP− 1.1 VP− 1 − V
lower video clipping voltage level − 0.7 0.9 V
output resistance note 2 −−10 Ω
internal DC bias current for

emitter-follower

I

21 max(sink)

maximum AC and DC output
sink current

I

21 max(source)

maximum AC and DC output
source current

B

−1

B

−3

α

H

−1 dB video bandwidth CL< 50 pF; RL> 1kΩ;

−3 dB video bandwidth CL< 50 pF; RL> 1kΩ;

suppression of video signal
harmonics

PSRR power supply ripple rejection at

pin 21

see Fig.8 0.88 1.0 1.12 V

1.6 2.0 − mA

1.0 −−mA

2.0 −−mA

56−MHz

AC load

78−MHz

AC load

CL< 50 pF; RL> 1kΩ;

35 40 − dB

AC load; note 9

video signal; grey level; see

Fig.9

M and B/G standard 32 35 − dB
L standard 26 30 − dB

CVBS buffer amplifier (only) and noise clipper (pins 10 and 22)

R

i,22

C

i,22

V

I,22

G

v

input resistance note 2 2.6 3.3 4.0 kΩ
input capacitance note 2 1.4 2 3.0 pF
DC input voltage 1.5 1.8 2.1 V
voltage gain M, B/G and L standard;

note 10

V

10(clu)

V

10(cll)

R

o,10

I

int 10

upper video clipping voltage level 3.9 4.0 − V
lower video clipping voltage level − 1.0 1.1 V
output resistance note 2 −−10 Ω
DC internal bias current for

emitter-follower

I

o,10 max(sink)

maximum AC and DC output
sink current

I

o,10 max(source)

maximum AC and DC output
source current

B

−1

−1 dB video bandwidth CL< 20 pF; RL> 1kΩ;

AC load

B

−3

−3 dB video bandwidth CL< 20 pF; RL> 1kΩ;

AC load

6.5 7 7.5 dB

2.0 2.5 − mA

1.4 −−mA

2.4 −−mA

8.4 11 − MHz

11 14 − MHz

1996 Aug 02 10

Philips Semiconductors Preliminary specification

Multistandard vision and sound-IF PLL with

TDA9819

DVB-IF processing

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Measurements from IF input to CVBS output (pin 10; 330 Ω between pins 21 and 22, sound carrier off)

V

o CVBS(p-p)

CVBS output signal voltage on
pin 10 (peak-to-peak value)

V

o CVBS(sync)

∆V

o

sync voltage level M and B/G standard − 1.35 − V

deviation of CVBS output signal
voltage at M and B/G standard

∆V

o(blBG)

black level tilt in M and
B/G standard

∆V

o(blL)

black level tilt for worst case in
L standard

G

diff

ϕ

diff

B

−1

B

−3

differential gain
differential phase

−1 dB video bandwidth CL< 20 pF; RL> 1kΩ;

−3 dB video bandwidth CL< 20 pF; RL> 1kΩ;

S/N (W) weighted signal-to-noise ratio see Fig.5 and note 12 56 60 − dB
S/N unweighted signal-to-noise ratio see Fig.5 and note 12 49 53 − dB
IMα

1.1

intermodulation attenuation at
‘blue’

intermodulation attenuation at
‘yellow’

IMα

3.3

intermodulation attenuation at
‘blue’

intermodulation attenuation at
‘yellow’

α

c(rms)

residual vision carrier
(RMS value)

α

H(sup)

suppression of video signal
harmonics

α

H(spur)

spurious elements note 14 40 −−dB

PSRR power supply ripple rejection at

pin 10

note 10 1.7 2.0 2.3 V

L standard − 1.35 − V

50 dB gain control −−0.5 dB

30 dB gain control −−0.1 dB

gain variation; note 11 −−1%

vision carrier modulated by

−−1.9 %
test line (VITS) only; gain
variation; note 11

“CCIR, line 330”
“CCIR, line 330”

− 25%

− 1 2 deg

56−MHz
AC load; M, B/G and
L standard

78−MHz
AC load; M, B/G and
L standard

f = 1.1 MHz; see Fig.6 and

58 64 − dB
note 13

f = 1.1 MHz; see Fig.6 and

60 66 − dB
note 13

f = 3.3 MHz; see Fig.6 and

58 64 − dB
note 13

f = 3.3 MHz; see Fig.6 and

59 65 − dB
note 13

fundamental wave and

− 210mV
harmonics; M, B/G and
L standard

note 9 35 40 − dB

video signal; grey level;
see Fig.9

M and B/G standard 25 28 − dB
L standard 20 23 − dB

1996 Aug 02 11