Philips TDA9815 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA9815

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

Product speciﬁcation Supersedes data of 1995 Oct 03 File under Integrated Circuits, IC02

1998 Feb 11

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

FEATURES

• 5 V supply voltage

• Two switched VIF inputs, gain controlled wide band

VIF-amplifier (AC-coupled)

• True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)

• Robustness for over-modulation better than 105% due to gated phase detector at L/L accent standard

• VCO frequency switchable between L and L accent (alignment external) picture carrier frequency

• Separate video amplifier for sound trap buffering with high video bandwidth

• VIF-AGC detector for gain control, operating as peak sync detector for B/G, peak white detector for L and peak level for MAC (optional external AGC); signal controlled reaction time for L and MAC

• Tuner AGC with adjustable takeover point (TOP)

• AFC detector without extra reference circuit

• AC-coupled limiter amplifier for sound intercarrier signal

with input switch for additional FM signal

• Two alignment-free FM-PLL demodulators with high linearity

• SIF input for single reference QSS mode (PLL controlled); SIF AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode

• AM demodulator without extra reference circuit

• Stabilizer circuit for ripple rejection and to achieve

constant output signals

• ESD protection for all pins.

TDA9815

GENERAL DESCRIPTION

The TDA9815 is an integrated circuit for multistandard vision IF signal processing (inclusive MAC) and sound AM and dual FM demodulation, with single reference QSS-IF in TV and VCR sets.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9815 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

1998 Feb 11 2

PACKAGE

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF

TDA9815

and dual FM-PLL/AM demodulator

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

i VIF(rms)

o CVBS(p-p)

−3

S/N (W) weighted signal-to-noise ratio for

α1.1

α3.3

H(sup)

i SIF(rms)

o(rms)

THD total harmonic distortion 54% modulation

S/N (W) weighted signal-to-noise ratio 54% modulation

supply voltage 4.5 5 5.5 V supply current 93 109 125 mA vision IF input signal voltage

−1 dB video at output − 60 100 µV

sensitivity (RMS value) CVBS output signal voltage

1.7 2.0 2.3 V

(peak-to-peak value)

−3 dB video bandwidth on pin CVBS B/G and L standard; CL< 20 pF; > 1kΩ; AC load

78−MHz

MAC standard 11 14 − MHz

56 60 − dB

video intermodulation attenuation at ‘blue’ f = 1.1 MHz 58 64 − dB intermodulation attenuation at ‘blue’ f = 3.3 MHz 58 64 − dB suppression of harmonics in video

35 40 − dB

signal sound IF input signal voltage

−3 dB at intercarrier output − 30 70 µV

sensitivity (RMS value) audio output signal voltage for FM

B/G standard; 54% modulation − 0.5 − V

(RMS value) audio output signal voltage for AM

L standard; 54% modulation − 0.5 − V

(RMS value)

FM − 0.15 0.5 % AM − 0.5 1.0 %

FM − 60 − dB AM 47 53 − dB

1998 Feb 11 3

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1998 Feb 11 4

TOP

VIF input/

MAC switch

VAGC

MAC

tuner AGC

ook, full pagewidth

loop filter

2 x f

AFC

23242571928 63

BLOCK DIAGRAM

Multistandard/MAC VIF-PLL with QSS-IF

and dual FM-PLL/AM demodulator

Philips Semiconductors Product speciﬁcation

VIFB

VIFA

SIF

5 4

VIF AMPLIFIER

INPUT SWITCH

1 32 31

INTERNAL VOLTAGE

STABILIZER

29 27 26 9 8

5 V

AND

TUNER AND VIF-AGC

AMPLIFIER

SIF-AGC

VP1/2

standard

switch

SIF

SAGC

FPLL

SINGLE REFERENCE

MIXER AND

AM DEMODULATOR

11 20 17

L/L accent switch,

FM input switch

VCO TWD

AFC DETECTOR

VIDEO DEMODULATOR

AND AMPLIFIER

5.5

6/6.5

5.74 SIF

VIDEO

BUFFER

TDA9815

FM DETECTOR (PLL)

AF AMPLIFIER AND

SWITCH

FM DETECTOR (PLL)

AF AMPLIFIER

18 16 14

MED679 - 3

video

1 V (p-p)

CVBS

2 V (p-p)

i(vid)

AF1

AF2

TDA9815

Fig.1 Block diagram.

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

PINNING

SYMBOL PIN DESCRIPTION

i VIF1

i VIF2

BL/MAC

i VIF3

i VIF4

TADJ 6 tuner AGC takeover adjust (TOP) T

PLL

SAGC

STD 9 standard switch V

o CVBS

FMLSWI 11 FM input select and L/L accent

o AF1

o AF2

DEC2

DEC1

i FM2

i FM1

i FM3

TAGC 19 tuner AGC output V

o QSS

o(vid)

i(vid)

AFC 23 AFC output VCO1 24 VCO1 reference circuit for 2f VCO2 25 VCO2 reference circuit for 2f C

ref

GND 27 ground C

VAGC

INSWI 30 VIF input switch V

i SIF1

i SIF2

1 VIF differential input signal voltage 1 2 VIF differential input signal voltage 2 3 black level detector/MAC capacitor 4 VIF differential input signal voltage 3 5 VIF differential input signal voltage 4

7 PLL loop ﬁlter 8 SIF AGC capacitor

10 CVBS output signal voltage

switch 12 audio voltage frequency output 1 13 audio voltage frequency output 2 14 decoupling capacitor 2 15 decoupling capacitor 1 16 sound intercarrier input voltage 2 17 sound intercarrier input voltage 1 18 sound intercarrier input voltage 3

20 single reference QSS output voltage 21 composite video output voltage 22 video buffer input voltage

PC PC

261⁄2VP reference capacitor

28 VIF-AGC capacitor 29 supply voltage

31 SIF differential input signal voltage 1 32 SIF differential input signal voltage 2

handbook, halfpage

V V

BL/MAC

V V

o CVBS

FMLSWI

V C C

i VIF1 i VIF2

i VIF3 i VIF4

TADJ

PLL

SAGC

STD

o AF1 o AF2 DEC2 DEC1

i FM2

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

TDA9815

Fig.2 Pin configuration.

MED680

TDA9815

i SIF2

i SIF1

INSWI V

VAGC

GND

ref

VCO2

VCO1

AFC

i(vid)

o(vid)

o QSS

TAGC

i FM3

i FM1

1998 Feb 11 5

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

FUNCTIONAL DESCRIPTION

The integrated circuit comprises the functional blocks as shown in Fig.1:

• Vision IF amplifier and input switch

• Tuner and VIF-AGC

• Frequency Phase Locked Loop detector (FPLL)

• VCO, Travelling Wave Divider (TWD) and AFC

• Video demodulator and amplifier

• Video buffer

• SIF amplifier and AGC

• Single reference QSS mixer

• AM demodulator

• FM-PLL demodulator

• Internal voltage stabilizer and

Vision IF ampliﬁer and input switch

The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration. The first differential stage is extended by two pairs of emitter followers to provide two IF input channels. The VIF input can be selected by pin 30.

Tuner and VIF-AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (open-collector output). The tuner AGC takeover point can be adjusted. This allows the tuner and the SAW filter to be matched to achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitor to the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level. Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected. In order to reduce the reaction time for positive (or MAC) modulation, where a very large time constant is needed, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step. The additional level information is given by the black level detector voltage.

⁄2VP-reference.

TDA9815

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency. In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals.

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the PC frequency. The VCO is controlled by two integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the frequency-phase detector (FPLL) and fed via the loop filter to the first variable capacitor. This control voltage is amplified and additionally converted into a current which represents the AFC output signal. The VCO centre frequency can be decreased (required for L accent standard) by activating an additional internal capacitor. This is achieved by using the L accent switch. In this event the second variable capacitor can be controlled by a variable resistor at the L accent switch for setting the VCO centre frequency to the required L accent value. At centre frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency.

Video demodulator and ampliﬁer

The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the travelling wave divider output. In the demodulator stage the video signal polarity can be switched in accordance with the TV standard.

1998 Feb 11 6

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics for B/G and L standard. The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation. The video output signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of B/G and L standard. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted for operating in combination with ceramic sound traps. The output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.

For MAC standard a second buffer amplifier with 6 dB gain is used. This buffer amplifier is selected by the standard switch.

SIF ampliﬁer and AGC

The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration.

The SIF AGC detector is related to the SIF input signals (average level of AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to ‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC is set to ‘fast’ mode controlled by the VIF-AGC detector. In FM mode this reaction time is also set to ‘fast’ controlled by the standard switch.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO). The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 20. With this system a high performance hi-fi stereo sound processing can be achieved.

TDA9815

AM demodulator

The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the AF amplifier.

FM-PLL demodulator

Each FM-PLL demodulator consists of a limiter, an FM-PLL and an AF amplifier. The limiter provides the amplification and limitation of the FM sound intercarrier signal before demodulation. The result is high sensitivity and AM suppression. The amplifier consists of 7 stages which are internally AC-coupled in order to minimize the DC offset and to save pins for DC decoupling.

At the input of one limiter a signal switch is available for selecting one of the two intercarrier signals. Controlled by the voltage at pin 11, either the input pin 17 or pin 18 is active for handling different intercarrier frequencies.

The other limiter is extended with an additional level detector consisting of a rectifier and a comparator. By means of this the AF2 signal is set to mute and the PLL VCO is switched off, if the intercarrier signal at pin 16 is below 1 mV (RMS) in order to avoid false identification of a stereo decoder. Note that noise at pin 16 disables the mute state (at low SIF input signal), but this will not lead to false identification. This ‘auto-mute’ function can be disabled by connecting a 5.6 kΩ resistor from pin 16 to V (see Fig.13).

Furthermore the AF output signals can be muted by connecting a resistor between the limiter inputs pin 16 or pin 17 and ground.

The FM-PLL consists of an integrated relaxation oscillator, an integrated loop filter and a phase detector. The oscillator is locked to the FM intercarrier signal, output from the limiter. As a result of locking, the oscillator frequency tracks with the modulation of the input signal and the oscillator control voltage is superimposed by the AF voltage. The FM-PLL operates as an FM-demodulator.

1998 Feb 11 7

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator

The AF amplifier consists of two parts:

1. The AF preamplifier for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator, by principle a small output signal, is amplified by approximately 33 dB. The low-pass characteristic of the amplifier reduces the harmonics of the intercarrier signal at the sound output terminal. An additional DC control circuit is implemented to keep the DC level constant, independent of process spread.

2. The AF output amplifier (10 dB) provides the required output level by a rail-to-rail output stage. This amplifier makes use of an input selector for switching to AM/FM or mute state, controlled by the standard switching voltage and the mute switching voltage.

Internal voltage stabilizer and

The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage.

⁄2VP-reference

TDA9815

For all audio output signals the constant reference voltage cannot be used because large output signals are required. Therefore these signals refer to half the supply voltage to achieve a symmetrical headroom, especially for the rail-to-rail output stage. For ripple and noise attenuation

the

⁄2VP voltage has to be filtered via a low-pass filter by

using an external capacitor together with an integrated resistor (fg= 5 Hz). For a fast setting to 1⁄2VP an internal start-up circuit is added.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

supply voltage (pin 29) maximum chip temperature

0 7.0 V

of 125 °C; note 1

voltage at pins 1 to 9, 11 to 19, 22, 23 and

26 to 32

s(max)

stg

amb

maximum short-circuit time − 10 s tuner AGC output voltage 0 13.2 V storage temperature −25 +150 °C operating ambient temperature −20 +70 °C electrostatic handling voltage note 2 −300 +300 V

Notes

1. I

= 125 mA; T

=70°C; R

amb

th(j-a)

= 60 K/W.

2. Machine model class B (L = 2.5 µH).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 60 K/W

1998 Feb 11 8

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF

TDA9815

and dual FM-PLL/AM demodulator

CHARACTERISTICS

VP=5V; T (sync-level for B/G, peak white level for L, peak level for MAC); video modulation DSB; residual carrier B/G and MAC: 10%; L = 3%; video signal in accordance with unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin 29)

Vision IF ampliﬁer (pins 1, 2, 4 and 5)

i VIF(rms)

i max(rms)

∆V

o(int)

IFcr

i(diff)

1,2,4,5

ct IF

=25°C; see Table 1 for input frequencies and carrier ratios; input level V

amb

“CCIR, line 17”

; measurements taken in Fig.13;

i IF 1-2,4-5

= 10 mV RMS value

supply voltage note 1 4.5 5 5.5 V supply current 93 109 125 mA

input signal voltage sensitivity (RMS value)

maximum input signal voltage (RMS value)

internal IF amplitude difference between picture and sound carrier

B/G standard;

−1 dB video at output B/G standard;

+1 dB video at output within AGC range

B/G standard; ∆f = 5.5 MHz

MAC standard;

− 60 100 µV

120 200 − mV

− 0.7 1 dB

− 1.0 1.3 dB

∆f = 8.4 MHz

IF gain control range see Fig.3 65 70 − dB differential input resistance note 2; activated input 1.7 2.2 2.7 kΩ differential input capacitance note 2; activated input 1.2 1.7 2.5 pF DC input voltage note 2; activated input − 3.4 − V input resistance to ground note 2; not activated input − 1.1 − kΩ DC input voltage note 2; not activated input − 0.2 − V crosstalk attenuation of IF

notes 2 and 3 55 60 − dB input switch at pins 1, 2, 4 and 5

True synchronous video demodulator; note 4 f

VCO(max)

maximum oscillator

f=2f

frequency for carrier regeneration

∆f

/∆T oscillator drift as a function

osc

of temperature

0 ref(rms)

oscillator voltage swing at

oscillator is free-running;

= 0; note 5

AFC

pins 24 and 25 (RMS value)

PC CR

picture carrier capture range B/G, L and MAC standard ±1.4 ±1.8 − MHz

L accent standard;

= 33.9 MHz; R11= 5.6 kΩ

PC(fr)

PC(alg)CR

picture carrier frequency (free-running) accuracy

L accent alignment

L accent standard;

fPC= 33.9 MHz; R11= 5.6 kΩ

=0 ±400 ±600 − kHz

AFC

frequency range

acq

acquisition time BL = 75 kHz; note 6 −−30 ms

1998 Feb 11 9

125 130 − MHz

−−±20 × 10−6K

−1

70 100 130 mV

±0.9 ±1.2 − MHz

−±200 ±400 kHz

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF

TDA9815

and dual FM-PLL/AM demodulator

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

i VIF(rms)

Composite video ampliﬁer (pin 21; sound carrier off)

o video(p-p)

V/S ratio between video

∆V

o(video)

21(sync)

21(clu)

21(cll)

o,21

int 21

21 max(sink)

21 max(source)

−1

−3

H(sup)

PSRR power supply ripple rejection

VIF input signal voltage

maximum IF gain; note 7 − 30 70 µV sensitivity for PLL to be locked (RMS value; pins 1, 2, 4 and 5)

output signal voltage

see Fig.8 0.88 1.0 1.12 V (peak-to-peak value)

1.9 2.33 3.0 − (black-to-white) and sync level

output signal voltage difference

difference between B/G and L standard

−−±12 %

sync voltage level B/G and L standard − 1.5 − V upper video clipping voltage

VP− 1.1 VP− 1 − V

level lower video clipping voltage

− 0.7 0.9 V level

output resistance note 2 −−10 Ω internal DC bias current for

2.2 3.0 − mA emitter-follower

maximum AC and DCoutput

1.6 −− mA sink current

maximum AC and DCoutput

2.9 −− mA source current

−1 dB video bandwidth B/G and L standard;

56− MHz CL< 50 pF; RL> 1kΩ; AC load

−3 dB video bandwidth B/G and L standard;

78− MHz CL< 50 pF; RL> 1kΩ; AC load

suppression of video signal harmonics

CL< 50 pF; RL> 1kΩ; AC load; note 8a

35 40 − dB

video signal; grey level;

at pin 21

see Fig.11

B/G standard 32 35 − dB L standard 26 30 − dB

CVBS buffer ampliﬁer (only) and noise clipper (pins 10 and 22)

i,22

I,22

10(clu)

input resistance note 2 2.6 3.3 4.0 kΩ input capacitance note 2 1.4 2 3.0 pF DC input voltage 1.4 1.7 2.0 V voltage gain B/G and L standard; note 9 6.5 7 7.5 dB upper video clipping voltage

level

1998 Feb 11 10

3.9 4.0 − V

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF

TDA9815

and dual FM-PLL/AM demodulator

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

10(cll)

o,10

int 10

o,10 max(sink)

o,10 max(source)

−1

−3

Measurements from IF input to CVBS output (pin 10; 330 Ω between pins 21 and 22, sound carrier off)

o CVBS(p-p)

o CVBS(sync)

o CVBS(peak)

∆V

o(blB/G)

∆V

o(blL)

diff

−1

−3

S/N (W) weighted signal-to-noise

S/N unweighted signal-to-noise

lower video clipping voltage

− 1.0 1.1 V

level output resistance note 2 −−10 Ω DC internal bias current for

2.0 2.5 − mA

emitter-follower maximum AC and DCoutput

1.4 −− mA

sink current maximum AC and DCoutput

2.4 −− mA

source current

−1 dB video bandwidth B/G and L standard;

8.4 11 − MHz CL< 20 pF; RL> 1kΩ; AC load

−3 dB video bandwidth B/G and L standard;

11 14 − MHz CL< 20 pF; RL> 1kΩ; AC load

CVBS output signal voltage

note 9 1.7 2.0 2.3 V

on pin 10 (peak-to-peak value)

sync voltage level B/G standard − 1.35 − V

L standard − 1.35 − V

peak voltage level MAC standard − 1.35 − V deviation of CVBS output

signal voltage at B/G black level tilt in

50 dB gain control −−0.5 dB 30 dB gain control −−0.1 dB gain variation; note 10 −−1%

B/G standard black level tilt for worst case

in L standard

picture carrier modulated by test line (VITS) only; gain

−−1.9 %

variation; note 10

differential gain differential phase

“CCIR, line 330” “CCIR, line 330”

− 25 %

− 1 2 deg

−1 dB video bandwidth CL< 20 pF; RL> 1kΩ;

AC load

B/G and L standard 5 6 − MHz MAC standard 8.4 11 − MHz

−3 dB video bandwidth CL< 20 pF; RL> 1kΩ; AC load

B/G and L standard 7 8 − MHz MAC standard 11 14 − MHz

see Fig.5 and note 11 56 60 − dB

ratio

see Fig.5 and note 11 49 53 − dB

ratio

1998 Feb 11 11

Philips Semiconductors Product speciﬁcation

Multistandard/MAC VIF-PLL with QSS-IF

TDA9815

and dual FM-PLL/AM demodulator

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IMα

1.1

IMα

3.3

pc(rms)

∆f

unwanted(p-p)

∆ϕ robustness for modulator

H(sup)

H(spur)

PSRR power supply ripple rejection

intermodulation attenuation at ‘blue’

intermodulation attenuation at ‘yellow’

intermodulation attenuation at ‘blue’

intermodulation attenuation at ‘yellow’

residual picture carrier (RMS value)

f = 1.1 MHz; see Fig.6 and note 12

f = 3.3 MHz; see Fig.6 and note 12

fundamental wave and harmonics

58 64 − dB

60 66 − dB

58 64 − dB

59 65 − dB

B/G and L standard − 25 mV MAC standard − 520 mV

robustness for unwanted frequency deviation of picture carrier

L standard; residual carrier: 3%; serration pulses: 50%; note 2

−−12 kHz

(peak-to-peak value)

imbalance

L standard; residual carrier: 0%;

−−3%

serration pulses: 50%; note 2

suppression of video signal

note 8a 35 40 − dB

harmonics spurious elements note 8b 40 −− dB

video signal; grey level;

at pin 10

see Fig.11

B/G standard 25 28 − dB L standard 20 23 − dB

VIF-AGC detector (pin 28)

charging current B/G, L and MAC standard;

note 10

additional charging current L standard in event of

missing VITS pulses and no white video content

discharging current B/G standard 15 20 25 µA

normal mode L and MAC standard

fast mode L and MAC standard

resp

AGC response to an increasing VIF step

AGC response to a decreasing VIF step

B/G, L and MAC standard; note 13

B/G standard − 2.2 3.5 ms/dB fast mode L and

MAC standard normal mode L and

MAC standard; note 13

1998 Feb 11 12

0.75 1 1.25 mA

1.9 2.5 3.1 µA

225 300 375 nA

30 40 50 µA

− 0.05 0.1 ms/dB

− 1.1 1.8 ms/dB

− 150 240 ms/dB

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