Philips TDA9813T-V2, TDA9813T-V3, TDA9813T-V4 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA9813T

VIF-PLL with QSS-IF and dual FM-PLL demodulator

Product specification

1999 Sep 16

Supersedes data of 1995 Oct 03

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

FEATURES

∙5 V supply voltage

∙Gain controlled wide band VIF amplifier (AC-coupled)

∙True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)

∙Separate video amplifier for sound trap buffering with high video bandwidth

∙VIF-AGC detector for gain control, operating as peak sync detector

∙Tuner AGC with adjustable takeover point (TOP)

∙AFC detector without extra reference circuit

∙AC-coupled limiter amplifier for sound intercarrier signal

∙Two alignment-free FM-PLL demodulators with high linearity

∙SIF input for single reference QSS mode (PLL controlled); SIF-AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode

∙Stabilizer circuit for ripple rejection and to achieve constant output signals

∙ESD protection for all pins.

ORDERING INFORMATION

GENERAL DESCRIPTION

The TDA9813T is an integrated circuit for vision IF signal processing and sound dual FM demodulation, with single reference QSS-IF in TV and VCR sets. For negative modulation standards only.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	TDA9813T	SO28	plastic small outline package; 28 leads; body width 7.5 mm	SOT136-1

1999 Sep 16

2

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VP	supply voltage		4.5	5	5.5	V
IP	supply current		93	109	125	mA
Vi VIF(rms)	vision IF input signal voltage sensitivity	−1 dB video at output	−	60	100	μV
	(RMS value)
Vo CVBS(p-p)	CVBS output signal voltage		1.7	2.0	2.3	V
	(peak-to-peak value)
B−3	−3 dB video bandwidth on pin 8	CL < 20 pF; RL > 1 kΩ; AC load	7	8	−	MHz
S/N(W)	weighted signal-to-noise ratio for video		56	60	−	dB
IMα1.1	intermodulation attenuation at ‘blue’	f = 1.1 MHz	58	64	−	dB
IMα3.3	intermodulation attenuation at ‘blue’	f = 3.3 MHz	58	64	−	dB
αH(sup)	suppression of harmonics in video		35	40	−	dB
	signal
Vi SIF(rms)	sound IF input signal voltage	−3 dB at intercarrier output	−	30	70	μV
	sensitivity (RMS value)
Vo(rms)	audio output signal voltage for FM	B/G standard; 54% modulation	−	0.5	−	V
	(RMS value)
THD	total harmonic distortion	54% modulation	−	0.15	0.5	%
S/N(W)	weighted signal-to-noise ratio	54% modulation	−	60	−	dB

1999 Sep 16

3

_

16 Sep 1999

TOP

tuner

2 x f PC

DIAGRAM BLOCK

demodulator PLL-FM dual

and IF-QSS with PLL-VIF

Semiconductors Philips

CAGC

loop

AGC

filter

AFC

n.c.

25

3

4

16

5

22

21

20

TUNER AND VIF-AGC

VCO TWD

AFC DETECTOR

18

video

2

1 V (p-p)

VIF

1

VIF AMPLIFIER

FPLL

VIDEO DEMODULATOR

AND AMPLIFIER

8

CVBS

VIDEO

19

2 V (p-p)

4

BUFFER

Vi(vid)

28

TDA9813T

13

SIF

SIF

SINGLE REFERENCE

27

AMPLIFIER

MIXER

FM DETECTOR (PLL)

10

AF1

AF AMPLIFIER

INTERNAL VOLTAGE

SIF-AGC

FM DETECTOR (PLL)

11

AF2

STABILIZER

AF AMPLIFIER

26

24

23

7

6

9

17

15

14

12

1/2 VP

5.5

MHA037

n.c.

C AGC

n.c.

5.74

5 V

SIF

Fig.1

Block diagram.

TDA9813T

specification Product

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

PINNING

SYMBOL	PIN	DESCRIPTION
Vi VIF1	1	VIF differential input signal voltage 1
Vi VIF2	2	VIF differential input signal voltage 2
n.c.	3	not connected
TADJ	4	tuner AGC takeover adjust (TOP)
TPLL	5	PLL loop filter
CSAGC	6	SIF-AGC capacitor
n.c.	7	not connected
Vo CVBS	8	CVBS output signal voltage
n.c.	9	not connected
Vo AF1	10	audio voltage frequency output 1
Vo AF2	11	audio voltage frequency output 2
CDEC2	12	decoupling capacitor 2
CDEC1	13	decoupling capacitor 1
Vi FM2	14	sound intercarrier input voltage 2
Vi FM1	15	sound intercarrier input voltage 1
TAGC	16	tuner AGC output
Vo QSS	17	single reference QSS output voltage
Vo(vid)	18	composite video output voltage
Vi(vid)	19	video buffer input voltage
AFC	20	AFC output
VCO1	21	VCO1 reference circuit for 2fPC
VCO2	22	VCO2 reference circuit for 2fPC
Cref	23	1¤2VP reference capacitor
GND	24	ground
CVAGC	25	VIF-AGC capacitor
VP	26	supply voltage
Vi SIF1	27	SIF differential input signal voltage 1
Vi SIF2	28	SIF differential input signal voltage 2

handbook, halfpageVi VIF1					Vi SIF2
		1		28
Vi VIF2					Vi SIF1
		2		27
	n.c.				VP
		3		26
					CVAGC
	TADJ	4		25
	TPLL
		5		24	GND
CSAGC					Cref
		6		23
	n.c.	7	TDA9813T	22	VCO2
Vo CVBS
		8		21	VCO1
	n.c.	9		20	AFC
Vo AF1					Vi(vid)
		10		19
Vo AF2					Vo(vid)
		11		18
CDEC2					Vo QSS
		12		17
CDEC1
		13		16	TAGC
					Vi FM1
V	i FM2	14		15
			MHA038

Fig.2 Pin configuration.

1999 Sep 16

5

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

FUNCTIONAL DESCRIPTION

The integrated circuit comprises the functional blocks as shown in Fig.1:

·Vision IF amplifier

·Tuner and VIF-AGC

·Frequency Phase Locked Loop (FPLL) detector

·VCO, Travelling Wave Divider (TWD) and AFC

·Video demodulator and amplifier

·Video buffer

·SIF amplifier and SIF-AGC

·Single reference Quasi Split Sound (QSS) mixer

·FM-PLL demodulator

·Internal voltage stabilizer and 1¤2VP reference.

Vision IF amplifier

The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration.

Tuner and VIF-AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (open-collector output).

The tuner AGC takeover point can be adjusted. This allows the tuner and the SAW filter to be matched to achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitor to the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level.

Therefore the sync level of the video signal is detected.

Frequency Phase Locked Loop (FPLL) detector

The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency.

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the PC frequency. The VCO is controlled by two integrated variable capacitors.

The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the frequency-phase detector (FPLL) and fed via the loop filter to the first variable capacitor. This control voltage is amplified and additionally converted into a current which represents the AFC output signal. At centre frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency.

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the travelling wave divider output.

The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics. The video output signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is used. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted for operating in combination with ceramic sound traps. The output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.

SIF amplifier and SIF-AGC

The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration.

The SIF-AGC detector is related to the SIF input signals (average level of FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the single reference QSS mixer.

1999 Sep 16

6

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO).

The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 17. With this system a high performance hi-fi stereo sound processing can be achieved.

FM-PLL demodulator

Each FM-PLL demodulator consists of a limiter, an FM-PLL and an AF amplifier. The limiter provides the amplification and limitation of the FM sound intercarrier signal before demodulation. The result is high sensitivity and AM suppression. The amplifier consists of 7 stages which are internally AC-coupled in order to minimize the DC offset and to save pins for DC decoupling.

The second limiter is extended with an additional level detector consisting of a rectifier and a comparator.

By means of this the AF2 signal is set to mute and the PLL VCO is switched off, if the intercarrier signal at pin 14 is below 1 mV (RMS) in order to avoid false identification of a stereo decoder. It should be noted that noise at pin 14 disables the mute state (at low SIF input signal), but this will not lead to false identification. This ‘auto-mute’ function can be disabled by connecting a 5.6 kW resistor from

pin 14 to VP (see Fig.11).

Furthermore the AF output signals can be muted by connecting a resistor between the limiter inputs pin 14 or pin 15 and ground.

The FM-PLL consists of an integrated relaxation oscillator, an integrated loop filter and a phase detector.

The oscillator is locked to the FM intercarrier signal, output from the limiter. As a result of locking, the oscillator frequency tracks with the modulation of the input signal and the oscillator control voltage is superimposed by the AF voltage. The FM-PLL operates as an FM demodulator.

The AF amplifier consists of two parts:

1.The AF preamplifier for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator, by principle a small output signal, is amplified by approximately 33 dB. The low-pass characteristic of the amplifier reduces the harmonics of the intercarrier signal at the sound output terminal. An additional DC control circuit is implemented to keep the DC level constant, independent of process spread.

2.The AF output amplifier (10 dB) provides the required output level by a rail-to-rail output stage. This amplifier makes use of an input selector for switching to FM or mute state, controlled by the mute switching voltage.

Internal voltage stabilizer and 1¤2VP reference

The band gap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage.

For all audio output signals the constant reference voltage cannot be used because large output signals are required. Therefore these signals refer to half the supply voltage to achieve a symmetrical headroom, especially for the rail-to-rail output stage. For ripple and noise attenuation the 1¤2VP voltage has to be filtered via a low-pass filter by using an external capacitor together with an integrated resistor (fg = 5 Hz). For a fast setting to 1¤2VP an internal start-up circuit is added.

1999 Sep 16

7

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VP	supply voltage (pin 26)	maximum chip temperature	0	5.5	V
		of 125 °C; note 1
Vn	voltage at pins 1 to 7, 9 to 16, 19, 20 and		0	VP	V
	23 to 28
ts(max)	maximum short-circuit time		−	10	s
V16	tuner AGC output voltage		0	13.2	V
Tstg	storage temperature		−25	+150	°C
Tamb	ambient temperature		−20	+70	°C
Ves	electrostatic handling voltage	note 2	−300	+300	V

Notes

1.IP = 125 mA; Tamb = 70 °C; Rth(j-a) = 80 K/W.

2.Machine model class B (L = 2.5 μH).

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	VALUE	UNIT
Rth(j-a)	thermal resistance from junction to ambient	in free air	80	K/W

1999 Sep 16

8

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

CHARACTERISTICS

VP = 5 V; Tamb = 25 °C; see Table 1 for input frequencies and carrier ratios (B/G standard); input level

Vi IF 1-2 = 10 mV RMS value (sync-level); video modulation DSB; residual carrier: 10%; video signal in accordance with “CCIR, line 17”; measurements taken in Fig.11; unless otherwise specified.

	SYMBOL		PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply (pin 26)
VP			supply voltage	note 1	4.5	5	5.5	V
IP			supply current		93	109	125	mA
Vision IF amplifier (pins 1 and 2)
Vi VIF(rms)			input signal voltage	−1 dB video at output	−	60	100	μV
			sensitivity (RMS value)
Vi max(rms)			maximum input signal	+1 dB video at output	120	200	−	mV
			voltage (RMS value)
Vo(int)			internal IF amplitude	within AGC range;	−	0.7	1	dB
			difference between picture	f = 5.5 MHz
			and sound carrier
GIFcr			IF gain control range	see Fig.3	65	70	−	dB
Ri(diff)			differential input resistance	note 2	1.7	2.2	2.7	kΩ
Ci(diff)			differential input capacitance	note 2	1.2	1.7	2.5	pF
V1,2			DC input voltage	note 2	−	3.4	−	V
True synchronous video demodulator; note 3
fVCO(max)			maximum oscillator	f = 2fPC	125	130	−	MHz
			frequency for carrier
			regeneration
f		/ T	oscillator drift as a function	oscillator is free-running;	−	−	±20 × 10−6	K−1
	osc		of temperature	IAFC = 0; note 4
Vo ref(rms)			oscillator voltage swing at		70	100	130	mV
			pins 21 and 22 (RMS value)
fPC CR			picture carrier capture range		±1.4	±1.8	−	MHz
tacq			acquisition time	BL = 75 kHz; note 5	−	−	30	ms
Vi VIF(rms)			VIF input signal voltage	maximum IF gain; note 6	−	30	70	μV
			sensitivity for PLL to be
			locked (RMS value; pins 1
			and 2)
Composite video amplifier (pin 18; sound carrier off)
Vo video(p-p)			output signal voltage	see Fig.8	0.88	1.0	1.12	V
			(peak-to-peak value)
V/S			ratio between video		1.9	2.33	3.0	−
			(black-to-white) and
			sync level
V18(sync)			sync voltage level		−	1.5	−	V
V18(clu)			upper video clipping voltage		VP − 1.1	VP − 1	−	V
			level

1999 Sep 16

9

Philips Semiconductors	Product specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
V18(cll)	lower video clipping voltage		−	0.7	0.9	V
	level
Ro,18	output resistance	note 2	−	−	10	Ω
Iint 18	internal DC bias current for		2.2	3.0	−	mA
	emitter-follower
I18 max(sink)	maximum AC and DC output		1.6	−	−	mA
	sink current
I18 max(source)	maximum AC and DC output		2.9	−	−	mA
	source current
B−1	−1 dB video bandwidth	CL < 50 pF; RL > 1 kΩ;	5	6	−	MHz
		AC load
B−3	−3 dB video bandwidth	CL < 50 pF; RL > 1 kΩ;	7	8	−	MHz
		AC load
αH(sup)	suppression of video signal	CL < 50 pF; RL > 1 kΩ;	35	40	−	dB
	harmonics	AC load; note 7a
PSRR	power supply ripple rejection	video signal; grey level;	32	35	−	dB
	at pin 18	see Fig.9
CVBS buffer amplifier (only) and noise clipper (pins 8 and 19)
Ri,19	input resistance	note 2	2.6	3.3	4.0	kΩ
Ci,19	input capacitance	note 2	1.4	2	3.0	pF
VI,19	DC input voltage		1.4	1.7	2.0	V
Gv	voltage gain	note 8	6.5	7	7.5	dB
V8(clu)	upper video clipping voltage		3.9	4.0	−	V
	level
V8(cll)	lower video clipping voltage		−	1.0	1.1	V
	level
Ro,8	output resistance	note 2	−	−	10	Ω
Iint 8	DC internal bias current for		2.0	2.5	−	mA
	emitter-follower
Io,8 max(sink)	maximum AC and DC output		1.4	−	−	mA
	sink current
Io,10 max(source)	maximum AC and DC output		2.4	−	−	mA
	source current
B−1	−1 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	8.4	11	−	MHz
		AC load
B−3	−3 dB video bandwidth	CL < 20 pF; RL > 1 kΩ;	11	14	−	MHz
		AC load
Measurements from IF input to CVBS output (pin 8; 330 Ω between pins 18 and 19, sound carrier off)
Vo CVBS(p-p)	CVBS output signal voltage	note 8	1.7	2.0	2.3	V
	on pin 8
	(peak-to-peak value)
Vo CVBS(sync)	sync voltage level		−	1.35	−	V

1999 Sep 16

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