Philips tda9813t DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA9813T

VIF-PLL with QSS-IF and
dual FM-PLL demodulator

Preliminary specification
File under Integrated Circuits, IC02

1995 Oct 03

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

FEATURES

• 5 V supply voltage

• Gain controlled wide band VIF-amplifier (AC-coupled)

• True synchronous demodulation with active carrier

regeneration (very linear demodulation, good
intermodulation figures, reduced harmonics, excellent
pulse response)

• Separate video amplifier for sound trap buffering with
high video bandwidth

• VIF AGC detector for gain control, operating as peak
sync detector

• Tuner AGC with adjustable takeover point (TOP)

• AFC detector without extra reference circuit

• AC-coupled limiter amplifier for sound intercarrier signal

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

I

P

V

i VIF(rms)

supply voltage 4.5 5 5.5 V
supply current 93 109 125 mA
vision IF input signal voltage

sensitivity (RMS value)

V

o CVBS(p-p)

CVBS output signal voltage
(peak-to-peak value)

B

−3

−3 dB video bandwidth on pin CVBS B/G standard; CL< 20 pF;

S/N (W) weighted signal-to-noise ratio for

video
IM
IM

α

H(sup)

α1.1
α3.3

intermodulation attenuation at ‘blue’ f = 1.1 MHz 58 64 − dB

intermodulation attenuation at ‘blue’ f = 3.3 MHz 58 64 − dB

suppression of harmonics in video

signal
V

i SIF(rms)

sound IF input signal voltage

sensitivity (RMS value)
V

o(rms)

audio output signal voltage for FM

(RMS value)
THD total harmonic distortion 54% modulation − 0.15 0.5 %
S/N (W) weighted signal-to-noise ratio 54% modulation − 60 − dB

• Two alignment-free FM-PLL demodulators with high
linearity

• SIF input for single reference QSS mode (PLL
controlled); SIF AGC detector for gain controlled SIF
amplifier; single reference QSS mixer able to operate in
high performance single reference QSS mode

• Stabilizer circuit for ripple rejection and to achieve
constant output signals.

GENERAL DESCRIPTION

The TDA9813T is an integrated circuit for vision IF signal
processing and sound dual FM demodulation, with single
reference QSS-IF in TV and VCR sets. For negative
modulation standards only.

−1 dB video at output − 60 100 µV

1.7 2.0 2.3 V

78−MHz

> 1kΩ; AC load

R

L

56 60 − dB

35 40 − dB

−3 dB at intercarrier output − 30 70 µV

B/G standard;

− 0.5 − V

54% modulation

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA9813T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1995 Oct 03 2

PACKAGE

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and
dual FM-PLL demodulator

BLOCK DIAGRAM

20212251625 43

AFC

PC

2 x f

video

1 V (p-p)

18

AFC DETECTOR

VIDEO DEMODULATOR

(vid)

CVBS

Vi

2 V (p-p)

8

19

VIDEO

BUFFER

AND AMPLIFIER

13

10

FM DETECTOR (PLL)

TDA9813T

AF1

11

AF AMPLIFIER

FM DETECTOR (PLL)

AF2

AF AMPLIFIER

14 12

MHA037

5.5

5.74

TDA9813T

SIF

andbook, full pagewidth

TOP

loop

tuner

AGC

C

filter

AGC

n.c.

VCO TWD

FPLL

TUNER AND VIF-AGC

VIF AMPLIFIER

2

1

VIF

MIXER

SINGLE REFERENCE

SIF

AMPLIFIER

28

27

SIF

917 15

n.c.n.c.

AGC

C

SIF-AGC

P

V
1/2

STABILIZER

26 24 23 7 6

INTERNAL VOLTAGE

Fig.1 Block diagram.

5 V

1995 Oct 03 3

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and
dual FM-PLL demodulator

PINNING

SYMBOL PIN DESCRIPTION

V

i VIF1

V

i VIF2

n.c. 3 not connected
TADJ 4 tuner AGC takeover adjust (TOP)
T

PLL

C

SAGC

n.c. 7 not connected
V

o CVBS

n.c. 9 not connected
V

o AF1

V

o AF2

C

DEC2

C

DEC1

V

i FM2

V

i FM1

TAGC 16 tuner AGC output
V

o QSS

V

o(vid)

V

i(vid)

AFC 20 AFC output
VCO1 21 VCO1 reference circuit for 2f
VCO2 22 VCO2 reference circuit for 2f
C

ref

GND 24 ground
C

VAGC

V

P

V

i SIF1

V

i SIF2

1 VIF differential input signal voltage 1
2 VIF differential input signal voltage 2

5 PLL loop filter
6 SIF AGC capacitor

8 CVBS output signal voltage

10 audio voltage frequency output 1
11 audio voltage frequency output 2
12 decoupling capacitor 2
13 decoupling capacitor 1
14 sound intercarrier input voltage 2
15 sound intercarrier input voltage 1

17 single reference QSS output voltage
18 composite video output voltage
19 video buffer input voltage

PC
PC

231⁄2VP reference capacitor

25 VIF AGC capacitor
26 supply voltage
27 SIF differential input signal voltage 1
28 SIF differential input signal voltage 2

handbook, halfpage

V
V

C

V

o CVBS

V
V
C
C

V

i VIF1
i VIF2

n.c.

TADJ

T

PLL

SAGC

n.c.

n.c.

o AF1
o AF2
DEC2
DEC1

i FM2

1
2
3
4
5
6
7

TDA9813T

8

9
10
11
12
13
14

Fig.2 Pin configuration.

MHA038

TDA9813T

V

28

i SIF2

V

27

i SIF1

V

26

P

C

25

VAGC

24

GND
C

23

ref

22

VCO2

21

VCO1

20

AFC
V

19

i(vid)

V

18

o(vid)

V

17

o QSS

16

TAGC
V

15

i FM1

1995 Oct 03 4

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and
dual FM-PLL demodulator

FUNCTIONAL DESCRIPTION
Vision IF amplifier

The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage
comprises a feedback network controlled by
emitter degeneration.

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF
control signal, and is fed to the tuner AGC to generate the
tuner AGC output current (open-collector output). The
tuner AGC takeover point can be adjusted. This allows the
tuner and the SWIF filter to be matched to achieve the
optimum IF input level.

The AGC detector charges/discharges the AGC capacitor
to the required voltage for setting of VIF and tuner gain in
order to keep the video signal at a constant level.
Therefore the sync level of the video signal is detected.

Frequency Phase Locked Loop (FPLL) detector

TDA9813T

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The vision
IF input signal is multiplied with the ‘in phase’ signal of the
travelling wave divider output.

The demodulator output signal is fed via an integrated
low-pass filter for attenuation of the carrier harmonics to
the video amplifier. The video amplifier is realized by an
operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an
attenuation of the carrier harmonics. The video output
signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational
amplifier with internal feedback is used. This amplifier is
featured with a high bandwidth and 7 dB gain. The input
impedance is adapted for operating in combination with
ceramic sound traps. The output stage delivers a nominal
2 V (p-p) positive video signal. Noise clipping is provided.

The VIF-amplifier output signal is fed into a frequency
detector and into a phase detector via a limiting amplifier.
During acquisition the frequency detector produces a DC
current proportional to the frequency difference between
the input and the VCO signal. After frequency lock-in the
phase detector produces a DC current proportional to the
phase difference between the VCO and the input signal.
The DC current of either frequency detector or phase
detector is converted into a DC voltage via the loop filter,
which controls the VCO frequency.

VCO, travelling wave divider and AFC

The VCO operates with a resonance circuit (with L and C
in parallel) at double the PC frequency. The VCO is
controlled by two integrated variable capacitors. The
control voltage required to tune the VCO from its
free-running frequency to actually double the PC
frequency is generated by the Frequency-Phase detector
and fed via the loop filter to the first variable capacitor
(FPLL). This control voltage is amplified and additionally
converted into a current which represents the AFC output
signal. At centre frequency the AFC output current is equal
to zero.

The oscillator signal is divided-by-two with a Travelling
Wave Divider (TWD) which generates two differential
output signals with a 90 degree phase difference
independent of the frequency.

SIF amplifier and AGC

The sound IF amplifier consists of two AC-coupled
differential amplifier stages. Each differential stage
comprises a controlled feedback network provided by
emitter degeneration.

The SIF AGC detector is related to the SIF input signals
(average level of FM carriers) and controls the SIF
amplifier to provide a constant SIF signal to the single
reference QSS mixer.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier.
The SIF amplifier output signal is fed to the single
reference QSS mixer and converted to intercarrier
frequency by the regenerated picture carrier (VCO). The
mixer output signal is fed via a high-pass for attenuation of
the video signal components to the output pin 17. With this
system a high performance hi-fi stereo sound processing
can be achieved.

1995 Oct 03 5

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and
dual FM-PLL demodulator

FM detectors

Each FM detector consists of a limiter, an FM-PLL and an
AF amplifier. The limiter provides the amplification and
limitation of the FM sound intercarrier signal before
demodulation. The result is high sensitivity and AM
suppression. The amplifier consists of 7 stages which are
internally AC-coupled in order to minimize the DC offset
and to save pins for DC decoupling.

The second limiter is extended with an additional level
detector consisting of a rectifier and a comparator. By
means of this the AF2 signal is set to mute and the
PLL VCO is switched off, if the intercarrier signal at pin 14
is below 1 mV (RMS) in order to avoid false identification
of a stereo decoder. Note that noise at pin 14 disables the
mute state (at low SIF input signal), but this will not lead to
false identification. This ‘auto-mute’ function can be
disabled by connecting a 5.6 kΩ resistor from
pin 14 to +V

Furthermore the AF output signals can be muted by
connecting a resistor between the limiter inputs pin 14 or
pin 15 and ground.

(see Fig.11).

P

TDA9813T

1

Internal voltage stabilizer and

The bandgap circuit internally generates a voltage of
approximately 1.25 V, independent of supply voltage and
temperature. A voltage regulator circuit, connected to this
voltage, produces a constant voltage of 3.6 V which is
used as an internal reference voltage.

For all audio output signals the constant reference voltage
cannot be used because large output signals are required.
Therefore these signals refer to half the supply voltage to
achieve a symmetrical headroom, especially for the
rail-to-rail output stage. For ripple and noise attenuation

1

the

⁄2VP voltage has to be filtered via a low-pass filter by

using an external capacitor together with an integrated
resistor (fg= 5 Hz). For a fast setting to 1⁄2VP an internal
start-up circuit is added.

⁄2VP-reference

The FM-PLL consists of an integrated relaxation oscillator,
an integrated loop filter and a phase detector. The
oscillator is locked to the FM intercarrier signal, output
from the limiter. As a result of locking, the oscillator
frequency tracks with the modulation of the input signal
and the oscillator control voltage is superimposed by the
AF voltage. The FM-PLL operates as an FM-demodulator.

The AF amplifier consists of two parts:

1. The AF preamplifier for FM sound is an operational
amplifier with internal feedback, high gain and high
common mode rejection. The AF voltage from the PLL
demodulator, by principle a small output signal, is
amplified by approximately 33 dB. The low-pass
characteristic of the amplifier reduces the harmonics of
the intercarrier signal at the sound output terminal. An
additional DC control circuit is implemented to keep
the DC level constant, independent of process spread.

2. The AF output amplifier (10 dB) provides the required
output level by a rail-to-rail output stage. This amplifier
makes use of an input selector for switching to FM or
mute state, controlled by the mute switching voltage.

1995 Oct 03 6

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

i

t

s(max)

V

19

T

stg

T

amb

V

es

Notes

1. I

P

2. Machine model class B.

supply voltage (pin 26) maximum chip temperature of

0 5.5 V

125 °C; note 1

voltage at pins 1 to 7, 9 to 16, 19, 20 and

0V

23 to 28
maximum short-circuit time − 10 s
tuner AGC output voltage 0 13.2 V
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
electrostatic handling voltage note 2 −300 +300 V

= 125 mA; T

=70°C; R

amb

th j-a

= 80 K/W.

P

V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 80 K/W

1995 Oct 03 7

Philips Semiconductors Preliminary specification

VIF-PLL with QSS-IF and

TDA9813T

dual FM-PLL demodulator

CHARACTERISTICS

VP=5V; T
video modulation DSB; residual carrier: 10%; video signal in accordance with
Fig.11; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin 26)

V

P

I

P

Vision IF amplifier (pins 1 and 2)

V

i VIF(rms)

V

i max(rms)

∆V

o(int)

G

IFcr

R

i(diff)

C

i(diff)

V

1, 2

True synchronous video demodulator; note 3
f

VCO(max)

/∆T oscillator drift as a function

∆f

osc

V

0 ref(rms)

f

pcCR

t

acq

V

i VIF(rms)

I

FPLL(offset)

=25°C; see Table 1 for input frequencies and level;input level V

amb

supply voltage note 1 4.5 5 5.5 V
supply current 93 109 125 mA

input signal voltage
sensitivity (RMS value)

maximum input signal
voltage (RMS value)

internal IF amplitude
difference between picture
and sound carrier

B/G standard;

−1 dB video at output
B/G standard;

+1 dB video at output
within AGC range;

B/G standard;

∆f = 5.5 MHz
IF gain control range see Fig.3 65 70 − dB
differential input resistance note 2 1.7 2.2 2.7 kΩ
differential input capacitance 1.2 1.7 2.5 pF
DC input voltage − 3.4 − V

maximum oscillator

f=2f

PC

frequency for carrier
regeneration

oscillator is free-running;
of temperature

oscillator voltage swing at

I

= 0; note 4

AFC

B/G standard 70 100 130 mV
pins 21 and 22 (RMS value)

picture carrier capture

B/G standard ±1.5 ±2.0 − MHz
frequency range

acquisition time BL = 180 kHz; note 5 −−30 ms
VIF input signal voltage

maximum IF gain; note 6 − 30 70 µV
sensitivity for PLL to be
locked (RMS value;
pins 1 and 2)

FPLL offset current at pin 5 note 7 −−±4.5 µA

= 10 mV RMS value (sync-level);

iIF1,2

“CCIR, line 17”

; measurements taken in

− 60 100 µV

120 200 − mV

− 0.7 1 dB

125 130 − MHz

−−±20 ppm/K

1995 Oct 03 8