Philips TDA9810T-V2, TDA9810T-V1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA9810

Multistandard VIF-PLL with QSS-IF and AM demodulator

Product specification

1999 May 07

Supersedes data of 1997 Jun 19

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

FEATURES

∙5 V supply voltage

∙Gain controlled wide band Video Intermediate Frequency (VIF)-amplifier (AC-coupled)

∙True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)

∙Gated phase detector for L/L accent standard; robustness for over-modulation until 105%

∙Voltage Controlled Oscillator (VCO) frequency switchable between L and L accent (alignment external) picture carrier frequency

∙Separate video amplifier for sound trap buffering with high video bandwidth

∙VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for B/G (optional external AGC) and peak white detector for L; signal controlled reaction time for L

∙Tuner AGC with adjustable TakeOver Point (TOP)

∙AFC detector without extra reference circuit

∙SIF-input for single reference Quasi Split Sound (QSS) mode (Phase Locked Loop (PLL) controlled); Sound Intermediate Frequency (SIF) AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode

∙AM demodulator without extra reference circuit

∙AM mute (especially for NICAM)

∙Stabilizer circuit for ripple rejection and to achieve constant output signals.

GENERAL DESCRIPTION

The TDA9810 is an integrated circuit for multistandard vision IF signal processing and sound AM demodulation, with single reference QSS-IF in TV and VCR sets.

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	TDA9810	SDIP24	plastic shrink dual in-line package; 24 leads (400 mil)	SOT234-1
	TDA9810T	SO24	plastic small outline package; 24 leads; body width 7.5 mm	SOT137-1

1999 May 07

2

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VP	supply voltage		4.5	5	5.5	V
IP	supply current		77	90	103	mA
Vi(VIF)(rms)	vision IF input signal voltage sensitivity	−1 dB video at output	−	60	100	μV
	(RMS value)
Vo(CVBS)(p-p)	CVBS output signal voltage		1.7	2.0	2.3	V
	(peak-to-peak value)
B−3	−3 dB video bandwidth on pin CVBS	B/G and L standard;	7	8	−	MHz
		CL < 20 pF; RL > 1 kΩ;
		AC load
S/NW(video)	weighted signal-to-noise ratio for video		56	60	−	dB
αIM(1.1)	intermodulation attenuation at ‘blue’	f = 1.1 MHz	58	64	−	dB
αIM(3.3)	intermodulation attenuation at ‘blue’	f = 3.3 MHz	58	64	−	dB
αH(sup)	suppression of video signal harmonics		35	40	−	dB
Vi(SIF)(rms)	sound IF input signal voltage sensitivity	−3 dB at intercarrier output	−	30	70	μV
	(RMS value)
Vo(intercarrier)(rms)	IF intercarrier level (RMS value)	SC1 output signal	100	140	180	mV
		SCAM output signal	100	140	180	mV
		SCNICAM output signal	14	20	26	mV
Vo(AF)(rms)	AF output signal voltage (RMS value)	L standard;	−	500	−	mV
		54% modulation
THD	total harmonic distortion	54% modulation	−	0.5	1.0	%
S/NW	weighted signal-to-noise ratio	54% modulation	47	53	−	dB

1999 May 07

3

_

07 May 1999

TOP

tuner

2 x fpc

DIAGRAM BLOCK

demodulator AM

VIF Multistandard

Semiconductors Philips

AGC

L/L accent

CVAGC

CBL

RTOP

loop

filter

AFC

gating switch

-

14

21

15

3

16

4

18

19

17

PLL

TUNER AND VIF-AGC

VCO TWD

AFC DETECTOR

with

9

video

2

1 V (p-p)

QSS

VIF

1

VIF AMPLIFIER

FPLL

VIDEO DEMODULATOR

SAW

AND AMPLIFIER

VIDEO

12

CVBS

IF-

and

2 V (p-p)

BUFFER

13

4

Vi(vid)

23

SINGLE REFERENCE

SIF

SIF

TDA9810

24

MIXER AND

SAW

AMPLIFIER

AM DEMODULATOR

AF AMPLIFIER

6

AF/AM

AMPLIFIER SWITCH

INTERNAL VOLTAGE

SIF-AGC

STABILIZER

22

20

8

5

10

7

11

MHA713

standards

CSAGC

L/L accent

VP = +5 V

QSS

switch

GND

selection

AM mute

switch

intercarrier

switch

output

specification Product

Fig.1

Block diagram.

TDA9810

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

PINNING

SYMBOL	PIN	DESCRIPTION
Vi VIF1	1	VIF differential input signal voltage 1
Vi VIF2	2	VIF differential input signal voltage 2
TADJ	3	tuner AGC takeover point adjust
TPLL	4	PLL loop filter
CSAGC	5	SIF AGC capacitor
Vo AF	6	AM audio frequency output voltage
LSWI	7	L/L accent switch
STD	8	standard switch
Vo(vid)	9	composite video output voltage
Vo QSS	10	single reference QSS output voltage
MUTE	11	AM mute switch
Vo CVBS	12	CVBS output signal voltage

SYMBOL	PIN	DESCRIPTION
Vi(vid)	13	video buffer input voltage
LGATSWI	14	L/L accent gating switch
CBL	15	black level detector
TAGC	16	tuner AGC output
AFC	17	AFC output
VCO1	18	VCO1 reference circuit for 2fpc
VCO2	19	VCO2 reference circuit for 2fpc
GND	20	ground
CVAGC	21	VIF AGC capacitor
VP	22	supply voltage
Vi SIF1	23	SIF differential input signal voltage 1
Vi SIF2	24	SIF differential input signal voltage 2

					handbook, halfpage
handbook, halfpage				Vi SIF2	Vi VIF1						Vi SIF2
Vi VIF1	1		24			1				24
Vi VIF2	2		23	Vi SIF1	Vi VIF2	2				23	Vi SIF1
TADJ	3		22	VP	TADJ	3				22	VP
TPLL	4		21	CVAGC	TPLL	4				21	CVAGC
CSAGC	5		20	GND	CSAGC	5				20	GND
Vo AF	6	TDA9810	19	VCO2	Vo AF	6			TDA9810T	19	VCO2
LSWI	7		18	VCO1	LSWI	7				18	VCO1
STD	8		17	AFC	STD	8				17	AFC
Vo(vid)	9		16	TAGC	Vo(vid)	9				16	TAGC
Vo QSS 10			15	CBL	Vo QSS 10					15	CBL
MUTE 11			14	LGATSWI	MUTE 11					14	LGATSWI
Vo CVBS	12		13	Vi(vid)	Vo CVBS	12				13	Vi(vid)
		MHA712							MHA722

Fig.2 Pin configuration SDIP24 package.

Fig.3 Pin configuration SO24 package.

1999 May 07

5

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

FUNCTIONAL DESCRIPTION

Vision IF amplifier

The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration.

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (pin TAGC, open-collector output). The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitor to the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level.

Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected. In order to reduce the reaction time for positive modulation, where a very large time constant is needed, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step.

The additional level information is given by the black-level detector voltage.

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency. In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals. This mode can be switched off by the L/L accent gating switch.

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the Picture Carrier (PC) frequency.

The VCO is controlled by two integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the Frequency-Phase detector and fed via the loop filter to the first variable capacitor (FPLL). This control voltage is amplified and additionally converted into a current which represents the AFC output signal. The VCO centre frequency can be decreased (required for L accent standard) by activating an additional internal capacitor. This is achieved by using the L/L accent gating switch. In this event the second variable capacitor can be controlled by a variable resistor at the L/L accent gating switch for setting the VCO centre frequency to the required L accent value. At centre frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency.

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the travelling wave divider output. In the demodulator stage the video signal polarity can be switched in accordance with the TV standard.

The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics for B/G and

L standard. The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation. The video output signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of B/G and L standard. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted for operating in combination with ceramic sound traps. The output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.

1999 May 07

6

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

SIF amplifier and AGC

The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration.

The SIF AGC detector is related to the SIF input signals (average level of AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to ‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is also set to ‘fast’ controlled by the standard switch.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO).

The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 10. With this system a high performance hi-fi stereo sound processing can be achieved.

AM demodulator

The AM demodulator is realized by a multiplier.

The modulated SIF amplifier output signal is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the AF amplifier. This AM output signal can be muted by using the AM mute switch.

Internal voltage stabilizer and 1¤2VP-reference

The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage.

For all audio output signals the constant reference voltage cannot be used because large output signals are required. Therefore these signals refer to half the supply voltage to achieve a symmetrical headroom, especially for the rail-to-rail output stage. For ripple and noise attenuation the 1¤2VP voltage has to be filtered via a low-pass filter by using an external capacitor together with an integrated

resistor (f−3dB = 5 Hz). For a fast setting to 1¤2VP an internal start-up circuit is available.

1999 May 07

7

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VP	supply voltage (pin 22)	maximum chip temperature	0	5.5	V
		of 125 °C; note 1
VI	input voltage at pins 1 to 8, 11, 13 to 17		0	VP	V
	and 20 to 24
tsc(max)	maximum short-circuit time		−	10	s
VTAGC	tuner AGC output voltage		0	13.2	V
Tstg	storage temperature		−25	+150	°C
Tamb	operating ambient temperature		−20	+70	°C
Ves	electrostatic handling voltage	note 2	−300	+300	V

Notes

1.IP = 103 mA; Tamb = 70 °C; Rth j-a = 69 K/W for SDIP24 and Rth j-a = 90 K/W for SO24.

2.Machine Model class B: L = 2.5 μH.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient	in free air
	SOT234-1		69	K/W
	SOT137-1		90	K/W

1999 May 07

8

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

CHARACTERISTICS

VP = 5 V; Tamb = 25 °C; see Table 1 for input frequencies and level; input level Vi(IF)(rms) = 10 mV (sync-level for B/G, peak white level for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation DSB; residual carrier

B/G: 10%; L = 3%; video signal in accordance with “CCIR, line 17”; measurements taken in Fig.14; unless otherwise specified.

SYMBOL		PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply (pin 22)
VP		supply voltage		note 1	4.5	5	5.5	V
IP		supply current			77	90	103	mA
Vision IF amplifier (pins 1 and 2)
Vi(VIF)(rms)		input signal voltage		B/G standard; −1 dB video	−	60	100	μV
		sensitivity (RMS value)		at output
Vi(max)(rms)		maximum input signal		B/G standard; +1 dB video	120	200	−	mV
		voltage (RMS value)		at output
Vo(int)		internal IF amplitude		within AGC range;	−	0.7	1	dB
		difference between picture		B/G standard;
		and sound carrier		f = 5.5 MHz
GIFcr		IF gain control range		see Fig.4	65	70	−	dB
Ri(diff)		differential input resistance		note 2	1.7	2.2	2.7	kΩ
Ci(diff)		differential input capacitance		note 2	1.2	1.7	2.5	pF
VI(1,2)		DC input voltage		note 2	−	3.4	−	V
True synchronous video demodulator; note 3
fVCO(max)		maximum oscillator		f = 2fpc	125	130	−	MHz
		frequency for carrier
		regeneration
f	/ T	oscillator drift as a function		oscillator is free-running;	−	−	±20 × 10−6	K−1
osc		of temperature		IAFC = 0; note 4
VVCO(rms)		oscillator voltage swing at			70	100	130	mV
		pins 18 and 19 (RMS value)
fcr(pc)		picture carrier capture		B/G and L standard	±1.5	±2.0	−	MHz
		frequency range		L accent standard;	±1.0	±1.3	−	MHz
				fpc = 33.9 MHz;
				R7 = 5.6 kΩ
fpc(fr)		picture carrier frequency		L accent standard;	−	±200	±400	kHz
		(free-running) accuracy		fpc = 33.9 MHz;
				R7 = 5.6 kΩ
falg(L accent)		L accent alignment		IAFC = 0	±400	±600	−	kHz
		frequency range
tacq		acquisition time		BL = 70 kHz; note 5	−	−	30	ms
Vi(VIF)(rms)		VIF input signal voltage		maximum IF gain; note 6	−	30	70	μV
		sensitivity for PLL to be
		locked (RMS value;
		pins 1 and 2)
Ioffset(FPLL)		FPLL offset current at pin 4		note 7	−	−	±4.5	μA

1999 May 07

9

Philips Semiconductors	Product specification

Multistandard VIF-PLL with QSS-IF and

TDA9810

AM demodulator

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Composite video amplifier (pin 9; sound carrier off)
Vo(video)(p-p)	output signal voltage	see Fig.9	0.88	1.0	1.12	V
	(peak-to-peak value)
V/S	ratio between video		1.9	2.33	3.0	−
	(black-to-white) and
	sync level
Vsync(9)	sync voltage level	B/G and L standard	−	1.5	−	V
Vclu(9)	upper video clipping voltage		VP − 1.1	VP − 1	−	V
	level
Vcll(9)	lower video clipping voltage		−	0.3	0.4	V
	level
Ro(9)	output resistance	note 2	−	−	10	Ω
Ibias(9)(int)	internal DC bias current for		2.2	3.0	−	mA
	emitter-follower
Isink(9)(max)	maximum AC and DC output		1.6	−	−	mA
	sink current
Isource(9)(max)	maximum AC and DC output		2.9	−	−	mA
	source current
B−1	−1 dB video bandwidth	B/G and L standard;	5	6	−	MHz
		CL < 50 pF; RL > 1 kΩ;
		AC load
B−3	−3 dB video bandwidth	B/G and L standard;	7	8	−	MHz
		CL < 50 pF; RL > 1 kΩ;
		AC load
αH(sup)	suppression of video signal	CL < 50 pF; RL > 1 kΩ;	35	40	−	dB
	harmonics	AC load; note 8a
PSRR	power supply ripple rejection	video signal; grey level;
	at pin 9	see Fig.12
		B/G standard	32	35	−	dB
		L standard	26	30	−	dB
CVBS buffer amplifier (only) and noise clipper (pins 12 and 13)
Ri(13)	input resistance	note 2	2.6	3.3	4.0	kΩ
Ci(13)	input capacitance	note 2	1.4	2	3.0	pF
VI(13)	DC input voltage		1.4	1.7	2.0	V
Gv	voltage gain	B/G and L standard; note 9	6.5	7	7.5	dB
Vclu(12)	upper video clipping voltage		3.9	4.0	−	V
	level
Vcll(12)	lower video clipping voltage		−	1.0	1.1	V
	level
Ro(12)	output resistance	note 2	−	−	10	Ω
Ibias(12)(int)	DC internal bias current for		2.0	2.5	−	mA
	emitter-follower
Isink(12)(max)	maximum AC and DC output		1.4	−	−	mA
	sink current

1999 May 07

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