Philips TDA9810 Datasheet

INTEGRATED CIRCUITS
DATA SH EET
TDA9810
Multistandard VIF-PLL with QSS-IF and AM demodulator
Product specification Supersedes data of 1997 Jun 19 File under Integrated Circuits, IC02
1999 May 07
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and AM demodulator

FEATURES

5 V supply voltage
Gain controlled wide band Video Intermediate
Frequency (VIF)-amplifier (AC-coupled)
True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
Gated phase detector for L/L accent standard; robustness for over-modulation until 105%
Voltage Controlled Oscillator (VCO) frequency switchable between L and L accent (alignment external) picture carrier frequency
Separate video amplifier for sound trap buffering with high video bandwidth
VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for B/G (optional external AGC) and peak white detector for L; signal controlled reaction time for L
TDA9810
Tuner AGC with adjustable TakeOver Point (TOP)
AFC detector without extra reference circuit
SIF-input for single reference Quasi Split Sound (QSS)
mode (Phase Locked Loop (PLL) controlled); Sound Intermediate Frequency (SIF) AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode
AM demodulator without extra reference circuit
AM mute (especially for NICAM)
Stabilizer circuit for ripple rejection and to achieve
constant output signals.

GENERAL DESCRIPTION

The TDA9810 is an integrated circuit for multistandard vision IF signal processing and sound AM demodulation, with single reference QSS-IF in TV and VCR sets.

ORDERING INFORMATION

TYPE NUMBER
NAME DESCRIPTION VERSION
TDA9810 SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 TDA9810T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PACKAGE
1999 May 07 2
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and
TDA9810
AM demodulator

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
P
I
P
V
i(VIF)(rms)
V
o(CVBS)(p-p)
B
3
S/N
W(video)
α
IM(1.1)
α
IM(3.3)
α
H(sup)
V
i(SIF)(rms)
V
o(intercarrier)(rms)
V
o(AF)(rms)
THD total harmonic distortion 54% modulation 0.5 1.0 % S/N
W
supply voltage 4.5 5 5.5 V supply current 77 90 103 mA vision IF input signal voltage sensitivity
1 dB video at output 60 100 µV
(RMS value) CVBS output signal voltage
1.7 2.0 2.3 V
(peak-to-peak value)
3 dB video bandwidth on pin CVBS B/G and L standard;
78MHz CL< 20 pF; RL> 1kΩ; AC load
weighted signal-to-noise ratio for video 56 60 dB intermodulation attenuation at ‘blue’ f = 1.1 MHz 58 64 dB intermodulation attenuation at ‘blue’ f = 3.3 MHz 58 64 dB suppression of video signal harmonics 35 40 dB sound IF input signal voltage sensitivity
3 dB at intercarrier output 30 70 µV
(RMS value) IF intercarrier level (RMS value) SC1 output signal 100 140 180 mV
SC
output signal 100 140 180 mV
AM
SC
AF output signal voltage (RMS value) L standard;
output signal 14 20 26 mV
NICAM
500 mV
54% modulation
weighted signal-to-noise ratio 54% modulation 47 53 dB
1999 May 07 3
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1999 May 07 4
handbook, full pagewidth
BLOCK DIAGRAM
Multistandard VIF-PLL with QSS-IF and
AM demodulator
Philips Semiconductors Product specification
VIF
SAW
SIF
SAW
L/L accent
gating switch
2
VIF AMPLIFIER
1
23 24
INTERNAL VOLTAGE
STABILIZER
22 20 8 5
C
VAGC
TOP
C
BL
TUNER AND VIF-AGC
SIF
AMPLIFIER
SIF-AGC
R
TOP
tuner AGC
loop filter
FPLL
SINGLE REFERENCE
MIXER AND
AM DEMODULATOR
2 x f
VCO TWD
10
pc
AFC DETECTOR
VIDEO DEMODULATOR
AND AMPLIFIER
TDA9810
7
AFC
1719184162114 315
AMPLIFIER SWITCH
VIDEO
BUFFER
AF AMPLIFIER
11
9
12
13
6
video
1 V (p-p)
CVBS
2 V (p-p)
V
i(vid)
AF/AM
MHA713
VP = +5 V
GND
standards
selection
switch
C
SAGC
Fig.1 Block diagram.
QSS
intercarrier
output
L/L accent
switch
AM mute
switch
TDA9810
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and AM demodulator

PINNING

SYMBOL PIN DESCRIPTION
V
i VIF1
V
i VIF2
TADJ 3 tuner AGC takeover point adjust T
PLL
C
SAGC
V
oAF
LSWI 7 L/L accent switch STD 8 standard switch V
o(vid)
V
o QSS
MUTE 11 AM mute switch V
o CVBS
1 VIF differential input signal voltage 1 2 VIF differential input signal voltage 2
4 PLL loop filter 5 SIF AGC capacitor 6 AM audio frequency output voltage
9 composite video output voltage
10 single reference QSS output voltage
12 CVBS output signal voltage
TDA9810
SYMBOL PIN DESCRIPTION
V
i(vid)
LGATSWI 14 L/L accent gating switch C
BL
TAGC 16 tuner AGC output AFC 17 AFC output VCO1 18 VCO1 reference circuit for 2f VCO2 19 VCO2 reference circuit for 2f GND 20 ground C
VAGC
V
P
V
i SIF1
V
i SIF2
13 video buffer input voltage
15 black level detector
21 VIF AGC capacitor 22 supply voltage 23 SIF differential input signal voltage 1 24 SIF differential input signal voltage 2
pc pc
handbook, halfpage
V
V
i VIF1
V
i VIF2
TADJ
T
PLL
C
SAGC V
o AF
LSWI
STD
V
o(vid)
V
o QSS
MUTE
o CVBS
1 2 3 4 5 6 7 8
9 10 11 12
TDA9810
MHA712
V
24
V
23
V
22
C
21 20
GND
19
VCO2
18
VCO1
17
AFC
16
TAGC C
15 14
LGATSWI V
13
i SIF2 i SIF1
P VAGC
BL
i(vid)
handbook, halfpage
V
V
i VIF1
V
i VIF2
TADJ
T
PLL
C
SAGC V
o AF
LSWI
STD
V
o(vid)
V
o QSS
MUTE
o CVBS
1 2 3 4 5 6
TDA9810T
7 8
9 10 11 12
MHA722
V
24
V
23
V
22
C
21 20
GND
19
VCO2
18
VCO1
17
AFC
16
TAGC C
15 14
LGATSWI V
13
i SIF2 i SIF1
P VAGC
BL
i(vid)
Fig.2 Pin configuration SDIP24 package.
1999 May 07 5
Fig.3 Pin configuration SO24 package.
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and AM demodulator
FUNCTIONAL DESCRIPTION Vision IF amplifier
The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration.

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (pin TAGC, open-collector output). The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level.
The AGC detector charges/discharges the AGC capacitor to the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level. Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected. In order to reduce the reaction time for positive modulation, where a very large time constant is needed, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step. The additional level information is given by the black-level detector voltage.

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency. In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals. This mode can be switched off by the L/L accent gating switch.

VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the Picture Carrier (PC) frequency.
TDA9810
The VCO is controlled by two integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the Frequency-Phase detector and fed via the loop filter to the first variable capacitor (FPLL). This control voltage is amplified and additionally converted into a current which represents the AFC output signal. The VCO centre frequency can be decreased (required for L accent standard) by activating an additional internal capacitor. This is achieved by using the L/L accent gating switch. In this event the second variable capacitor can be controlled by a variable resistor at the L/L accent gating switch for setting the VCO centre frequency to the required L accent value. At centre frequency the AFC output current is equal to zero.
The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency.
Video demodulator and amplifier
The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the travelling wave divider output. In the demodulator stage the video signal polarity can be switched in accordance with the TV standard.
The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics for B/G and L standard. The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation. The video output signal is 1 V (p-p) for nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of B/G and L standard. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted for operating in combination with ceramic sound traps. The output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.
1999 May 07 6
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and AM demodulator
SIF amplifier and AGC
The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration.
The SIF AGC detector is related to the SIF input signals (average level of AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to ‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is also set to ‘fast’ controlled by the standard switch.

Single reference QSS mixer

The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO). The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 10. With this system a high performance hi-fi stereo sound processing can be achieved.
TDA9810

AM demodulator

The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the AF amplifier. This AM output signal can be muted by using the AM mute switch.
Internal voltage stabilizer and
The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage.
For all audio output signals the constant reference voltage cannot be used because large output signals are required. Therefore these signals refer to half the supply voltage to achieve a symmetrical headroom, especially for the rail-to-rail output stage. For ripple and noise attenuation
1
the
⁄2VP voltage has to be filtered via a low-pass filter by
using an external capacitor together with an integrated resistor (f start-up circuit is available.
= 5 Hz). For a fast setting to 1⁄2VP an internal
3dB
1
⁄2VP-reference
1999 May 07 7
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and
TDA9810
AM demodulator

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
P
V
I
supply voltage (pin 22) maximum chip temperature
input voltage at pins 1 to 8, 1 1, 13 to 17 and 20 to 24
t
sc(max)
V
TAGC
T
stg
T
amb
V
es
maximum short-circuit time 10 s tuner AGC output voltage 0 13.2 V storage temperature 25 +150 °C operating ambient temperature 20 +70 °C electrostatic handling voltage note 2 300 +300 V
Notes
1. I
= 103 mA; T
P
=70°C; R
amb
= 69 K/W for SDIP24 and R
th j-a
2. Machine Model class B: L = 2.5 µH.
of 125 °C; note 1
th j-a
= 90 K/W for SO24.
0 5.5 V
0V
P
V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air
SOT234-1 69 K/W SOT137-1 90 K/W
1999 May 07 8
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and
TDA9810
AM demodulator

CHARACTERISTICS

VP=5V; T peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier B/G: 10%; L = 3%; video signal in accordance with specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply (pin 22)
V
P
I
P
Vision IF amplifier (pins 1 and 2)
V
i(VIF)(rms)
V
i(max)(rms)
V
o(int)
G
IFcr
R
i(diff)
C
i(diff)
V
I(1,2)
True synchronous video demodulator; note 3 f
VCO(max)
f
/T oscillator drift as a function
osc
V
VCO(rms)
f
cr(pc)
f
pc(fr)
f
alg(L accent)
t
acq
V
i(VIF)(rms)
I
offset(FPLL)
=25°C; see Table 1 for input frequencies and level; input level V
amb
“CCIR, line 17”
; measurements taken in Fig.14; unless otherwise
supply voltage note 1 4.5 5 5.5 V supply current 77 90 103 mA
input signal voltage sensitivity (RMS value)
maximum input signal voltage (RMS value)
internal IF amplitude difference between picture and sound carrier
B/G standard; 1 dB video at output
B/G standard; +1 dB video at output
within AGC range; B/G standard;
f = 5.5 MHz IF gain control range see Fig.4 65 70 dB differential input resistance note 2 1.7 2.2 2.7 k differential input capacitance note 2 1.2 1.7 2.5 pF DC input voltage note 2 3.4 V
maximum oscillator
f=2f
pc
frequency for carrier regeneration
oscillator is free-running; of temperature
I
AFC
= 0; note 4
oscillator voltage swing at pins 18 and 19 (RMS value)
picture carrier capture frequency range
B/G and L standard ±1.5 ±2.0 MHz
L accent standard;
f
= 33.9 MHz;
pc
R7= 5.6 k picture carrier frequency
(free-running) accuracy
L accent standard;
fpc= 33.9 MHz;
R7= 5.6 k L accent alignment
I
=0 ±400 ±600 kHz
AFC
frequency range acquisition time BL = 70 kHz; note 5 −−30 ms VIF input signal voltage
maximum IF gain; note 6 30 70 µV sensitivity for PLL to be locked (RMS value; pins 1 and 2)
FPLL offset current at pin 4 note 7 −−±4.5 µA
i(IF)(rms)
= 10 mV (sync-level for B/G,
60 100 µV
120 200 mV
0.7 1 dB
125 130 MHz
−−±20 × 106K
70 100 130 mV
±1.0 ±1.3 MHz
−±200 ±400 kHz
1
1999 May 07 9
Philips Semiconductors Product specification
Multistandard VIF-PLL with QSS-IF and
TDA9810
AM demodulator
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Composite video amplifier (pin 9; sound carrier off)
V
o(video)(p-p)
output signal voltage (peak-to-peak value)
V/S ratio between video
(black-to-white) and sync level
V
sync(9)
V
clu(9)
sync voltage level B/G and L standard 1.5 V upper video clipping voltage
level
V
cll(9)
lower video clipping voltage level
R
o(9)
I
bias(9)(int)
output resistance note 2 −−10 internal DC bias current for
emitter-follower
I
sink(9)(max)
maximum AC and DCoutput sink current
I
source(9)(max)
maximum AC and DC output source current
B
1
B
3
α
H(sup)
1 dB video bandwidth B/G and L standard;
3 dB video bandwidth B/G and L standard;
suppression of video signal harmonics
PSRR power supply ripple rejection
at pin 9
see Fig.9 0.88 1.0 1.12 V
1.9 2.33 3.0
VP− 1.1 VP− 1 V
0.3 0.4 V
2.2 3.0 mA
1.6 −− mA
2.9 −− mA
56 MHz CL< 50 pF; RL> 1kΩ; AC load
78 MHz CL< 50 pF; RL> 1kΩ; AC load
CL< 50 pF; RL> 1kΩ;
35 40 dB AC load; note 8a
video signal; grey level; see Fig.12
B/G standard 32 35 dB L standard 26 30 dB
CVBS buffer amplifier (only) and noise clipper (pins 12 and 13)
R
i(13)
C
i(13)
V
I(13)
G
v
V
clu(12)
input resistance note 2 2.6 3.3 4.0 k input capacitance note 2 1.4 2 3.0 pF DC input voltage 1.4 1.7 2.0 V voltage gain B/G and L standard; note 9 6.5 7 7.5 dB upper video clipping voltage
level
V
cll(12)
lower video clipping voltage level
R
o(12)
I
bias(12)(int)
output resistance note 2 −−10 DC internal bias current for
emitter-follower
I
sink(12)(max)
maximum AC and DC output sink current
1999 May 07 10
3.9 4.0 V
1.0 1.1 V
2.0 2.5 mA
1.4 −− mA
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