Philips TDA8767 User Manual

INTEGRATED CIRCUITS

DATA SH EET

TDA8767

12-bit high-speed Analog-to-Digital
Converter (ADC)

Preliminary specification
Supersedes data of 1997 Jun 27
File under Integrated Circuits, IC02

1999 Feb 16

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

FEATURES

• 12-bit resolution

• Sampling rate up to 30 MHz

•−3 dB bandwidth of 18 MHz

• No missing codes guaranteed

• 5 V power supplies

• Binary or two’s complement CMOS outputs

• In-range CMOS output

• TTL/CMOS compatible static digital inputs

• 3 to 5 V CMOS digital outputs

• TTL compatible clock input

• Power dissipation 335 mW (typ.)

• Low analog input capacitance (typ. 2 pF), no buffer

amplifier required

• No external sample-and-hold circuit required

• Differential or single analog Input

• External amplitude range control

• Voltage controlled regulator included.

TDA8767

APPLICATIONS

• High-speed analog-to-digital conversion for:
– Video signal digitizing
– High Definition TV (HDTV)
– Imaging (camera, scanner)
– Medical imaging
– Telecommunication
– Base-station receiver.

GENERAL DESCRIPTION

The TDA8767 is a bipolar 12-bit Analog-to-Digital
Converter (ADC) for imaging or other applications.
It converts the analog input signal into 12-bit binary coded
digital words at a maximum sampling rate of 30 MHz.
All digital inputs and outputs are CMOS compatible.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

ILE integral non-linearity f
DLE differential non-linearity f

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 40 tbf mA
digital supply current − 22 tbf mA
output supply current f

= 4 MHz; fi= 400 kHz − 3.2 tbf mA

clk

= 4 MHz; fi= 400 kHz −±3.0 ±4.0 LSB

clk

= 4 MHz; fi= 400 kHz;

clk

−±0.6 ±1 LSB

no missing codes

f

clk(max)

maximum clock frequency

TDA8767H/1 10 −−MHz
TDA8767H/2 20 −−MHz
TDA8767H/3 30 −−MHz

P

tot

total power dissipation − 335 − mW

1999 Feb 16 2

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

ORDERING INFORMATION

41

PACKAGE

CLK

36

CLOCK DRIVER

V

CCD1

37

LATCHES

V

CCD2

15

SOT307-2

18

CMOS

OUTPUTS

SAMPLING

FREQUENCY (MHz)

OETC

19

D11

21

28
29

32

33

D1022
D923
D824
D725
D626
D527
D4
D3
D230
D131
D0

MSB

data outputs

LSB

V

CCO

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8767H/1
TDA8767H/2 20

QFP44

plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm

TDA8767H/3 30

BLOCK DIAGRAM

V

V

V

handbook, full pagewidth

V

ref

V
V

SH

V

CCA1

CCA2

9

2

CCA3

CCA4

3

TDA8767

11

AMP

42

I

43

I

sample-

and-hold

39

ANALOG-TO-DIGITAL

CONVERTER

10

44

AGND1

10

AGND2

analog ground

4

AGND3

40

AGND4

38

DGND1

digital ground

Fig.1 Block diagram.

1999 Feb 16 3

IN-RANGE

LATCH

17

DGND2

CMOS

OUTPUT

OGND

20

34

IR

MBH142

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
V

CCA1

V

CCA3

AGND3 4 analog ground 3
n.c. 5 not connected
n.c. 6 not connected
n.c. 7 not connected
n.c. 8 not connected
V

CCA2

AGND2 10 analog ground 2
V

ref

n.c. 12 not connected
n.c. 13 not connected
n.c. 14 not connected
V

CCD2

n.c. 16 not connected
DGND2 17 digital ground 2
TC 18 output two’s complement
OE 19 output enable input

IR 20 in-range output
D11 21 data output; bit 11 (MSB)
D10 22 data output; bit 10

2 analog supply voltage 1 (+5 V)
3 analog supply voltage 3 (+5 V)

9 analog supply voltage 2 (+5 V)

11 reference voltage

15 digital supply voltage 2 (+5 V)

(CMOS level; active LOW)

TDA8767

SYMBOL PIN DESCRIPTION

D9 23 data output; bit 9
D8 24 data output; bit 8
D7 25 data output; bit 7
D6 26 data output; bit 6
D5 27 data output; bit 5
D4 28 data output; bit 4
D3 29 data output; bit 3
D2 30 data output; bit 2
D1 31 data output; bit 1
D0 32 data output; bit 0 (LSB)
V

CCO

OGND 34 output ground
n.c. 35 not connected
CLK 36 clock input
V

CCD1

DGND1 38 digital ground 1
SH 39 sample-and-hold enable input

AGND4 40 analog ground 4
V

CCA4

V

I

V

I

AGND1 44 analog ground 1

33 output supply voltage (3 to 5.25 V)

37 digital supply voltage 1 (+5 V)

(CMOS level; active HIGH)

41 analog supply voltage 4 (+5 V)
42 complementary analog input voltage
43 analog input voltage

1999 Feb 16 4

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

IVI

V

43

42

n.c.

V

CCA1

V

CCA3

AGND3

n.c.
n.c.

n.c.
n.c.

V

CCA2

AGND2

V

ref

AGND1
44

1
2
3
4
5
6
7
8

9
10
11

CCA4

V

41

AGND4

SH

40

39

TDA8767

DGND1

V

38

37

CCD1

CLK

36

n.c.
35

OGND
34

TDA8767

V

33

CCO

D0

32
31

D1

30

D2
D3

29
28

D4
D5

27
26

D6
D7

25
24

D8
D9

23

12
n.c.

13

14

15

16

17

n.c.

n.c.

CCD2

V

n.c.

DGND2

Fig.2 Pin configuration.

18

TC

19
OE

20

21

IR

D11

22

D10

MBH143

1999 Feb 16 5

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
∆V

V
V

I

O

T
T
T

CCA
CCD
CCO

CC

I
i(p-p)

stg
amb
j

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output supply voltage note 1 −0.3 +7.0 V
supply voltage difference

− V

V
V
V

CCA
CCO
CCA

− V

− V

CCD

CCD

CCO

input voltage referenced to AGND 0.3 V
input voltage for differential clock

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

CCA

− V

CCD

drive (peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 70 °C
junction temperature − +150 °C

V
V

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

CCO

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE (TYP.) UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

1999 Feb 16 6

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

CHARACTERISTICS

V

CCA=V2

V

CCO=V33

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Inputs

CLK (
V

IL

V

IH

I

IL

I

IH

Z

i

C

i

TC; SH AND OE (REFERENCED TO DGND); see Tables 3 and 4
V

IL

V

IH

I

IL

I

IH

V

AND V

I

I

IL

I

IH

Z

i

C

i

V

ios(d)

V

ios(s)

to V44, V9to V10, V3to V4 and V41to V40= 4.75 to 5.25 V; V

to V34= 3.0 to 5.25 V; AGND and DGND shorted together; T

= 5 V and V

CCO

= 3.3 V; V

i(p-p)

− V

= 2.0 V; CL= 15 pF and T

i(p-p)

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 3.0 3.3 5.25 V
analog supply current − 40 tbf mA
digital supply current − 22 tbf mA
output supply current f

REFERENCED TO DGND)

= 20 MHz; fi= 4.43 MHz − 12 tbf mA

clk

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
LOW-level input current V
HIGH-level input current V

input impedance f
input capacitance f

= 0.3V

clk
clk

V

clk=VCCD

= 30 MHz − 2 − kΩ

clk

= 30 MHz − 2 − pF

clk

= 0.7V

CCD
CCD

LOW-level input voltage 0 − 0.8 V
HIGH-level input voltage 2.0 − V
LOW-level input current VIL= 0.3V
HIGH-level input current VIH= 0.7V

(REFERENCED TO AGND; see Tables 1 AND 2); V

I

LOW-level input current Vi= V
HIGH-level input current Vi= V

CCD

CCD

ref=VCCA

i
i

input impedance fi= 4.43 MHz − 10 − kΩ
input capacitance fi= 4.43 MHz − 2 − pF
input offset voltage in

differential mode

input offset voltage in single
mode

VI= VI; output code 2047

V

= 5 V tbf 2.5 tbf V

CCA

V

= 4.75 V tbf 2.25 tbf V

CCA

V

= 5.25 V tbf 2.75 tbf V

CCA

VI=V

ios(s)

; output

code 2047

= 5 V tbf 2.5 tbf V

V

CCA

V

= 4.75 V tbf 2.25 tbf V

CCA

V

= 5.25 V tbf 2.75 tbf V

CCA

CCD=V37

amb

− 2V

to V38and V15to V17= 4.75 to 5.25 V;

= 0 to +70 °C; typical values measured at

=25°C; unless otherwise specified.

amb

CCD

−400 −−µA

−−100 µA

−−300 µA

CCD

−400 −−µA

−−20 µA

− 10 −µA

− 10 −µA

V

V

1999 Feb 16 7

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Voltage controlled regulator input V

V

ref(FS)

V

i(p-p)

− V

full scale fixed voltage V
input voltage amplitude

i(p-p)

(peak-to-peak value)

I

ref

input current at V

ref

Outputs (referenced to DGND)

D

IGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)

V

OL

V

OH

I

O

LOW-level output voltage IOL= 2 mA 0 − 0.5 V
HIGH-level output voltage IOH= −0.4 mA V
output current in 3-state 0.5 V < VO<V

Switching characteristics

C

LOCK FREQUENCY f

f

clk(min)

f

clk(max)

minimum clock frequency SH = HIGH −−1 MHz

maximum clock frequency

(see Fig.3)

clk

TDA8767H/1 10 −−MHz
TDA8767H/2 20 −−MHz
TDA8767H/3 30 −−MHz

t

CPH

t

CPL

clock pulse width HIGH 8.5 −−ns
clock pulse width LOW 8.5 −−ns

Analog signal processing; 50% clock duty factor; V

(referenced to V

ref

=5V − 3.175 − V

CCA

differential mode − 2.0 − V
single mode;

SH = LOW −−1 kHz

)

CCA

Vi= 2.5 V − 2.0 − V

− 10 −µA

− 0.5 − V

CCO

CCO

− Vi= 2.0 V; V

i

−20 − +20 µA

ref=VCCA

− 2V;see Table 1

CCD

V

INEARITY

L
ILE integral non-linearity f

DLE differential non-linearity f

= 4 MHz; ramp input −±3.0 ±4.0 LSB

clk

= 4 MHz; ramp input;

clk

−±0.6 ±1 LSB

no missing codes

OFER offset error V

CCA=VCCD=VCCO

T

=25°C; Vi= Vi; output

amb

=5V;

tbf − tbf LSB

code = 2047

GER gain error amplitude; spread

from device to device

BANDWIDTH (f

= 30 MHz); note 1

clk

V

CCA=VCCD=VCCO

T

=25°C; Vi− Vi= 2.0 V

amb

=5V;

tbf − tbf LSB

B analog bandwidth −1dB − 9 − MHz

−3dB − 18 − MHz

t

STLH

t

STHL

analog input settling time
LOW-to-HIGH transition

analog input settling time
HICH-to-LOW transition

full scale square wave;
note 3

full scale square wave;
note 3

− tbf − ns

− tbf − ns

HARMONICS
THD total harmonic distortion f

= 30 MHz; fi= 4.43 MHz;

clk

−−64 − dB

note 2

1999 Feb 16 8

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S

IGNAL-TO-NOISE RATIO

S/N signal-to-noise ratio without harmonics;

f

= 30 MHz; fi= 4.43 MHz

clk

Timing (C

t

ds

t

h

t

d

= 15 pF); note 4; see Fig.3

L

sampling delay time −−2ns
output hold time 8 −−ns
output delay time V

= 4.75 V − 12 15 ns

CCO

V

= 3.15 V 15 18 ns

CCO

3-state output delay times; see Fig.4
t

dZH

t

dZL

t

dHZ

t

dLZ

enable HIGH − 14 18 ns
enable LOW − 16 20 ns
disable HIGH − 16 20 ns
disable LOW − 14 18 ns

Notes to the characteristics

1. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.

2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

THD 20 log

---------------------------------------------------------------------------------------------------------------=
(2nd)2(3rd)2(4th)2(5th)2(6th)

++++

F

2

F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).

4. Output data acquisition: the output data is available after the maximum delay of t

− 61 − dB

.

d

1999 Feb 16 9

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

Table 1 Output coding with differential inputs (typical values to AGND); V

BINARY OUTPUTS

CODE V

I

V

I

IR

D11 to D0 D11 to D0

underflow <2.0 >3.0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 2.0 3.0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00
1 −−1 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 1

↓−−↓ ↓ ↓

2047 2.5 2.5 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−−↓ ↓ ↓

4094 −−1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0
4095 3.0 2.0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

overflow >3.0 <2.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

Table 2 Output coding with single input (typical values to AGND); V

= 2.0 V (p-p); V

FS

BINARY OUTPUTS

CODE V

I

IR

D11 to D0 D11 to D0

underflow <1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 1.5 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00
1 − 1 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 1

↓−↓ ↓ ↓

2047 2.5 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−↓ ↓ ↓

4094 − 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0
4095 3.5 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

overflow >3.5 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

I(p-p)

− V

= 2.0 V; V

I(p-p)

ref=VCCA

TWO’S COMPLEMENT

OUTPUTS

ref=VCCA

− 2V

TWO’S COMPLEMENT

OUTPUTS

− 2V

Table 3 Mode selection

TC OE D0 to D11 and IR

0 0 binary; active
1 0 two’s complement; active

(1)

X

1 high impedance

Note

1. Where: X = don’t care.

Table 4 Sample-and-hold selection

SH SAMPLE-AND-HOLD

1 active
0 inactive; tracking mode

1999 Feb 16 10

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

t

handbook, full pagewidth

CLK

V

l

DATA
D0 to D11

sample N

DATA

N - 2

t

CPH

t

CPL

ds

sample N + 1

DATA

N - 1

TDA8767

HIGH
50 %
LOW

sample N + 2

t

h

DATA

N

t

d

DATA

N + 1

HIGH
50 %
LOW

MBG855

handbook, full pagewidth

fOE= 100 kHz.

V

OE

output
data

output
data

CCD

0V

LOW

Fig.3 Timing diagram.

OE

HIGH

t

dZL

t

dLZ

10 %

TDA8767

50 %

15 pF

HIGH

3.3 kΩ

t

90 %

dHZ

LOW

V

S1

CCD

50 %

t

dZH

50 %

TEST

t

dLZ

t

dZL

t

dHZ

t

dZH

S1

V

CCD

V

CCD

DGND
DGND

MBH144

Fig.4 Timing diagram and test conditions of 3-state output delay time.

1999 Feb 16 11

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

t

handbook, full pagewidth

code 1023

V

code 0

CLK

MBD875

I

STLH

50 %

5 ns

50 %

2 ns

5 ns

t

STHL

50 %

50 %

TDA8767

2 ns

Fig.5 Analog input settling time diagram.

1999 Feb 16 12

Philips Semiconductors Preliminary specification

h

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

APPLICATION INFORMATION

andbook, full pagewidth

220 nF

IN

100 Ω 100 Ω

4.7 µF

1 : 1

10
nF

R1

R2

V

CCA

5 V

(2)

5 V

100 nF

V

100 nF

100 nF

ref

V

I

V

I

n.c.

n.c.
n.c.
n.c.
n.c.

(3)

100 nF

44 43 42 41 40 39 38 37 36 35 34

1
2

3
4
5
6
7
8
9
10
11

12

13 14 15 16 17 18 19 20 21 22

TDA8767H

mode

5 V5 V SH

100 nF

CLK

(1)

n.c.

5 V

33
32
31
30
29
28
27
26
25
24
23

100 nF

D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9

n.c.

MBH145

The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and V
(2) R1, and R2 must be determined in order to obtain a middle voltage of 2.5 V; see Table 1. To ensure a sufficient analog input stability, the minimum

current into these resistors must be about 1 mA.

must be decoupled to V

(3) V

ref

CCA

.

n.c. n.c.

n.c.
5 V

100 nF

IR

D10

D11

(MSB)

chip select input (OE)

output format select (TC)

CCD

.

Fig.6 Application diagram (differential input mode).

1999 Feb 16 13

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

andbook, full pagewidth

V

50 Ω

CCA

220 nF

IN

4.7
µF

50 Ω50 Ω

10
nF

5 V

100 nF

V

R1

(2)

R2

5 V
100 nF

100 nF

ref

V

I

V

I

n.c.

n.c.
n.c.
n.c.
n.c.

(3)

5 V5 V SH

100 nF

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8
9
10
11

12

13 14 15 16 17 18 19 20 21 22

mode

TDA8767H

100 nF

CLK

(1)

n.c.

TDA8767

5 V

33
32
31
30
29
28
27
26
25
24
23

100 nF

D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8

D9

n.c.

MBH146

The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and V
(2) R1, and R2 must be determined in order to obtain a voltage of 2.5 V on VI and VI; see Table 1. To ensure a sufficient analog input stability, the

minimum current into these resistors must be about 1 mA.

must be decoupled to V

(3) V

ref

CCA

.

n.c. n.c.

n.c.
5 V

100 nF

IR

D10

D11

(MSB)

chip select input OE
output format select TC

CCD

.

Fig.7 Application diagram (single input mode).

1999 Feb 16 14

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA8767

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

D

cE

p

0.40

0.25

0.20

0.14

D

10.1

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

v M

D

H

E

A

B

E

12.9

12.3

E

LL

0.95

0.55

A

p

A

2

A

1

detail X

Z

D

0.15 0.10.15

1.2

0.8

(A )

3

L

p

L

Zywv θ

E

1.2

0.8

θ

o

10

o

0

OUTLINE
VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1999 Feb 16 15

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

TDA8767

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Feb 16 16

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital

TDA8767

Converter (ADC)

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Feb 16 17

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8767

NOTES

1999 Feb 16 18

Philips Semiconductors Preliminary specification

12-bit high-speed Analog-to-Digital
Converter (ADC)

TDA8767

NOTES

1999 Feb 16 19

Philips Semiconductors – a worldwide company

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Middle East: see Italy
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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545004/750/03/pp20 Date of release: 1999 Feb 16 Document order number: 9397 750 04713