Philips tda8041 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
TDA8041H
Quadrature demodulator controller
Preliminary specification
File under Integrated Circuits, IC03
Philips Semiconductors
November 1994
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
FEATURES
• Generates all control signals for Quadrature Phase-Shift
Keying (QPSK) and Binary Phase-Shift Keying (BPSK)
APPLICATIONS
• Demodulation of BPSK and QPSK modulated signals in
satellite and telephone applications.
demodulation
• Can be used in applications with low Eb/No and high
symbol rate (up to 30 × 106 symbols/s)
• Digital I and Q outputs (3 bits) for soft decision within
error correction
• Two matched analog-to-digital converters to quantize
the I and Q signals
• A digital detector for each control loop to generate the
required control signals
• Digital-to-analog converters and operational amplifiers
to allow high flexibility for loop time constants
• Special input stage to interface with the voltage
controlled crystal oscillator
• Positive 5 V supply voltage.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD(A)
supply voltage for operational
4.75 5.0 5.25 V
amplifiers (pin 5)
V
DDA(C)
analog supply voltage for
4.75 5.0 5.25 V
converters (pin 20)
V
DD(I/O)
supply voltage for digital
4.75 5.0 5.25 V
inputs/outputs (pin 30)
V
DDD
supply voltage for digital
4.75 5.0 5.25 V
section (pin 35)
V
DD(C)
supply voltage for digital part
4.75 5.0 5.25 V
of ADC and DAC (pin 42)
I
DD(tot)
V
IQ
R
sym
I
O(DAC)
total supply current VDD=5 V − 30 − mA
I and Q input voltage − 1.0 − V
symbol rate −−30 × 106symbols/s
DAC output current −100 − +100 mA
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
plastic quad flat package; 44 leads (lead length 1.3 mm);
TDA8041H QFP44
(1)
body 10 × 10 × 1.75 mm; high stand-off height
Note
1. When using reflow soldering it is recommended that the Drypack instructions in the
(order number 9398 510 63011) are followed.
November 1994 2
SOT307-2
“Quality Reference Handbook”
November 1994 3
handbook, full pagewidth
BLOCK DIAGRAM
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
mode
control
V
ref(pos)
V
ref(mid)
V
ref(neg)
AFC1
AFC2
TEST
Q
I
ana
BQN
ana
I
bias
18
V
DD
R4
7
R3
8
R2
9
R1
V
SS
38
36
37
40
19
41
GENERATOR
CLK2
ADC
ADC
CLK2
BIAS
4
A
4
A
I
bias
I
bias
I
bias
IDO0 to IDO2
31 to 33
3
LOGIC
TDA8041H
LOGIC
ADC
DAC
OPAMP
QDO0 to QDO2
3
4
I (3..0)
4
Q (3..0)
26 to 28 5
V
DD(A)
LOCK
DETECTOR
CARRIER
RECOVERY
LOGIC
AFC2
AGC
CLOCK
RECOVERY
CLK1
6
V
SS(A)
V
SS2
11
V
data
data
data
data
data
17
SSA(C)
LCK
CAR
AFC2
AGC
CLK
V
4
4
5
2
5
20
DDA(C)
V
CLK1
CLK1
CLK1
CLK1
CLK1
24
SS1
LCKDAC LCKTC
44 1
I
LCK
DAC
I
29
SS(I/O)
CAR
I
AFC2
I
AGC
I
CLK
V
DD(I/O)
30
DAC
DAC
DAC
DAC
V
V
ref(mid)
V
ref(mid)
V
ref(mid)
V
ref(mid)
V
SSD
CLK2
CLK1
34
V
DDD
LCKO
2
4
LCKIO
3
LCKTH
15
CARTC
16
CARO
39
V
th
2
35
42
43
V
SS(C)
V
DD(C)
SWEEP
14
SWPO
10
AFC2O
12
AGCTC
13
AGCO
21
CLKRTC
22
CLKRO
23
CLKIX
25
CLKSR
MBE167
Fig.1 Block diagram.
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
PINNING
SYMBOL PIN DESCRIPTION
LCKTC 1 carrier lock time constant
LCKO 2 carrier lock output
LCKTH 3 carrier lock threshold voltage
LCKIO 4 carrier lock indicator output
V
DD(A)
5 supply voltage for operational
amplifiers
V
SS(A)
6 negative supply voltage for
operational amplifiers
V
ref(pos)
7 positive reference voltage for
converters
V
ref(mid)
8 middle reference voltage for
converters
V
ref(neg)
9 negative reference voltage for
converters
AFC2O 10 AFC 2 output
V
SS2
11 negative supply voltage 2
AGCTC 12 automatic gain control time
constant
AGCO 13 automatic gain control output
SWPO 14 sweep current output
CARTC 15 carrier recovery time constant
CARO 16 carrier recovery output
V
SSA(C)
17 analog negative supply voltage for
converters
I
ana
Q
ana
V
DDA(C)
18 analog input I
19 analog input Q
20 analog supply voltage for
converters
CLKRTC 21 clock recovery time constant
CLKRO 22 clock recovery output
CLKIX 23 clock input from crystal circuit
(at double symbol rate)
SYMBOL PIN DESCRIPTION
V
SS1
24 negative supply voltage 1
CLKSR 25 clock output at symbol rate
QDO2 26 Q digital output (bit 2)
QDO1 27 Q digital output (bit 1)
QDO0 28 Q digital output (bit 0)
V
SS(I/O)
29 negative supply voltage for digital
inputs/outputs
V
DD(I/O)
30 supply voltage for digital
inputs/outputs
IDO2 31 I digital output (bit 2)
IDO1 32 I digital output (bit 1)
IDO0 33 I digital output (bit 0)
V
SSD
34 negative supply voltage for digital
section
V
DDD
35 supply voltage for digital section
AFC1 36 AFC control switch 1 (1 = on;
0=off)
AFC2 37 AFC control switch 2 (1 = on;
0=off)
BQN 38 BPSK/QPSK control switch
(1 = BPSK; 0 = QPSK)
SWEEP 39 sweep control switch (1 = on;
0=off)
TEST 40 test control switch (1 = on; 0 = off)
I
bias
V
DD(C)
41 input bias current for analog blocks
42 supply voltage for digital part of
ADC and DAC
V
SS(C)
43 negative supply voltage for digital
part of ADC and DAC
LCKDAC 44 carrier lock DAC output
November 1994 4
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
handbook, full pagewidth
LCKTC
LCKO
LCKTH
LCKIO
V
DD(A)
V
SS(A)
V
ref(pos)
V
ref(mid)
V
ref(neg)
AFC2O
V
SS2
DD(C)
SS(C)
bias
V
V
43
13
AGCO
I
42
14
SWPO
41
TDA8041H
15
CARTC
LCKDAC
44
1
2
3
4
5
6
7
8
9
10
11
12
AGCTC
TEST
40
16
CARO
BQN
SWEEP
39
38
17
18
ana
I
SSA(C)
V
Q
AFC2
37
19
ana
V
AFC1
36
35
20
DDA(C)
V
DDD
V
34
21
22
CLKRO
CLKRTC
33
32
31
30
29
28
27
26
25
24
23
IDO0
IDO1
IDO2
V
DD(I/O)
V
SS(I/O)
QDO0
QDO1
QDO2
CLKSR
V
SS1
CLKIX
MBE166
SSD
Fig.2 Pin configuration.
November 1994 5
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