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TDA8020HL
Technical data
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Philips TDA8020HL Technical data

INTEGRATED CIRCUITS
DATA SH EET
TDA8020HL
Dual IC card interface
Product specification Supersedes data of 2001 Aug 15
2003 Nov 06
Dual IC card interface TDA8020HL

FEATURES

• Two independent 6 contacts smart card interfaces
• Supply voltage to the cards: VCC= 5 V and ICC up to 60 mA or 3 V ±5% and ICC up to 55 mA
• Integrated DC-to-DC converter (doubler, tripler or
follower) for allowing power supply from 2.7 to 6.5 V
• Independent supply voltage for interface signals (from
1.5 to 6.5 V)
• Control and status via the I2C-bus
• Four possible devices in parallel due to two I2C-bus
address pins
• Electrical specifications according to ISO 7816 or EMV2000
• Automatic activation and deactivation sequences by means of integrated sequencers
• Automaticclockcountandresettogglingduringwarmor cold reset
• Interrupt request output to the controller
• 6 kV ESD protection on cards contacts
• Automatic emergency deactivation in the event of
supply drop-out, overload, overheating, card take-off or DC-to-DC malfunctioning
• Current limitation on pins CLK, RST, I/O and V
• Integrated voltage supervisor for power-on reset and
drop-out detection.
CC

APPLICATIONS

• Set top boxes
• Banking terminals
• Internet terminals.

GENERAL DESCRIPTION

The TDA8020HL is a one-chip dual smart card interface. Controlled by the I2C-bus, it guarantees conformity to ISO 7816 or EMV2000 with very few external components.

ORDERING INFORMATION

TYPE NUMBER
NAME DESCRIPTION VERSION
TDA8020HL/C1 LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 TDA8020HL/C2 LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1
2003 Nov 06 2
PACKAGE
Dual IC card interface TDA8020HL

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DD
V
DDI
I
DD
I
DDA
Card supply
, V
V
CC1
CC2
V
ripple(p-p)
I
, I
CC1
CC2
General
V
th1
V
hys1
t
de
P
tot
T
amb
supply voltage on pins VDD and V
DDA
supply voltage for interface signals 1.5 − V supply current VDD= 3.3 V; inactive mode −−150 µA
V
= 3.3 V; Power-down mode;
DD
2 cards activated; V I
CC1=ICC2
= 100 µA;
CC1=VCC2
=5V;
CLK1 and CLK2 stopped
= 3.3 V; active mode;
V
DD
V
CC1=VCC2
I
CC1+ICC2
=5V;
= 80 mA;
CLK1 = CLK2 = 5 MHz V
= 3.3 V; active mode;
DD
V
CC1=VCC2
I
CC1=ICC2
=3V;
= 10 mA;
CLK1 = CLK2 = 5 MHz
DC-to-DC converter supply current inactive mode; V
f
=10MHz
xtal
active mode; V f
= 10 MHz; no load
xtal
DDA
DDA
=5V;
=5V;
card supply voltage including ripple 5 V card; DC ICC< 60 mA 4.75 − 5.25 V
5 V card; AC current spikes of 40 nAs 4.65 − 5.25 V 3 V card; DC I
< 55 mA 2.85 − 3.15 V
CC
3 V card; AC current spikes of 40 nAs 2.76 − 3.20 V ripple voltage (peak-to-peak value) 20 kHz to 200 MHz −−350 mV card supply current 0 V to 5 V −−60 mA
0Vto 3V −−55 mA
threshold voltage for the supervisor on V
DD
hysteresis on V
th1
deactivation cycle duration 50 80 100 µs continuous total power dissipation T
= −40 to +85 °C −−0.50 W
amb
ambient temperature TDA8020HL/C1 −30 − +85 °C
TDA8020HL/C2 −40 − +85 °C
2.7 − 6.5 V
V
DD
−−2mA
−−400 mA
−−80 mA
−−0.1 mA
−−10 mA
2.1 − 2.4 V
50 − 100 mV
2003 Nov 06 3
Dual IC card interface TDA8020HL

BLOCK DIAGRAM

V
I2C-BUS
AND
LEVEL
DD
SAP
20 14 19 15 17
SAM SBP SBM
DC-to-DC
CONVERTER
TDA8020HL
CLOCK
CIRCUITRY
CARD1
DRIVERS
SEQUENCER1
CLOCK
CIRCUITRY
CARD2
DRIVERS
SEQUENCER2
16
V
DDA
13
V
UP
3
CLK1
5
RST1
4
V
CC1
2
CGND1
32
I/O1
1
PRES1
9
CLK2
11
RST2
10
V
CC2
8
CGND2
6
I/O2
7
PRES2
handbook, full pagewidth
C
DEL
SAD0 SAD1
SCL SDA
IRQ
CLKIN2 CLKIN1
I/O1uC I/O2uC
V
DDI
SUPPLY SUPERVISOR
30
VOLTAGE REFERENCE
INTERNAL
OSCILLATOR
23 24 21
REGISTERS
22
25
29 26 27
SHIFTERS
28
31
AGND GND
Fig.1 Block diagram.
2003 Nov 06 4
1218
FCE834
Dual IC card interface TDA8020HL

PINNING

SYMBOL PIN TYPE DESCRIPTION
PRES1 1 I card 1 presence contact input (active HIGH) CGND1 2 supply ground connection output to card 1 (C5 contact) CLK1 3 O clock output to card 1 (C3 contact) V
CC1
RST1 5 O reset output to card 1 (C2 contact) I/O2 6 I/O I/O contact to card 2 (C7 contact); internal 15 kΩ pull-up resistance to
PRES2 7 I card 2 presence contact input (active HIGH) CGND2 8 supply ground connection output to card 2 (C5 contact) CLK2 9 O clock output to card 2 (C3 contact) V
CC2
RST2 11 O reset output to card 2 (C2 contact) GND 12 supply ground connection V
UP
SAP 14 I/O capacitor connection for the DC-to-DC converter; a 220 nF capacitor with
SBP 15 I/O capacitor connection for the DC-to-DC converter; a 220 nF capacitor with
V
DDA
SBM 17 I/O capacitor connection for the DC-to-DC converter; a 220 nF capacitor with
AGND 18 supply analog ground for the DC-to-DC converter SAM 19 I/O capacitor connection for the DC-to-DC converter; a 220 nF capacitor with
V
DD
SCL 21 I serial clock input of I SDA 22 I/O serial data input/output of I SAD0 23 I I SAD1 24 I I IRQ 25 O interrupt request output to host (open drain; active LOW) CLKIN1 26 I external clock input for card 1 I/O1uC 27 I/O I/O connection to host for card 1; internal 11 kΩ pull-up resistor to V I/O2uC 28 I/O I/O connection to host for card 2; internal 11 kΩ pull-up resistor to V CLKIN2 29 I external clock input for card 2 C
DEL
V
DDI
I/O1 32 I/O I/O contact to card 1 (C7 contact); internal 14 kΩ pull-up resistor to V
4 supply supply voltage output to card 1 (C1 contact); decouple to pin CGND1 with
2 × 100 nF capacitors with ESR < 100 mΩ
pin V
CC2
10 supply supply voltage output to card 2 (C1 contact); decouple to pin CGND2 with
2 × 100 nF capacitors with ESR < 100 mΩ
13 I/O output of DC-to-DC converter; a 220 nF capacitor with ESR < 100 mΩ must
be connected to pin AGND
ESR < 100 mΩ must be connected between pins SAP and SAM
ESR < 100 mΩ must be connected between pins SBP and SBM
16 supply analog supply voltage for the DC-to-DC converter
ESR < 100 mΩ must be connected between pins SBP and SBM
ESR < 100 mΩ must be connected between pins SAP and SAM
20 supply power supply voltage
2
C-bus (open drain)
2
C-bus (open drain)
2
C-bus address selection input 0
2
C-bus address selection input 1
DDI DDI
30 I/O delay capacitor connection for the voltage supervisor (1 ms per 2 nF) 31 I interface signals reference supply voltage
CC1
2003 Nov 06 5
Dual IC card interface TDA8020HL
handbook, full pagewidth
DEL
DDI
V
I/O1
31
32
CLKIN2
C
30
29
I/O2uC
28
I/O1uC
27
CLKIN1
26
IRQ
25
PRES1
CGND1
CLK1
V
CC1
RST1
I/O2
PRES2
CGND2
1 2 3 4
TDA8020HL
5 6 7 8
9
CLK2
10
CC2
V
11
RST2
12
GND
13
14
15
UP
SAP
V
SBP
16
DDA
V
24 23 22 21 20 19 18 17
FCE833
SAD1 SAD0 SDA SCL
V
DD
SAM AGND SBM
Fig.2 Pin configuration.
2003 Nov 06 6
Dual IC card interface TDA8020HL

FUNCTIONAL DESCRIPTION

Throughoutthisspecification,itisassumedthatthereader is familiar with ISO 7816 terminology.

Supply

The TDA8020HL operates with a supply voltage from
2.7 to6.5 V. An integrated voltage supervisor ensures that nospikeappearsoncardscontactsduringpower-on or off. The supervisor also initializes the device, and forces an automatic emergency deactivation of the contacts in the event of a supply drop-out.
As long as the supply voltage is below the threshold voltageV the supply voltage reaches V
,thecapacitorC
th1
remainsuncharged.When
DEL
th1
and V
hys1
, then C
DEL
is chargedwithasmallcurrent source of approximately 2 µA. When the voltage on C
reaches V
DEL
, then the
th2
supervisor is no longer active. As long as the supervisor is active (pin IRQ is LOW), bit SUPL in the status register is set. When pin IRQ goes HIGH the voltage supervisor becomes inactive (see Fig.3).
Separatesupplypinsareusedfor the DC-to-DC converter, allowing specific decoupling for counteracting the noise the switching transistors may induce on the supply.
A specific reference supply voltage, V
, is used for the
DDI
interface signals CLKIN1, CLKIN2, I/O1uC, I/O2uC, SAD0, SAD1, SCL, SDA and IRQ, which can be lower thanVDD(minimum 1.5 V),thusallowingdirectcontrol with a low voltage supplied device.
Pins SCL, SDA and IRQ are open-drain outputs, and may be externally pulled up to a voltage higher than VDD.
handbook, full pagewidth
V
V
th1
V
CDEL
DD
+ V
IRQ
hys1 V
th1
V
th2
t
w
status read
after event
BUS NOT RESPONDING BUS OK
Fig.3 Voltage supervisor.
t
w
BUS NOT
RESPONDING
BUS OK BUS NOT
RESPONDING
FCE835
2003 Nov 06 7
Dual IC card interface TDA8020HL

DC-to-DC converter

V
is the supply voltage for card 1 contacts and V
CC1
CC2
the supply voltage for card 2 contacts. Card 1 and card 2 may be independently powered-down, powered at 5 V or poweredat3 V.Acapacitor type step-up converter is used for generating these voltages. This step-up converter acts either as a doubler, tripler or follower. An hysteresis of 100 mV is present on the different threshold voltages.
If VCCis the maximum value of V
CC1
and V
, then there
CC2
are 5 possible situations:
• VDD< 3.4 V and VCC= 3 V: in this case, the DC-to-DC
converter acts as a doubler with a regulation of approximately 4.0 V
• VDD< 3.4 V and VCC= 5 V: in this case, the DC-to-DC
converter acts as a tripler with a regulation of approximately 5.5 V
• VDD> 3.5 V and VCC= 3 V: in this case, the DC-to-DC
converter acts as a follower: VDD is applied on V
UP
• 5.8V>VDD> 3.5 V and VCC= 5 V: in this case, the
DC-to-DC converter acts as a doubler with a regulation of approximately 5.5 V
• VDD> 5.9 V and VCC= 5 V: in this case, the DC-to-DC
converter acts as a follower and VDD is applied on VUP.
The output voltage, VUP, is fed internally to the V generators. V
CC1,VCC2
and CGND1, CGND2 are used as
CC
a reference for all other cards contacts. The sum of I
CC1
and I
shall not exceed 80 mA, which
CC2
means that when a card is drawing its maximum current (around 60 mA at VCC= 5 V, 55 mA at VCC= 3 V), the other card should be set in low power consumption mode (less than 20 or 25 mA). Note that during the card Advice to Receive (ATR) process, the current may be maximum; so, a card should only be activated if the other card draws lessthan20or25 mA. The DC-to-DC converter issupplied via separate supply pins V
and AGND to allow
DDA
decoupling separate from the other supply pins. Duringnormaloperationoractivation,each card is allowed
to draw independently a current of up to 60 mA at VCC= 5 V or up to 55 mA at VCC= 3 V, with a supply voltage from 2.7 V up to 6.5 V provided the sum of I
CC1
and I
does not exceed 80 mA.
CC2
If VDD> 3 V, for 5 V cards, then both cards can draw up to 60 mA at the same time.
If VDD> 3 V, for 3 V cards, then both cards can draw up to 55 mA at the same time.
2
C-bus
I
is
A 400 kHz I2C-bus slave interface is used for configuring the device and reading the status.
2
C-BUS PROTOCOL
I The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The serial bus consists of two bidirectional lines; one for data (SDA), and one for the clock (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.
US CONDITIONS
B The following bus conditions have been defined:
• Bus not busy: both data and clock lines remain HIGH
• Start data transfer: a change in the state of the data line,
fromHIGH-to-LOW, while the clock is HIGH, defines the START condition
• Stop data transfer: a change in the state of the data line, fromLOW-to-HIGH, while the clock is HIGH, defines the STOP condition
• Data valid: the state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per data bit.
DATA TRANSFER Each data transfer is initiated with a START condition and
terminated with a STOP condition. Data transfer is unlimited in the read mode. The
information is transmitted in bytes and each receiver acknowledges with a ninth bit.
The TDA8020HL operates in standard mode (100 kHz clock rate) and fast mode (400 kHz clock rate) defined in the I2C-bus specification.
By definition, a device that sends a signal is called a transmitter, and the device which receives the signal is called a receiver. The device which controls the signal is
2003 Nov 06 8
Dual IC card interface TDA8020HL
called the master. The devices that are controlled by the master are called slaves.
Each byte is followed by one HIGH-level acknowledge bit asserted by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver whichis addressed is obliged to generate an acknowledge after the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave
Table 1 Proposed device address bit allocations
Device
76543210
TDA8020HL 0 1 0 0 0/1 A1 A0 R/
transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, thetransmittermustleavethedatalineHIGHtoenablethe master generation of the STOP condition.
See Chapter “Characteristics” for timing information.
DEVICE ADDRESSING Each device has 2 different addresses, one for each card. An application can use up to four devices in parallel by the
use of address selection pins SAD0 and SAD1. Pins SAD0 and SAD1 are externally hardwired to VDD or GND; SAD0 specifies address bit A0, SAD1 specifies address bit A1; Address bit R/W specifies either read or write operation: logic 1 = Read, logic 0 = Write (see Tables 1 and 2).
Address bits
W
Table 2 Proposed I
PIN SAD1 PIN SAD0 CARD 1 CARD 2
LOW LOW 40H 48H
LOW HIGH 42H 4AH HIGH LOW 44H 4CH HIGH HIGH 46H 4EH
2
C-bus addresses for 4 devices in parallel
2003 Nov 06 9
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