Philips TDA6503A, TDA6502A, TDA6502 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA6502; TDA6502A; TDA6503;
TDA6503A

5 V mixers/oscillators and
synthesizers for cable TV and VCR
2-band tuners

Preliminary specification
Supersedes data of 2000 Jan 24
File under Integrated Circuits, IC02

2000 Mar 16

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION

3.1 I2C-bus format

3.2 3-wire bus format
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Control mode selection

8.2 I2C-bus data format

8.2.1 I2C-bus address selection

8.2.2 Write mode

8.2.3 Read mode

8.2.4 Power-on reset

8.3 3-wire bus data format

8.3.1 Power-on reset
9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 TIMING CHARACTERISTICS

13 TEST AND APPLICATION INFORMATION

13.1 Test circuits

13.2 Measurement circuit

13.3 Tuning amplifier

13.4 Crystal oscillator

13.5 ExamplesofI2C-busdataformatsequencesfor

13.5.1 Write sequences to register C2

13.5.2 Read sequences from register C3

13.6 Examplesof 3-wire busdata format sequences

13.6.1 18-bit sequence

13.6.2 19-bit sequence

13.6.3 27-bit sequence
14 INTERNAL PIN CONFIGURATION
15 PACKAGE OUTLINE
16 SOLDERING

16.1 Introduction to soldering surface mount

16.2 Reflow soldering

16.3 Wave soldering

16.4 Manual soldering
17 DEFINITIONS
18 LIFE SUPPORT APPLICATIONS
19 PURCHASE OF PHILIPS I2C COMPONENTS

TDA6502; TDA6502A;

TDA6503; TDA6503A

TDA6502 and TDA6503

for TDA6502 and TDA6503

packages

2000 Mar 16 2

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

1 FEATURES

• Single-chip 5 V mixer/oscillator and synthesizer for
cable TV and VCR tuners

• Pin-to-pin compatible with TDA6402, TDA6402A,
TDA6403 and TDA6403A

• Universal bus protocol (I2C-bus or 3-wire bus)
– Bus protocol for 18 or 19-bit transmission (3-wire

bus)

– Extraprotocolfor27-bittransmission(testmodesand

features for 3-wire bus)

– Address + 4 data bytes transmission (I2C-bus ‘write’

mode)
– Address + 1 status byte (I2C-bus ‘read’ mode)
– 4 independent I2C-bus addresses.

• 1 PMOS buffer for UHF band selection (25 mA)

• 3 PMOS buffers for general purpose, e.g. 2 VHF

sub-bands, FM sound trap (25 mA)

• 33 V tuning voltage output

• In-lock detector

• 5-step analog-to-digital converter (3 bits in I2C-bus

mode)

• 15-bit programmable divider

• Programmable reference divider ratio (64, 80 or 128)

• Programmable charge pump current (60 or 280 µA)

• Varicap drive disable

• Balanced mixer with a common emitter input for VHF

(single input)

• Balanced mixer with a common base input for UHF
(balanced input)

• 2-pin common emitter oscillator for VHF

• 4-pin common emitter oscillator for UHF

• IF preamplifier with asymmetrical 75 Ω output
impedance able to drive loads from 75 Ω upwards

• Low power

• Low radiation

• Small size

• TheTDA6502AandTDA6503Adiffer from the TDA6502

and TDA6503 by the UHF port protocol in the I2C-bus
mode (see Tables 3 and 4).

TDA6502; TDA6502A;

TDA6503; TDA6503A

2 APPLICATIONS

• Cable tuners for TV and VCR (switched concept for
VHF).

3 GENERAL DESCRIPTION

The TDA6502, TDA6502A, TDA6503 and TDA6503A are
programmable2-band mixers/oscillators andsynthesizers
intended for VHF/UHF TV and VCR tuners (see Fig.1).

Partitioning of the bands is the responsibility of the
customer providing VHF is below 500 MHz and UHF is
below 900 MHz.

The devices include two double balanced mixers and two
oscillators for the VHF and UHF band respectively, an
IF amplifier and a PLL synthesizer. The VHF band can be
split-up into two sub-bands using a proper oscillator
application and a switchable inductor.

Two pins are available between the mixer output and the
IF amplifier input to enable IF filtering for improved signal
handling.

The port register provides four PMOS ports. Band
selection is provided by port register UHF. When port
register UHF is ‘on’, the UHF mixer-oscillator is active and
the VHF band is switched off. When port register UHF is
‘off’, the VHF mixer-oscillator is active and the UHF band
is off. Port registers VHFL and VHFH are used to select
the VHF sub-bands. Port register FMST is a general
purposeport, that can be usedtoswitch an FM sound trap.
Whenthe ports areused,the sum ofthedrain currents has
to be limited to 30 mA.

Thesynthesizerconsists of a 15-bitprogrammabledivider,
a crystal oscillator and its programmable reference divider
and a phase comparator (phase/frequency detector)
combined with a charge pump which drives the tuning
amplifier, including the 33 V output at pin VT. Depending
on the reference divider ratio (64, 80 or 128), the phase
comparator operates at 62.5, 50 or 31.25 kHz with a
4 MHz crystal.

2000 Mar 16 3

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

Depending on thevoltage applied to pin SW (see Table 2)
the device is operating in the I2C-bus mode or 3-wire bus
mode.

In the 3-wire bus mode, pin LOCK/ADCis the ‘lock’ output
of the PLL and is at LOW level when the PLL is locked.
Lockdetectorbit FL of the statusbyteisset to logic 1 when
the loop is locked and is read on the SDA line during a
READ operation in I2C-bus mode only.

In the I2C-bus mode only,pin LOCK/ADC is the ADC input
for digital AFC control. The ADC code is read during a
READ operation on the I2C-bus.

In the test mode, in both I2C-bus mode and 3-wire bus
mode, pin LOCK/ADC is used as a test output for f

1

⁄2f

.

DIV

2

3.1 I

Five serial bytes (including the address byte) are required
to address thedevice, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I2C-bus addresses which can be selected by applying a
specific voltage to pin CE/AS.

C-bus format

REF

and

TDA6502; TDA6502A;

TDA6503; TDA6503A

Table 1 Data word length for 3-wire bus format

DATA WORD

18-bit 64 62.50 kHz
19-bit 128 31.25 kHz
27-bit programmable programmable

Note

1. The selection of the reference divider is given by an

automatic identification of the data word length. When
the 27-bit format is used, the reference divider is
controlled by bits RSA and RSB (see Table 8). More
details are given in Section 8.3.

REFERENCE

DIVIDER

(1)

FREQUENCY

STEP

3.2 3-wire bus format

Data is transmitted to the device during a HIGH level on
pin CE/AS (enable line). The device is accessible with
18-bit and 19-bit data formats (see Figs 4 and 5). The first
four bits are used to program the PMOS ports and the
remaining bits control the programmable divider. A 27-bit
data format (seeFig.6) may alsobe used to set thecharge
pump current, the reference divider ratio and the test
modes.

It is not allowed to address the device with words whose
length is different from 18, 19 or 27 bits.

2000 Mar 16 4

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

TDA6502; TDA6502A;

TDA6503; TDA6503A

4 QUICK REFERENCE DATA

Measured over full voltage and temperature ranges.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I

CC

CC

supply voltage operating 4.5 5 5.5 V
supply current all PMOS ports are off;

− 71 − mA

VCC=5V

f

XTAL

I

o(PMOS)

P

tot

T

stg

T

amb

f

RF

crystal oscillator frequency − 4.0 − MHz
PMOS port output current note 1 −−30 mA
total power dissipation note 2 −−520 mW
IC storage temperature −40 − +150 °C
ambient temperature −20 − +85 °C
RF frequency VHF band 40 − 800 MHz

UHF band 200 − 900 MHz

G

V

voltage gain VHF band − 20 − dB

UHF band − 32 − dB

NF noise figure VHF band − 7.5 − dB

UHF band − 7 − dB

V

o

output voltage (causing 1% cross
modulation in channel)

VHF band − 110 − dBµV
UHF band − 110 − dBµV

Notes

1. One buffer ‘on’, Io= 25 mA; two buffers ‘on’, maximum sum of Io= 30 mA.

2. The power dissipation is calculated as follows:
P

tot

V

CCICCIo

–()V

P(sat)Io

0.5 33V×()

+×+×=

--------------------------------­22 kΩ

2

where:
V

= output saturation voltage on the buffer output

P(sat)

I

= source current for one buffer output.

o

5 ORDERING INFORMATION

TYPE

NUMBER

TDA6502;

NAME DESCRIPTION VERSION

SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

PACKAGE

TDA6502A;
TDA6503;
TDA6503A

2000 Mar 16 5

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

6 BLOCK DIAGRAM

handbook, full pagewidth

VHFIN

RFGND

UHFIN1

UHFIN2

3 (26)

BS

4 (25)

1 (28)
2 (27)

RF INPUT

VHF

TDA6502
TDA6502A
(TDA6503)

(TDA6503A)

RF INPUT

UHF

IFFIL1 IFFIL2

5 (24)

6 (23)

BS

BSBS

VHF

MIXER

UHF

MIXER

V

CC

19 (10)

BS

TDA6502; TDA6502A;

TDA6503; TDA6503A

(5) 24

VHF

BS

OSCILLATOR

IF

PREAMPLIFIER

UHF

OSCILLATOR

(7) 22
(6) 23

(9) 20

(1) 28
(2) 27
(3) 26
(4) 25

VHFOSCOC

VHFOSCIB
OSCGND

IFOUT

UHFOSCIB2
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1

XTAL

CL

DA

SW

CE/AS

18 (11)

14 (15)
13 (16)
11 (18)

12 (17)

XTAL

OSCILLATOR

4 MHz

POWER-DOWN

DETECTOR

SCL
SDA
SW

I

CE/AS

REFERENCE

RSA RSB

PROGRAMMABLE

FREQUENCY

FL

2

C-bus / 3-WIRE BUS

TRANSCEIVER

3-BIT ADC

DIVIDER

64, 80, 128

15-BIT

DIVIDER

15-BIT

REGISTER

f

REF

COMPARATOR

f

DIV

DETECTOR

f

REF

FL

GATE

15 (14)

LOCK/ADC

PHASE

IN-LOCK

FL

1/2f

DIV

T0, T1, T2

CHARGE

PUMP

T0, T1, T2

CP T2 T1 T0 RSA RSB OS

UHF VHFH VHFL FMST

BS

9 (20)

PUHF

CP

CONTROL

REGISTER

REGISTER

PVHFH

PORT

8 (21)

OPAMP

OS

7 (22)

PVHFL

FMST

10 (19)

(13) 16
(12) 17

(8) 21

FCE527

CP

VT

GND

The pin numbers in parenthesis represent the TDA6503 and TDA6503A.

Fig.1 Block diagram.

2000 Mar 16 6

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

7 PINNING

PIN

SYMBOL

UHFIN1 1 28 UHF RF input 1
UHFIN2 2 27 UHF RF input 2
VHFIN 3 26 VHF RF input
RFGND 4 25 RF ground
IFFIL1 5 24 IF filter output 1
IFFIL2 6 23 IF filter output 2
PVHFL 7 22 PMOS port output, general purpose (e.g. VHF low sub-band)
PVHFH 8 21 PMOS port output, general purpose (e.g. VHF high sub-band)
PUHF 9 20 PMOS port output, UHF band
FMST 10 19 PMOS port output, general purpose (e.g. FM sound trap)
SW 11 18 bus format selection input: I
CE/AS 12 17 chip enable input in 3-wire bus mode or address selection input in

DA 13 16 serial data input/output
CL 14 15 serial clock input
LOCK/ADC 15 14 lock detector output in 3-wire bus mode or ADC input in I

CP 16 13 charge pump output
VT 17 12 tuning voltage output
XTAL 18 11 crystal oscillator input
V

CC

IFOUT 20 9 IF output
GND 21 8 digital ground
VHFOSCIB 22 7 VHF oscillator input base
OSCGND 23 6 oscillator ground
VHFOSCOC 24 5 VHF oscillator output collector
UHFOSCIB1 25 4 UHF oscillator input 1 (base)
UHFOSCOC1 26 3 UHF oscillator output 1 (collector)
UHFOSCOC2 27 2 UHF oscillator output 2 (collector)
UHFOSCIB2 28 1 UHF oscillator input 2 (base)

TDA6502;

TDA6502A

19 10 supply voltage

TDA6503;

TDA6503A

2

I

C-bus mode

mode

TDA6502; TDA6502A;

TDA6503; TDA6503A

DESCRIPTION

2

C-bus mode or 3-wire bus mode

2

C-bus

2000 Mar 16 7

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1
IFFIL2

PVHFL

PVHFH

PUHF
FMST

SW

CE/AS

DA

CL

1
2
3
4
5
6
7

TDA6502

TDA6502A

8

9
10
11
12
13

FCE570

UHFOSCIB2

28

UHFOSCOC2

27

UHFOSCOC1

26

UHFOSCIB1

25

VHFOSCOC

24
23

OSCGND
VHFOSCIB

22
21

GND
IFOUT

20

V

19

CC

XTAL

18

VT

17

CP

16
1514

LOCK/ADC

handbook, halfpage

UHFOSCIB2
UHFOSCOC2
UHFOSCOC1

UHFOSCIB1

VHFOSCOC

VHFOSCIB

LOCK/ADC

OSCGND

GND

IFOUT

V

CC

XTAL

VT

CP

TDA6502; TDA6502A;

TDA6503; TDA6503A

1
2

3
4
5
6
7

TDA6503

TDA6503A

8
9

10
11
12
13

FCE571

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

UHFIN1
UHFIN2
VHFIN
RFGND
IFFIL1
IFFIL2
PVHFL
PVHFH
PUHF
FMST
SW
CE/AS
DA
CL

Fig.2 Pin configuration for TDA6502 and

TDA6502A.

Fig.3 Pin configuration for TDA6503 and

TDA6503A.

8 FUNCTIONAL DESCRIPTION

8.1 Control mode selection

The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2).
A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data

(SDA) and serial clock (SCL) input respectively.
A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock

inputs respectively.

Table 2 Bus format selection

PIN

SYMBOL

TDA6502;

TDA6502A

TDA6503;

TDA6503A

I2C-BUS MODE 3-WIRE BUS MODE

SW 11 18 LOW-level voltage or ground HIGH-level voltage or open-circuit
CE/AS 12 17 address selection input enable input
DA 13 16 serial data input data input
CL 14 15 serial clock input clock input
LOCK/ADC 15 14 ADC input or test output lock detector output or test output

2000 Mar 16 8

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

8.2 I2C-bus data format

2

8.2.1 I
The module address contains programmable address

bits MA1 and MA0 (see Tables 3, 4 and 9) which offer the
possibility of having several synthesizers (up to 4) in one
system by applying a specific voltage on pin CE/AS.
The relationship between bits MA1 and MA0 and theinput
voltage applied to pin CE/AS is given in Table 6.

8.2.2 W
The write mode is defined by the address byte ADB with

bit R/W = 0 (see Tables 3 and 4).
Data bytes can be sent to the device after the address

transmission (first byte). Four data bytes are needed to
fully program the device.

Table 3 I

Address byte ADB 11000MA1MA0R/
Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8
Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0
Control byte CB 1 CP T2 T1 T0 RSA RSB OS
Band-switch byte BB XXXXFMST PUHF PVHFH PVHFL

C-BUS ADDRESS SELECTION

RITE MODE

2

C-bus data format for write mode of TDA6502 and TDA6503

NAME BYTE

MSB LSB

The bus transceiver has an auto-increment facility which
permits the programming of the device within one single
transmission (address byte + 4 data bytes). The device
can also be partially programmed providing that the first
data byte following the address byte is divider byte DB1 or
the control byte CB.

The first bit of byte DB1 indicates whether frequency data
(first bit = 0) or control and band-switch data (first bit = 1)
will follow. Until an I
controller,additional data bytescanbe entered without the
need to re-address the device.

The frequency register is loaded after the 8th clock pulse
of byte DB2, the control register is loaded after the 8th
clock pulse of the byte CB and the band-switch register is
loaded after the 8th clock pulse of byte BB.

BITS

TDA6502; TDA6502A;

TDA6503; TDA6503A

2

C-bus STOP command is sent by the

W=0

2

Table 4 I

Address byte ADB 11000MA1MA0R/
Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8
Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0
Control byte CB 1 CP T2 T1 T0 RSA RSB OS
Band-switch byte BB XXXXPUHF FMST PVHFH PVHFL

2000 Mar 16 9

C-bus data format for write mode of TDA6502A and TDA6503A

BIT

NAME BYTE

MSB LSB

W=0

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

Table 5 Description of the bits used in Tables 3 and 4

BIT DESCRIPTION

MA1 and MA0 programmable address bits (see Table 6)

W logic 0 for write mode

R/

14

N14 to N0 programmable divider bits: N = N14 × 2
CP charge pump current control bit:

logic 0: charge pump current is 60 µA

logic 1: charge pump current is 280 µA (default)
T2, T1 and T0 test bits (see Table 7)
RSA and RSB reference divider ratio select bits (see Table 8)
OS tuning amplifier control bit:

logic 0: tuning voltage is ‘on’ (during normal operating)

logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (default)
PVHFL, PVHFH, PUHF and FMST PMOS ports control bits:

logic 0: corresponding buffer is ‘off’ (default)

logic 1: corresponding buffer is ‘on’
X don’t care

+ N13 × 213+ ... + N1 × 21+N0

TDA6502; TDA6502A;

TDA6503; TDA6503A

Table 6 Address selection bits (I

2

C-bus mode)

MA1 MA0 VOLTAGE APPLIED TO PIN CE/AS

0 0 0 V to 0.1V

CC

0 1 0.2VCCto 0.3VCC or open-circuit
1 0 0.4V
1 1 0.9VCCto 1.0V

CC

to 0.6V

CC
CC

Table 7 Test mode bits

T2 T1 T0 TEST MODE

0 0 0 normal mode
0 0 1 normal mode (note 1)
0 1 X charge pump is off
1 1 0 charge pump is sinking current
1 1 1 charge pump is sourcing current
100f
101

is available on pin LOCK/ADC (note 2)

REF

1

⁄

f

is available on pin LOCK/ADC (note 2)

2

DIV

Notes

1. This is the default mode at Power-on reset.

2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.

2000 Mar 16 10

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

Table 8 Reference divider ratio select bits

RSA RSB REFERENCE DIVIDER RATIO FREQUENCY STEP (kHz)

X 0 80 50
0 1 128 31.25
1 1 64 62.5

8.2.3 R
The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).
After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is

transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data
bytecan be read from the device if the microcontroller generates an acknowledge on the SDA line (masteracknowledge).

End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.

Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)

A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC
information to the microcontroller of the IF section of the television.

EAD MODE

TDA6502; TDA6502A;

TDA6503; TDA6503A

Table 9 Read data format

NAME BYTE

Address byte ADB 1 1 0 0 0 MA1 MA0 R/
Status byte SB POR FL R 1 1 A2 A1 A0

Note

1. MSB is transmitted first.

Table 10 Description of the bits used in Table 9

BIT DESCRIPTION

MA1 and MA0 programmable address bits (see Table 6)
R/

W logic1 for read mode

POR Power-on reset flag:

logic 0: at power-off
logic 1: at power-on

FL in-lock flag:

logic 0: loop is not locked
logic 1: loop is locked

R ready flag:

logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked
logic 1: in other conditions

A2, A1 and A0 digital outputs of the 5-level ADC (see Table 11)

MSB

(1)

BIT

LSB

W=1

2000 Mar 16 11

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

Table 11 Digital outputs for analog input levels (note 1)

A2 A1 A0 VOLTAGE APPLIED TO PIN LOCK/ADC

0 0 0 0 to 0.15V
0 0 1 0.15VCCto 0.30V
0 1 0 0.30VCCto 0.45V
0 1 1 0.45VCCto 0.60V
1 0 0 0.60VCCto 1.00V

Note

1. Accuracy is ±0.03 × V

8.2.4 POWER-ON RESET
The power-on detection threshold voltage V

reset to the power-on state.
At power-on state the following actions take place:

• The charge pump current is set to 280 µA

• The tuning voltage output is disabled

• The test bits T2, T1 and T0 are set to logic ‘001’

• The divider bit RSB is set to logic 1

• Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the

VHF oscillator and the VHFmixer areswitched on.Port registers VHFL and VHFH are ‘off’, which means that the VHF
tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off untilthe firsttransmission. Inthat
case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of
the VHF low sub-band.

CC

.

is set to 3.2 V at room temperature. Below this threshold the device is

POR

CC

TDA6502; TDA6502A;

TDA6503; TDA6503A

CC
CC
CC
CC

Table 12 Default setting of the bits at Power-on reset

NAME BYTE

MSB LSB

Address byte ADB 1 1 0 0 0 MA1 MA0 X
Divider byte 1 DB1 0 XXXXXXX
Divider byte 2 DB2 XXXXXXXX
Control byte CB 1 1 0 0 1 X 1 1
Band switch byte BB XXXX0000

2000 Mar 16 12

BITS

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

8.3 3-wire bus data format

During a HIGH level on pin CE/AS (enable line), the data
is clocked into the data register at the HIGH-to-LOW
transition of the clock (see Figs 4 and 5).

The first four bits control the PMOS ports and are loaded
intothe internal band-switchregisteron the 5thrising edge
of the clock pulse.

The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the enable line when an
18-bit or 19-bit data word is transmitted. When a 27-bit
dataword is transmitted,thefrequency bits areloadedinto
the frequency register on the 20th rising edge of the clock
pulseand the controlbits at theHIGH-to-LOW transition of
the enable line (see Fig.6).

In this control mode the reference divider is given by
bits RSA and RSB (see Table 8).

The test bits T2, T1 and T0, the charge pump bit CP, the
ratio select bit RSB and bit OS can only be selected or
changed with a 27-bit transmission. They remain
programmed if an 18-bit or 19-bit transmission occurs.
Onlybit RSA is controlledbythe transmission lengthwhen
the 18-bit or 19-bit format is used. When an 18-bit data
word is transmitted, the most significant bit of the divider
(bit N14) is internally set to logic 0 and bit RSA is set to
logic 1. When a 19-bit data word is transmitted, bit RSA is
set to logic 0.

It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits. A data word of
lessthan 18 bits willnot affect the frequencyregister of the
device.

TDA6502; TDA6502A;

TDA6503; TDA6503A

8.3.1 POWER-ON RESET
The power-on detection threshold voltage V

3.2 Vatroom temperature. Below this threshold thedevice
is reset to the power-on state.

At power-on state the following actions take place:

• The charge pump current is set to 280 µA

• The test bits T2, T1 and T0 are set to logic ‘001’

• The divider bit RSB is set to logic 1

• The tuning voltage output is disabled

• The tuning amplifiercontrol bit OS isautomatically reset

to logic 0 in 18-bit and 19-bit modes when the first data
word is received to allow normal operation

• Port register UHF is ‘off’, which means that the UHF
oscillator and the UHF mixer are switched off.
Consequently,the VHF oscillatorandthe VHF mixerare
switched on. Port registers VHFL and VHFH are ‘off’,
which means that theVHF tank circuitis operating inthe
VHF low sub-band. The tuning amplifier is switched off
until the first transmission. In that case, the tank circuit
is supplied with the maximum tuning voltage.
The oscillator is therefore operating at the end of the
VHF low sub-band

• The reference divider ratio is set to 64 or 128 if the first
sequence to the device has 18 bits or 19 bits; if the
sequence has 27 bits, the reference divider ratio is set
by bits RSA and RSB (see Table 8).

POR

is set to

The definition of the bits is unchanged compared to the
I2C-bus mode.

2000 Mar 16 13

Philips Semiconductors Preliminary specification

5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners

handbook, full pagewidth

DA

CL

CE

INVALID

DATA

BAND-SWITCH

DATA

FMST

PVHFL

PUHF

PVHFH

145 18

LOAD BAND-SWITCH

N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

REGISTER

FREQUENCY

DATA

TDA6502; TDA6502A;

TDA6503; TDA6503A

INVALID

DATA

LOAD FREQUENCY

REGISTER

FCE572

handbook, full pagewidth

INVALID

DATA

DA

CL

CE

Fig.4 18-bit data format (bit RSA = 1).

BAND-SWITCH

DATA

FMST

PVHFL

PUHF

PVHFH

145 19

LOAD BAND-SWITCH

REGISTER

N13N14 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

FREQUENCY

DATA

LOAD FREQUENCY

INVALID

DATA

REGISTER

FCE573

Fig.5 19-bit data format (bit RSA = 0).

2000 Mar 16 14