Philips tda6402 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA6402; TDA6403

5 V mixer/oscillator and synthesizer
for cable TV and VCR 2-band
tuners

Preliminary specification
File under Integrated Circuits, IC02

1996 Oct 15

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

FEATURES

• Single-chip 5 V mixer/oscillator and synthesizer for
cable TV and VCR tuners

• Synthesizer function compatible with existing TSA5526

• Universal bus protocol (I2C-bus or 3-wire bus)

– bus protocol for 18 or 19-bit transmission (3-wire bus)
– extra protocol for 27-bit transmission (test modes and

features for 3-wire bus)

– address + 4 data bytes transmission (I2C-bus WRITE

mode)
– address + 1 status byte (I2C-bus READ mode)
– 4 independent I2C-bus addresses

• 1 PNP buffer for UHF band selection (25 mA)

• 3 PNP buffers for general purpose, e.g. 2 VHF

sub-bands, FM sound trap (25 mA)

• 33 V tuning voltage output

• In-lock detector

• 5-step A/D converter (3 bits in I2C-bus mode)

• 15-bit programmable divider

• Programmable reference divider ratio (512, 640 or

1024)

• Programmable charge pump current (60 or 280 µA)

• Programmable automatic charge pump current switch

• Varicap drive disable

• Mixer/oscillator function compatible with existing

TDA5732

• Balanced mixer with a common emitter input for VHF
(single input)

• Balanced mixer with a common base input for UHF
(balanced input)

• 2-pin common emitter oscillator for VHF

• 4-pin common emitter oscillator for UHF

• IF preamplifier with asymmetrical 75 Ω output
impedance to drive a low-ohmic impedance (75 Ω)

• Low power

• Low radiation

• Small size.

TDA6402;

TDA6403

APPLICATIONS

• Cable tuners for TV and VCR (switched concept for
VHF)

• Recommended RF bands for the USA:

55.25 to 133.25 MHz, 139.25 to 361.25 MHz and

367.25 to 801.25 MHz.

GENERAL DESCRIPTION

The TDA6402 and TDA6403 are programmable 2-band
mixer/oscillators and synthesizers intended for VHF/UHF
cable tuners (see Fig.1).

The devices include two double balanced mixers and two
oscillators for the VHF and UHF band respectively, an IF
amplifier and a PLL synthesizer. The VHF band can be
split-up into two sub-bands using a proper oscillator
application and a switchable inductor. Two pins are
available between the mixer output and the IF amplifier
input to enable IF filtering for improved signal handling.
Four PNP ports are provided. Band selection is provided
by using pin PUHF. When PUHF is ‘ON’, the UHF
mixer-oscillator is active and the VHF band is switched off.
When PUHF is ‘OFF’, the VHF mixer-oscillator is active
and the UHF band is ‘OFF’. PVHFL and PVHFH are used
to select the VHF sub-bands. FMST is a general purpose
port, that can be used to switch an FM sound trap.
When it is used, the sum of the collector currents has to be
limited to 30 mA.

The synthesizer consists of a divide-by-eight prescaler, a
15-bit programmable divider, a crystal oscillator and its
programmable reference divider and a phase/frequency
detector combined with a charge-pump which drives the
tuning amplifier, including 33 V output.

Depending on the reference divider ratio (512, 640 or

1024), the phase comparator operates at 7.8125 kHz,

6.25 kHz or 3.90625 kHz with a 4 MHz crystal.

1996 Oct 15 2

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

The device can be controlled according to the I2C-bus
format or 3-wire bus format depending on the voltage
applied to pin SW (see Table 2). In the 3-wire bus mode
(SW = HIGH), pin LOCK/ADC is the lock output.
The LOCK output is LOW when the PLL loop is locked.
In the I2C-bus mode (SW = LOW), the lock detector bit FL
is set to logic 1 when the loop is locked and is read on the
SDA line (Status Byte) during a READ operation in I2C-bus
mode only. The Analog-to-Digital Converter (ADC) input is
available on pin LOCK/ADC for digital AFC control in the
I2C-bus mode only. The ADC code is read during a READ
operation on the I2C-bus (see Table 10). In test mode, pin
LOCK/ADC is used as a TEST output for f
in both I2C-bus mode and 3-wire bus mode (see Table 6).

When the automatic charge-pump current switch mode is
activated and when the loop is phase-locked, the
charge-pump current value is automatically switched to
LOW. This action is taken to improve the carrier-to-noise
ratio. The status of this feature can be read in the ACPS
flag during a read operation on the I2C-bus (see Table 8).

REF

and1⁄2f

DIV

TDA6402; TDA6403

2

C-bus format (SW = GND)

I

Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four ports, set the charge-pump current and set the
reference divider ratio. The device has four independent
I2C-bus addresses which can be selected by applying a
specific voltage on input CE (see Table 5).

3-wire bus format (SW = V

Data is transmitted to the devices during a HIGH-level on
input CE (enable line). The device is compatible with 18-bit

,

and 19-bit data formats, as shown in Figs 4 and 5. The first
four bits are used to program the PNP ports and the
remaining bits control the programmable divider. A 27-bit
data format may also be used to set the charge-pump
current, the reference divider ratio and for test purposes
(see Fig.6).

It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.

or OPEN)

CC

Table 1 Data word length for 3-wire bus

TYPE NUMBER DATA WORD REFERENCE DIVIDER

TDA6402; TDA6403 18-bit 512 62.50 kHz
TDA6402; TDA6403 19-bit 1024 31.25 kHz
TDA6402; TDA6403 27-bit programmable programmable

Note

1. The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit
format is used, the reference divider is controlled by RSA and RSB bits (see Table 7). More details are given in
Chapter “PLL functional description”, Section “3-wire bus mode (SW = OPEN or V

ORDERING INFORMATION

TYPE

NUMBER

TDA6402M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
TDA6403M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

NAME DESCRIPTION VERSION

PACKAGE

(1)

CC

FREQUENCY STEP

)”.

1996 Oct 15 3

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

BLOCK DIAGRAM

handbook, full pagewidth

VHFIN

RFGND

UHFIN1

UHFIN2

3 (26)

4 (25)

1 (28)
2 (27)

BS

RF INPUT

VHF

TDA6402
TDA6403

RF INPUT

UHF

IFFIL1 IFFIL2

5 (24)

6 (23)

BS

BSBS

VHF

MIXER

UHF

MIXER

V

CC

19 (10)

BS

BS

TDA6402; TDA6403

(5) 24

(7) 22
(6) 23

(9) 20

(1) 28
(2) 27
(3) 26
(4) 25

VHFOSCOC

VHFOSCIB
OSCGND

IFOUT

UHFOSCIB2
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1

VHF

OSCILLATOR

IF

PREAMPLIFIER

UHF

OSCILLATOR

XTAL

CL

DA

SW

CE/AS

18 (11)

14 (15)
13 (16)
11 (18)

12 (17)

XTAL

OSCILLATOR

4 MHz

PRESCALER

DIVIDE BY 8

POWER-DOWN

DETECTOR

SCL

2

SDA

I

C / 3-WIRE BUS TRANSCEIVER

SW

CE/AS

3-BIT A/D

CONVERTER

PRESCALER

DIVIDE BY

512, 640, 1024

RSA RSB

15-BIT

PROGRAMMABLE

DIVIDER

15-BIT

FREQUENCY

REGISTER

FL

f

REF

COMPARATOR

f

DIV

IN LOCK

DETECTOR

f

REF

1/2f

FL

GATE

15 (14)

LOCK/ADC

PHASE

FL

DIV

T0, T1, T2

CHARGE

PUMP

T0, T1, T2 CP

CP T2 T1 T0 RSA RSB OS

UHF VHFH VHFL FMST

BS

9 (20)

PUHF

CONTROL

REGISTER

PORT

REGISTER

8 (21)

PVHFH

OPAMP

7 (22)

PVHFL

OS

FMST

10 (19)

(13) 16

(12) 17

(8) 21

MGE692

CP

VT

GND

The pin numbers in parenthesis represent the TDA6403.

1996 Oct 15 4

Fig.1 Block diagram.

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for

TDA6402; TDA6403

cable TV and VCR 2-band tuners

PINNING

SYMBOL

UHFIN1 1 28 UHF RF input 1
UHFIN2 2 27 UHF RF input 2
VHFIN 3 26 VHF RF input
RFGND 4 25 RF ground
IFFIL1 5 24 IF filter output 1
IFFIL2 6 23 IF filter output 2
PVHFL 7 22 PNP port output, general purpose (e.g. VHF low sub-band)
PVHFH 8 21 PNP port output, general purpose (e.g. VHF high sub-band)
PUHF 9 20 PNP port output, UHF band
FMST 10 19 PNP port output, general purpose (e.g. FM sound trap)
SW 11 18 bus format selection input (I
CE/AS 12 17 chip Enable/Address Selection input
DA 13 16 serial data input/output
CL 14 15 serial clock input
LOCK/ADC 15 14 lock detector output (3-wire bus)/ADC input (I
CP 16 13 charge pump output
VT 17 12 tuning voltage output
XTAL 18 11 crystal oscillator input
V

CC

IFOUT 20 9 IF output
GND 21 8 digital ground
VHFOSCIB 22 7 VHF oscillator input base
OSCGND 23 6 oscillator ground
VHFOSCOC 24 5 VHF oscillator output collector
UHFOSCIB1 25 4 UHF oscillator input base 1
UHFOSCOC1 26 3 UHF oscillator output collector 1
UHFOSCOC2 27 2 UHF oscillator output collector 2
UHFOSCIB2 28 1 UHF oscillator input base 2

TDA6402 TDA6403

PIN

19 10 supply voltage

DESCRIPTION

2

C-bus/3-wire bus)

2

C-bus)

1996 Oct 15 5

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

handbook, halfpage

UHFIN1

UHFIN2

VHFIN

RFGND

IFFIL1
IFFIL2

PVHFL

PVHFH

PUHF
FMST

SW

CE/AS

DA

CL

1
2
3
4
5
6
7
8

9
10
11
12
13

TDA6402

MGE690

UHFOSCIB2

28

UHFOSCOC2

27

UHFOSCOC1

26

UHFOSCIB1

25

VHFOSCOC

24
23

OSCGND
VHFOSCIB

22
21

GND
IFOUT

20

V

19

CC

XTAL

18

VT

17

CP

16
1514

LOCK/ADC

handbook, halfpage

UHFOSCIB2
UHFOSCOC2
UHFOSCOC1

UHFOSCIB1

VHFOSCOC

VHFOSCIB

LOCK/ADC

OSCGND

GND

IFOUT

V

CC

XTAL

VT

CP

TDA6402; TDA6403

1
2
3
4
5
6
7
8

9
10
11
12
13

TDA6403

MGE691

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

UHFIN1
UHFIN2
VHFIN
RFGND
IFFIL1
IFFIL2
PVHFL
PVHFH
PUHF
FMST
SW
CE/AS
DA
CL

Fig.2 Pin configuration for TDA6402.

Fig.3 Pin configuration for TDA6403.

PLL FUNCTIONAL DESCRIPTION

The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied on the SW input. A HIGH
level on the SW input enables the 3-wire bus; CE/AS, DA and CL inputs are used as ENABLE (CE), DATA and CLOCK
inputs respectively. A LOW level on SW input enables the I2C-bus; the CE/AS, DA and CL inputs are used as address
selection (AS), SDA and SCL input respectively (see Table 2).

Table 2 Bus format selection

SYMBOL

PIN

3-WIRE BUS MODE I

2

C-BUS MODE

TDA6402 TDA6403

SW 11 18 HIGH level or OPEN LOW level or GND
CE/AS 12 17 ENABLE input Address selection input
DA 13 16 DATA input SDA input
CL 14 15 CLOCK input SCL input
LOCK/ADC 15 14 LOCK/TEST output ADC input/TEST output

1996 Oct 15 6

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for

TDA6402; TDA6403

cable TV and VCR 2-band tuners

I2C-bus mode (SW = GND)

W

RITE MODE; R/W = 0 (see Table 3)

Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are needed to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).

The device can also be partially programmed providing
that the first data byte following the address is divider
byte 1 (DB1) or control byte (CB). The bits in the data
bytes are defined in Table 3. The first bit of the first data
byte transmitted indicates whether frequency data (first
bit = 0) or control and band-switch data (first bit = 1) will
follow. Until an I2C-bus STOP command is sent by the

Table 3 I2C-bus data format, write mode

NAME BYTE

Address byte ADB 11000MA1MA0R/W=0A
Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8 A
Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0 A
Control byte CB 1 CP T2 T1 T0 RSA RSB OS A
Band-switch byte BB XXXXFMST PUHF PVHFH PVHFL A

MSB LSB

controller, additional data bytes can be entered without the
need to re-address the device. The frequency register is
loaded after the 8
(DB2), the control register is loaded after the 8th clock
pulse of the control byte (CB) and the band-switch register
is loaded after the 8th clock pulse of the band switch byte
(BB).

2

C-BUS ADDRESS SELECTION

I
The module address contains programmable address bits

(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 4) in one system by applying a
specific voltage on the CE input. The relationship between
MA1 and MA0 and the input voltage applied to the CE
input is given in Table 5.

BITS

th

clock pulse of the second divider byte

ACK

Table 4 Description of symbols used in Table 3

SYMBOL DESCRIPTION

A acknowledge
MA1, MA0 programmable address bits (see Table 5)

14

N14 to N0 programmable divider bits; N = N14 × 2
CP charge pump current

CP=0=60µA

CP = 1 = 280 µA (default)
T2, T1, T0 test bits (see Table 6)
RSA, RSB reference divider ratio select bits (see Table 7)
OS tuning amplifier control bit:

OS = 0; normal operation; tuning voltage is ‘ON’ (default)

OS = 1; tuning voltage is ‘OFF’ (high impedance)
PVHFL, PVHFH,

PUHF, FMST

X don’t care; may be a ‘0’ or a ‘1’

1996 Oct 15 7

PNP ports control bits:

bit = 0; buffer n is ‘OFF’ (default)

bit = 1; buffer n is ‘ON’

+ N13 × 213+ ... + N1 × 21+N0

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

Table 5 Address selection (I2C-bus mode)

MA1 MA0 VOLTAGE APPLIED ON CE INPUT (SW = GND)

0 0 0Vto0.1×V
0 1 open or 0.2 × VCCto 0.3 × V
1 0 0.4 × VCCto 0.6 × V
1 1 0.9 × VCCto 1.0 × V

Table 6 Test modes

T2 T1 T0 TEST MODES

0 0 0 automatic charge-pump switched off
0 0 1 automatic charge-pump switched on (note 1)
0 1 X charge-pump is ‘OFF’
1 1 0 charge-pump is sinking current
1 1 1 charge-pump is sourcing current
100f
101

CC

CC
CC

REF

1

⁄

f

2

DIV

TDA6402; TDA6403

CC

is available on pin LOCK/ADC (note 2)

is available on pin LOCK/ADC (note 2)

Notes

1. This is the default mode at power-on reset.

2. The ADC input cannot be used when these test modes are active; see Section “Read mode; R/W = 1 (see Table 8)”
for more information.

Table 7 Reference divider ratio select bits

RSA RSB REFERENCE DIVIDER RATIO

X 0 640

0 1 1024
1 1 512

Note

1. X = don’t care; may be a ‘0’ or a ‘1’.

READ MODE; R/W = 1 (see Table 8)
Data can be read from the device by setting the R/W bit

to 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH-level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge
occurs. The device will then release the data line to allow
the microcontroller to generate a STOP condition.
The POR flag is set to 1 at power-on. The flag is reset
when an end-of-data is detected by the device

(end of a READ sequence). Control of the loop is made
possible with the in-lock flag FL which indicates when the
loop is locked (FL = 1).

The automatic charge-pump switch flag (ACPS) is LOW
when the automatic charge-pump switch mode is ‘ON’ and
the loop is locked. In other conditions, ACPS = 1.
When ACPS = 0, the charge-pump current is forced to the
LOW value.

A built-in ADC is available on LOCK/ADC pin (I

2

C-bus
mode only). This converter can be used to apply AFC
information to the microcontroller from the IF section of the
television. The relationship between the bits A2, A1 and A0
is given in Table 10.

1996 Oct 15 8

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for

TDA6402; TDA6403

cable TV and VCR 2-band tuners

Table 8 Read data format

NAME BYTE

MSB

(1)

Address byte ADB 11000MA1MA0R/W=1A
Status byte SB POR FL ACPS 1 1 A2 A1 A0 −

Note

1. MSB is transmitted first.

Table 9 Description of symbols used in Table 8

SYMBOL DESCRIPTION

A acknowledge
POR power-on reset flag (POR = 1 at power-on)
FL in-lock flag (FL = 1 when the loop is locked)
ACPS automatic charge-pump switch flag:

ACPS = 0; active
ACPS = 1; not active

A2, A1, A0 digital outputs of the 5-level ADC

BITS

ACK

LSB

Table 10 A to D converter levels (note 1)

A2 A1 A0 VOLTAGE APPLIED ON ADC INPUT

1 0 0 0.60 × V
0 1 1 0.45 × VCCto 0.60 × V
0 1 0 0.30 × VCCto 0.45 × V
0 0 1 0.15 × VCCto 0.30 × V
0 0 0 0 to 0.15 × V

to 1.00 × V

CC

CC

CC
CC
CC
CC

Note

1. Accuracy is ± 0.03 × V

OWER-ON RESET

P

CC

.

Table 11 Default bits at power-on reset

BITS

NAME BYTE

MSB LSB

Address byte ADB 1 1 0 0 0 MA1 MA0 X
Divider byte 1 DB1 0 XXXXXXX
Divider byte 2 DB2 XXXXXXXX
Control byte CB 1 1 0 0 1 X 1 0
Band switch byte BB XXXX0000

1996 Oct 15 9

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

The power-on detection threshold voltage V
VCC= 2 V at room temperature. Below this threshold, the
device is reset to the power-on state.

At power-on state, the charge-pump current is set to
280 µA, the tuning voltage output is disabled, the test bits
T2, T1 and T0 are set to ‘001’ (automatic charge-pump
switch ‘ON’) and RSB is set to 1.

PUHF is ‘OFF’, which means that the UHF oscillator and
the UHF mixer are switched off. Consequently, the VHF
oscillator and the VHF mixer are switched on. PVHFL and
PVHFH are ‘OFF’, which means that the VHF tank circuit
is working in the VHF I sub-band. The tuning amplifier is
switched off until the first transmission. In that case, the
tank circuit in VHF I is supplied with the maximum tuning
voltage. The oscillator is therefore working at the end of
the VHF I sub-band.

3-wire bus mode (SW = OPEN or V

During a HIGH-level on the CE input (ENABLE line), the
data is clocked into the data register at the HIGH-to-LOW
transition of the clock. The first four bits control the PNP
ports and are loaded into the internal band switch register
on the 5
are loaded into the frequency register at the HIGH-to-LOW
transition of the chip enable line when an 18-bit or 19-bit
data word is transmitted (see Figs 4 and 5).

When a 27-bit data word is transmitted, the frequency bits
are loaded into the frequency register on the 20th rising
edge of the clock pulse and the control bits at the
HIGH-to-LOW transition of the chip enable line (see Fig.6).
In this mode, the reference divider is given by the RSA and
RSB bits (see Table 7). The test bits T2, T1 and T0, the
charge-pump bit CP, the ratio select bit RSB and the OS
bit can only be selected or changed with a 27-bit
transmission. They remain programmed if an 18-bit or
19-bit transmission occurs. Only RSA is controlled by the

th

rising edge of the clock pulse. The frequency bits

CC

)

POR

is set to

TDA6402; TDA6403

transmission length when the 18-bit or 19-bit format is
used. When an 18-bit data word is transmitted, the most
significant bit of the divider N14 is internally set to 0 and
the bit RSA is set to 1. When a 19-bit data word is
transmitted, the bit RSA is set to 0.

A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to I

It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.

OWER-ON RESET

P
The power-on detection threshold voltage V

VCC= 2 V at room temperature. Below this threshold, the
device is reset to the power-on state.

At power-on state, the charge-pump current is set to
280 µA, the tuning voltage output is disabled, the test bits
T2, T1 and T0 are set to ‘001’ (automatic charge-pump
switch ‘ON’) and RSB is set to 1.

PUHF is ‘OFF’, which means that the UHF oscillator and
the UHF mixer are switched off. Consequently, the VHF
oscillator and the VHF mixer are switched on. PVHFL and
PVHFH are ‘OFF’, which means that the VHF tank circuit
is working in the VHF I sub-band. The tuning amplifier is
switched off until the first transmission. In that case, the
tank circuit in VHF I is supplied with the maximum tuning
voltage. The oscillator is therefore working at the end of
the VHF I sub-band.

If the first sequence transmitted to the device
has 18 or 19 bits, the reference divider ratio is set to 512
or 1024, depending on the sequence length.
If the sequence has 27 bits, the reference divider ratio is
fixed by RSA and RSB bits (see Table 7).

2

C-bus mode.

POR

is set to

1996 Oct 15 10

Philips Semiconductors Preliminary specification

5 V mixer/oscillator and synthesizer for
cable TV and VCR 2-band tuners

handbook, full pagewidth

INVALID

DATA

DA

CL

CE

BAND SWITCH

DATA

FMST

PVHFL

PUHF

145 18

PVHFH

LOAD BAND SWITCH

N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

REGISTER

FREQUENCY

DATA

TDA6402; TDA6403

INVALID

DATA

LOAD FREQUENCY

REGISTER

MGE693

handbook, full pagewidth

INVALID

DATA

DA

CL

CE

Fig.4 Normal mode; 18-bit data format (RSA = 1).

BAND SWITCH

DATA

FMST

PVHFL

PUHF

PVHFH

145 19

LOAD BAND SWITCH

REGISTER

N13N14 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

FREQUENCY

DATA

LOAD FREQUENCY

INVALID

DATA

REGISTER

MGE694

1996 Oct 15 11

Fig.5 Normal mode; 19-bit data format (RSA = 0).