Philips TDA6103Q-N3, TDA6103Q-N1 Datasheet
DATA SH EET
Preliminary specification
File under Integrated Circuits, IC02
March 1994
INTEGRATED CIRCUITS
Philips Semiconductors
TDA6103Q
Triple video output amplifier
March 1994 2
Philips Semiconductors Preliminary specification
Triple video output amplifier TDA6103Q
FEATURES
• High bandwidth: 7.5 MHz typical; 60 V (peak-to-peak
value)
• High slew rate: 1600 V/µs
• Simple application with a variety of colour decoders
• Only one supply voltage needed
• Internal protection against positive appearing
Cathode-Ray Tube (CRT) flashover discharges
• One non-inverting input with a low minimum input
voltage of 1 V
• Thermal protection
• Controllable switch-off behaviour.
GENERAL DESCRIPTION
The TDA6103Q includes three video output amplifiers in
one single in-line 9-pin medium power (SIL9MP) package
SOT111BE, using high-voltage DMOS technology,
intended to drive the three cathodes of a colour CRT.
ORDERING INFORMATION
BLOCK DIAGRAM
EXTENDED TYPE
NUMBER
PACKAGE
PINS PIN POSITION MATERIAL CODE
TDA6103Q 9 DBS9 plastic SOT111BE
Fig.1 Block diagram (one amplifier shown).
FLASH-
DIODE
MIRROR 3
LEVEL-
SHIFTER 1
DIFFERENTIAL
STAGE
V
DD
1x
THERMAL
PROTECTION
V
DD
V
bias
CURRENT
SOURCES
MIRROR 2
V
DD
MIRROR 1
LEVEL-
SHIFTER 2
9,8,7
1,2,3
V
DD
V
DD
inverting
input
(3x)
V
oc
(3x)
non-inverting
input
V
ip
5
4
6
V
DD
GND
MGA968
3x
TDA6103Q
March 1994 3
Philips Semiconductors Preliminary specification
Triple video output amplifier TDA6103Q
PINNING
SYMBOL PIN DESCRIPTION
V
i1
1 inverting input 1
V
i2
2 inverting input 2
V
i3
3 inverting input 3
GND 4 ground, fin
V
ip
5 non-inverting input
V
DD
6 supply voltage
V
oc3
7 cathode output 3
V
oc2
8 cathode output 2
V
oc1
9 cathode output 1
Fig.2 Pin configuration.
1
2
3
4
5
6
7
8
9
MGA969
V
i1
GND
V
DD
V
oc3
TDA6103Q
V
i2
V
i3
V
oc2
V
oc1
V
ip
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages measured with respect to GND (pin 4);
currents as specified in Fig.1; unless otherwise specified.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see
“Handling MOS Devices”
).
QUALITY SPECIFICATION
Quality specification
“SNW-FQ-611 part E”
is applicable and can be found in the
“Quality reference pocketbook”
(ordering
number 9398 510 34011).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage 0 250 V
V
i
input voltage 0 12 V
V
idm
differential mode input voltage −6+6V
V
oc
cathode output voltage 0 V
DD
V
I
ocsmL
LOW non-repetitive peak cathode
output current
flashover discharge = 50 µC05A
I
ocsmH
HIGH non-repetitive peak cathode
output current
flashover discharge = 100 nC 0 10 A
T
stg
storage temperature −55 +150 °C
T
j
junction temperature −20 +150 °C
V
es
electrostatic handling
human body model (HBM) − tbf V
machine model (MM) − tbf V
March 1994 4
Philips Semiconductors Preliminary specification
Triple video output amplifier TDA6103Q
THERMAL RESISTANCE
Note
1. An external heatsink is necessary.
SYMBOL PARAMETER THERMAL RESISTANCE
R
th j-fin
from junction to fin; note 1 11 K/W
R
th h-a
from heatsink to ambient 18 K/W
Fig.3 Power derating curves.
(1) Infinite heatsink.
(2) No heatsink.
0 50 100–50
2
0
MGA972
150
P
tot
(W)
4
6
T ( C)
o
amb
(1)
(2)
1
3
5
Thermal protection
The internal thermal protection circuit gives a decrease of
the slew rate at high temperatures: 10% decrease at
130 °C and 30% decrease at 145 °C (typical values on the
spot of the thermal protection circuit).
Fig.4 Equivalent thermal resistance network.
Thermal protection circuit
5 K/W
6 K/W
OUTPUTS
FIN
MGA970
March 1994 5
Philips Semiconductors Preliminary specification
Triple video output amplifier TDA6103Q
CHARACTERISTICS
Operating range: T
j
= −20 to 150 °C; VDD = 180 to 210 V; Vip = 1 to 4 V.
Test conditions (unless otherwise specified): T
amb
= 25 °C; VDD = 200 V; Vip = 1.3 V; V
oc1
= V
oc2
= V
oc3
=1⁄2VDD;
C
L
= 10 pF (CL consists of parasitic and cathode capacitance); R
th h-a
= 18 K/W; measured in test circuit Fig.5.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DD
quiescent supply current 7.0 9.25 11.5 mA
I
bias
input bias current inverting inputs
(pins 1, 2 and 3)
−5 −1+1µA
I
bias
input bias current non-inverting
input (pin 5)
−15 −3+1µA
V
i(offset)
input offset voltage
(pins 1, 2 and 3)
−50 − +50 mV
∆V
i(offset)
differential input offset voltage
temperature drift between pins 1
and 5; 2 and 5; 3 and 5
− tbf − mV/K
C
icm
common-mode input capacitance
(pins 1, 2 and 3)
− 5 − pF
C
icm
common-mode input capacitance
(pin 5)
− 10 − pF
C
idm
differential mode input capacitance
between 1 and 5; 2 and 5; 3 and 5
− 1 − pF
V
oc(min)
minimum output voltage
(pins 7, 8 and 9)
V
1−5
= V
2−5
= V
3−5
= −1V − 510V
V
oc(max)
maximum output voltage
(pins 7, 8 and 9)
V
1−5
= V
2−5
= V
3−5
= 1 V;
note 1
VDD− 10 VDD− 6 − V
GB gain-bandwidth product of
open-loop gain:
V
oc1, 2, 3/Vi1-5, 2-5, 3-5
f = 500 kHz − 0.75 − GHz
B
S
small signal bandwidth
(pins 7, 8 and 9)
V
oc(p-p)
= 60 V 6 7.5 − MHz
B
L
large signal bandwidth
(pins 7, 8 and 9)
V
oc(p-p)
= 100 V 5 7 − MHz
t
pd
cathode output propagation delay
time 50% input to 50% output
(pins 7, 8 and 9)
V
oc(p-p)
= 100 V square
wave; f < 1 MHz;
tr=tf= 40 ns (pins 1, 2
and 3); see Figs 7 and 8
− 38 − ns
∆t
p
difference in cathode output
propagation time 50% input to
50% output (pins 7 and 8, 7 and 9
and 8 and 9)
V
oc(p-p)
= 100 V square
wave; f < 1 MHz;
tr=tf= 40 ns (pins 1, 2
and 3)
−10 0 +10 ns
t
r
cathode output rise time 10%
output to 90% output
(pins 7, 8 and 9)
Voc = 50 to 150 V square
wave; f < 1 MHz; tf = 40 ns
(pins 1, 2 and 3); see Fig.7
48 60 73 ns
t
f
cathode output fall time 90% output
to 10% output (pins 7, 8 and 9)
Vo = 150 to 50 V square
wave; f < 1 MHz; tr = 40 ns
(pins 1, 2 and 3); see Fig.8
48 60 73 ns
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