Philips TDA1548TZ, TDA1548T Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA1548T

Bitstream continuous calibration filter-DAC with headphone driver and DSP

Product specification

1995 Nov 15

Supersedes data of 1995 Aug 02

File under Integrated Circuits, IC01

Philips Semiconductors	Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

FEATURESPRODUCT SPECIFICATION

Easy application

∙Only first-order analog post-filtering required

∙Headphone amplifiers and digital filter integrated

∙Component saving common headphone output

∙Selectable system clock (SYSCLK) 64fs, 256fs or 384fs

∙16, 18 or 20 bits I2S-bus or LSB justified serial input format

∙Input pins suitable with 5 V low supply voltage interfacing

∙Small package (SSOP28)

∙Single rail supply (3 V).

High performance

∙Superior signal-to-noise ratio

∙Wide dynamic range

∙Continuous calibration digital-to-analog conversion combined with noise shaping technique.

Features

∙Low power dissipation

∙Digital volume control

∙Soft mute

∙Digital tone control (Bass Boost and Treble)

∙Digital de-emphasis

∙Analog control of digital sound control functions.

GENERAL DESCRIPTION

The TDA1548T is a dual CMOS digital-to-analog converter (DAC) with up-sampling filter and noise shaper and

integrated headphone driver featuring unique signal processing functions. The digital processing features are of high sound processing quality due to the wide dynamic range of the bitstream conversion technique.

The TDA1548T supports the I2S-bus data input mode with word lengths of up to 20 bits and the LSB justified serial data input format with word lengths of 16, 18 or 20 bits. The clock system is selectable (64fs, 256fs or 384fs) by means of selection pins. Two cascaded half band filters, linear interpolator and a sample-and-hold function increase the oversampling rate from 1fs to 64fs.

A second-order noise shaper converts this oversampled data into a bitstream for the 5-bit continuous calibration DACs.

On board amplifiers convert the output current to a voltage signal capable of driving a headphone or line output. The common operational amplifier application eliminates the need for capacitors.

The TDA1548T has some sound processing functions which are controllable by a potentiometer. These functions are volume, bass boost and treble. The flat/min/max switch can also be controlled by a potentiometer.

The analog values are converted to a digital code, which is then further translated internally to a set of coefficients for either volume, bass boost or treble.

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA1548T	SO28	plastic small outline package; 28 leads; body width 7.5 mm	SOT136-1
TDA1548TZ	SSOP28	plastic shrink small outline package; 28 leads; body width 5.3 mm	SOT341-1

1995 Nov 15

2

Philips Semiconductors	Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VDD	supply voltage	note 1	2.7	3.0	4.0	V
IDD	supply current	note 2	−	15	−	mA
VoFS(rms)	full-scale output voltage	VDD = 3 V	0.57	0.64	0.71	V
(THD+N)/S	total harmonic distortion	0 dB signal	−	−65	−60	dB
	plus noise as a function of
			−	0.056	0.1	%
	signal
		0 dB signal; ROL = 5 kΩ	−	−85	−78	dB
			−	0.006	0.013	%
		−60 dB signal; ROL = 32 Ω	−	−35	−30	dBA
		or ROL = 5 kΩ
			−	1.778	3.162	%
S/N	signal-to-noise ratio	A-weighted;	90	95	−	dBA
		at code 00000H
BR	input bit rate at data input	fsys = 384fs	−	48fs	−
		fsys = 256fs	−	64fs	−
		fsys = 64fs	−	64fs	−
fsys	system clock frequency		2.048	−	18.432	MHz
TC	full-scale temperature		−	±100 × 10−6	−
FS	coefficient at analog
	outputs (VOL and VOR)
Tamb	operating ambient		−20	−	+70	°C
	temperature
Notes

1.All VDD and VSS pins must be connected to the same supply or ground respectively.

2.Measured at input code 00000H and VDD = 3 V.

1995 Nov 15

3

Philips Semiconductors	Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

BLOCK DIAGRAM

		IF1	IF2	DATA	WS		BCK
		13	14	9	8		7
				SERIAL DATA INPUT					16	MUTE
									15
										DEEM
								VOLUME	22
	12			VOLUME CONTROL						AD3S
SYSCLK								AND	21
		TIMING		SOFT MUTE CONTROL				SOUND		ADVC
	17							CONTROL	20
CLSEL										ADBB
									19
				SOUND CONTROL						ADTR
							VDDA
	5						1 fs
MODE0				FILTER STAGE 1
								−
							2 fs		18
	6							OP4		ADref
MODE1
				FILTER STAGE 2				+
							4 fs
				LINEAR INTERPOLATOR				VSSA
							8 fs
			8 x OVERSAMPLING			8 x OVERSAMPLING
			(SAMPLE-AND-HOLD)			(SAMPLE-AND-HOLD)
			2nd ORDER				2nd ORDER		11	VSSD
			NOISE SHAPER			NOISE SHAPER
			DATA				DATA		10	VDDD
			ENCODER				ENCODER
FILTCL	4		16 (4-bit)				16 (4-bit)		26	FILTCR
			CALIBRATED				CALIBRATED
			CURRENT				CURRENT
		RCONV1	SOURCES				SOURCES	RCONV2
1.8 nF										1.8 nF
CEXT1		1.2 kΩ	LEFT				RIGHT	1.2 kΩ		CEXT2
	3	−	OUTPUT				OUTPUT	−	27
		OP1	SWITCHES				SWITCHES	OP2
VOL										VOR
		+		REFERENCE				+
		VDDA	16 (4-bit)	SOURCE			16 (4-bit)
			CALIBRATED				CALIBRATED
			CURRENT				CURRENT
		6 kΩ	SINKS				SINKS
Vref	25
10		6 kΩ			+	−
					OP3			TDA1548T
μF
VSSA		VSSA
		1	28			2	23	24
								MGC668
		VSSO	VDDO		VCOM		VDDA	VSSA
				Fig.1 Block diagram.
1995 Nov 15					4

Philips Semiconductors	Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

PINNING

SYMBOL	PIN	DESCRIPTION
VSSO	1	operational amplifier ground
VCOM	2	common output pin
VOL	3	left channel audio voltage output
FILTCL	4	capacitor for left channel first-order
		filter function should be connected
		between this pin and VOL (pin 3)
MODE0	5	mode 0 selection pin
MODE1	6	mode 1 selection pin
BCK	7	bit clock input
WS	8	word select input
DATA	9	data input
VDDD	10	digital supply voltage
VSSD	11	digital ground
SYSCLK	12	system clock 64fs, 256fs or 384fs
IF1	13	input format selection 1
IF2	14	input format selection 2
DEEM	15	de-emphasis input (fs = 44.1 kHz)
		(active HIGH)
MUTE	16	soft-mute input (active HIGH)
CLSEL	17	system clock selection input
ADref	18	reference voltage output to
		external potentiometer
ADTR	19	analog sense input for treble
		setting
ADBB	20	analog sense input for bass boost
		setting
ADVC	21	analog sense input for volume
		control setting
AD3S	22	3-position switch input for
		flat/min/max setting
VDDA	23	analog supply voltage
VSSA	24	analog ground
Vref	25	internal reference voltage
		(0.5VDDA typ)
FILTCR	26	capacitor for right channel
		first-order filter function should be
		connected between this pin and
		VOR (pin 27)
VOR	27	right channel audio voltage output
VDDO	28	operational amplifier supply
		voltage

handbook, halfpage
VSSO	1		28	VDDO
VCOM	2		27	VOR
VOL	3		26	FILTCR
FILTCL	4		25	Vref
MODE0	5		24	VSSA
MODE1	6		23	VDDA
BCK	7	TDA1548T	22	AD3S
WS	8		21	ADVC
DATA	9		20	ADBB
VDDD	10		19	ADTR
VSSD	11		18	ADref
SYSCLK	12		17	CLSEL
IF1	13		16	MUTE
IF2	14		15	DEEM
		MGC669

Fig.2 Pin configuration.

1995 Nov 15

5

Philips Semiconductors	Product specification

Bitstream continuous calibration filter-DAC

TDA1548T

with headphone driver and DSP

FUNCTIONAL DESCRIPTION

The TDA1548T CMOS DAC incorporates an up-sampling digital filter, a linear interpolator, a noise shaper, continuous calibrated current sources and headphone amplifiers. The 1fs input data is increased to an oversampling rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple first-order analog post-filtering.

System clock and data input format

The TDA1548T accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable at pins CLSEL, MODE0 and MODE1

(see Table 1).

The TDA1548T supports the following data input modes (see Table 2):

I2S-bus with data word length of up to 20 bits

LSB justified serial format with data word length of 16, 18 or 20 bits.

The input formats are illustrated in Fig.4. Left and right data-channel words are time multiplexed.

Analog control of digital sound processing features

Digital sound processing settings are controlled via analog sense inputs that translate an analog voltage from, for example, a potentiometer wiper to a digital code, which is then further translated internally to a set of coefficients for either treble, bass boost or volume.

The analog input value is acquired by an internal 6-bit ADC, sampling the three input pins ADVC, ADBB and ADTR and the three-mode selection pin ADS3 (see Section “Single pin three mode selection”) in a multiplexed fashion. Sampling of the input voltage is performed by a straight forward technique of linear approximation; from the starting value of 0 V, an internal linear approximation voltage is incremented periodically in steps of 1/66th of the scale, with an internal comparator detecting when the approximation value oversteps the input value. Tolerance is built in at the top and bottom end of the scale by dimensioning the resistive elements at the top and bottom of the ladder equals 1R. Thus the ladder is built up of

64 elements of value R, two of value R, making a typical quantization step size of approximately 1.5 V (ADref) divided-by-66 (amount of Rs), equals 22.7 mV.

For each multiplexed timeslot the full approximation cycle is completed, immediately after which the next input will start being sampled.

The time slot for one input lasts 64 steps at a step advance rate of 8 × fs, which amounts to 181 μs at fs = 44.1 kHz. Because four inputs are multiplexed, the sample rate for each analog input is 1.38 kHz.

A buffered version of an internally generated reference voltage is available at output pin ADref. Because the internal AD derives from the same reference voltage, this allows for optimum mapping of the external analog control value onto the useful AD input voltage range. The idea is to bias a potentiometer to ADref, using a wiper to control the input voltage between 0 V and ADref. Hysteresis is implemented to improve noise immunity of the AD in order to prevent a stable setting of the potentiometer, to a point near a quantization threshold, from producing two alternating digital codes which could give rise to audible volume or boost changes. An hysteresis of 1 LSB is implemented digital. A shift in code must be at least 2 LSB either up or down from the current value, otherwise the internal digital code will remain at the current value.

SINGLE PIN THREE MODE SELECTION

A special input pin AD3S (pin 22), controls the mode in which the sound processing block operates. Not between two but three modes; whether the DSP should follow the AD inputs applying maximum effect, the minimum effect or overrule the boost effects thereby resulting in a flat frequency characteristic in the treble and bass boost sections.

Internally the same AD is used to detect the input level present at this pin as is used for the three sound control pins. An internal bias circuit containing of two MOSTs supplies a mid-range voltage so that this input can be operated with a minimum of external components. A HIGH

or LOW input level is created by tying the pin to ADref or ground respectively, the intermediate value is achieved by

leaving the pin open-circuit.

Volume control

Since there is no headroom included into the sound control section, the volume control precedes the sound control. Full volume and neutral setting (flat) of the sound control results in a full-scale output. Any tone boost will immediately cause clipping, which can be avoided by reducing the volume setting.

1995 Nov 15

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