INTEGRATED CIRCUITS
TDA1547
Dual top-performance bitstream DAC
Product specification |
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September 1991 |
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File under Integrated Circuits, IC01 |
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Philips Semiconductors |
Product specification |
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Dual top-performance bitstream DAC |
TDA1547 |
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FEATURES
∙Top-grade audio performance
–very low harmonic distortion
–high signal-to-noise ratio
–wide dynamic range of approximately 108 dB (not A-weighted)
∙High crosstalk immunity
∙Bitstream concept
–high over-sampling rate up to 192 fs
–pulse-density modulation
–inherently monotonic
–no zero-crossing distortion
GENERAL DESCRIPTION
The TDA1547 is a dedicated one-bit digital-to-analog converter to facilitate a high fidelity sound reproduction of digital audio. The TDA1547 is extremely suitable for use in high quality audio systems such as Compact Disc and DAT players, or in digital amplifiers and digital signal processing systems. The TDA1547 is used in combination with the SAA7350 bitstream circuit, which includes the
ORDERING INFORMATION
third-order noise shaper. The excellent performance of the SAA7350 and TDA1547 bitstream conversion system is obtained by separating the noise shaping circuit and the one-bit conversion circuit over two IC's, thereby reducing the crosstalk between the digital and analog parts. The TDA1547 one-bit converter is processed in BIMOS. In the digital logic and drivers bipolar transistors are used to optimize speed and to reduce digital noise generation. In the analog part the bipolar transistors are used to obtain high performance of the operational amplifiers. Special layout precautions have been taken to achieve a high crosstalk immunity. The layout of the TDA1547 has fully separated left and right channels and supply voltage lines between the digital and analog sections.
EXTENDED TYPE |
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PACKAGE |
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NUMBER |
PINS |
PIN POSITION |
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MATERIAL |
CODE |
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TDA1547(1) |
32 |
SDIL |
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plastic |
SOT232A |
Note
1. SOT-232-1; 1996 August 23.
September 1991 |
2 |
Philips Semiconductors |
Product specification |
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Dual top-performance bitstream DAC |
TDA1547 |
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handbook, halfpage |
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VSUB |
DGND |
1 |
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32 |
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VDDD |
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VSSD |
2 |
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31 |
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IN R |
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IN L |
3 |
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30 |
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n.c. |
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n.c. |
4 |
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29 |
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CLK R |
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CLK L |
5 |
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28 |
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VDDD R |
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VDDD L |
6 |
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27 |
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VSSD R |
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VSSD L |
7 |
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26 |
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Vref R |
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Vref L |
8 |
TDA1547 |
25 |
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AGND DAC L |
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AGND DAC R |
9 |
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24 |
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– DAC R |
10 |
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23 |
– DAC L |
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+ DAC R |
11 |
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22 |
+ DAC L |
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AGND R |
12 |
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21 |
AGND L |
n.c. |
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n.c. |
13 |
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20 |
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+ OUT R |
14 |
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19 |
+ OUT L |
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– OUT R |
15 |
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18 |
– OUT L |
VSSA |
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VDDA |
16 |
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17 |
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MCD294 |
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Fig.1 Pinning diagram.
September 1991 |
3 |
Philips Semiconductors |
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Product specification |
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Dual top-performance bitstream DAC |
TDA1547 |
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PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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DGND |
1 |
0 V digital supply |
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VDDD |
2 |
5 V digital supply for both channels |
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IN R |
3 |
serial one-bit data input for the right channel |
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n.c. |
4 |
pin not connected; should preferably be connected to digital ground |
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CLK R |
5 |
clock input for the right channel |
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VDDD R |
6 |
5 V digital supply for the right channel; this voltage determines the internal logic HIGH level |
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in the right channel |
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VSSD R |
7 |
−3.5 V digital supply for the right channel; this voltage determines the internal logic LOW |
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level in the right channel |
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Vref R |
8 |
−4 V reference voltage for the right channel switched capacitor DAC |
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AGND DAC R |
9 |
0 V reference voltage for the right channel switched capacitor DAC; this pin should be |
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connected to analog ground |
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−DAC R |
10 |
output from the right negative switched capacitor DAC; feedback connection for the right |
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negative operational amplifier |
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+DAC R |
11 |
output from the right positive switched capacitor DAC; feedback connection for the right |
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positive operational amplifier |
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AGND R |
12 |
0 V reference voltage for both right channel operational amplifiers |
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n.c. |
13 |
pin not connected; should preferably be connected to analog ground |
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+OUT R |
14 |
+ output of the switched capacitor operational amplifier |
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−OUT R |
15 |
− output of the switched capacitor operational amplifier |
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VSSA |
16 |
−5 V analog supply |
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VDDA |
17 |
5 V analog supply |
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−OUT L |
18 |
− output of the switched capacitor operational amplifier |
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+OUT L |
19 |
+ output of the switched capacitor operational amplifier |
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n.c. |
20 |
pin not connected; should preferably be connected to analog ground |
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AGND L |
21 |
0 V reference voltage for both left channel operational amplifiers |
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+DAC L |
22 |
output from the left positive switched capacitor DAC; feedback connection for the left |
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positive operational amplifier |
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−DAC L |
23 |
output from the left negative switched capacitor DAC; feedback connection for left negative |
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operational amplifier |
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AGND DAC L |
24 |
0 V reference voltage for the left channel switched capacitor DAC; this pin should be |
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connected to analog ground |
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Vref L |
25 |
−4 V reference voltage for the left channel switched capacitor DAC |
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VSSD L |
26 |
−3.5 V digital supply for the left channel; this voltage determines the internal logic LOW level |
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in the left channel |
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VDDD L |
27 |
5 V digital supply for the left channel; this voltage determines the internal logic HIGH level in |
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the left channel |
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September 1991 |
4 |
Philips Semiconductors |
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Product specification |
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Dual top-performance bitstream DAC |
TDA1547 |
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SYMBOL |
PIN |
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DESCRIPTION |
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CLK L |
28 |
clock input for the left channel |
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n.c. |
29 |
pin not connected; should preferably be connected to digital ground |
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IN L |
30 |
serial one-bit data input for the left channel |
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VSSD |
31 |
−5 |
V digital supply for both channels |
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VSUB |
32 |
−5 |
V substrate voltage |
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QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITION |
MIN |
TYP |
MAX |
UNIT |
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Supply voltages |
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VDDD L. R |
positive digital supply voltage for one |
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4.5 |
5.0 |
5.5 |
V |
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channel; pins 27 and 6 |
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VDDD |
digital supply voltage for both channels; |
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4.5 |
5.0 |
5.5 |
V |
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pin 2 |
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VSSD L. R |
negative digital supply voltage for one |
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−4.0 |
−3.5 |
−3.0 |
V |
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channel; pins 26 and 7 |
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VSSD |
negative digital supply voltage for both |
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−5.5 |
−5.0 |
−4.5 |
V |
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channels; pin 31 |
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VDDA |
positive analog supply voltage; pin 17 |
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4.5 |
5.0 |
6 |
V |
VSSA |
negative analog supply voltage; pin 16 |
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−6.0 |
−5.0 |
−4.5 |
V |
Supply current |
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IDDD L. R |
positive digital supply current for one |
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− |
0.1 |
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mA |
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channel; pins 27 and 6 |
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IDDD |
digital supply current for both channels; |
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− |
29.0 |
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mA |
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pin 2 |
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ISSD L. R |
negative digital supply current for one |
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−0.1 |
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mA |
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channel; pins 26 and 7 |
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ISSD |
negative supply current for both channels; |
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− |
−28.0 |
− |
mA |
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pin 31 |
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IDDA |
positive analog supply current; pin 17 |
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− |
51.0 |
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mA |
ISSA |
negative analog supply current; pin 16 |
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− |
−51.0 |
− |
mA |
Ptot |
total power dissipation |
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− |
800 |
− |
mW |
VOUT(RMS) |
output voltage (RMS value) |
fCLK = 8.46 MHz; |
0.85 |
1.0 |
1.15 |
V |
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notes 1 and 2 |
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September 1991 |
5 |
Philips Semiconductors |
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|
Product specification |
|||
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|
|
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|
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Dual top-performance bitstream DAC |
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TDA1547 |
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SYMBOL |
PARAMETER |
CONDITION |
MIN |
TYP |
MAX |
UNIT |
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Supply current |
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(THD + N)/S |
THD + Noise; 0 dB |
1 kHz; notes 2 and 3 |
− |
−101 |
−96 |
dB |
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− |
0.0009 |
0.0016 |
% |
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(THD + N)/S |
THD + Noise; 0 dB |
f = 20 Hz to 20 kHz; |
− |
−101 |
- |
dB |
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notes 2 and 4 |
− |
0.0009 |
- |
% |
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(THD + N)/S |
THD + Noise; −20 dB |
f = 1 kHz; |
− |
−88 |
−84 |
dB |
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notes 2 and 3 |
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(THD + N)/S |
THD + Noise; −60 dB |
f = 1 kHz; |
− |
−48 |
−44 |
dB |
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notes 2 and 3 |
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S/N |
signal-to-noise ratio |
pattern 0101..; |
109 |
111 |
− |
dB |
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notes 2 and 5 |
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S/N |
signal-to-noise ratio; “A”-weighting |
pattern 0101..; |
− |
113 |
− |
dB |
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notes 2 and 5 |
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fCLK |
maximum clock frequency |
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− |
10 |
MHz |
α |
channel separation |
f = 1 kHz |
101 |
115 |
− |
dB |
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Tamb |
operating ambient temperature |
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−20 |
− |
70 |
°C |
Notes to the quick reference data
1.Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R).
2.Device measured in differential mode with external components as shown in Fig.5.
3.Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
4.Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth.
5.The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5.
FUNCTIONAL DESCRIPTION
Both channels are completely separated to reach the desired high crosstalk suppression level. Each channel consists of the following functional parts:
−One-bit input, which latches the incoming data to the system clock.
−Switch driver circuit, which generates the non-overlapping clockand data-signals that control the DAC switched capacitor networks.
−Switched capacitor network, this forms the actual DAC function, it supplies charge packets to the low-pass filter, under control of the incoming one-bit code.
−Two high performance operational amplifiers, that perform the charge packet to voltage conversion and deliver a differential output signal. The first pole of the low-pass filter is built around them.
THERMAL RESISTANCE
SYMBOL |
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PARAMETER |
MAX. |
UNIT |
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Rth j-a |
from junction to ambient |
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60 |
K/W |
September 1991 |
6 |
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