Philips TDA1545A-N2 Datasheet

DATA SH EET

Preliminary specification
Supersedes data of March 1993
File under Integrated Circuits, IC01

1997 Sep 04

INTEGRATED CIRCUITS

TDA1545A

Stereo continuous calibration DAC

1997 Sep 04 2

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FEATURES

• Space saving packages

• Low power consumption

• Low total harmonic distortion

• Wide dynamic range (16-bit resolution)

• Continuous calibration concept

• Easy application: single 3 to 5.5 V rail power supply and

output- and bias current are proportional to the supply
voltage

• Fast settling time permits 2×, 4× and 8× oversampling
(serial input) or double speed operation at 4×
oversampling

• Internal bias current ensures maximum dynamic range

• Wide operating temperature range of −40 to +85 °C

• Compatible with most of the Japanese input formats:

time multiplexed, two's complement and TTL

• No zero crossing distortion.

GENERAL DESCRIPTION

The TDA1545A is the first device of a new generation of
the digital-to-analog converters which embodies the
innovative technique of continuous calibration. The largest
bit-currents are repeatedly generated by one single
current reference source. This duplication is based upon
an internal charge storage principle having an accuracy
insensitive to ageing, temperature and process variations.

The device is fabricated in a 1.0 µm CMOS process and
features an extremely low power dissipation, small
package size and easy application. Furthermore, the
accuracy of the high coarse current combined with the
implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the continuous calibration
digital-to-analog converter is eminently suitable for use in
(portable) digital audio equipment.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA1545A DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
TDA1545AT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TDA1545ATT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

1997 Sep 04 3

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

supply voltage 3 5 5.5 V

I

DD

supply current VDD=5V;

at code 0000H

− 3.0 4.0 mA

I

FS

full-scale output current VDD= 5 V 0.9 1.0 1.1 mA

V

DD

=3V − 0.6 − mA

THD total harmonic distortion including noise

at 0 dB −−88 −78 dB
at 0 dB − 0.004 0.01 %
at −60 dB −−33 −24 dB
at −60 dB − 2.2 6 %
at −60 dB; −−35 − dB
A-weighting
at −60 dB; − 1.7 − %
A-weighting
at −60 dB; − 1.4 − %
A-weighting;
R3=R4=11kΩ;
I

FS

=2mA

S/N signal-to-noise ratio at bipolar zero

A-weighting;
at code 0000H

86 98 − dB

R3=R4=11kΩ;
I

FS

=2mA

− 101 − dB

t

cs

current settling time to ±1 LSB − 0.2 −µs
BR input bit rate at data input −−18.4 Mbits/s
f

BCK

clock frequency at clock input −−18.4 MHz
TC

FS

full-scale temperature coefficient at

analog outputs (IOL; IOR)

−±400 − ppm

P

tot

total power dissipation at code 0000H

V

DD

=5V − 15 20 mW

V

DD

=3V − 6 − mW

T

amb

operating ambient temperature −40 − +85 °C

1997 Sep 04 4

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

, full pagewidth

BCK

WS

DATA

MCD287 - 1

LEFT INPUT LATCH

LEFT BIT SWITCHES

LEFT OUTPUT LATCH

RIGHT INPUT LATCH

RIGHT BIT SWITCHES

RIGHT OUTPUT LATCH

1 CALIBRATED

SPARE

SOURCE

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

11-BIT

PASSIVE

DIVIDER

11-BIT

PASSIVE

DIVIDER

CONTROL

AND

TIMING

I

BR

I

BL

REFERENCE

SOURCE

I

BL

I

BR

3.9 kΩ

1 nF

C1

R1

IOL

V

REF

3.9 kΩ

1 nF

C2

R2

IOR

V

REF

OP1

OP2

V

out

right

V

out

left

33 kΩ

R4

22 kΩ

R3

V

REF

V

DD

100 nF

C3

ground

(9) 5

(7) 4

(10) 6

(14) 8

(13) 7

1 (1)

2 (2)

3 (6)

TDA1545A

I

REF

R

REF

11 kΩ

I

REF

(E24)

(E24)

C4

1 µF

AND AND

1 CALIBRATED

SPARE

SOURCE

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

I

REF

I

REF

Fig.1 Block diagram.

The numbers given in parenthesis refer to the TDA1545ATT (SOT402-1) version.

1997 Sep 04 5

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

PINNING

SYMBOL

PIN

DESCRIPTION

SOT96-1;

SOT97-1

SOT402-1

BCK 1 1 bit clock input
WS 2 2 word select input
DATA 3 6 data input
GND 4 7 ground
V

DD

5 9 positive supply voltage
IOL 6 10 left channel output
I

REF

7 13 reference current input
IOR 8 14 right channel output
n.c. − 3, 4, 5, 8, 11, 12 not connected

Fig.2 Pin configuration (SOT96-1; SOT97-1).

handbook, halfpage

1
2
3
4

8
7
6
5

MCD288 - 1

BCK

WS

DATA

GND

IOR
I

REF

IOL

DD

V

TDA1545A

Fig.3 Pin configuration (SOT402-1).

handbook, halfpage

TDA1545ATT

MBK230

1BCK IOR

WS I

REF

n.c. n.c.
n.c. n.c.
n.c. IOL

DATA V

DD

GND n.c.

2
3
4
5
6
7

14
13
12
11
10

9
8

1997 Sep 04 6

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is
illustrated in Fig.4. The figure shows the calibration
principle (Fig.4a) and operation principle (Fig.4b). During
calibration of the MOS current source (Fig.4a) transistor
M1 is connected as a diode by applying a reference
current. The voltage Vgs on the intrinsic gate-source
capacitance Cgs of M1 is then determined by the transistor
characteristics. After calibration of the drain current to the
reference value I

REF

, the switch S1 is opened and S2 is
switched to the other position (Fig.4b). The gate-to-source
voltage V

gs

of M1 is not changed because the charge on
Cgs is preserved. Therefore the drain current of M1 will still
be equal to I

REF

and this exact duplicate of I

REF

is now

available at the I

out

terminal. The 32 current sources and
the spare current source of the TDA1545A are
continuously calibrated (see Fig.1).

The spare current is included to allow for continuous
convertor operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by the LSB
currents.

The TDA1545A accepts input serial data formats of 16-bit
word length. Left and right data words are time
multiplexed. The most significant bit (bit 1) must always be
first. The format of data input is shown in Figs 5 and 6.
With a LOW level on the word select input (WS) input data
is placed in the right input register and with a HIGH level
on the WS input data is placed in the left input register.

The data in the input registers is simultaneously latched in
the output registers which control the bit switches.
An internal bias current I

bias

(see IBL and IBR in Fig.1) is
added to the full-scale output current IFS in order to
achieve the maximum dynamic range at the outputs of
OP1 and OP2 (see Fig.1). The reference input current I

REF

controls with gain AFS the current IFS which is a sink
current and with gain A

bias

the I

bias

which is a source

current (note 1). The current I

REF

is proportional to VDD so

the IFS and I

bias

will also be proportional to VDD (note 2)

because AFS and A

bias

are constant.

The reference output voltage V

REF

in Fig.1 is2⁄3VDD. In this
way the maximum dynamic range is achieved over the
entire power supply range. The tolerance of the reference
input current in Fig.1 depends on the tolerance of the
resistors R3, R4 and R

REF

(note 3).

Notes to the functional description

1. I

FS=AFS

× I

REF

and I

bias=Abias

× I

REF

2.

3.

V

DD1

V

DD2

-------------

I

FS1

I

FS2

----------

I

bias1

I

bias2

------------- -

==

∆I

REF

I=

REF

V

DD

R3 ∆R3 R4 ∆R4 R

REF

∆R

REF

++++ +

---------------------------------------------------------------------------------------------------------

–