Philips tda1545a DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA1545A

Stereo continuous calibration DAC

Preliminary specification
File under Integrated Circuits, IC01

March 1993

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FEATURES

• Space saving package (SO8 or DIL8)

• Low power consumption

• Low total harmonic distortion

• Wide dynamic range (16-bit resolution)

• Continuous calibration concept

• Easy application: single 3 to 5.5 V rail power supply and

output- and bias current are proportional to the supply
voltage

• Fast settling time permits 2 ×, 4 × and 8 × oversampling
(serial input) or double speed operation at 4 ×
oversampling

• Internal bias current ensures maximum dynamic range

• Wide operating temperature range of −40 °C to +85 °C

• Compatible with most of the Japanese input formats:

time multiplexed, two's complement and TTL

• No zero crossing distortion.

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

TDA1545A
TDA1545AT

(1)

(2)

PINS PIN POSITION MATERIAL CODE

8 DIL plastic SOT97
8 mini-pack plastic SO8; SOT96A

GENERAL DESCRIPTION

The TDA1545A is the first device of a new generation of
the digital-to-analog convertors which embodies the
innovative technique of continuous calibration. The largest
bit-currents are repeatedly generated by one single
current reference source. This duplication is based upon
an internal charge storage principle having an accuracy
insensitive to ageing, temperature and process variations.

The device is fabricated in a 1.0 µm CMOS process and
features an extremely low power dissipation, small
package size and easy application. Furthermore, the
accuracy of the high coarse current combined with the
implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the continuous calibration
digital-to-analog convertor is eminently suitable for use in
(portable) digital audio equipment.

PACKAGE

Notes

1. SOT97-1; 1996 August 19.

2. SOT96-1; 1996 August 19.

March 1993 2

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

I

FS

THD total harmonic distortion including noise

S/N signal-to-noise ratio at bipolar zero

t

cs

BR input bit rate at data input −−18.4 Mbits/s
f

BCK

TC

FS

P

tot

T

amb

supply voltage 3 5 5.5 V
supply current VDD = 5 V; − 3.0 4.0 mA

at code 0000H

full scale output current

= 5 V 0.9 1.0 1.1 mA

V

DD

= 3 V − 0.6 − mA

V

DD

at 0 dB −−88 −78 dB
at 0 dB − 0.004 0.01 %
at −60 dB −−33 −24 dB
at −60 dB − 2.2 6 %
at −60 dB; −−35 − dB
A-weighting
at −60 dB; − 1.7 − %
A-weighting
at −60 dB; − 1.4 − %
A-weighting;
R3 = R4 = 11 kΩ;

= 2 mA

I

FS

A-weighting;

86 98 − dB

at code 0000H
R3 = R4 = 11 kΩ;

= 2 mA

I

FS

− 101 − dB

current settling time to ±1 LSB − 0.2 −µs

clock frequency at clock input −−18.4 MHz
full scale temperature coefficient −±400 − ppm
at analog outputs (IOL; IOR)
total power dissipation at code 0000H

= 5 V − 15 20 mW

V

DD

= 3 V − 6 − mW

V

DD

operating ambient temperature −40 − +85 °C

March 1993 3

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

C4

1 nF

C1

out

left

V

C2

OP1

R1

3.9 kΩ

IOL

6

BL

I

V

1 nF

REF

out

right

V

OP2

R2

3.9 kΩ

REF

V

IOR

8

BR

I

REF

DIVIDER

I

11-BIT

PASSIVE

I

I

I

V

BR

REF

BL

REF

R4

(E24)

33 kΩ

7

REF

I

SOURCE

REFERENCE

1 µF

R3

R

(E24)

REF

DD

22 kΩ

11 kΩ

V

C3

100 nF

ground

5

4

MCD287 - 1

handbook, full pagewidth

RIGHT OUTPUT LATCH

LEFT OUTPUT LATCH

RIGHT BIT SWITCHES

LEFT BIT SWITCHES

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

11-BIT

DIVIDER

PASSIVE

&

SPARE

SOURCE

1 CALIBRATED

&

SPARE

SOURCE

1 CALIBRATED

REF

I

LEFT INPUT LATCH

RIGHT INPUT LATCH

TDA1545A

&

TIMING

CONTROL

Fig.1 Block diagram.

March 1993 4

1

BCK

2

3

WS

DATA

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input
WS 2 word select input
DATA 3 data input
GND 4 ground
V

DD

5 positive supply voltage
IOL 6 left channel output
I

REF

7 reference current input
IOR 8 right channel output

handbook, halfpage

1

BCK

2

WS

DATA

GND

TDA1545A

3
4

MCD288 - 1

Fig.2 Pin configuration.

8

IOR
I

7

REF

IOL

6

V

5

DD

March 1993 5

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration
principle (Fig.3a) and operation principle (Fig.3b). During
calibration of the MOS current source (Fig.3a) transistor
M1 is connected as a diode by applying a reference
current. The voltage Vgs on the intrinsic gate-source
capacitance Cgs of M1 is then determined by the transistor
characteristics. After calibration of the drain current to the
reference value I

, the switch S1 is opened and S2 is

REF

switched to the other position (Fig.3b). The gate-to-source
voltage Vgs of M1 is not changed because the charge on
Cgs is preserved. Therefore the drain current of M1 will still
be equal to I
available at the I

and this exact duplicate of I

REF

terminal. The 32 current sources and

out

REF

is now

the spare current source of the TDA1545A are
continuously calibrated (see Fig.1). The spare current is
included to allow for continuous convertor operation. The
output of one calibrated source is connected to an 11-bit
binary current divider consisting of 2048 transistors. A
symmetrical offset decoding principle is incorporated and
arranges the bit switching in such a way that the
zero-crossing is performed only by the LSB currents.

The TDA1545A accepts input serial data formats of 16-bit
word length. Left and right data words are time
multiplexed. The most significant bit (bit 1) must always be
first. The format of data input is shown in Fig.4 and Fig.5.
With a LOW level on the word select input (WS) input data
is placed in the right input register and with a HIGH level
on the WS input data is placed in the left input register.
The data in the input registers is simultaneously latched in
the output registers which control the bit switches.
An internal bias current I

(see IBL and IBR in Fig.1) is

bias

added to the full scale output current IFS in order to
achieve the maximum dynamic range at the outputs of
OP1 and OP2 (see Fig.1). The reference input current
IREF controls with gain AFS the current IFS which is a sink
current and with gain Abias the I
current (note 1). The current I
the IFS and I
because AFS and A
voltage V

will also be proportional to VDD (note 2)

bias

are constant. The reference output

bias

in Fig.1 is2⁄3 VDD. In this way the maximum

REF

which is a source

bias

is proportional to VDD so

REF

dynamic range is achieved over the entire power supply
range. The tolerance of the reference input current in Fig.1
depends on the tolerance of the resistors R3, R4 and R

REF

(note 3).

Notes to the functional description

1. I

2.

3. ∆I

= AFS× I

FS

V

DD1

==

------------­V

DD2

=

REF

–

I

---------------------------------------------------------------------------------------------------------

REF

R3 ∆ R3 R4 ∆R4 R

handbook, full pagewidth

I

FS1

---------­I

FS2

REF

and I

I

------------- ­I

bias1
bias2

bias

= A

V

DD

bias

× I

++++ +

S1

C

gs

REF

∆R

REF

out out

V

gs

M1

S2

REF

I

REF

S1

C

gs

(a)

(b)

I

REF

V

I

REF

S2

M1

gs

MCD289 - 1

March 1993 6

Fig.3 Calibration principle; (a) calibration, (b) operation.