Philips tda1545a DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA1545A

Stereo continuous calibration DAC

Preliminary specification
Supersedes data of March 1993
File under Integrated Circuits, IC01

1997 Sep 04

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FEATURES

• Space saving packages

• Low power consumption

• Low total harmonic distortion

• Wide dynamic range (16-bit resolution)

• Continuous calibration concept

• Easy application: single 3 to 5.5 V rail power supply and

output- and bias current are proportional to the supply
voltage

• Fast settling time permits 2×, 4× and 8× oversampling
(serial input) or double speed operation at 4×
oversampling

• Internal bias current ensures maximum dynamic range

• Wide operating temperature range of −40 to +85 °C

• Compatible with most of the Japanese input formats:

time multiplexed, two's complement and TTL

• No zero crossing distortion.

ORDERING INFORMATION

TYPE

NUMBER

TDA1545A DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
TDA1545AT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TDA1545ATT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

NAME DESCRIPTION VERSION

GENERAL DESCRIPTION

The TDA1545A is the first device of a new generation of
the digital-to-analog converters which embodies the
innovative technique of continuous calibration. The largest
bit-currents are repeatedly generated by one single
current reference source. This duplication is based upon
an internal charge storage principle having an accuracy
insensitive to ageing, temperature and process variations.

The device is fabricated in a 1.0 µm CMOS process and
features an extremely low power dissipation, small
package size and easy application. Furthermore, the
accuracy of the high coarse current combined with the
implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the continuous calibration
digital-to-analog converter is eminently suitable for use in
(portable) digital audio equipment.

PACKAGE

1997 Sep 04 2

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DD

I

FS

THD total harmonic distortion including noise

S/N signal-to-noise ratio at bipolar zero

t

cs

BR input bit rate at data input −−18.4 Mbits/s
f

BCK

TC

FS

P

tot

T

amb

supply voltage 3 5 5.5 V
supply current VDD=5V;

− 3.0 4.0 mA

at code 0000H

full-scale output current VDD= 5 V 0.9 1.0 1.1 mA

V

=3V − 0.6 − mA

DD

at 0 dB −−88 −78 dB
at 0 dB − 0.004 0.01 %
at −60 dB −−33 −24 dB
at −60 dB − 2.2 6 %
at −60 dB; −−35 − dB
A-weighting
at −60 dB; − 1.7 − %
A-weighting
at −60 dB; − 1.4 − %
A-weighting;
R3=R4=11kΩ;
I

=2mA

FS

A-weighting;

86 98 − dB

at code 0000H
R3=R4=11kΩ;

I

=2mA

FS

− 101 − dB

current settling time to ±1 LSB − 0.2 −µs

clock frequency at clock input −−18.4 MHz
full-scale temperature coefficient at

−±400 − ppm

analog outputs (IOL; IOR)
total power dissipation at code 0000H

V

=5V − 15 20 mW

DD

V

=3V − 6 − mW

DD

operating ambient temperature −40 − +85 °C

1997 Sep 04 3

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

C4

1 nF

C1

out

left

V

C2

OP1

R1

3.9 kΩ

IOL

V

1 nF

REF

out

right

V

OP2

R2

3.9 kΩ

REF

V

IOR

V

REF

R4

33 kΩ

(E24)

1 µF

R3

22 kΩ

(E24)

DD

V

C3

100 nF

ground

, full pagewidth

BR

(10) 6

BL

I

I

(14) 8

11-BIT

PASSIVE

DIVIDER

I

REF

I

I

I

BR

REF

BL

(13) 7

REF

I

SOURCE

REFERENCE

R

REF

(9) 5

11 kΩ

(7) 4

MCD287 - 1

TDA1545A

RIGHT OUTPUT LATCH

RIGHT BIT SWITCHES

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

SPARE

SOURCE

1 CALIBRATED

Fig.1 Block diagram.

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

AND AND

SPARE

SOURCE

1 CALIBRATED

LEFT INPUT LATCH

RIGHT INPUT LATCH

LEFT OUTPUT LATCH

LEFT BIT SWITCHES

11-BIT

DIVIDER

PASSIVE

I

REF

1997 Sep 04 4

1 (1)

BCK

2 (2)

WS

AND

TIMING

CONTROL

3 (6)

DATA

The numbers given in parenthesis refer to the TDA1545ATT (SOT402-1) version.

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

PINNING

PIN

SYMBOL

SOT96-1;

SOT97-1

SOT402-1

BCK 1 1 bit clock input
WS 2 2 word select input
DATA 3 6 data input
GND 4 7 ground
V

DD

5 9 positive supply voltage
IOL 6 10 left channel output
I

REF

7 13 reference current input
IOR 8 14 right channel output
n.c. − 3, 4, 5, 8, 11, 12 not connected

DESCRIPTION

handbook, halfpage

BCK

WS

DATA

GND

1
2
3
4

TDA1545A

MCD288 - 1

8

IOR
I

7

IOL

6

V

5

Fig.2 Pin configuration (SOT96-1; SOT97-1).

REF

DD

handbook, halfpage

Fig.3 Pin configuration (SOT402-1).

1BCK IOR
2

WS I

3

n.c. n.c.

4

n.c. n.c.

TDA1545ATT

5

n.c. IOL

6

DATA V

7

GND n.c.

14
13
12
11
10

9
8

MBK230

REF

DD

1997 Sep 04 5

Philips Semiconductors Preliminary specification

Stereo continuous calibration DAC TDA1545A

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is
illustrated in Fig.4. The figure shows the calibration
principle (Fig.4a) and operation principle (Fig.4b). During
calibration of the MOS current source (Fig.4a) transistor
M1 is connected as a diode by applying a reference
current. The voltage Vgs on the intrinsic gate-source
capacitance Cgs of M1 is then determined by the transistor
characteristics. After calibration of the drain current to the
reference value I

, the switch S1 is opened and S2 is

REF

switched to the other position (Fig.4b). The gate-to-source
voltage V

of M1 is not changed because the charge on

gs

Cgs is preserved. Therefore the drain current of M1 will still
be equal to I
available at the I

and this exact duplicate of I

REF

terminal. The 32 current sources and

out

REF

is now

the spare current source of the TDA1545A are
continuously calibrated (see Fig.1).

The spare current is included to allow for continuous
convertor operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by the LSB
currents.

The TDA1545A accepts input serial data formats of 16-bit
word length. Left and right data words are time
multiplexed. The most significant bit (bit 1) must always be
first. The format of data input is shown in Figs 5 and 6.
With a LOW level on the word select input (WS) input data
is placed in the right input register and with a HIGH level
on the WS input data is placed in the left input register.

The data in the input registers is simultaneously latched in
the output registers which control the bit switches.
An internal bias current I

(see IBL and IBR in Fig.1) is

bias

added to the full-scale output current IFS in order to
achieve the maximum dynamic range at the outputs of
OP1 and OP2 (see Fig.1). The reference input current I

REF

controls with gain AFS the current IFS which is a sink
current and with gain A
current (note 1). The current I
the IFS and I

will also be proportional to VDD (note 2)

bias

because AFS and A
The reference output voltage V

the I

bias

are constant.

bias

which is a source

bias

is proportional to VDD so

REF

in Fig.1 is2⁄3VDD. In this

REF

way the maximum dynamic range is achieved over the
entire power supply range. The tolerance of the reference
input current in Fig.1 depends on the tolerance of the
resistors R3, R4 and R

(note 3).

REF

Notes to the functional description

× I

1. I

2.

3.

FS=AFS

V

DD1

==

------------­V

DD2

∆I

REF

and I

I

FS1

---------­I

FS2

I=

REF

REF

bias=Abias

I

bias1

------------- ­I

bias2

–

--------------------------------------------------------------------------------------------------------­R3 ∆R3 R4 ∆R4 R

++++ +

× I

REF

V

DD

REF

∆R

REF

1997 Sep 04 6