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TDA1313; TDA1313T
Stereo continuous calibration DAC
(CC-DAC)
Objective specification
File under Integrated Circuits, IC01
July 1993
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Philips Semiconductors Objective specification
Stereo continuous calibration DAC
(CC-DAC)
FEATURES
• 4/8 × oversampling (multiplexed/simultaneous input)
possible
• Voltage output (capable of driving headphone)
• Space saving package (SO16 or DIL16)
• Low power consumption
• Wide dynamic range (16-bit resolution)
• Continuous Calibration concept
• Easy application:
– single 3 to 5.5 V supply rail
– output voltage is proportional to the supply voltage
– integrated current-to-voltage converter
• Internal bias current ensures maximum dynamic range
• Wide operating temperature range (−40 °C to +85 °C)
• Compatible with most current Japanese input format
multiplexed/simultaneous, two's complement and
CMOS)
• No zero crossing distortion
• Cost efficient
• High signal-to-noise ratio
• Low total harmonic distortion.
TDA1313; TDA1313T
GENERAL DESCRIPTION
The TDA1313; 1313T is a voltage driven digital-to-analog
converter, and is of a new generation of DACs which
incorporates the innovative technique of Continuous
Calibration (CC). The largest bit-currents are repeatedly
generated from one single current reference source. This
duplication is based upon an internal charge storage
principle having an accuracy which is insensitive to
ageing, temperature and process variations.
The TDA1313; 1313T is fabricated in a 1.0 µm CMOS
process and features an extremely low power dissipation,
small package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the CC-DAC is eminently
suitable for use in (portable) digital audio equipment.
ORDERING INFORMATION
EXTENDED TYPE NUMBER
TDA1313
TDA1313T
Notes
1. SOT38-1; 1996 August 15.
2. SOT109-1; 1996 August 15.
(1)
(2)
PACKAGE
PINS PIN POSITION MATERIAL CODE
16 DIL plastic SOT38GG
16 SO16 plastic SOT109AG
July 1993 2
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Philips Semiconductors Objective specification
Stereo continuous calibration DAC
TDA1313; TDA1313T
(CC-DAC)
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
I
DD
V
FS
(THD+N)/S total harmonic distortion
S/N signal-to-noise ratio at
t
CS
BR input bit rate at data input −−18.4 Mbits/s
f
BCK
TC
FS
T
amb
P
tot
supply voltage 3.0 5.0 5.5 V
supply current VDD = 5 V; at code
− 8 9.5 mA
0000H
full scale output voltage VDD = 5 V 3.8 4.2 4.6 V
at 0 dB signal level −−88 −81 dB
plus noise
at 0 dB signal level;
see Fig.8
− 0.004 0.009 %
−−70 − dB
− 0.03 − %
at −60 dB signal level −−36 −28 dB
− 1.6 4.0 %
at −60 dB; A-weighted −−38 − dB
− 1.3 − %
bipolar zero
current setting time to
A-weighted at code
0000H
93 98 − dB
− 0.2 −µs
±1LSB
clock frequency at clock
−−18.4 MHz
input
full scale temperature
− 400 − ppm
coefficient at analog outputs
(VOL; VOR)
operating ambient
−40 − +85 °C
temperature
total power dissipation VDD = 5 V; at code
− 40 53 mW
0000H
= 3 V; at code
V
DD
− 15 − mW
0000H
July 1993 3
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Philips Semiconductors Objective specification
Stereo continuous calibration DAC
(CC-DAC)
OR
V
C2
1 nF
RIN
7
R2
ROUT
8
4 kΩ
OP2
REF
V
11-BIT
PASSIVE
DIVIDER
C6
1 µF
REF
V
4
SOURCE
REFERENCE
TDA1313; TDA1313T
MGE230
DDA
V
C5
100 nF
12 11
SSA
V
handbook, full pagewidth
RIGHT INPUT REGISTER
LEFT INPUT REGISTER
R1
10
LIN
RIGHT BIT SWITCHES
RIGHT OUTPUT REGISTER
LEFT BIT SWITCHES
LEFT OUTPUT REGISTER
OP1
4 kΩ
9
LOUT
C1
1 nF
OL
V
32 (5-BIT)
CURRENT
SOURCES
CALIBRATED
32 (5-BIT)
CURRENT
SOURCES
CALIBRATED
11-BIT
DIVIDER
PASSIVE
REF
V
1 CALIBRATED
SPARE SOURCE
1 CALIBRATED
SPARE SOURCE
3
16
4/8FSSEL
TDA1313
AND
TIMING
CONTROL
1215
BCK
SI/LSI
LRSEL/RSI
DDO
C4
C3
V
100 nF
SSO
V
DDD
V
100 nF
SSD
V
TDA1313T
56
13 14
WS
Fig.1 Block diagram.
July 1993 4
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Philips Semiconductors Objective specification
Stereo continuous calibration DAC
(CC-DAC)
PINNING
SYMBOL PIN DESCRIPTION
LRSEL/RSI 1 left/right select; right serial
input
SI/LSI 2 serial input; left serial input
4/8FSSEL 3 4/8 oversampling select
V
REF
V
SSO
V
DDO
RIN 7 right analog input
ROUT 8 right analog output
LOUT 9 left analog output
LIN 10 left analog input
V
DDA
V
SSA
V
SSD
V
DDD
WS 15 word select
BCK 16 bit clock input
4 reference voltage output
5 operational amplifier ground
6 operational amplifier supply
voltage
11 analog supply voltage
12 analog ground
13 digital ground
14 digital supply voltage
handbook, halfpage
LRSEL/RSI
4/8FSSEL
TDA1313; TDA1313T
1
SI/LSI
2
3
4
V
REF
V
SSO
V
DDO
RIN
ROUT
Fig.2 Pin configuration.
TDA1313
TDA1313T
5
6
7
8
MGE229
16
BCK
15
WS
14
V
DDD
13
V
SSD
12
V
SSA
11
V
DDA
10
LIN
9
LOUT
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage Vgs on the
intrinsic gate-source capacitance Cgs of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
REF
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage Vgs of M1 is
not changed because the charge on Cgs is preserved.
Therefore, the drain current of M1 will still be equal to I
and this exact duplicate of I
is now available at the I
REF
REF
O
terminal.
In the TDA1313; 1313T, 32 current sources and one spare
current source are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current devider which
consists of 2048 transistors. A symmetrical offset
decoding principle is incorporated and arranges the bit
switching in such a way that the zero-crossing is
performed by switching only the LSB currents.
The TDA1313; T (CC-DAC) accepts serial input data
format of 16 bit word length. The most significant bit (bit 1)
must always be first. The timing is illustrated in Fig.4 and
,
the input data formats are illustrated in Figs 5 and 6.
Data is placed in the right and left input registers (Fig.1).
The data in the input registers is simultaneously latched to
the output registers which control the bit switches.
V
and VFS are proportional to VDD.
REF
Where: V
DD1/VDD2
= V
FS1
/V = V
REF1/VREF2
July 1993 5