Philips TDA1313T installation Guide

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TDA1313; TDA1313T

Stereo continuous calibration DAC (CC-DAC)

Objective speciﬁcation File under Integrated Circuits, IC01

July 1993

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

FEATURES

• 4/8 × oversampling (multiplexed/simultaneous input) possible

• Voltage output (capable of driving headphone)

• Space saving package (SO16 or DIL16)

• Low power consumption

• Wide dynamic range (16-bit resolution)

• Continuous Calibration concept

• Easy application:

– single 3 to 5.5 V supply rail – output voltage is proportional to the supply voltage – integrated current-to-voltage converter

• Internal bias current ensures maximum dynamic range

• Wide operating temperature range (−40 °C to +85 °C)

• Compatible with most current Japanese input format

multiplexed/simultaneous, two's complement and CMOS)

• No zero crossing distortion

• Cost efficient

• High signal-to-noise ratio

• Low total harmonic distortion.

TDA1313; TDA1313T

GENERAL DESCRIPTION

The TDA1313; 1313T is a voltage driven digital-to-analog converter, and is of a new generation of DACs which incorporates the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated from one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy which is insensitive to ageing, temperature and process variations.

The TDA1313; 1313T is fabricated in a 1.0 µm CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.

ORDERING INFORMATION

EXTENDED TYPE NUMBER

TDA1313

TDA1313T

Notes

1. SOT38-1; 1996 August 15.

2. SOT109-1; 1996 August 15.

(1)

(2)

PACKAGE

PINS PIN POSITION MATERIAL CODE

16 DIL plastic SOT38GG 16 SO16 plastic SOT109AG

July 1993 2

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC

TDA1313; TDA1313T

(CC-DAC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(THD+N)/S total harmonic distortion

S/N signal-to-noise ratio at

BR input bit rate at data input −−18.4 Mbits/s f

BCK

amb

tot

supply voltage 3.0 5.0 5.5 V supply current VDD = 5 V; at code

− 8 9.5 mA

0000H

full scale output voltage VDD = 5 V 3.8 4.2 4.6 V

at 0 dB signal level −−88 −81 dB

plus noise

at 0 dB signal level; see Fig.8

− 0.004 0.009 %

−−70 − dB

− 0.03 − %

at −60 dB signal level −−36 −28 dB

− 1.6 4.0 %

at −60 dB; A-weighted −−38 − dB

− 1.3 − %

bipolar zero current setting time to

A-weighted at code 0000H

93 98 − dB

− 0.2 −µs

±1LSB

clock frequency at clock

−−18.4 MHz

input full scale temperature

− 400 − ppm coefﬁcient at analog outputs (VOL; VOR)

operating ambient

−40 − +85 °C temperature

total power dissipation VDD = 5 V; at code

− 40 53 mW

0000H

= 3 V; at code

− 15 − mW

0000H

July 1993 3

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

C2

1 nF

RIN 7

ROUT

4 kΩ

OP2

REF

11-BIT

PASSIVE

DIVIDER

C6

1 µF

REF

SOURCE

REFERENCE

TDA1313; TDA1313T

MGE230

DDA

100 nF

12 11

SSA

handbook, full pagewidth

RIGHT INPUT REGISTER

LEFT INPUT REGISTER

10 LIN

RIGHT BIT SWITCHES

RIGHT OUTPUT REGISTER

LEFT BIT SWITCHES

LEFT OUTPUT REGISTER

OP1

4 kΩ

LOUT

C1

1 nF

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

32 (5-BIT)

CURRENT

SOURCES

CALIBRATED

11-BIT

DIVIDER

PASSIVE

REF

1 CALIBRATED

SPARE SOURCE

1 CALIBRATED

SPARE SOURCE

4/8FSSEL

TDA1313

AND

TIMING

CONTROL

1215

BCK

SI/LSI

LRSEL/RSI

DDO

100 nF

SSO

DDD

100 nF

SSD

TDA1313T

13 14

Fig.1 Block diagram.

July 1993 4

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

PINNING

SYMBOL PIN DESCRIPTION

LRSEL/RSI 1 left/right select; right serial

input SI/LSI 2 serial input; left serial input 4/8FSSEL 3 4/8 oversampling select V

REF

SSO

DDO

RIN 7 right analog input ROUT 8 right analog output LOUT 9 left analog output LIN 10 left analog input V

DDA

SSA

SSD

DDD

WS 15 word select BCK 16 bit clock input

4 reference voltage output 5 operational ampliﬁer ground 6 operational ampliﬁer supply

voltage

11 analog supply voltage 12 analog ground 13 digital ground 14 digital supply voltage

handbook, halfpage

LRSEL/RSI

4/8FSSEL

TDA1313; TDA1313T

SI/LSI

2 3 4

REF

SSO

DDO

RIN

ROUT

Fig.2 Pin configuration.

TDA1313

TDA1313T

5 6 7 8

MGE229

BCK

DDD

SSD

SSA

DDA

LIN

LOUT

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value I

REF

the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to I and this exact duplicate of I

is now available at the I

REF

terminal. In the TDA1313; 1313T, 32 current sources and one spare

current source are continuously calibrated (see Fig.1). The spare current source is included to allow continuous

converter operation. The output of one calibrated source is connected to an 11-bit binary current devider which consists of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed by switching only the LSB currents.

The TDA1313; T (CC-DAC) accepts serial input data format of 16 bit word length. The most significant bit (bit 1) must always be first. The timing is illustrated in Fig.4 and

the input data formats are illustrated in Figs 5 and 6. Data is placed in the right and left input registers (Fig.1).

The data in the input registers is simultaneously latched to the output registers which control the bit switches.

and VFS are proportional to VDD.

REF

Where: V

DD1/VDD2

= V

FS1

/V = V

REF1/VREF2

July 1993 5

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

handbook, halfpage

Fig.3 Calibration principle; (a) calibration (b) operation.

(a) (b)

REF

TDA1313; TDA1313T

REF

MGE231

REF

Table 1 Mode application

4/8FSSEL LRSEL/RSI MODE FIGURE

0 1 4FS/left = HIGH 6 0 0 4FS/left = LOW 6 1 data right 8FS 5

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V T T T V

DD XTAL stg amb ES

supply voltage − 6.0 V maximum crystal temperature − +150 °C storage temperature −55 +150 °C operating ambient temperature −40 +85 °C electrostatic handling note 1 −2000 +2000 V

note 2 −200 +200 V

Notes

1. Human body model: C = 100 pF; R = 1500 Ω; 3 zaps positive and negative.

2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and negative.

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

th j-a

from junction to ambient in free air

DIL16 75 K/W SO16 120 K/W

July 1993 6

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC

TDA1313; TDA1313T

(CC-DAC)

CHARACTERISTICS

= V

DDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

DDD

DDA

DDO

PSRR power supply ripple rejection at code 0000H; note 1 − 30 − dB

Digital inputs; pins WS, BCK, 4/8FSSEL, LRSEL/RSI and SI/LSI

 input leakage current LOW VI = 0.V −− 10 µA

I

 input leakage current HIGH VI = 5.5 V −− 10 µA

I

BCK

BR bit rate data input −− 18.4 Mbits/s f

Timing (see Fig.4) t

BCKH

BCKL

SU;DAT

HD:DAT

HD:WS

SU;WS

DDA

= V

DDO

= 5 V; T

= 25 °C; measured in Fig.7; unless otherwise speciﬁed.

amb

supply voltage 3.0 5.0 5.5 V total supply current at code 0000H − 8.0 9.5 mA digital supply current at code 0000H; no clock

− 0.2 − mA

running analog supply current − 4.6 5.5 mA operational ampliﬁer supply − 3.4 4 mA current

clock frequency −− 18.4 MHz

word select input frequency −− 384 kHz

rise time −− 12 ns fall time −− 12 ns bit clock cycle time 54 −− ns bit clock pulse width HIGH 15 −− ns bit clock pulse width LOW 15 −− ns data set-up time 12 −− ns data hold time to bit clock 10 −− ns word select hold time 10 −− ns word select set-up time 12 −− ns

July 1993 7

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC

TDA1313; TDA1313T

(CC-DAC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog outputs; pins V

V TC

full-scale voltage 3.8 4.2 4.6 V full-scale temperature

coefﬁcient

REF

load resistance 3 −− kΩ load capacitance −− 200 pF reference output voltage 3.16 3.33 3.5 V output DC voltage 2.25 2.5 2.75 V

(THD+N)/S total harmonic distortion plus

noise

current settling time to ±1 LSB

α channel separation 86 95 − dB

 unbalance between outputs note 2 − 0.2 0.3 dB

δI

 time delay between outputs −±0.2 −µs

t

S/N signal-to-noise ratio at

bipolar zero

and V

−±400 − ppm

at 0 dB signal level; note 2 −−88 −81 dB

− 0.004 0.009 % at 0 dB signal level; see −−70 − dB Fig.8 − 0.03 − % at −60 dB signal level;

note 2 at −60 dB signal level;

A-weighted; note 2 at 0 dB signal level;

f = 20 Hz to 20 kHz

−−36 −28 dB

− 1.6 4.0 %

−−38 − dB

− 1.3 − %

−−84 −70 dB

− 0.006 0.03 %

− 0.2 −µs

see Fig.8 − 70 − dB

A-weighted; at code 0000H 93 98 − dB

Notes

1. V

= 1% of the supply voltage; f

ripple

= 100 Hz.

ripple

2. Measured with 1 kHz sinewave generated at a sampling rate of 384 kHz.

QUALITY SPECIFICATION

In accordance with UZW-BO/FQ-0601.

July 1993 8

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

BCK

DATAR DATAL

<12

r

>15

HB

CY

>54

<12

f

LB

>15

LSB

HD; WS

>10

MSB

>12

SU; WS

SAMPLE OUT

TDA1313; TDA1313T

SU; DAT

>12

HD; DAT

>10

MGE234

Fig.4 Timing of input signals.

July 1993 9

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

MGE235

LSB

TDA1313; TDA1313T

LSB

RIGHT

MSB

MGE236

RIGHT



RSI

MSB

LSI

BCK

SAMPLE OUT

LSB

Fig.5 Format of input signals at 8FS.

MSB

BCK

LEFT

WS if

LRSEL = 1

LEFT

WS if

LRSEL = 0

Fig.6 Format of input signals at 4FS.

SAMPLE OUT

July 1993 10

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

APPLICATION INFORMATION

handbook, full pagewidth

OUTL

200

kΩ

1 nF

3

9 3

16 1 2 15

13 14

100 nF

DDD

TDA1313T

100 nF

DDO

12 11

100 nF

DDA

TDA1313; TDA1313T

1 nF

200

OUTR

MGE232

22 µF

kΩ

3

handbook, full pagewidth

OUTL

Fig.7 TDA1313T as line driver with 3 kΩ/200 pF load.

8.2

2

kΩ

100 µF 100 µF

32 Ω 32 Ω

3 16 1 2 15

13 14

100 nF

DDD

TDA1313T

100 nF

DDO

12 11

100 nF

DDA

8.2

2

kΩ

22 µF

MGE233

OUTR

Fig.8 TDA1313T as headphone driver with 32 Ω load.

July 1993 11

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

PACKAGE OUTLINES

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

seating plane

w M

TDA1313; TDA1313T

SOT38-1

(e )

pin 1 index

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

4.7 0.51 3.7

OUTLINE VERSION

SOT38-1

min.

1 2

max.

0.15

IEC JEDEC EIAJ

050G09 MO-001AE

1.40

1.14

0.055

0.045

0.53

0.38

0.021

0.015

cEe M

0.32

0.23

0.013

0.009

REFERENCES

21.8

21.4

0.86

0.84

scale

(1) (1)

6.48

6.20

0.26

0.24

(1)

0.30

0.15

0.13

3.9

3.4

8.25

7.80

0.32

0.31

EUROPEAN

PROJECTION

9.5

8.3

0.37

0.33

0.2542.54 7.62

0.010.100.0200.19

ISSUE DATE

92-10-02 95-01-19

max.

2.2

0.087

July 1993 12

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

SO16: plastic small outline package; 16 leads; body width 3.9 mm

TDA1313; TDA1313T

SOT109-1

v M

pin 1 index

0 2.5 5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

max.

1.75

0.069

A1A

0.25

0.10

0.0098

0.0039

1.45

1.25

0.057

0.049

0.25

0.01

0.49

0.25

0.36

0.19

0.0098

0.019

0.0075

0.014

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

10.0

9.8

0.39

0.38

scale

eHELLpQZywv θ

4.0

1.27

3.8

0.16

0.050

0.15

w M

6.2

5.8

0.24

0.23

1.05

0.041

detail X

1.0

0.7

0.4

0.6

0.028

0.039

0.020

0.016

(A )

0.25 0.1

0.25

0.01

0.01 0.004

0.7

0.3

0.028

0.012

OUTLINE

VERSION

SOT109-1

IEC JEDEC EIAJ

076E07S MS-012AC

REFERENCES

July 1993 13

EUROPEAN

PROJECTION

ISSUE DATE

91-08-13 95-01-23

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC (CC-DAC)

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

DIP

OLDERING BY DIPPING OR BY WA VE

S The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

REFLOW SOLDERING Reflow soldering techniques are suitable for all SO

packages.

(order code 9398 652 90011).

). If the

stg max

TDA1313; TDA1313T

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

AVE SOLDERING

W Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must be parallel to the solder flow.

• The package footprint must incorporate solder thieves at the downstream end.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

July 1993 14

Philips Semiconductors Objective speciﬁcation

Stereo continuous calibration DAC

TDA1313; TDA1313T

(CC-DAC)

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

July 1993 15

Philips TDA1313T installation Guide

Specifications and Main Features

Frequently Asked Questions

User Manual