Philips TDA10045H User Manual

INTEGRATED CIRCUITS

DATA SH EET

TDA10045H

DVB-T channel receiver

Product speciﬁcation Supersedes data of 2000 Jun 21 File under Integrated Circuits, IC02

2001 Nov 08

Philips Semiconductors Product speciﬁcation

DVB-T channel receiver TDA10045H

FEATURES

• 2 and 8 kbytes Coded Orthogonal Frequency Division Multiplexer (COFDM) demodulator (fully DVB-T compliant: ETSI 300-744)

• All modes supported, including hierarchical modes

• Fully automatic transmission parameters detection

(including Fast Fourier Transformer (FFT) size and guard interval)

• Digital Signal Processor (DSP) based synchronization (software can be upgraded on the fly)

• No extra-host software required

• On-chip 10-bit Analog-to-Digital Converter (ADC)

• 2nd or 1st IF variable analog input

• Only fundamental crystal oscillator required (4 MHz typical ±100 ppm)

• 6, 7 and 8 MHz channels with the same crystal

• Pulse killer algorithm to protect against impulse noise

• Digital frequency correction (±90 kHz)

• Frequency offset (±1/6MHz) automatic estimator to

speed-up the scan

• RF tuner input power measurement

• Parallel or serial transport stream interface

• BER measurement (before and after Viterbi decoder)

• Signal-to noise ratio estimation

• Constellation, CSI and channel frequency response

outputs

• TPS bits I2C-bus readable (including spare ones)

• Controllable dedicated I2C-bus for the tuner

(5 V tolerant)

• 3 low frequency spare DACs and 2 spare inputs

• CMOS 0.2 µm technology.

GENERAL DESCRIPTION

The TDA10045H is a single-chip channel receiver for 2 and 8 kbytes COFDM modulated signals based on the ETSI specification (ETSI 300-744). The device interfaces directly to anIF signal, which could be either 1st or 2nd IF and integrates a 10-bit Analog-to-Digital Converter (ADC), a Numerically Controlled Oscillator (NCO) and a Phase-Locked Loop (PLL), simplifying external logic requirements and limiting system costs.

The TDA10045H performs all the COFDM demodulation tasks from IF signal to the MPEG-2 transport stream. An internal DSP core manages the synchronization and the control of the demodulation process, and implements specially developed software for robustness against co-channelandadjacent channel interference, to deal with Single Frequency Network (SFN) echo situations, and to assist in a very fast scan of the bandwidth. After baseband conversion and FFT demodulation, the channel frequency response is estimated, which is based on the scattered pilots, and filtered in both time and frequency domains. This estimation is used as a correction on the signal, carrier by carrier. A common phase error and estimator is usedtodealwiththetunerphasenoise.The Forward Error Correction (FEC) decoder is automatically synchronized by the frame synchronization algorithm that uses the TPS information included in the modulation. An embedded ‘pulse killer’ algorithm enables the bad effects of short and strong impulsive noise interference that could be caused by electrical domestic devices and/or car traffic to be greatly reduced.

APPLICATIONS

• DVB-T fully compatible

• Digital data transmission using COFDM modulation.

2001 Nov 08 2

This device is controlled via an I2C-bus (master). The chip provides 2 switchable I2C-buses derived from the master: a tuner I2C-bus to be disconnected from the I2C-bus master when not necessary and an EEPROM I2C-bus. The DSP software code can be fed to the chip via the master I2C-bus or via the dedicated EEPROM I2C-bus.

Designed in 0.2 µm CMOS technology and housed in a 100 pin QFP package, the TDA10045H operates over the commercial temperature range.

Philips Semiconductors Product speciﬁcation

DVB-T channel receiver TDA10045H

ORDERING INFORMATION

TYPE

NUMBER

TDA10045H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

NAME DESCRIPTION

body 14 × 20 × 2.8 mm

PACKAGE

VERSION

SOT317-2

2001 Nov 08 3

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2001 Nov 08 4

VAGC

BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

DVB-T channel receiver TDA10045H

digital IF

FI (9:0)

analog IF

(VIM, VIP)

SACLK

XIN

D C

PLL

SP_IN(1:0)

DS_SPARE(3:1)

SCL_EEP SDA_EEP

SCL SDA

SCL_TUN

SDA_TUN

BASEBAND

CONVERSION

spare inputs

3 SPARE ∆Σ

optional

I2C-BUS

INTERFACE

MPEG-2

OUTPUT

INTERFACE

RECOVERY

3* 10

DESCRAMBLER

CPT_UNCOR

DIGITAL FRONT-END

∆ΣAGC

TIME

(NCO)

CARRIER

RECOVERY

AND COFDM

DEMODULATION

DSP CORE

SYNCHRONIZATION

FREQUENCY, TIME, FRAME, RECOVERY

FFT WINDOW POSITIONING

TPS DECODING

DECODER

CHANNEL DECODER

OUTER

FORNEY

DE-INTERLEAVER

FFT

COARSE

TIME

ESTIMATOR

TDA10045H

VBER

VITERBI

DECODER

COFDM

spectrum

CONFIDENCE

CALCULATION

confidence

frequency response

BIT

DE-INTERLEAVER

CBER

CHANNEL ESTIMATION

AND CORRECTION

CPE

CALCULATION

PARTIAL CHANNEL

ESTIMATION

TIME

INTERPOLATION

FREQUENCY

INTERPOLATION

CHANNEL

CORRECTION

(I,Q)

constellation

INNER

FREQUENCY

DE-INTERLEAVER

AND DE-MAPPER

Fig.1 Block diagram.

handbook, full pagewidth

MGU414

Philips Semiconductors Product speciﬁcation

DVB-T channel receiver TDA10045H

PINNING

SYMBOL PIN TYPE DESCRIPTION

DDD33

SSD

DS_SPARE3 3 O spare delta-sigma output; managed by the DSP to generate an analog level

VAGC 4 O output value from the Delta-Sigma modulator, used to control a log-scaled

SCL_EEP 5 O extra I

DDD33

SSD

SDA_EEP 8 I/OD extra I

SCL_TUN 9 OD

SDA_TUN 10 I/OD tuner I

SCL 11 I SDA 12 I/OD I

n.c. 13 − not connected CLR# 14 I EEPADDR 15 I

SADDR[1:0] 16 and 17 I

DDD18

SSD

TM[3:0] 20 to 23 I SCAN_EN 24 I V

DDD50

SSD

DWNLOAD 27 I

SP_IN[1:0] 28 and 29 I

1 − digital supply voltage for the pads (3.3 V typ.) 2 − digital ground supply (0 V

(after a RC low-pass ﬁlter)

ampliﬁer (after analog ﬁltering)

C-bus clock to download DSP code from an external EEPROM (optional

mode); can be connected to the master I2C-bus 6 − digital supply voltage for the pads (3.3 V typ.) 7 − digital ground supply (0 V)

C-bus data bus to download DSP code from an external EEPROM (optional mode). It can be connected to the master I2C-bus; this pin is open-drain which requires an external pull-up resistor (to V

DDD33

or V

DDD50

even if not used.

(1)

tuner I2C-bus serial clock signal; this signal is derived from the master SCL and is open-drain which requires an external pull-up resistor (to V

DDD33

or V

DDD50

even if not used

C-bus serial data signal; this signal is derived from the master SDA and is open-drain which requires an external pull-up resistor (to V

DDD33

or V

DDD50

even if not used

(2)

I2C-bus master serial clock; up to 700 kbit/s

C-bus master serial data input/output, open-drain I/O pad, which requires an

external pull-up resistor (to V

(2)

asynchronous reset signal; active LOW

(2)

EEPADDR is the LSB of the I2C-bus address of the EEPROM. The MSBs are

DDD33

or V

DDD50

)

internally set to 101000. Therefore the complete I2C-bus address of the EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR.

(2)

SADDR[1:0] are the 2 LSBs of the I2C-bus address of the TDA10045; the MSBs are internally set to 00010; therefore the complete I2C-bus address of the TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0]

18 − digital supply voltage for the core (1.8 V typ.) 19 − digital ground supply (0 V)

(2)

test mode bus; for test purpose; must be set to ‘0000’

(2)

scan enable for production test; connected to GND

25 − digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V

tolerant I/O is not required

26 − digital ground supply (0 V)

(2)

processor control, boot mode; if set to logic 0, the DSP downloads the software from an external EEPROM on the dedicated I2C-bus (pins SDA_EEP and SCL_EEP). If set to logic 1 the software is downloaded in the I2C-bus register CODE_IN from the host; in this case the external EEPROM is not needed.

(2)

spare inputs

2001 Nov 08 5

Philips Semiconductors Product speciﬁcation

DVB-T channel receiver TDA10045H

SYMBOL PIN TYPE DESCRIPTION

FFT_WIN 30 I/O output or input signal indicating the start of the active data; equals 1 during

complex sample 0 of the active FFT block; can be used to synchronize 2 chips

DDD33

SSD

SACLK 33 O sampling frequency output; this output clock can be fed to an external (10-bit)

FI[9:5] 34 to 38 I/O input data from an external ADC, FI must be tied to ground when unused,

DDD18

SSD

FI[4:0] 41 to 45 IO input data from an external ADC, FI must be tied to ground when unused,

DDD50

SSD

IT 48 OD

FEL 49 OD

n.c. 50 − not connected n.c. 51 − not connected TRSTN 52 I TMS 53 I TDI 54 I TCK 55 I TDO 56 O output port for boundary scan; not connected if not used V

DDD18

SSD

DS_SPARE2 59 O spare delta-sigma output; managed by the DSP or by an I

DS_SPARE1 60 O spare delta-sigma output; managed by the DSP to handle a low frequency DAC

DDD33

SSD

UNCOR 63 O RS error ﬂag, active HIGH on one RS packet if the RS decoder fails to correct

PSYNC 64 O pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a

31 − digital supply voltage for the pads (3.3 V typ.) 32 − digital ground supply (0 V)

ADC as a sampling clock; SACLK can also provide twice the sampling clock

positive notation (from 0 to 1023) or twos complement notation (from

−512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response).

39 − digital supply voltage for the core (1.8 V typ.) 40 − digital ground supply (0 V)

positive notation (from 0 to 1023) or twos complement notation (from

−512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response).

46 − digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant

I/O is not required

47 − digital ground supply (0 V)

(1)

interrupt line; this output interrupt line can be conﬁgured by the I2C-bus interface. This pin is an open-drain output and therefore requires an external pull-up resistor (to V

(1)

front-end lock; FEL is an open-drain output and therefore requires an external pull-up resistor (to V

(2)

asynchronous reset signal for boundary scan; connected to GND if not used

(2)

mode programming signal for boundary scan; connected to GND if not used

(2)

input port for boundary scan; connected to GND if not used

(2)

clock signal for boundary scan; connected to GND if not used)

DDD33

or V

DDD50

)

57 − digital supply voltage for the core (1.8 V typ.) 58 − digital ground supply (0 V)

C-bus register to

generate an analog level (after a RC low-pass ﬁlter)

(automatic ﬁrst stage tuner AGC measurement or 2nd AGC loop control as examples)

61 − digital supply voltage for the pads (3.3 V typ.) 62 − digital ground supply (0 V)

the errors

synchro byte is provided, then goes LOW until the next synchro byte

2001 Nov 08 6

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