Philips TCM2.0E Schematic

Page 1
Colour TV Chassis
H_17740_000.eps
240408
MG8MG8
ME8ME8
TCM2.0E

Contents Page Contents Page

1. Technical Specifications, Connections, and Chassis Overview 2
2. Safety Instructions, Warnings, and Notes 5
3. Directions for Use 6
4. Mechanical Instructions 7
5. Service Modes, Error Codes, and Fault Finding 12
6. Block Diagrams, Test Point Overview, and
Waveforms
Wiring Diagram Of Connector 19", 20", and 22" 19 Wiring Diagram Of Connector 26" 19 Block Diagram MT5335 20
7. Circuit Diagrams and PWB Layouts Diagram PWB Main Power Supply (20") (A)21 22 Main Power Supply (26") (A1)23 25 Standby Power Supply (26") (A2)24 26 SSB v1: Tuner (B01)27 46-47 SSB v1: MCU Standby (B02)28 46-47 SSB v1: DC / DC (B03)29 46-47 SSB v1: Digital Channel Decoder (B04)30 46-47 SSB v1: DVBT/ CI Decoder (B05)31 46-47 SSB v1: Audio Amplifier (B06)32 46-47 SSB v1: MT5335 Video Processor (B07)33 46-47 SSB v1: MT5335 Interface USB/HDMI (B08)34 46-47 SSB v1: Interface LVDS TTL (B09)35 46-47 SSB v1: Flash Memory (B10)36 46-47 SSB v1: SDRAM (B11)37 46-47 SSB v1: MT5335 Interface VGA (B12)38 46-47 SSB v1: D/A Converter (B13)39 46-47 SSB v1: HDMI Switch (B14)40 46-47 SSB v1: I/O Scart (B15)41 46-47 SSB v1: I/O Side AV, S-Video, Audio (B16)42 46-47 SSB v1: MT5335 Interface YPbPr & VGA (B17)43 46-47 SSB v1: I/O VGA (B18)44 46-47 SSB v1: LVDS Receiver (B19)45 46-47
©
Copyright 2009 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.
SSB v2: Tuner (B01)48 67-68 SSB v2: MCU Standby (B02)49 67-68 SSB v2: DC / DC (B03)50 67-68 SSB v2: Digital Channel Decoder (B04)51 67-68 SSB v2: DVBT/ CI Decoder (B05)52 67-68 SSB v2: Audio Amplifier (B06)53 67-68 SSB v2: MT5335 Video Processor (B07)54 67-68 SSB v2: MT5335 Interface USB/HDMI (B08)55 67-68 SSB v2: Interface LVDS TTL (B09)56 67-68 SSB v2: Flash Memory (B10)57 67-68 SSB v2: SDRAM (B11)58 67-68 SSB v2: MT5335 Interface VGA (B12)59 67-68 SSB v2: D/A Converter (B13)60 67-68 SSB v2: HDMI Switch (B14)61 67-68 SSB v2: I/O Scart (B15)62 67-68 SSB v2: I/O Side AV, S-Video, Audio (B16)63 67-68 SSB v2: MT5335 Interface YPbPr & VGA (B17)64 67-68 SSB v2: I/O VGA (B18)65 67-68 SSB v2: LVDS Receiver (B19)66 67-68 Keyboard Control Panel(E) 69 69 Inverter Panel (I)70 71 IR LED Panel (J)72 72
8. Alignments 73
9. Circuit Descriptions, Abbreviation List, and IC Data Sheets 74 Abbreviation List 75 IC Data Sheets 78
10. Spare Parts List & CTN Overview 86
11. Revision List 86
Published by JY 0963 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 17953
Page 2
EN 2 TCM2.0E LA1.
Technical Specifications, Connections, and Chassis Overview

1. Technical Specifications, Connections, and Chassis Overview

Index of this chapter:

1.1 Technical Specifications

1.2 Connection Overview
1.3 Chassis Overview
Notes:
Figures can deviate due to the different set executions.
Specifications are indicative (subject to change).
1.1 Technical Specifications

1.1.1 Vision

Display type : LCD Screen size : 19" (48 cm), 16:9
: 20" (51 cm), 4:3 : 22" (56 cm), 16:9 : 26" (66 cm), 16:9
Resolution (H × V pixels) : 640×480 (20")
2
Light output (cd/m
Contrast ratio : 800:1 (20", 26")
Typ. response time (ms) : 12 (20")
Viewing angle (H × V degrees) : 178×178 (20")
Tuning system : PLL Colour systems : PAL, SECAM Video playback : PAL, SECAM, NTSC Tuner bands : UHF, VHF, S, Hyper
) : 300 (19", 20", 22")
: 1 366×768 (26") : 1 440×900 (19") : 1680×1050 (22")
: 500 (26")
: 1000:1 (19", 22")
: 8 (26") : 5 (19", 22")
: 170×160 (19", 22") : 160×160 (26")

1.1.3 Miscellaneous

Power supply
- Mains voltage (V
- Mains frequency (Hz) : 50, 60 Power consumption (W) : ~50 (19")
Stand-by (W) : < 0.3 Dimensions (W × H × D in mm) : 475 × 334 × 71 (19")
Weight (kg) : ? (19")
) : 100 to 240
AC
: ~58 (20") : ~53 (22") : ~120 (26")
: 470 × 406 × 71 (20") : 538 × 375 × 71 (22") : 671 × 458 × 90 (26")
: 5.8 (20") : ? (22") : 7.7 (26")
Supported Computer Formats 60 Hz : 640×480(max.for 20") 60 Hz : 800×600 (all exc.20") 60 Hz : 1 024×768(all exc.20") 60 Hz : 1 280×768 (26" only) 60 Hz : 1 280×1 024 (26" only) 60 Hz : 1 366×768 (26" only) 50 Hz, 75 Hz : 1 440×900 (26", only)
Supported Video Formats 60 Hz : 480i 60 Hz : 480p 50 Hz : 576i 50 Hz : 576p 50 Hz, 60 Hz : 720p 50 Hz, 60 Hz : 1080i 50 Hz, 60 Hz : 1080p (19", 22" only)

1.1.2 Sound

Sound systems : Mono
:Stereo
Maximum power (W) : 2 × 3 (19", 20")
:2 × 5 (22", 26")
Page 3
Technical Specifications, Connections, and Chassis Overview
TV (75Ω)
EXT 3
HDMI 2 VGA PC EXT 1
VGA
AUDIO SPDIF
LR
YPrPb
COMMON INTERFACE
S-VIDEO
EXT 2
L AUDIO R
CVBS
HDMI 1
I_17950_001.eps
080508
1 2 3 4
E_06532_022.eps
300904
19
1
18 2
E_06532_017.eps
250505
1
6
10
11
5
15
E_06532_002.eps
171108

1.2 Connection Overview

EN 3TCM2.0E LA 1.

Figure 1-1 Rear and side I/O connections

Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, and Ye= Yellow.

1.2.1 Side connections

EXT 2: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 V Wh - Audio L 0.5 V Rd - Audio R 0.5 V
/ 75 ohm jq
PP
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
EXT 2: S-Video (Hosiden): Video Y/C - In
1 -Ground Y Gnd H 2 -Ground C Gnd H 3 -Video Y 1 V 4 -Video C 0.3 V
/ 75 ohm j
PP
P / 75 ohm j
PP
EXT 2: Mini Jack: Audio Head phone - Out
Bk - Head phone 32 - 600 ohm / 10 mW ot
EXT 2: Common Interface
68p - See diagram B05 jk

1.2.2 Rear Connections

USB2.0
1 -D2+ Data channel j 2 -Shield Gnd H 3 -D2- Data channel j 4 -D1+ Data channel j 5 -Shield Gnd H 6 -D1- Data channel j 7 -D0+ Data channel j 8 -Shield Gnd H 9 -D0- Data channel j 10 - CLK+ Data channel j 11 - Shield Gnd H 12 - CLK- Data channel j 13 - n.c. 14 - n.c. 15 - DDC_SCL DDC clock j 16 - DDC_SDA DDC data jk 17 - Ground Gnd H 18 - +5V j 19 - HPD Hot Plug Detect j 20 - Ground Gnd H
VGA PC: Video RGB - In and Service UART
Figure 1-4 VGA Connector
1-+5V k 2 -Data (-) jk 3 -Data (+) jk 4 -Ground Gnd H
HDMI 1 & 2: Digital Video, Digital Audio - In
Figure 1-2 USB (type A)
Figure 1-3 HDMI (type A) connector
1 -Video Red 0.7 V 2 -Video Green 0.7 V 3 -Video Blue 0.7 V 4-n.c. 5 -Ground Gnd H 6 -Ground Red Gnd H 7 -Ground Green Gnd H 8 -Ground Blue Gnd H 9 -+5V_dc +5 V j 10 - Ground Sync Gnd H 11 - n.c. 12 - DDC_SDA DDC data j 13 - H-sync 0 - 5 V j 14 - V-sync 0 - 5 V j 15 - DDC_SCL DDC clock j
/ 75 ohm j
PP
/ 75 ohm j
PP
/ 75 ohm j
PP
Page 4
EN 4 TCM2.0E LA1.
21
20
1
2
E_06532_001.eps
050404
I_17950_002.eps
080508
I
INVERTER PANEL
(OPTONAL)
B
SMALL SIGNAL BOARD
A(1)
MAIN POWER SUPPLY
E
KEYBOARD
CONTROL PANEL
A2
STANDBY POWER
SUPPLY UNIT
(OPTIONAL)
J
IR LED PANEL
Technical Specifications, Connections, and Chassis Overview
EXT 3: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y 1 V Bu - Video Pb 0.7 V Rd - Video Pr 0.7 V Wh - Audio L 0.5 V Rd - Audio R 0.5 V
EXT 3: Mini Jack: VGA Audio - In
Bk - Audio L/R 0.5 V
EXT 1: Video RGB/YC - In, CVBS - In/Out, Audio - In/Out
Figure 1-5 SCART connector
1 -Audio R 0.5 V 2 -Audio R 0.5 V 3 -Audio L 0.5 V 4 -Ground Audio Gnd H
/ 75 ohm jq
PP
/ 75 ohm jq
PP
/ 75 ohm jq
PP
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
/ 1 kohm k
RMS
/ 10 kohm j
RMS
/ 1 kohm k
RMS

1.3 Chassis Overview

5 -Ground Blue Gnd H 6 -Audio L 0.5 V 7 -Video Blue/C-out 0.7 V 8 -Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3 j 9 - Ground Green Gnd H 10 - Easylink P50 0 - 5 V / 4.7 kohm jk 11 - Video Green 0.7 V 12 - n.c. 13 - Ground Red Gnd H 14 - Ground P50 Gnd H 15 - Video Red/C 0.7 V 16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm j 17 - Ground Video Gnd H 18 - Ground FBL Gnd H 19 - Video CVBS 1 V 20 - Video CVBS/Y 1 V 21 - Shield Gnd H
Aerial - In
- - IEC-type (EU) Coax, 75 ohm D
Cinch: S/PDIF - Out
Bk - Coaxial 0.4 - 0.6V
/ 10 kohm j
RMS
/ 75 ohm jk
PP
/ 75 ohm j
PP
/ 75 ohm j
PP
/ 75 ohm k
PP
/ 75 ohm j
PP
/ 75 ohm kq
PP

Figure 1-6 PWB/CBA locations (26" model)

Page 5
Safety Instructions, Warnings, and Notes

2. Safety Instructions, Warnings, and Notes

EN 5TCM2.0E LA 2.
Index of this chapter:

2.1 Safety Instructions

2.2 Warnings

2.3 Notes

2.1 Safety Instructions
Safety regulations require the following during a repair:
Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA).
Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points:
Route the wire trees correctly and fix them with the mounted cable clamps.
Check the insulation of the Mains/AC Power lead for external damage.
Check the strain relief of the Mains/AC Power cord for proper function.
Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any inner parts by the customer.
2.2 Warnings
All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.
Be careful during measurements in the high voltage section.
Never replace modules or other components while the unit is switched “on”.
When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
2.3 Notes

2.3.1 General

Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode (see chapter 5) with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or
61.25 MHz for NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

2.3.2 Schematic Notes

All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ).
Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
All capacitor values are given in micro-farads (μ=× 10 nano-farads (n =× 10
Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).
An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.
The correct component values are listed in the Spare Parts List. Therefore, always check this list when there is any doubt.

2.3.3 BGA (Ball Grid Array) ICs

Introduction
For more information on how to handle BGA devices, visit this URL: www.atyourservice.ce.philips.com (needs subscription, not available for all regions). After login, select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile, which is coupled to the 12NC. For an overview of these profiles, visit the website www.atyourservice.ce.philips.com (needs subscription, but is not available for all regions) You will find this and more technical information within the “Magazine”, chapter “Repair downloads”. For additional questions please contact your local repair help desk.

2.3.4 Lead-free Soldering

Due to lead-free technology some rules have to be respected by the workshop during a repair:
Use only lead-free soldering tin Philips SAC305 with order code 0622 149 00106. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.
Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
-9
), or pico-farads (p =× 10
-12
-6
),
).
Page 6
EN 6 TCM2.0E LA3.
E_06532_024.eps
260308
MODEL :
PROD.NO:
~
S
32PF9968/10
MADE IN BELGIUM
220-240V 50/60Hz
128W
AG 1A0617 000001
VHF+S+H+UHF
BJ3.0E LA

2.3.5 Alternative BOM identification

It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
Directions for Use
Figure 2-1 Serial number (example)

2.3.6 Board Level Repair (BLR) or Component Level Repair (CLR)

If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!

2.3.7 Practical Service Precautions

It makes sense to avoid exposure to electrical shock.
While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.
Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.

3. Directions for Use

You can download this information from the following websites:
http://www.philips.com/support http://www.p4c.philips.com
Page 7

4. Mechanical Instructions

I_17950_003.eps
080508
Mechanical Instructions
EN 7TCM2.0E LA 4.
Index of this chapter:

4.1 Cable Dressing

4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
4.1 Cable Dressing
Notes:
Figures below can deviate slightly from the actual situation, due to the different set executions.
Follow the disassemble instructions in described order. They apply mostly to the 26" model unless otherwise specified, but the described method is comparable for the other screen sizes.

Figure 4-1 Cable dressing (20" model)

Page 8
EN 8 TCM2.0E LA4.
I_17950_004.eps
080508
E_06532_018.eps
171106
1
Required for sets
42"
1
Mechanical Instructions

4.2 Service Positions

For easy servicing of this set, there are a few possibilities created:
The buffers from the packaging.
Foam bars (created for Service).

4.2.1 Foam Bars

Figure 4-2 Cable dressing (26" model)

The foam bars (order code 3122 785 90580 for two pieces) can be used for all types and sizes of Flat TVs. See figure “Foam bars” for details. Sets with a display of 42” and larger, require four foam bars [1]. Ensure that the foam bars are always supporting the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! By laying the TV face down on the (ESD protective) foam bars, a stable situation is created to perform measurements and alignments. By placing a mirror under the TV, you can monitor the screen.
Figure 4-3 Foam bars
Page 9

4.3 Assy/Panel Removal

I_17950_005.eps
080508
1
1
1
1
I_17951_010.eps
060808
Side
Side
Top
I_17951_011.eps
060808
I_17930_041.eps
240408
2
3

4.3.1 Stand

1. Refer to next figure.
2. Place the TV set upside down on a table top, using the foam bars (see section “Service Position”).
3. Remove the screws that secure the stand and remove the stand.
Mechanical Instructions
Figure 4-5 Front cover latch location [1/2]
EN 9TCM2.0E LA 4.
Figure 4-4 Stand

4.3.2 Rear Cover

Warning: Disconnect the mains power cord before you remove
the rear cover.
1. Refer to next figures.
2. Place the TV set upside down on a table top, using the foam bars (see section “Service Positions”).
3. Remove the screws that secure the rear cover. The screws are located at the sides. Be careful: Some models (mainly the smaller screen sizes) use latches for securing the rear and front cover together (see figure “Front cover latch location”). These
must be unlocked first before you can open the TV-set!
To open them, use e.g. a (plastic) putty knife. Insert the tool into the gap between the front and rear cover (be extremely careful not to scratch or dent the cabinet when inserting the tool). Gently release the internal latches. Note: You will hear little popping sounds as the latches release and the rear cover moves away from the front cover.
4. Now the rear cover could be lifted but the SSB and power supply panel(s) are mounted in the rear cover and still connected to the LCD panel and other boards. Those
cables should be released first!
5. To release the LVDS cable lift the back cover a few centimetres and move it downwards the set. Now unplug the LVDS connector [2]. Caution: be careful, as this is a very fragile connector!
6. Remove the screw [3].
7. Now the rear cover can be lifted to gain access to the speaker cables and the IR/LED panel cable. Release the connectors [4].
Figure 4-6 Front cover latch location [2/2]
Figure 4-7 LVDS release
Page 10
EN 10 TCM2.0E LA4.
I_17930_042.eps
240408
4
4
4
I_17930_063.eps
240408
2
1
1
I_17930_043.eps
240408
1 1
22 22
I_17950_006.eps
080508
4
4
2
2
4
4
2
2
1
1
3
Figure 4-8 Speaker and IR/LED panel cable release

4.3.3 Keyboard Control Board

1. Refer to next figure.
2. Unscrew two screws[1]
3. Unplug connector [2] and remove the board. When defective, replace the whole unit
Mechanical Instructions
Figure 4-10 IR/LED Board and Speakers

4.3.5 Power Supply Board

Due to different set executions this chassis is supplied with one or two power supply boards and figures may differ. Caution: it is absolutely mandatory to remount all different screws and cables at their original position during re-assembly. Failure to do so may result in damaging the power supply.
1. Refer to next figure.
2. Unplug all the connectors [1].
3. Remove the fixation screws [2]
4. Remove the main power supply board.
5. Unplug all the connectors [3].
6. Remove the fixation screws [4]
7. Remove the stand-by power supply board.
Figure 4-9 Keyboard control board

4.3.4 IR/LED Board and Speakers

1. Refer to next figure.
2. Remove the screws [1] and remove the IR/LED board.
3. Remove the screws [2] and remove the speakers. When defective, replace the whole unit.
Figure 4-11 Power Supply Unit(s)
Page 11

4.3.6 Inverter Board (19", 20", and 22" versions)

I_17930_065.eps
240408
1
1
1
2
2
2
I_17950_007.eps
080508
1 1
I_17950_008.eps
080508
2
2
4
4
3
2
2
Due to different set executions this chassis some versions are supplied with an inverter board. Figures may differ.
1. Refer to next figure.
2. Unplug all connectors [1].
3. Release the clips [2]
4. Take out the inverter board.
Mechanical Instructions

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse order.
EN 11TCM2.0E LA 4.
Figure 4-14 SSB
Figure 4-12 Inverter Board

4.3.7 Small Signal Board (SSB)

Caution: it is absolutely mandatory to remount all different
screws at their original position during re-assembly. Failure to do so may result in damaging the SSB.
Removing the SSB
1. See next figures.
2. Remove the screws [1] from the SSB connector plate.
3. Remove the screws [2] from the SSB.
4. On the outside of the set, lift the rear cover near the tuner connector approximately 3 mm in the indicated direction and keep it lifted, while
5. On the inside of the set, slide the metal plate in the indicated direction.
6. Gently lift the board from the rear cover.
7. Now unplug the LVDS connector [3]. Caution: be careful, as this is a very fragile connector! Unplug the rest of the cables [4].
Notes:
While re-assembling, make sure that all cables are placed and connected in their original position. See figure “Cable dressing”.
Pay special attention not to damage the EMC foams at the SB shields. Make sure, that EMC foams are put correctly on their places.
Figure 4-13 SSB connector plate
Page 12
EN 12 TCM2.0E LA5.
I_17950_014.eps
050808
I_17950_015.eps
050808
I_17950_017.eps
050808
I_17950_018.eps
050808
I_17950_019.eps
050808
Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:

5.1 Test Points

5.2 Service Modes

5.3 Error Codes
5.5 Service Tools
5.1 Test Points
This chassis is NOT equipped with test points in the service printing. No test points are mentioned in the service manual.
5.2 Service Modes
The Service Mode feature is split into different parts:
Service Alignment Mode (SAM).
Service Default Mode (SDM).
Customer Service Mode (CSM).
SDM and SAM offer features, which can be used by the Service engineer to repair/align a TV set. Some features are:
Activates the blinking LED procedure for error identification when no picture is available (SDM).
Make alignments (e.g. white tone), (de)select options, enter options codes, reset the error buffer (SAM).
Display information (“SAM” indication in upper right corner of screen, error buffer, software version, options and option codes, sub menus).
The CSM is a Service Mode that can be enabled by the consumer. The CSM displays diagnosis information, which the customer can forward to the dealer or call centre. In CSM mode, “CSM”, is displayed in the top right corner of the screen. The information provided in CSM and the purpose of CSM is to:
Increase the home repair hit rate.
Decrease the number of nuisance calls.
Solved customers' problem without home visit.

5.2.1 Service Alignment Mode (SAM)

How to Enter
To enter SAM, use the following method:
Press on the remote control the code “062596” directly followed by the “INFO” key.
Figure 5-2 SAM menu, Clear
Figure 5-3 SAM menu, RGB Align
After entering SAM, the following screen is visible, the values can be adjusted according to the requested (see Chapter 8).
Figure 5-1 SAM menu, System Information
Figure 5-4 SAM menu, NVM Editor
Figure 5-5 SAM menu, NVM Update
Page 13
Service Modes, Error Codes, and Fault Finding
I_17950_020.eps
050808
I_17950_043.eps
080508
I_17950_044.eps
080508
I_17950_045.eps
080508
Figure 5-6 SAM menu, Clear OAD
How to EXIT
Put set in <stand-by> by using the remote control.
EN 13TCM2.0E LA 5.
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Contents of CSM

5.2.2 Service Default Mode (SDM)

Purpose
To create a pre-defined setting, to get the same measurements as given in this manual.
To override SW protections.
To start the blinking LED procedure.
How to enter
To enter SAM, use the following method:
Press on the remote control the code “062596” directly followed by the “MENU” key.
After entering SDM, the following screen is visible.
Figure 5-7 SDM menu
From top to bottom, it gives the following information:
Operation hours
Software version
Error buffer display.
Figure 5-8 CSM Menu -1-
Figure 5-9 CSM Menu -2-
Menu Explanation
1. Model Number. Type number and region.
2. Production Serial Number. Product serial no.
3. SW Version. Software cluster and version is displayed (TC = TCL, M2 = MTK2, E = Europe, 0.49 = software version).
4. Codes. Error buffer contents.
5. SSB. SSB serial number.
6. DISPLAY. Display type.
7. NVM Version. NVM version.
8. Key (HDCP) HDMI. Shows valid or invalid HDCP key when HDMI connected. Else blank.
9. Digital Signal Quality. Quality of antenna signal in %.
10. Audio System. Audio system (Mono/Stereo/NICAM)
11. n.a.
12. Video Format. Video format.
13. Stand-by μP SW ID. SW version Stand-by microprocessor.

5.2.3 Customer Service Mode (CSM)

Purpose
When a customer is having problems with his TV-set, he can call his dealer or the Customer Help desk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible.
How to exit
Press “MENU” on the RC-transmitter.
Page 14
EN 14 TCM2.0E LA5.
No Picture, no sound, no Black light, Fuse Broken
For Q800,pin5~6
of is 5V & pin7~8
is12V , OK?
Is
U800~U808&U2
01 OK?
Replace the bad
one of
u800~u808&U201
For P804 ,Pin 8~11
is 12V& Pin2~3 of
is 5v
, OK?
Check Pin 10 Of
U810. is it 3.3v?
Check
LQFP jointing of
U203
NO NO
NO
YES YES
YES
Check
X200,C221,C222,C
23,L214 & IIC Bus
YES
Check jointing of
U204,R271~R288,R
248~R260.
YES
Check PSU
I_17950_009.eps
080508
Service Modes, Error Codes, and Fault Finding

5.2.4 Blinking LED Procedure

The software is capable of identifying different kinds of errors. Because it is possible that more than one error can occur over time, an error buffer is available which is capable of storing the last five errors that occurred. This is useful if the OSD is not working properly.
Errors can also be displayed by the blinking LED procedure. The method is to repeatedly let the front LED pulse with as many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is “off”. Then this sequence is repeated. Any RC command terminates the sequence. Error code LED blinking is in white colour.
Example: the contents of the error buffer is “013 007 000 000 000”. After entering SDM, the following occurs:
1 long blink of 5 seconds to start the sequence
1 medium blink of 3 seconds and then 3 short blinks followed by a pause of 1.5 seconds
7 short blinks followed by a pause of 1.5 seconds
1 long blink of 1.5 seconds to finish the sequence.
The sequence starts again with 12 short blinks.

5.4 Fault Finding

5.3 Error Codes

The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right.
Basically there are six kind of errors:
Code Description Detection method Type
0 no error
3 μP Control I
4 General I
bus Error
7 Tuner I
8 Demodulator I
10 MT8295 I
13 HDMI switch I
2
C-bus Error log +
2
C
I2C-bus Protection +
2
C-bus Error log +
2
C-bus Error log +
2
C-bus Error log +
2
C-bus Error log +
blinking in SDM
spontaneous
blinking in SDM
blinking in SDM
blinking in SDM
blinking in SDM

Figure 5-10 No picture, no sound, no backlight, fuse broken (19", 20", and 22" sets)

Page 15
Service Modes, Error Codes, and Fault Finding
No Picture, no sound, no Black light, Fuse Broken
pin4~5 is 5V &
pin7~8 is12V of
U505 OK?
Pin 8~11 of P804 is
12V, OK?
Check Pin 4 Of
UM01 is 3.3v
Check
LQFP jointing of
U203
NO NO
NO
YES YES
YES
Pin2~3 of P804 is 5v&Pin 1 is 5v,OK?
Check X200,C221,C222,C 23,L214 & IIC Bus
YES
Check jointing of U204,R271~R288
,R248~R260.
YES
NO
Check sub PSU
for standby
Check Main
PSU
YES
Is
U800~U808&U2
01 OK?
Replace the
bad one of
u800~u808&U2
01
I_17950_010.eps
080508
No Picture, Black light & Sound OK
Check the
output voltage
of Q203. is it
OK?
Check
waveform of
L200~L209 is
OK?
Check the voltage of
C of Q204.
Yes
No
Yes
Is
Pin220,229,238
of U203 shorted
to earth?
Replace Q203
Yes
No
check the
cable to panel
check Pin
221~228&Pin
230~242 of U203
No
I_17950_011.eps
080508
EN 15TCM2.0E LA 5.

Figure 5-11 No Picture, no sound, no backlight, fuse broken (26" sets)

Figure 5-12 No Picture, Backlight & Sound OK

Page 16
EN 16 TCM2.0E LA5.
Picture OK, No sound
Check the voltage of
Pin 3,13 of u600,is it 12v?
Check Q800
Check the wave of
pin186,185 of
U203,is it OK?
Check
R & L speaker
Check the wave
of Pin of source
input,such as
pin170~177.
Check
Pin 7 of U600 is
6V
No
Check C of Q602 is
5V,B of Q602 is Low
OK?
Yes
No
Check stby
Pin 7 & Mute Pin6 of U600,is it OK?
Yes
Yes
Replace
u203
Yes
NO
Yes
Change the
damage
component
No
No
Yes
Check IF circuit
or Replace
U100
TV source
Check
the input circuit
No
NO
Replace U600
I_17950_012.eps
080508
No colour
Colour system is
Right & another
channel colour is
right ?
Dose the TV
signal too weak?
Check
Pin 17 of U100
OK?
Check
U100
Reset
To
Local system
Check
Tuner Input
cable & antenna
Check E2PROM
U205
Yes
NO
NO
No
YES
YES
Fine Frequency
YES
I_17950_013.eps
080508
Service Modes, Error Codes, and Fault Finding

Figure 5-13 Picture OK, No sound

Figure 5-14 No colour

Page 17
Service Modes, Error Codes, and Fault Finding
E_06532_036.eps
150208
TO
UART SERVICE
CONNECTOR
TO
UART SERVICE
CONNECTOR
TO I2C SERVICE CONNECTOR
TO TV
PC
HDMI I
2
C only
Optional power
5V DC
ComPair II Developed by Philips Brugge
RC out
RC in
Optional
Switch
Power ModeLink/
Activity
I
2
C
ComPair II
Multi
function
RS232 /UART

5.5 Service Tools

5.5.1 ComPair

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. You do not have to know anything about I yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available.
4. ComPair features TV software upgrade possibilities.
Specifications
ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The (new) ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).
2
C or UART commands
EN 17TCM2.0E LA 5.
How to Connect
This is described in the ComPair chassis fault finding database.
Figure 5-15 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!
How to Order
ComPair II order codes:
ComPair II interface: 312278591020.
For latest software see Philips Service website.
ComPair UART interface cable: 312278591070.
Note: If you encounter any problems, contact your local support desk.
Page 18
EN 18 TCM2.0E LA5.
User software upgrade flow chart
Power off the set
Plug-in th e USB
stick
Power- on the set
Detect USB
break-in’ and
check autorun fi le
Is USB sw
version > set
sw?
Set re-start &
Proceed with sw
upgrade
Display
upgrade
progress
Prompt user to
remove USB
and restart the
set
Successful?
Prompt user to
try again?
Y
N
N
Y
End
End
Display USB
sw newer than
the TV sw.
Prompt user to
confirm
Proceed?
Display USB
sw equal/older
than TV sw.
Prompt user to
confirm
N
Y
See layout 2
See layout 1
A newer version of software is
detected.
Do you want to upgrade?
YES NO
An equal/older version of software is
detected.
Do you want to proceed?
Note: Should be done on ly if
necessary.
YES NO
See layout 3
Kindly remove the USB stick and
restart the set.
See layout 4
Software update failed!
Would you like to try again?
layout 4
layout 3
layout 2
layout 1
YES NO
Retry?
N
Y
Valid auto-r un
file?
Y
N
Is USB sw
version =< set
sw?
Y
N
I_17920_046.eps
080508
Service Modes, Error Codes, and Fault Finding

5.6 Software Upgrading

5.6.1 Introduction

Software upgrading can be done by ComPair but this feature is a back up solution in case the normal procedure via USB does not work. Please use the USB upgrade method first. When the software is programmed via USB, you need the UPGRADE.PKG file on the USB stick. This file is available for customers on the Consumer Care website. When the software is programmed via ComPair, you need a *.BIN file. This file is only available for service workshops on the Servicer Network Support website.
The software upgrade feature does only work with the ComPairII interface.

5.6.2 Main Software Upgrade

In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “upgrade.pkg”. This software can be downloaded (as ZIP file) from the Philips Service website (an account is required). If named otherwise, rename the unzipped file always to “upgrade.pkg“.
How to upgrade:
1. Copy the “upgrade.pkg” file to the root of your USB stick.
2. Insert the USB stick in the USB connector on the TV while the TV is in “on” mode. The set will restart, and the upgrading will start automatically (see flowchart below). As soon as the programming is finished, you will get the message that you can remove your USB stick and restart the TV-set.
Figure 5-16 SW upgrade flowchart
Page 19
Block Diagrams, Test Point Overview, and Waveforms
40-PWL20C-PWI1XG
POWER BOARD
1
NU/SELECT
GND
GND
P800
1 2 3
5 6 7
4
BL ON/OFF
DIMMING
INVERTER_PWR 12V INVERTER_PWR 12V
P805
40-LDMK35-MAE2XG
MAIN BOARD
POWER_ON
1 2 3
5 6
4
5VSB DIIR GND
STANDBY
KEY GND
GND
1 2 3
5 6 7
4
NU 5V-PW 5V-PW
GND GND GND
INVERTER BOARD
CN1
GND
1 2 3
5 6
4
INVERT-SW
DIMMING
GND
INVERTER_PWR 12V
INVERTER_PWR 12V
8 9
5VSB
5V_KEY
GND
1 2 3
5 6
4
GND GND
GND
5V-PW
5V-PW
40-L19PFL-KEC1XG
KEY BOARD
40-L20PFL-IRC1XG
IR BOARD
GND
IR
SB-LCD
ON-LCD
1 2 3
5
4
5V-SB
5VSB-OUT
GND
KEY
1 2 3 4
5VSB-IN
P1
P601
1SP 408P
9 10 11
12V-IN 12V-IN
12V-IN 12V-IN
7 8 9 10
12V-IN 12V-IN
12V-IN 12V-IN
I_17951_001.eps
050808
_
_
19TCM2.0E LA 6.

6. Block Diagrams, Test Point Overview, and Waveforms

Wiring Diagram Of Connector 19", 20", and 22"

Wiring Diagram Of Connector 26"

P800
GND GND GND GND GND +24V +24V +24V +24V +24V
BL ON/OFF NU/SELECT DIMMING GND GND INVERTER INVERTER
1
PWR 12V PWR 12V
P5
40-1PL37C-PWF1XG
MAIN POWER
9 11 13 15 17 19 21 23 25 27
40-LDMK35-MAE2XG
MAIN BOARD
1 2 3 4 5 6 7
P805
1 2 3 4 5 6
8 9
5VSB DIIR GND STANDBY POWER_ON KEY GND 5VSB 5V_KEY
P804
1 2 3 4 5 6 7
9 10 11
NU 5V-PW 5V-PW GND GND GND GND
12V-IN 12V-IN
12V-IN 12V-IN
+24V +24V +24V +24V +24V GND GND GND GND GND VDIM VBLON PDIM GND
ON-LCD
SB-LCD
GND
IR
5V-SB
KEY
GND
5VSB-OUT
5VSB-IN
+12V +12V GND GND +12V +12V GND +12V GND
GND
+5V GND ON/OFF
P1
P601
P4
P5
PANEL INVERTER CONNECTOR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
40-L20PFL-IRC1XG
IR BOARD
1 2 3 4 5
40-L19PFL-KEC1XG
KEY BOARD
1 2 3 4
40-1PL37C-PWF1XG
1
MAIN POWER
2 3 4 5 6 7 8 9
10
40-PWL01B-STE1XG
STB POWER
1 2 3
I_17951_002.eps
050808
Page 20
CEC
COMMAND
VCC
+5V/
Standby+5v
+12V
VIF
SIF
SAW-D9453D
Broken line is option for TTL
interface panel!
OFF
ON
MT5335
MT5335
HDMI1
HDM2
HDMI SWITCH
SI8195
EDID EDID
VGA
EDID
YPbPr
62 OSCL1 63OSDA1
73 HDMI_5V
79 RX0_CB 80 RX0_C
81 RX0_0B 82 RXO_0
83 RX0_1B 84RXO_1
85 RX0_2B 86 RX0_2
205 DDC_SCL
204 DDC_SDA
104 R
98 B
102 G
96 VSYNC
97 HSYNC
120 Y_IN
121 Pb_IN
123 Pr_IN
173 YPbPr_L
174 YPbPr_R
176 VGA_R
177 VGA_L
SCART
170 SCT_R_IN
171 SCT_L_IN
116 SCT_R
108 SCT_G
114 SCT_B
149 SCT_FS
107 SCT_FB
187 SCT_R_OUT
189 SCT_L_OUT
O/P
AV
129 CVBS
172 R_IN
173 L_IN
126 SY
125 SC
SPDIF
201
SPDIF
_OUT
HEAD PHONE
185
HP_R_OUT
186
HP_L_OUT
PANEL
LVDS
To
TTL
386
LVDS
TTL
TUNER
TDQG4-601A
SAW-K7270M
TD
A98
86T
MT5133
MT8295
IF+/IF-
PARALLEL TS
SERIAL TS
AUDIO
AMP
LV
DS
DDR
32Mb
x16
FLASH
32Mbit
PRE AUDIO
AMP
R
/
L
132 TV_CVBS
CI
CARD
PARALLEL TS
PARALLEL TS
R
L
205 SCL
206 SDA
I2C
8051 WT6702F
15 KEY 9 POWERON
11 STANDBY 14 IR
KEY BOARD
152 KEY
93 IR
EEPROM
M24C16MN
DC-DC
12V to 5V RT8110
POWER
SUPPLY CONNECTOR
V0.1
I_17950_042.eps
080508
Block Diagrams, Test Point Overview, and Waveforms

Block Diagram MT5335

20TCM2.0E LA 6.
Page 21
Circuit Diagrams and PWB Layouts
I_17930_024.eps
220408
A A
MAIN POWER SUPPLY 19” & 20

7. Circuit Diagrams and PWB Layouts

Main Power Supply (20")

21TCM2.0E LA 7.
Page 22
Circuit Diagrams and PWB Layouts
I_17930_025.eps
220408
I_17930_026.eps
220408

Layout Main Power Supply (20") (Top Side)

22TCM2.0E LA 7.

Layout Main Power Supply (20") (Bottom Side)

Page 23

Main Power Supply (26")

I_17930_027.eps
220408
A1 A1
MAIN POWER SUPPLY 26
Circuit Diagrams and PWB Layouts
23TCM2.0E LA 7.
Page 24
Circuit Diagrams and PWB Layouts
I_17930_028.eps
220408
A2 A2
STANDBY POWER SUPPLY 26”

Standby Power Supply (26")

24TCM2.0E LA 7.
Page 25
Circuit Diagrams and PWB Layouts
I_17930_029.eps
220408
I_17930_030.eps
220408

Layout Main Power Supply (26") (Top Side)

25TCM2.0E LA 7.

Layout Main Power Supply (26") (Bottom Side)

Page 26
I_17930_075.eps
250408
Personal Notes:
E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts

Layout Standby Power Supply (26") (Top Side)

26TCM2.0E LA 7.
Page 27
Circuit Diagrams and PWB Layouts
IFOUT1
ANTPWR
B1
IFAGC
NC
TU
SCL
GND1
SDA
NC/GND1
NC/GND2
NC/RFAGC
NC1
XTALOUT
AS
ANALOG_IF
IFOUT2
OUT2
OUT1
GND
IN/GND
IN
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
OUT2
OUT1
GND
IN/GND
IN
NC
TAG C
REF
VAG C
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD CVBS
AGND
VPLL
VP
AFC
SIF1
SIF2
OP2
TOP
SDA
SCL
SIOMAD
OC
OUT1
OUT2
OUT3
EN
IN2
IN1
GND
Y
E
VCC
GND
Z
2
R130
75R
D110
LL4148
R145
12K
C2
47U
6V3
C139
0.1U
1
4
5
3
2
U101
4LVC1G66GV
C138
0.1U
C137
0.1U
R148
0R
Q105
2N7002
RF-AGC
R149
NC\0R
C3
0.01U
C115
0.1U
TUNER_5V
TUNER_5V
C119
0.01U
C103
NC/100U
6V3
C102
100U
6V3
C101
100U
6V3
R95
NC/100R
L104
NC/120
R96
NC/100R
R97
NC/4K7
C126
NC/0.1U
5
6
7
8
4
3
2
1
U206
NC/TPS2049
R105 NC
R138
220R
R132
NC
D100
BA592
TUNER_SCL0
TUNER_SCL0
TUNER_SDA0
TUNER_SDA0
B
C
E
Q103
C124ET
TUNER_SCL0_5V
TUNER_SDA0_5V
AV_5V
R828
10K
AV_5V
21
6
18
8 17
574133 22
15
11
10
23
24
12
14
9 16
1
2
20
19
U100
TDA9886T
54321
X102
TUNER_5V
R99
NC
R118
NC
R135 4K7
R126
100R
OSDA0
OSCL0
NC\100R
R94
NC\100R
R93
R115 100R
R116 100R
C100
1U
C110
0.22U
C120
1P5
R104
NC\47R
R103
NC\1K5
B
C
E
Q101
NC\BC847C
R102
NC\180R
R106
NC\6K8
TUNER_SCL0_5V
TUNER_SDA0_5V
R128
0R
L107
120R
C127
0.1U
0.47U
C114
X100
4M
L101
0.56UH
R117 NC
R108
5K6
R110 2K2
R109 2K2
C118
1000P
L106
0
R112
33R
R120
NC
L100
1UH
D102
BA982
D101
BA982
C125
22P
IF_AGC
R127
100R
TUNER_SDA0_5V
C124
22P
FAT_IN+
FAT_ IN-
C128
1000P
C106
1000P
C105
1000P
C117 0.47U
C116
0.01U
R124
100R
R125
100R
C113
0.01U
C109
0.01U
C108
0.01U
C104
0.01U
C123
0.01U
6K8
R113
L102
120R
L103
120R
TUNER_SCL0_5V
R133
33R
C122
0.1U TUNER_5V
54321
X101
21
1
2
18
6
111412
15
3
4
5
13
19
16
17
20
Z100
R131
0R
C121
47P
R129
75R
C132
0.01U
C131
0.01U
TUNER_5V
R123
0R
R121
22K
R119
5K6
5V-OUT
R114
22K
5V-OUT
5V-OUT
5V-OUT
D103
BA982
B
C
E
Q102
BC847C
B
C
E
Q100
BC847C
C112
20P
C111
1500P
C107
390P
R111
2K2
R107
0R
R101
330R
R100 680K
R141
22K
R140 6K8
R139 6K8
R137 220K
L108
30R
SIFN
SIFP
GND_TUNER
CVBS0
CVBS-OUT
SIF
5V-TUNER-ON/OF
5V-TUNER-INPUT
DV33
AV_ 5V
R829
10K
DV33
Q104
2N7002
R147
100K
ATV-IF-AGC
R146
12K
ATV-IF-AGC
RF-AGC
MT5133-GPIO-AD
CVBS_OUT
TUNER
B01 B01
I_17950_021.eps
070508
27TCM2.0E LA 7.

SSB v1: Tuner

Page 28

SSB v1: MCU Standby

8 76 543 21
Circuit Diagrams and PWB Layouts
28TCM2.0E LA 7.
B02 B02
F
KEY_5335
E
MCU STANDBY
5V_KEY
STANDBY
POWER_ON
+3V3SB
35KEY_5V
3K3
R842 NC
2N7002/NC
Q817
R819
KEY
D
+3V3SB_UP
HDMI_INT
C
SHORT_PROTECT
SW_UPDATE_CTL1
HSYNC
L811
600R
NC
R817
4K7
R815
33R
5V_KEY
NC
R833
5VSB
OIRI
R813
R83433R
R8350R
R81233R
L821
L822
L823
5V_KEY
5V_KEY
10K
R142
600R
600R
600R
+3V3SB_UP
R809 10K
600R
1
2
3
4
5
6
7
8
9
R807 10K
P805
OSCO
OSCI
CEC_IRQ
+3V3SB_UP
L820
600R
C871
1U
U810
116
OSCO VDD
2
OSCI
3
VSS
4
NRST
5
PWMI
6
RXD/IRQ3
7
TXD/IRQ2
8
HIN
WT6702F
AD0
AD3/IR
SCL1
SDA1
SCL2
SDA2
VIN
15
14
13
12
11
10
9
C823
0.1U
R81010K
R824 33R
R820
R823
R825
R814 33R
CEC
+3V3SB_UP
LL4148
R806
27K
33R
33R
33R
D801
C876
NC\1000P
C875
R822
R830
R805
100R
1000P
STANDBY
3V3SB_EN
VSYNC
OSCO
33R
33R
CEC_IRQ
100P
C819
R816
33R
KEY
OIRI_MCU
20P
C821
+3V3SB_UP
10K
R826
X800 32K7
R827
10K
OSCL0_SB
OSDA0_SB
OSCI
20P
C822
DV33
+3V3SB
R22
0R
Q810
2N7002
+3V3SB_UP
C820
0.1U
R10 0R
Q809
2N7002
1
2
3
4
OSCL0
OSDA0
ISP PORT
P802
F
E
D
C
1U
C802
OPTION for CEC Stand by Function
BT3904
OIRI_MCU
Q4
C
E
B
+3V3SB_UP
+3V3SB
1U
C824
L809
120R
C825
0.1U
RT9166
U811
2
C809
100U
6V3
GND
1
3
INOUT
6V3
0.1U
C826
C872
100U
5VSB
R144
4K7
GND
R143
10K
B
OIRI
B
A
A
I_17950_022.eps
070508
12345678
Page 29
Circuit Diagrams and PWB Layouts
T
GND
GND
GND
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND
A
3 21
F
E
D
C
B
8 76554 3 21
F
E
D
C
B
A
467
8
GND
D2B
D2A
G1
G2
S1
D1B
D1A
S2
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
BS
COMP
FB
GND
IN
SS
SW
NC2
NC1
EN
BOOT
DRIVE
FB GND
LGATE
PHASE
VCC
UGATE
OUTVIN
ADJ/GND
D1B
D1A
G2
G1
S2
D2B
D2A
S1
about 1mm
DIMMING
Back Light circuit
12V/4A
5V/2A
CONNECTOR
BL ON/OFF
POWER CINCH
R856 IS FOR 26"
19"20"22" NC
R852
4K7
R855
4K7
1
2
3
4
5
6
7
8
9
10
11
P804
1
2
3
4
5
6
7
P800
R2
510R
R849
10K
R850
4K7
R876
NC
R8013NC
R856
4K7
5VSB
D814
3V9
R10R
B
C
E
Q806
BT3904
R895
10K
B
C
E
Q805
BT3904
R5
10K
R4
10K
5V_OUTSIDE
5V_OUTSIDE
5VSB
R9NC
12V_IN
5V_PW
DV33A
+5V
12V
5VSB
C870
100U
6V3
C815
100U
6V3
C807
100U
6V3
C806
100U
6V3
7
8
4
2
3
5
6
1
U808
D13N03LT
C817
330U
16V
R8 47K
L816
120R
L13
200R
R882 15K
R801
330R
C839
0.1U
23
1
U809
NC/KD1084-33
R802
120R
AV33
R8001
10K
L802
200R
R889
4K7
D810
LL4148
AV33AV33
AV33
R890
2K7
DV33
1
2
3 6
5
8
4
7
U807
RT8110
R897
680R
R864
6K8
D818
LL4148
C804
4U7
C803 4U7
200R
L805
L804
200R
C801
1000U
16V
C800
1000U
16V
L801
15UH
C862
0.1U
C859
0.1U
C810
100U
16V
C816
100U
16V
L819
200R
R46
10K
R845
NC
R872
1K2
R871
NC
R831
2R7
0.1U C849
10K
R8011
2
8
7
6
4
10
5
3
1
9
U806
MP1411
C869
0.1U
C830
0.1U
C834
0.01U
R869
10R
R868
NC
R8012NC
R846
10K
R857 1K
C835
0.01U
R874 4K7
C813
100U
16V
C818
47U
6V3
C812
47U
6V3
C811
47U
6V3
C874
4U7
C814
47U
16V
AV12AV12
1
2
3
4
LD1117S33
U800
C853
0.1U
C858
1U
C852
1U
1
2
3
4
U801
LD1117S33
123
4
U803
LD1117S12
+5V
C829
0.1U
R854
0R
L800
15UH
R8010
4K7
R865
0R
R8003
0R
3V3SB_EN
+3V3SB
5V_PW
0R
R860
R866
22K
1U
C854
C827
1U
7
8
4
2
3
5
6
1
Q800
A04803
R867
10R
NC
C833
12V
C805
1U
C863
NC
C837
0.1U
12V
R844
1K
R847 NC
R843
4K7
C844
0.1U
R870
220R
R883
51K
R884
1K
R879
1K
R893
4K7
L813
30R
L815
600R
CI_DV18
C865
0.1U
0.1U
C842
DV10
C867
0.1U
C868
0.01U
5VSB
BL_ON/OFF
R803
5R1
R804
6R8
4
1
2
3
U802
LD1117S
AV33
+5V
CI_VCC
R862
6K8
R861
3K
D804
LL4148
12V
5V_KEY
+5V
12V_IN
R896
8K2
AV_5V
AV25
1
2
3
4
U804
LD1117S25
AV9VAV9V
0.1U
C845
R885
6K2
C843
0.1U
C841
0.1U
C840
0.1U
D817
LL4148
B
C
E
Q807
BT3904
C846
0.1U
R8006
10K
R898
47K
R894
100K
R892
2K7
R891
4K7
R888
2K7
R887
2K2
R886
3K9
D816
LL4148
D812
LL4148
D811
LL4148
D809
LL4148
12V
C848
0.1U
4
123
U805
LD1117S50
C851
0.1U
0.1U
C850
C828
0.1U
B
C
E
Q803 BT3904
C860
0.1U
R851
10K
B
C
E
Q802
BT3904
R848
100R
B
C
E
Q801
BT3904
SELECT
12V_IN
R859
4K7
R858
2K7
D805
LL4148
D806
LL4148
DDRV
R863
3K
D807
LL4148
AV25
C832
0.1U
C831
0.1U
D808
LL4148
D803
SK24
C866 120P NC
C864
0.01U
600R
L814
Z805
5VSB
B
C
E
Q816
BT3904
ON/OFF
2R7
R832
BL_DIM
200R
L818
200R
L15
L14
200R
12V
R92
2K2
R91
3K9
AV_5V
+5V
DV33
+3V3SB
ON/OFF
SHORT_PROTECT
R3
1K
R7
10K
R6
10K
+5V
DC-DC
B03 B03
I_17950_023.eps
070508
29TCM2.0E LA 7.

SSB v1: DC / DC

Page 30
Circuit Diagrams and PWB Layouts
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
AVD D33_3
AVSS33_3 AVSS33_2 XTALI XTALO AVDD33_2 ALC_IN VDD1.2 DGND1.2 TSDATA 7 TSDATA 6 TSDATA 5 VDD3.3
TSDATA 4
TSDATA 3
TSDATA 2
TSDATA 1
TSDATA 0
TSERR
TSVAL
TSSYNC
TSCLK
VDD3.3_1
DGND3.3
VDD1.2_1
HOST_SCL
HOST_SDA
VDD1.2_2
VDD3.3_2
DGND3.3_1
XTAL_SEL0
XTAL_SEL1
/RESET
GPIO0
VDD3.3_3
IF_AGC
RF_AGC
TUNER_SDA
TUNER_SCL
DGND1.2_1
VDD1.2_3
AVSS33_1
AVDD33_1
IN-
IN+
REFBOT
VCMEXT
REF_TOP
Digital 1.8V Bypass Caps
Digital 3.3V Bypass Caps
Analog 3.3V Bypass Caps
CLOSE TO MT5133
L510
120R
R151
NC/10K
DV33
R150
NC/1K
MT5133-GPIO-AD
MT5131_IF_AGC
R506
1K
33R R545
R54433R
33R R543
R54233R
NC/20P
C569
C568
NC/20P
C527
NC
L506
NC
R501
0R
OSDA0 OSCL0
R502 0R
TUNER_SCL0
600R
L501
TUNER_SDA0
R134
10K
R136
10K
R508
0R
C505
120P/NC
R504
10K
R505
100R
C503
1U
C502
1U
C501
1U
C500
1U
C512
0.22U
C510
0.22U
DVDD12
C509
0.047U
AV12
AV12
1000P
C513
C514
1000P
48
1 2
3
4 5 6 7
8
9 10 11 12
1314151617181920212223
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647
U502
MT5133
L502
600R
600R
L503
1
2
3
45
6
7
8
R536
33R
1
2
3
45
6
7
8
R535
33R
C504
120P/NC
AVD D33
FAT_IN+
FAT_ IN-
R507
0R
TS0INDATA5
TS0INDATA6
TS0INDATA0
TS0INVALID
TS0INSYNC
TS0INDATA7
DVD D33
ADVDD33_1
AV33
AV33
DVDD33DV33
DVD D12
C526
0.1U
C525
0.1U
C524
0.1U
C522
0.1U
C520
0.1U
C523
0.1U
C521
0.1U
C515
0.1U
C518
0.1U
C516
0.1U
C519
0.1U
C517
0.1U
REFTOP
REFBOT
MT5133_RESET
R503
NC
C508
0.1U
DVDD33
R500
1M
C507
27P
C506
27P
VCMEXT
SIF_SCL
SIF_SDA
IF_AGC
ADVDD33_1
AVDD33
DVDD12
DVD D33
DVDD33
DVDD12
DVDD12
AVDD33
TS0INCLK
XTALI
XTALO
TS0INDATA2
TS0INDATA4
TS0INDATA3
TS0INDATA1
X500
27M
TUNER_SDA
TUNER_SCL
L500
600R
DV33 DV33
0.22U
C511
DIGITAL CHANNEL DECODER
B04 B04
I_17950_024.eps
070508
30TCM2.0E LA 7.

SSB v1: Digital Channel Decoder

Page 31
Circuit Diagrams and PWB Layouts
GND
GND/ADJ
OUT
VIN
4
T
T
A
3 21
F
E
D
C
B
8 76554 3 21
F
E
D
C
B
A
467
8
GPIO0 GPIO1 GPIO2 GPIO3 VCC33 T0CLK_I_ T0SYNC_I_ T0VALID_I_ T0DATA0_I_ GND33 T0DATA1_I_ T0DATA2_I_ T0DATA3_I_ T0DATA4_I_
T0DATA5_I_ T0DATA6_I_ T0DATA7_I_
VCC18
D3
D4
D5
D6
D7
GND18
CE1#
A10
OE#
A11
A9
A8
A13
A14
GPIO4 GPIO5 GPIO6
VCC33_1
WE#
READY
A16
A15
A12
A7
A6
A5
GND33_1
A4
A3
A2
A1
A0
D0
D1
VCC33_2
D2
WP
CD1#
D11
D12
D13
D14
GND33_2
D15
CE2#
VS1#
GPIO7
GPIO8
GPIO9
VCC33_3
IORD#
IOWR#
A17
A18
A19
A20
A21
GND33_3
A22
A23
A24
A25
VS2#
RESET
VCC18_1
WAIT#
INPACK#
REG#
BVD2
BVD1
D8
GND18_1
D9
D10
CD2#
GPIO10
GPIO11
GPIO12
CI_CEB
CI_WEB
CI_DATA7
CI_DATA6
VCC33_4
CI_DATA5
CI_DATA4
CI_DATA3
CI_DATA2
CI_DATA1
CI_DATA0
GND33_4
CI_CLE
CI_RB
CI_INT
CI_OEB
RESETB
XTALI
XTALO
AVDD 33_XTAL
AVSS33_XTAL
AVDD18_PLL
AVSS18_PLL
VCC33_5
TS_VALIDO
TS_CKO
TS_DATAO
TS_SYNCO
GND33_5
GPIO13
GPIO14
CI_ALE
CLOSE TO MT8295
1.8V: 0.2W (100mA)
3.3V: 0.2W (60mA)
CLOSE TO MT8295
CLOSE TO CI CONNECTOR
CLOSE TO CI CONNECTOR
CLOSE TO MT8295
CLOSE TO MT8295
CLOSE TO MT8295
1 2
3
4 5 6 7
8
9 10 11 12 13 14
16 17 18
15
24
26
28
30
32
22
353739
4144464850
19 20 21
33
5355575962
64
66
69
43
71
73
75
78
80
83
85
52
87
89
23
25
27
29
31
76
343638
91
92
93
68
4042454749515460565861
63
65
67
82
70
72
74
77
79
81
90
84
86
88
118
119
120
94
96
98
9997100
101
102
95
115
116
104
105
106
114
117
107
110
109
108
111
112
113
121
122
123
124
125
126
127
128
103
U501
MT8295
10P
C567
10P
C561
CI_IOWR#
CI_IORD#
L511 120R
R548
NC
CI_RESET#
R54033R
33R R539
R53833R
C550
100U
6V3
TS_CKO
CI_CE1##
CI_OE##
CI_WE##
CI_WE##
CI_IOWR##
R532
NC\0R
R533
100R
CI_OUTCLK
CI_VS2#
CI_IOWR##
CI_IOWR#
CI_IORD##
CI_IORD#
CI_WE#
CI_OE##
CI_OE#
CI_CE1## CI_CE1#
R552
100R
R553
100R
R551
100R
R549
100R
DV33
R5474K7
CI_OEB
R512
10K
R5144K7
CI_RB
R546
4K7
OPWM2
OPWM1
R525
NC
C559
0.1U C560
0.1U
C538
0.1U
R511
4K7
GND
YPBPR_SW_IN
CI_POWE#
TS0I N DATA 7
HDMIED_WP
CI_GPIO0
CI_VPP5_EN
CI_VPP33_EN
CI_VS1#
CI_INSYNC CI_INDATA0
HDMI_SEL
R519
NC\10K
R517
NC\10K
C558
NC\0.1U
R526
100K/NC
C547
0.1U/NC
R527
47K/NC
R528
10K/NC
B
C
E
Q502
NC\C124ET
G
D
S
Q501
NC\A03401A
5V-TUNER-INPUT
5V-TUNER-ON/OF
5
1 2
3
4
6 7
8
9 10 11
13 14 15
12
22
21
20
19
18
17
16
34
33
32
31
30
29
28
27
26
25
24
23
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
41
40
39
38
37
36
35
68
42
P500
R531
NC/0R
C554
1U
C552
1U
C551
1U
6V3
47U
C556
C557
47U
6V3
1U
C1
C541
0.1U C544
0.1U
C530
10P
L508
600R
L505
600R
L504
600R
CI_VPP
CI_VCC
R515
100R
CI_DV33
Z502
Z501
X501 27M
R521
10K
1
2
3
4
U500
LD1117S18
CI_IOIS16#
CI_INPACK#
CI_DV33DV33 CI_DV18
CI_VPP
CI_VCC
CI_DV33
CI_AV18CI_DV18
CI_DV18CI_DV33
CI_AV33CI_DV33
CI_IOIS16#
CI_INPACK#
CI_IREQ#
+5V+5V+5V
CI_VCCCI_VCCCI_VCC
CI_VCC
CI_VCC
CI_VPP
L507
30R
CI_VCC
+5V
L509
30R
C546
0.1U
C545
0.1U
C542
0.1U
C543
0.1U
C540
0.1U
C536
0.1U
C537
0.1U
C534
0.1U
C535
0.1U
C539
0.1U
C532
0.1U
C531
0.1U
C533
0.1U
R524
10K
R523
10K
R520
10K
R518
10K
R516
10K
R522
10K
CI_GPIO1
CI_DV33
TS0INVALID TS0I N DATA 0
GND
CI_CD1#
CI_INCLK
R513
0R
R510
4K7
TS_VALIDO
TS_D ATAO
TS_SYNCO
RESET_N
CI_GPIO14
R509 1M
C528
27P
C529
27P
CI_XTALO
GND
GND
GND
GND
GND
GND
GND
CI_DV33
CI_DV33
CI_DV33
CI_DV33
CI_DV33
CI_INDATA7
CI_OUTCLK
CI_OUTDATA7
CI_OUTDATA2
CI_INDATA5
CI_REG#
CI_OUTDATA1
CI_CD1#
CI_VS1#
CI_OUTSYNC
CI_DV18
CI_DV18
CI_OUTDATA5
CI_INDATA1
CI_WAIT#
CI_WAIT#
CI_CE2#
CI_OUTDATA6
CI_OUTDATA0
CI_INDATA2
CI_RESET
CI_VCC_EN
CI_OUTDATA3
CI_IREQ#
CI_AV33
CI_IOIS16#
CI_INDATA3
CI_AV18
CI_OUTVALID
CI_INDATA6
CI_CD2#
CI_CD2#
CI_INDATA4
CI_OUTDATA4
CI_INPACK#
CI_IORD##
CI_PDD3
CI_PDD7
CI_D7
TS0INCLK
CI_D6
TS0I N DATA 5
CI_ALE
CI_PDD6
CI_A0
CI_PDD2
CI_INDATA7
CI_D3
CI_VS2#
CI_OUTDATA7
CI_A7
CI_OUTDATA2
CI_INDATA5
CI_A9
CI_REG#
CI_OUTDATA1
CI_D4
CI_A3
CI_A13
CI_VS1#
CI_INSYNC
TS0I N DATA 1
CI_OUTSYNC
CI_D0
CI_OUTDATA5
CI_A2
CI_INDATA1
CI_A5
CI_INT
CI_A10
CI_A12
CI_XTALI
CI_WAIT#
TS0I N DATA 2
CI_INDATA0
CI_CE2#
TS0I N DATA 6
CI_OUTDATA6
CI_OUTDATA0
CI_INDATA2
CI_RESET
CI_INVALID
TS0I N DATA 3
CI_OUTDATA3
TS0I N DATA 4
CI_A8
CI_A4
CI_A1
TS0INSYNC
CI_A11
CI_PDD5
CI_INDATA3
CI_D1
CI_A6
CI_CLE
CI_OUTVALID
CI_D5
CI_INDATA6
CI_D2
CI_INDATA4
CI_PDD4
CI_OUTDATA4
CI_A14
CI_A6 CI_A5 CI_A4 CI_A3 CI_A2 CI_A1 CI_A0 CI_D0 CI_D1 CI_D2
CI_IREQ#
CI_INVALID
CI_A12 CI_A7
CI_A8
CI_WE#
CI_A14
CI_A13
CI_A9
CI_A11
CI_OE#
CI_A10
CI_CE1#
CI_D7
CI_D5
CI_D4
CI_D3
CI_D6
CI_TS_SYNCO
CI_TS_DATAO
CI_TS_VALIDO
HPDIN
CI_VCC_EN
CI_CD1# CI_CD2#
CI_POCE1#
MTK_IC_RESET
CI_GPIO1
CI_GPIO0
CI_INCLK
10P
C562
10P
C565
10P
C566
10P
C564
10P
C563
R550
100R
CI_VS2#
CI_TS_CKO
33R
R541
PWRDN_EN
DVBT-CI-DECODER
B05 B05
I_17950_025.eps
070508
31TCM2.0E LA 7.

SSB v1: DVBT/ CI Decoder

Page 32

SSB v1: Audio Amplifier

Circuit Diagrams and PWB Layouts
32TCM2.0E LA 7.
B06 B06
AUDIO AMPLIFIER
AL1O
SPEAK-OUTL
AR1O
SPEAK-OUTR
NC
0R
R622
R621
R617 NC
R618 0R
R624
100K
R623
100K
Y600
PGND
P600
1
2
3
4
1
2
R620
2K2
2K2
R619
L-
GND
GND
L_OUT
U600 TDA7266
OUT1-
VCC1
2
1U
1U
2R7
3
R603
L600
L601
200R
IN1
4
C611
0.1U
200R
C610
4700P
C609
OUT1+
1
C612
4700P
C608
12V
NC1 5
2R7
MUTE 6
MUTE
R648
L+
STBY 7
SS
PGND
R+
S_GND
PW_GND
8
9
GND
16V
NC2
10
NC3
11
C607
1000U
IN2
12
0.1U
C615
VCC2
13
OUT2-
14
OUT2+
15
R_OUT
GND
GND
R-
R600
0R
Near the P502
R602
0R
R601
0R
Near the P502
PGND
PGND
12V
R643
220R
R639
R641
4K7
4K7
B
BT3906
PGND
Q607
R640
16V
GND
BT3906
4K7
100U
C602
R642
1K
GND
AMP_MUTE
LL4148
D600
4K7
R625
D601
LL4148
HW_MUTE
R644 10K
BT3904
Q602
B
R630 10K
12V
C
E
GND
R632 10K
R627
R647
10K
10K
GND
R628 10K
22U
C606
16V
SS
NC
R631
MUTE
R659
100R
R629
100R
R656
100R
R626
100R
C600
3300P
GND GND
3300P
C601
0R/NC
E
C
B
E
Q608
C
L602
L603
R6360R/NC
R637
100U
600R
600R
16V
C616
HP_L
HP_R
R+
R_OUT
GND
EAR
1
P601
2
C614
C613
4700P/NC
3
9
8
7
6
L+
L_OUT
5 4
4700P/NC
GND
C617
100U16V
I_17950_026.eps
070508
Page 33
Circuit Diagrams and PWB Layouts
T
T
T
T
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
T
SDA
SCL
WC
VCC
VSS
E2/NC
E1/NC
E0/NC
GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8
GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13
OSDA0 OSCL0 OSDA1 OSCL1 OPWM0 OPWM1 OPWM2
OPWRSB
OPCTRL0 OPCTRL1 OPCTRL2 OPCTRL3 OPCTRL4 OPCTRL5ORESET_
C_XREG
AVD D33_REG
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
AVD D33_SRV
XTALI
XTALO
VCXO
AVD D33_XTAL
TXC
IIC ADDRESS "A0"
Adjust the power on timing
AVDD33_XTAL
R200
180K
POWER_ON
MT5133_RESET
CI_CLE
NC
R37
CI_POWE#
207 208 209 59 60 210 211 212 214 215 216
204 205
63
62 191 202 203
72
92 91 76 75 90
8971
87
88
148
149
150
151
152
147
144
143
146
145
U203
MT5335PKU
EDID_PRT
EDID_PRT
CI_INT
LV DSVDD_EN
R38
10K
R44
10K
R36
10K
4K7
R39
B
C
E
Q1
BT3904
R40
NC\0R
DV33
DV33
R201
4K7
B
C
E
Q200
BT3904
R203
10K
PANEL_SLT
ORESET#
C_XREG
PWRDET
OSDA0
OSCL0
OSDA0 OSCL0
OSDA1 OSCL1
BL_DIM
OPWM1
OXTALO
OXTALI
AVC C_SRV
KEY
SCART_FS_IN
PWRDET
AVD D33_REG C_XREG ORESET#
SW_UPDATE_CTL
HDMI_INT
CEC
BL_ON/OFF
AMP_MUTE
CI_ALE
CI_OEB
CI_PDD7
CI_PDD6
CI_PDD5
CI_PDD4
CI_PDD3
X200
60M
C203
4U7
B
C
E
Q206
C124ET
DV33
C221
10P
C222
10P
C223
1000P
L214
0.82UH
C205
1U
C206
1U
5
6
7
8
4
3
2
1
U205
M24C16MN
R217 33R
Z958
C201
220U
16V
L211
600R
L210
600R
L212
600R
C204
1U
D200
LL4148
MTK_IC_RESET
OXTALI
DV33
R209
1K
R208
220R
R210
47K
OXTALO
DV33
C247
0.1U
R216
4K7
R215
4K7
R214
10K
DV33
R204
10K
R205
10K
DV33
DV33
DV33
DV33
R211
NC
C226
0.1U
C224
0.1U
C225
0.1U
B
C
E
Q202
BT3904
R207
10R
R206
1K
B
C
E
Q201
BT3904
R202
10K
AVD D33_REG
AVCC_SRV
AVDD33_XTAL
Z956
Z957
Z960
Z959
OPWM2
KEY_5335
MT5335 VIDEO PROCESSOR
B07 B07
I_17950_027.eps
070508
33TCM2.0E LA 7.

SSB v1: MT5335 Video Processor

Page 34
Circuit Diagrams and PWB Layouts

SSB v1: MT5335 Interface USB/HDMI

34TCM2.0E LA 7.
B08 B08
MT5335 INTERFACE - USB, HDMI
AV1 2
AV12
C228
1U
L215
600R
1U
C207
AVDD12_PLL
C249
0.01U
C250
0.1U
USB_VRT
USB_D-
USB_D+ AVD D33_USB AVDD12_USB
68 65 66 67
69 157 158
U203
USB_VRT USB_DM USB_DP AVD D33_USB AVDD12_USB TP0 TN0
AVDD12_KADCPLL
AVDD12_TVDPLL
AVDD12_KHDMIPLL
AVDD12_KAPLL
AVDD12_SYSPLL AVDD12_KDMPLL AVDD12_DTDPLL
160 155 153 161 159 156 154
AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL
AV33
GND
MT5335PKU
AV12
AV33
AV12
L216
600R
L217
600R
AVD D33_USB
1U
C208
AVDD12_USB
1U
C251
0.1U
C252
0.1U
GND
GND
USB_VRT
R218
5K1
SIFP SIFN
TS_VALIDO
TS_CKO
RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2
164 166 167
194
79
80 81 82 83 84 85 86
U203
SIFP SIFN
AF
TUNER_CLK
MT5335PKU
U203
RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2
MT5335PKU
AVDD25_SADC
AVSS25_SADC
RF_AGC
IF_AGCTUNER_DATA
EXT_RES
OPWR0_5V
AVD D33_HDMI
AVDD12_CVCC
163 165
193 192195
77 73
78
AVD D33_H
74
AVDD12_CVCC
AVDD25_SADC
TS_ DATA O
TS_SYNCO
GND
HDMI_5V
HDMI_5V
AV25
AV33
AV1 2
AV25
AV33
AV12
C229
1U
C230
1U
L218
600R
L219
L220
600R
600R
1U C210
C211
1U
C212
1U
C213
AVDD25_SADC
AVD D33_H
AVDD12_CVCC
0.01U
C255
0.1U
0.1U
C253
C248
GND
C254
0.1U
GND
GND
GND
I_17950_028.eps
070508
Page 35
Circuit Diagrams and PWB Layouts

SSB v1: Interface LVDS TTL

35TCM2.0E LA 7.
B09 B09
INTERFACE LVDS TTL
A0N A0P A1N A1P
A2N
A2P
CK1N
CK1P A3N A3P
A4N
A4P A5N
A5P
A6N
A6P
CK2N
CK2P
A7N A7P
Footprint is ACM-2012
GND
AV33
AV33
MT5335PKU
GND
GND
R222
0R
R223
0R
L200
EXC24C
A0N
14
A0P
2
L201
EXC24C
A1N
14
A1P
2
L202
EXC24C
A2N
14
A2P
2
L203
EXC24C
14
CK1P
2
L204
EXC24C
A3N
14
A3P
2
L205
EXC24C
A4N
14
A4P
2
L206
EXC24C
A5N
14
A5P
2
L207
EXC24C
A6N
14
A6P
2
L208
CK2N
CK2P CLK22+
EXC24C
14
2
L209
EXC24C
A7N
14
A7P
2
3
3
3
3
3
3
3
3
3
3
AN00
AP00
AN11
AP11
AN22
AP22
CLK11-CK1N
CLK11+
AN33
AP33
AN44
AP44
AN55
AP55
AN66
AP66
CLK22-
AN77
AP77
C328
C329
C320
C321
C322
C323
C324
C325
C326
C327
C330
C331
C332
C333
C334
C335
C336
C337
C338
C339
10P
10P
GND
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
GND
GND
GND
GND
GND
GND
GND
GND
U203
244
A0N
243
A0P
242
A2N
241
A2P
240
CK1N
239
CK1P
237
A3N
236
A3P
235
A4N
234
A4P
233
A5N
232
A5P
231
A6N
230
A6P
228
A7N
227
A7P
226
CK2N
225
CK2P
224
A8N
223
A8P
222
A9N
221
A9P
CLK11+
R2130R
0R
R212
PANEL_CTL1
PANEL_CTL2
GND
AP00
AP11
AP22
AP33
AP44
AP55
AP66
CLK22+
AP77
AVD D33_LVDSA AVD D33_LVDSB AVD D33_LVDSC
AVD D33_VPLL
TP2 TN2
220 229 238
217
218 219
AVD D33_LVDS AVD D33_LVDS AVD D33_LVDS
AVD D33_VPLL
CI_POCE1#
P202
39
37
35
33
31
29 30
27
25
23
21
19
17
15
13
11
9
7
5
3
40
AN00
38
AN11
36
AN22
34
32
CLK11-
AN33
28
26
24
22
AN44
20
AN55
18
AN66
16
CLK22-
14
AN77
12
10
8
6
4
12
VDD_PANEL
C260
0.1U
GND
12V
5V_OUTSIDE
+5V
R25NC
12V
35KEY_5V
PANEL_SLT
NC R26
L232
R232
NC
R26 FOR 19" 22" PANEL
R25 FOR OTHER +5V SUPPLY PANEL
NC/30R
P209
5
3
6
4
12
L233
NC/30R
LVD SVDD_EN
AV33
AV33
AV33
AV33
16V
GND
1U
1U
C231
C220
C202
220U
GND
L221
600R
L222
600R
4
6
R229 750R
0.1U
P204
LV DS OUT
C258
C
B
E
GND
1U
C214
C232
12
3
5
R219 10K
100K
Q204
C143ZT
AVD D33_LVDS
AVD D33_VPLL
1U
R221
R231 100K
1U
C209
Z210
T
C256
0.1U
C257
0.1U
6K8
R228
120R
R230
DV33
1
S1
2
S2
3
S3
G
DV33
GND
Q203
AO445 9
C259
0.1U
GND
R224 1K
R225 390R
R226 390R
R227
390R
8
D1
7
D2
6
D3
54
D4
C261
0.1U
Z212
T
VDD_PANEL
GND
GND
I_17950_029.eps
070508
Page 36

SSB v1: Flash Memory

5 4 3 2 1
Circuit Diagrams and PWB Layouts
36TCM2.0E LA 7.
B10 B10
D
C
B
FLASH MEMORY
R233
U0TX
U0RX
RS-232
10K
POCE0# POOE# PDD0 PDD1
CI_RB
CI_PDD2
R234
10K
252 251 250 249
245 248
MT5335PKU
OIRI_MT5335
AV33
GND
1
2
3
4
U203
POCE0_ POOE_ PDD0 PDD1
PAR B _ PDD2
BT3904
P201
DV33
L223
U0RX U0TX
OIRI
JTMS
JTRST_
JTCK
JTDO
JTDI
95 94
93
253 1 256 255 254
U0RX U0TX
OIRI_MT5335
JTMS
JTRST#
JTCK JTDO JTDI
600R
C240
POCE0#
PDD0
1U
GND
R289
10K
R245
0R
+5V
C
Q3
E
R89
4K7
R90
10K
B
OIRI
GND
USB_D-
USB_D+
1 2
+5V
C006
100U
6V3
0.1U
C007
GND
0R
R2011
R2012
0R
1
2
3
4
U202
116
HOLD# SCLK
2
VCC
3
NC
4
PO2
5
PO1
6
PO0
7
CS#
8
SO
WP#/ACC
PO6
PO5
PO4
PO3
GND
15
SI
14
13
12
11
10
9
POOE#
PDD1
DV33
R246
4K7
FRESET#
MX25L3205
GND
JTDO
DV33
JTRST#
JTDI
JTMS
JTCK
33R
R239
R270
10K
DV33
6
7
8
R235
1K
1
2
3
45
TVTREF#1
JTAG_DBGRQ
JTAG_DBGACK
4
6
8
10
12
14
16
18
20
12
3
5
7
9
11
13
15
17
19
P203
R236
10K
R238
R237
10K
10K
P200
R87
EZJZ1V270RA
21
GND
R88
EZJZ1V270RA
GND
0.1U
C262
GND
C264
0.1U
0.1U
C263
1U
C234
1U
C235
DV1 0
D
C
GND
B
DV33
R240
OPWM2
DV1 0
U203
14
VCCK
48
VCCK1
57
VCCK2
58
VCCK3
61
VCCK4
70
DVDD10
162
DVDD10_1
213
VCCK6
206
VCCK5
246
VCCK7
A
VCC2IO VCC2IO1 VCC2IO2 VCC2IO3 VCC2IO4 VCC2IO5 VCC2IO6 VCC2IO7 VCC2IO8 VCC2IO9
VCC3IO_3_2 VCC3IO_3_1
VCC3IO_3
E-PAD
10 12 16 18 27 30 52 54 55 56
64 197 247
257
DDRV_IC
DV33
GND
R244
4K7
Trap MODE
NORMAL MODE
ICE MODE
TRAP MODE
CORE RESET 1 US
AOBCK
AOLRCK
4K7
R241
4K7
R242
NC\4K7
GND
OPWM2 AOBLK AOLRCK
0
0
OPCTRL5
00
0
0
1
OPCTRL4
1
1U
C237
DDRV_IC
GND
1U
C238
GND
1U
C236
1U
C239
C265
C279
0.1U
0.1U
C266
C278
0.1U
0.1U
C267
C277
0.1U
0.1U
C270
0.1U
C276
0.1U C269
0.1U
C275
0.1U C268
C274
0.1U
0.1U
C272
C273
0.1U
0.1U
0.1U
C271
A
MT5335PKU
I_17950_030.eps
12345
070508
Page 37

SSB v1: SDRAM

Circuit Diagrams and PWB Layouts
37TCM2.0E LA 7.
B11 B11
RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15
MEM_VREF RCS#
MT5335PKU
6V3
SDRAM
U203
11
RDQS0
13
RDQM0
9
RDQ0
8
RDQ1
7
RDQ2
6
RDQ3
5
RDQ4
4
RDQ5
3
RDQ6
2
RDQ7
17
RDQS1
15
RDQM1
19
RDQ8
20
RDQ9
21
RDQ10
22
RDQ11
23
RDQ12
24
RDQ13
25
RDQ14
26
RDQ15
53
RVREF 0
46
RCS_
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
+5V
C200
100U
GND
RA0 RA7
RWE_
RBA0
RA6
RBA1
RA5
RRAS_
RA8
RA10
RA4
RCAS_
RA12
RCKE
RA11
RA9 RA3 RA1 RA2
RCLK0_
RCLK0
R275
47R
1
2
3
45
R276
47R
1
2
3
45
R277
47R
1
2
3
45
R278
47R
1
2
3
45
R279
47R
1
2
3
45
U201
LD1117S
VIN
3
0.1U
C303
RA0
47
RA7
36
RWE#
40
RBA0
43
RA6
37
RBA1
44
RA5
38
RRAS#
42
RA8
35
RA10
45
RA4
39
RCAS#
41
RA12
32
RCKE
31
RA11
33
RA9
34
RA3
51
RA1
49
RA2
50
RCLK0#
28
RCLK0
29
8
7
6
RA12
RA11
RA9
RA8
8
7
6
RA7
RA6
RA5
RA4
RWE#
8
7
RCAS#
RRAS#
6
RCS#
8
7
RBA0
RBA1
6
RA10
8
7
6
RA0
RA1
RA2
RA3
4
4
GND/ADJ
OUT
1
2
R262
110R
R263
120R
GND
1.25 x (1+120/110) = 2.6V
RCKE
RCLK0
RCLK0#
22R
22R
22R
R258
R259
R260
MEM_ADDR13
MEM_CLKEN
MEM_CLK0
R261
MEM_CLK0#
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15
DDRV_IC
100R
GND
10 11 13 54 56 57 59 60 62 63 65
14 17 19 25
43 50 53
18
33
15 55 61
34 48 66
12 52 58 64
2 4 5 7
8
1
3
9
6
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
NC NC1 NC2 NC3
NC4 NC5 NC6
VDD VDD1 VDD2 VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4
VSS VSS2 VSS1 VSSQ1 VSSQ2 VSSQ VSSQ3 VSSQ4
32M*16DDR
U204
A10/AP
VREF
LDQS UDQS
CKE
RAS CAS
LDM UDM
MEM_VREF
49
MEM_ADDR0
29
A0
30 31 32 35 36 37 38 39
40 28 41 42
45 46 44
24 23 22 21
16 51
20 47
26 27
L224
600R
MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9
MEM_ADDR10 MEM_ADDR11 MEM_ADDR12
MEM_CLK0
MEM_CLK0#
MEM_CLKEN
MEM_CS#
MEM_RAS# MEM_CAS#
MEM_WE#
MEM_DQS0 MEM_DQS1
MEM_DQM0 MEM_DQM1
MEM_BA0 MEM_BA1
R265
0R
0R
R264
0R
R266
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS0
RDQM0
RDQM1
RDQS1
RDQ11
RDQ10
RDQ9
RDQ8
R271
47R
1
2
3
45
R272
47R
1
2
3
45
47R
47R
47R
47R
R273
47R
1
3 6
R248
R249
R250
R251
8
7
6
8
7
6
MEM_DQS0
MEM_DQM0
MEM_DQM1
MEM_DQS1
8
72
54
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ11
MEM_DQ10
MEM_DQ9
MEM_DQ8
R287
75R
1
2
3
8
7
6
45
R286
75R
1
2
3
8
7
6
45
R254
75R
R255
75R
R256
75R
R257
75R
R285
75R
1
2
3
8
7
6
45
DDRV
GND
L225
R267
100K
600R
MEM_VREF
0.1U
R274
47R
MEM_DQ15
RDQ15
RDQ14
C306
C305
C304
0.1U
0.1U
RDQ13
RDQ12
1
2
3
45
8
7
MEM_DQ14
MEM_DQ13
6
MEM_DQ12
R288
75R
1
2
3
8
7
6
45
GND
47U
6V3 C217
NC3
NC2
NC1
RT9199
REFENVCNTL
U200
GND
VOUT
1
VIN
2
36
L226
600R
4
8
7
5
220U
R268
100K
C314
16V
R269
1K
GND
A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12
CLK CLK
CS
WE
BA0 BA1
+5V
+1V3D
+1V3D
R280
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#
DDRV
DDRV
C349 IS CLOSE TO PIN33 OF DDR
L213
600R
DDRV_IC
16V
0.1U
0.1U
C280
C281
0.1U
0.1U
C282
C283
0.1U
0.1U
C284
0.1U
C285
0.1U
C287
C286
C315
100U
6V3
C349
220U
GND
MEM_VREF
+1V3D
MEM_ADDR10
MEM_BA1
MEM_BA0
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_CLKEN
4U7
0.1U
C302
C215
0.1U
C300
GND
+1V3D
1U
0.1U
C301
C216
C296
0.1U C297
0.1U C299
0.1U
0.1U
C298
GND
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR13
MEM_ADDR3
MEM_ADDR2
1U
0.1U
0.1U
C294
C292
0.1U
C295
C316
0.1U
0.1U C288
C293
0.1U
C291
C290
0.1U
0.1U
C289
MEM_ADDR1
MEM_ADDR0
75R
1
2
3
8
7
6
45
R281
75R
1
2
3
8
7
6
45
R282
75R
1
2
3
8
7
6
45
R252
75R
R283
75R
1
2
3
8
7
6
45
R253
75R
R284
75R
1
2
3
8
7
6
45
GND
I_17950_031.eps
+1V3D
070508
Page 38
Circuit Diagrams and PWB Layouts

SSB v1: MT5335 Interface VGA

38TCM2.0E LA 7.
A
B12 B12
MT5335 INTERFACE - VGA
U203
VGA_ L VGA_ R YPBPR_L YPBPR_R AIN2_L AIN2_R
SCT_L SCT_R
AVD D33_AADC
GND VIMD_AADC REFP_AADC GND
MT5335PKU
AV33
AV33
A
4U7
C219
L227
600R
177
AIN0_L
176
AIN0_R
175
AIN1_L
174
AIN1_R
173
AIN2_L
172
AIN2_R
171
AIN3_L
170
AIN3_R
169
AVD D33_AADC
181
AVSS33_AADC
179
VMID_AADC
180
REFP_AADC
178
REFN_AADC
C241
1U
AVDD33_KADAC0 AVDD33_KADAC1
AVSS33_KADAC0 AVSS33_KADAC1
AVDD33_AADC
GND
ASPDIF
AOMCLK
AOLRC K
AOBCK
AOSDATA0
ADAC_VCM
AVDD33_DIG
0.1U
C307
AL1
AR1
AL2
AR2
201 198
AOLRC K
199 200
A0SDATA0
196 186 185 189 187
AVDD33_ADAC0
190
AVDD33_ADAC1
182
GND
188
GND
184
ADAC_VCM
183
AVDD33_DIG
168
ASPDIF
AOMCLK
AL1O
AR1O
AL2O
AR2O
AV33
AV33
L231
600R
L234
600R
AOBCK
1U
C245
AVD D33_ADAC1
GND
C311
0.1U
1U
C246
ADAC_VCM
0.1U
C313
A
GND
AV33
AV33
AV33
AV33
L228
L229
600R
600R
C242
1U
C243
1U
AVDD33_ADAC0
GND
REFP_AADC
GND
GND
C308
0.1U
C309
GND
0.1U
GND
AV33
AV33
L230
600R
1U
C244
AVD D33_DIG
GND
C310
GND
0.1U
GND
GND
4U7
C218
GND
GND
VIMD_AADC
C312
0.1U
GND
A
I_17950_032.eps
070508
Page 39

SSB v1: D/A Converter

GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
LRCLK
DIN
BCLK
ENABLE
VMID
ROUT
AGND
DGND
DVD D
DEEMPH
FORMAT
MCLK
LOUT
AVDD
2IN+
2IN-
2OUT
VCC+
1IN+
1IN-
1OUT
VCC-
DAC
A
A
A
A
5
6
7
8
3
2
1
4
U1
RC4558
C9009
1U
C9015
1U
L931
30R
L930
30R
SPEAK-OUTR
R9021
10K
C9016
1U
C9014
0.1U
L900
600R
L901
600R
1
2
3
4
5
6
7
10
11
12
13
14
9
8
U907
WM8501
R9030
33R
R902833R
R902733R
R9019 47K
R9017
0
C9017
1U
C9010
0.1U
C9008
1U
R9022
10K/NC
DV33
AOMCL K
DV33
DV33
DV33
+5V
C913
1000P1000P
C914
SCT1_AUL_OUT
SCT1_AUR_OUT
R9026
NC/33K
R9018
0
R9020 10K
C9018
0.1U
ADCVA
R9024
10K
DACVL
DACVL
10K R9023
C9012
0.1U
C9013
0.1U
R9029
33R
NC/33K
R9025
AOLRCK
A0SDATA0
AOBCK
ADCVA
DACVL
C9011
1U
ADCVA
C902
47U
6V3
C903
47U
6V3
C901
1U
1U
C900
AV9 V
AV9V OPAVREF
C912
1U
L16
600R
C910
1U
10K
R914
R904
10K
NC
C929
C925
2200P
C928
100P
C927
100P
C926
2200P
R908
10R
R900
100K
R907
5K1
R906
33K
R901 470R
100K
R902
470R
R903
R905
10K
33K
R909
5K1
R910
10R
R913
NC
C930
R915
10K
1U
C911
AR1O
AL1O
OPAVREF
OPAVREF
OPAVREF
SPEAK-OUTL
DIGITAL-ANALOG-CONVERTER
B13 B13
I_17950_033.eps
070508
Circuit Diagrams and PWB Layouts
39TCM2.0E LA 7.
Page 40

SSB v1: HDMI Switch

Circuit Diagrams and PWB Layouts
40TCM2.0E LA 7.
B14 B14
HDMI SWITCH
P901
RX0-
NC1
HPD
RX2+
RX2-
RX0+
RX0-
GND1
DDCDA
NC1
HPD
RX1+
RX1-
GND3
RXC+
RXC-
NC2
VCC
P903
GND1
RX1+
RX1-
GND3
RXC+
RXC-
NC2
DDCDA
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
CEC-IN
14
15
16
17
18
19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RX2+
RX2-
GND2
RX0+
GND4
DDCCLK
GND5
GND2
GND4
DDCCLK
GND5
R42 NC\0R
HDMI1_SCL
HDMI1_SDA
+5V_HDMI1
CEC
+5V_HDMI0
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20
DV33
DV33-HDMI
L9
600R
AV18-HDMI
R31
750R
C38
0.1U
0.1U
1U
C42
C39
GND
RX0_2 RX0_2B
RX0_1 RX0_1B
RX0_0 RX0_0B
RX0_C RX0_CB
NC\4K7
0.1U
C43
R15 4K7
DV33
GND
RESET_N
OSDA0
OSCL0
R54 4K7
R16 NC\4K7
R11
4K7
HDMI_SEL
R17
100R
100R 100R
R20 R18 R19
HPDIN
100R
OSDA1 OSCL1
HDMI_5V
0R
CEC-IN
1
R72
EZJZ1V270RA
2
GND
CI_DV18 AV18-HDMI
L11
600R
0.1U
0.1U
C12
C11
R45
CEC
DV33-HDMI
D5V0S1
D104
D105
10P
10P
C134
D5V0S1
D5V0S1
D106
D107
C133
D5V0S1
10P
10P
C136
C135
GND
CI_DV18
0.1U
0.1U
0.1U
C13
C14
0.1U
C15
C16
1U
C19
0.1U
C17
DV18-HDMI
L10
600R
0.1U
0.1U
C21
C20
1U
0.1U
C23
C22
R12
NC\4K7
R14 4K7
R13 4K7
GND
DV33
R32
R33
100R
NC\100R
R34
NC\100R
R35
R52 4K7
R55
4K7
C
Q2
B
BT3904
E
GND
100R
R53
D108
GND
134
2
D3V3L4
5
DV18-HDMI
R21
4K7
GND
R59
4K7
60 59 58 57 56 55 54
NC\0RR41
53 52 51 50 49 48 47 46 45 44 43 42 41
DV33
AGND7 RXC2+ RXC2­AVCC18D HPD2 AVCC33C CEC-A CEC-D RPWR1 DSCL1 DSDA1 AVDD18B R1X2+ R1X2­AGND6 R1X1+ R1X1­AVCC33B R1X0+ R1X0-
R30
GND
NC\4K7
63
6261656468
AVCC 33D
R2X0+
R2X0-
R2X1-
R1XC+
R1XC-
AGND5
AVCC18C
37
39
38
40
4K7
R51
R2X1+
HPD1
36
66
AGND8
35
67
R2X2-
I2CSEL/INT
34
R2X2+
DGND1
33
69
AVDD 18C
DSDA2
U904
SII9185
RPWR0
DVCC 18A
32
70
72
71
DSCL2
DVCC 18B
RPWR2
AVDD18A
DSCL0
DSDA0
29
30
31
DGND2
R0X2+
27
RSVDL
R0X2-
26
75
AGND4
767473
HPDIN
R0X1+
77
TSDA
R0X1-
80
79
78
AGND9
TSCL
TPWR/I2CADDR
AVCC 18A
EXTSWING
AVCC 18B
R0X0+
R0X0-
AVCC 33A
2221252428
23
TX2+
TX2-
AGND1
TX1+
TX1-
TX0+
TX0-
AGND2
TXC+
TXC-
RESET#
LSDA
LSCL
HPD0
R0XC-
R0XC+
AGND3
GND
HDMI0_SCL
HDMI0_SDA
R58
4K7
+5V_HDMI0
+5V_HDMI1
GND
D109
T
T
U905
1
A0
0.1U
C40
2
Z907
GND
A1
3
A2
4
GND
1
D3V3L4
345
2
T
AT24C02
VCC
SCL
SDA
8
R56 4K7
7
WP
6
5
R50
R49
47K
47K
HDMI0_SCL
HDMI0_SDA
T
T
Z906
Z905
T
Z908
0.1U
Z904
U906
1
VCC
A0
C41
2
WP
A1
3
SCL
A2
4
SDA
GND
AT24C02
GND
Z903
8
R57
R48
R47
4K7
47K
7
6
5
47K
HDMI1_SCL
HDMI1_SDA
T
T
Z901
Z902
GND
I_17950_034.eps
070508
Page 41

SSB v1: I/O Scart

GND
GND
GND
GND
GND
T
T
T
T
T
GND
GND
T
T
T
T
T
T
GND GND
GND
GND
GND
NEARLY MT5335
Nearly Connector
Nearly 5335
21
R62
EZJZ1V270RA
21
R60
EZJZ1V270RA
21
R67
EZJZ1V270RA
21
R68
EZJZ1V270RA
21
R66
EZJZ1V270RA
21
R65
EZJZ1V270RA
21
R64
EZJZ1V270RA
1U
C965
1
2
3
12
13
14
15
4
5
6
7
16
17
18
19
8
9
20
21
10
11
P1
PB0P
Y0N
STC1_FB_IN
SCT1_R_IN
SCT1_G_IN
SCT1_FS_IN
Z927
Z922
Z924
SCT1_AUL_OUT
SCT1_AUR_IN
Z925
Z921
SCT1_AUR_OUT
Z926
SCT1_AUR_IN
SCT1_AUL_IN
SCART_FS_IN
R962 10K
R963
0R
SCT1_AUL_OUT
SCT1_AUR_OUT
L1
30R
SCT1_AV_IN
Z918
Z919
Z920
Z928
SOY0
SC0
GND_SV
SY0
Y0P
PBR0N
PR0P
SCT_R
SCT_L
R977
68R
C968
0.047U
R972
100R
75R
R968
C969
1U
C979
470P
L908
30R
L907
30R
C963
470P
C977
0.01U
L906
30R
C976
16P
75R
R976
R978
100R
R974
100R
C974
0.01U
R973
68R
L905
30R
C973
16P
75R
R975
C972
0.01U
C971
0.01U
75R
R971
C970
16P
L904
30R
R969
68R
R970
100R
L903
30R
C967
47P
R967 10K
R966 10K
C964
470P
R965
10K
R964
10K
L2
30R
R961
33K
R960 75R
C975
0.01U
C978
0.047U
C980
470P
Z923
SCT1_B_IN
SCT1_AUL_IN
SCT1_AV_OUT
C966
1U
1 2
EZJZ1V270RA
R63
SCT1_AV_IN
STC1_FB_IN
SCT1_FS_IN
21
R61
EZJZ1V270RA
SCT1_G_IN
SCT1_B_IN
SCT1_R_IN
I/O - SCART
B15 B15
I_17950_035.eps
070508
Circuit Diagrams and PWB Layouts
41TCM2.0E LA 7.
Page 42
Circuit Diagrams and PWB Layouts
T
GND
TT
GND
GND
GND
GND
GND
GND
T
GND
GND
DVSS25_VADC
GND_TUNER
GD_CVBS
GND_SV
AVSS25_VFE
AVSS25_VADC
AVDD25_REF
AVSS25_REF
AVDD25_VFE
CVBS0 CVBS1
SY0 SC0 SY1 SC1
DVDD25_VADC
AVDD25_VADC
D2SA
CVBS2
T
T
GND
T
GND
RED
WHITE
YELLOW
GND
GND
Close to MT5382p
Nearly Connector
Nearly 5335
R918
0R
R919
NC
R924 0R
CI_GPIO14
C001
47U
6V3
R944
4K7
R921
4K7
B
C
E
Q815
BC847C
R9002 10K
CVBS_OUT
R9001
470R
L925
10R
21
R71
EZJZ1V270RA
21
R69
EZJZ1V270RA
21
R70
EZJZ1V270RA
8
5
6
7
9
P902
3
2
1
4
P902
Z978
Z974
SY1
Z917
C003
1U
140 133 131 124
134
142 137 138 135
132 130
128 127 126 125
139
141
136
129
U203
MT5335PKU
D2SA
SC1
SY1
SC0
CVBS2
C002
47P
R9004
75R
R9003
10K
C004
0.01U
Z975
DVDD25_VADC
C920
1U
SY0
CVBS0
C953
0.047U
AV2 5
AV25
AV2 5
AV25
AV2 5
AV25
AV25
AV2 5
L912
600R
C954
0.1U
R945
100R
C916
1U
L911
600R
GND
GND
GND
GND
AVDD25_VADC
AVDD25_REF
AVDD25_VFE
DVDD25_VADC
GND_CVBS GND_SV
C955
0.1U
C917
1U
L913
600R
C956
0.1U
C918
1U
L914
600R
C957
0.1U
C919
1U
GND_TUNER
AVDD25_VADC
AVDD25_REF
AVDD25_VFE
L915
30R
C959
0.047U
75R
R947
R946
100R
C958
47P
L916
30R
C961
0.047U
75R
R949
R948
100R
C960
47P
SC1
SCT1_AV_OUT
AV_ 5V
CVBS1
1U
C9001
C9004
470P
L926
30R
R9011 10K
R9012 10K
C9003
470P
R9009
10K
R9010
10K
L927
30R
Z980Z981
C9002
1U
C915
1U
C9007
47P
75R
R9014
L928
30R
C9006
0.047U
R9013
100R
AIN2_L
AIN2_R
CVBS2
GND_CVBS
Z976
R920
1K
B
C
E
Q906
BC847C
D2SA
I/O - SIDE AV, SVIDEO, AUDIO
B16 B16
I_17950_036.eps
070508

SSB v1: I/O Side AV, S-Video, Audio

42TCM2.0E LA 7.
Page 43
Circuit Diagrams and PWB Layouts
GND
GND
BLACK
GND
GND
GND
T
T
T
SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1 Y1P Y1N PB1P PBR1N PR1P
TN1 TP1
DVDD12_VGA AVSS12_RGBADC AVDD12_RGBADC
AVSS12_RGBFE
AVDD12_RGBFE
RP RN
BP BN GP GN
VSYNC HSYNC
SOG
GND
GND
GND
GND
WHITE
GREEN
RED
BLUE
RED
Nearly Connector
Nearly 5335
Y_IN
VGA_L_IN
VGA_R_IN
PR_IN
YPBPR_R_IN
YPBPR_L_IN
1
4
2
5
3
6
9
7
8
10
P907
21
R73
EZJZ1V270RA
21
R76
EZJZ1V270RA
21
R77
EZJZ1V270RA
21
R74
EZJZ1V270RA
PB_IN
21
R75
EZJZ1V270RA
1U
C720
YPBPR_R
YPBPR_L
YPBPR_R_IN
PR_IN
L6
30R
SOY1
Y1P
Y1N
PB1P
PR1P
R988 75R
C724
16P
L5
30R
C727
16P
R985 75R
PB_IN
Y_IN
L4
30R
PBR1N
PR1P
PBR1N
PB1P
Y1N
Y1P
SOY1
YPBPR_L_IN
107 108 109 114 115 116 118 119 120 121 122 123
112 111
117 113 110 105 101
104 106 98 99 102 103 96 97 100
U203
MT5335PKU
Z940
Z939
Z929
GN
SOG
GP
BN
BP
RN
RP
HSYNC
VSYNC
ASPDIF
AV12
AV12
AV12
AV12
AV12
AV12
1
2
P904
R984
0R
C728
4700P
C729
0.01U
R983
100R
C730
0.01U
R981
68R
C732
0.1U
C993
33P
R980 100R
R979
100R
DVDD12_VGA
GND
GND AVDD12_RGBADC
AVDD12_RGBFE
PB0P PBR0N
SOY0
PR0P
Y0N
Y0P
C988
0.1U
L909
600R
C987
1U
C990
0.1U
L910
600R
C989
1U
C992
0.1U
L3
600R
C991
1U
R982 75R
C731
16P
C725
0.01U
R987
100R
C726
0.01U
R986
68R
C723
0.01U
R989
68R
C719
470P
L8
30R
R993 10K
R992 10K
C722
470P
R991
10K
R990
10K
L7
30R
DVDD12_VGA
AVDD12_RGBADC
AVD D12 _RG BFE
C721
1U
SPDIF_OUT
MT5335 INTERFACE - YPBPR, VGA
B17 B17
I_17950_037.eps
070508

SSB v1: MT5335 Interface YPbPr & VGA

43TCM2.0E LA 7.
Page 44

SSB v1: I/O VGA

GND
GND
GND
T
T
GND
T
T
T
SDA
SCL
WP
VCC
GND
A2
A1
A0
T
GND
GND
GND
GND
T
T
T
T
T
T
T
T
T
GND
GND
GND
GND
Nearly Connector
Nearly 5335
R726
0R/NC
SW_UPDATE_CTL1
SW_UPDATE_CTL
22K
R718R717
22K
21
R85
EZJZ1V270RA
21
R84
EZJZ1V270RA
21
R82
EZJZ1V270RA
BLUE
GREEN
RED
21
R80
EZJZ1V270RA
VGASCL_IN
HSYNC_IN
12
EZJZ1V270RA
R83
C701
1U
VSYNC
VGASCL
BN
VGASCL_IN
W/P_CTR
VSYNC_IN
HSYNC_IN
VGASDA_IN
RN
100R
R997
C713
0.01U
L918
30R
R998
0R
C712
4700P
R719
33R
C714
0.01U
C715
16P
75R
R996
GREEN
BLUE
R701
100R
R703
100R
C706
0.01U
C707
0.01U
C709
0.01U
C710
0.01U
R720
33R
C711
16P
75R
R999
L919
30R
R721
33R
C708
16P
75R
R702
L920
30R
RED
12
3
D913
BAV70
R716
0R
C005
ESD_0402
Z945
Z941
Z942
Z943
Z944
Z955
Z946
Z948
Z947
VGA_PLUGPWR
+5V
R707 10K
R706 10K
R705
10K
R704
10K
C999
470P
HSYNC
L921
30R
C705
10P
C704
10P
L922
30R
R714 10K
U0RX
U0TX
5VSB
5VSB
R713 100R
R712
100R
R725 10K
B
C
E
Q905
C143ZT
VGASCL_IN
B
C
E
Q904
C143ZT
R709
100R
C998
16P
VGASDA
R711
100R
5VSB
5VSB
R710 10K
Z970
5
6
7
8
4
3
2
1
U903
AT24C02
Z971
Z972
Z973
VGASDA
VGASCL
W/P
6
4
11
14
15
7
12
8
5
13
3
10
9
1
2
16
17
P908
BP
GN
GP
SOG
VGA_L
VGA_R
5VSB
5VSB
C996
0.1U
VGA_PLUGPWR
VGA_PLUGPWR
R715 10K
B
C
E
Q903
C143ZT
R708 10K
Z950
L924
30R
L923
30R
Z949
C997
16P
VGASDA_IN
470P
C703
W/P
RP
VGA_R_IN
VGA_L_IN
1U
C702
VSYNC_IN
21
R81
EZJZ1V270RA
VGASDA _IN
21
R86
EZJZ1V270RA
I/O - VGA
B18 B18
I_17950_038.eps
070508
Circuit Diagrams and PWB Layouts
44TCM2.0E LA 7.
Page 45

SSB v1: LVDS Receiver

GND
GND
GND
GND
VCC4 RXOUT21 RXOUT20 RXOUT19
GND5 RXOUT18 RXOUT17 RXOUT16
VCC3 RXOUT15 RXOUT14 RXOUT13
GND4 RXOUT12 RXOUT11 RXOUT10
VCC2 RXOUT9 RXOUT8 RXOUT7
GND3 RXOUT6 RXOUT5 RXOUT4 RXOUT3
VCC1 RXOUT2 RXOUT1GND2
RXOUT0
RXCLKOUT
PWRDWN
PLLGND2
PLLVCC1
PLLGND1
LVD SGND3
RXIN3+
RXIN3-
RXCLKIN+
RXCLKIN-
RXIN2+
RXIN2-
LVD SGND2
LVD SVCC1
RXIN1+
RXIN1-
RXIN0+
RXIN0-
LVD SGND1
RXOUT27
RXOUT26
RXOUT25
GND1
RXOUT24
RXOUT23
RXOUT22
GND
GND
L239
120R
R24
100R
R23
100R
B
C
E
Q5
C143ZT
PWRDN_EN
R2005
100R
R2004
100R
R2003
100R
AP33
AP33
AN33
AN33
CLK11+
CLK11+
CLK11-
CLK11-
AN22
AP22
AN22
AN11
AP00
AP11
AP11
AN11
AP00
AN00
PANEL_CTL2
C2010
NC\TTL\0.1U
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
56
78
9
P205
C2011
NC\TTL\16P
R292
NC\TTL\33R
R291 NC\TTL\10K
1
2
3
45
6
7
8
R290
NC\TTL\33R
1
2
3
45
6
7
8
R299
NC\TTL\33R
1
2
3
45
6
7
8
R298
NC\TTL\33R
1
2
3
45
6
7
8
R296
NC\TTL\33R
1
2
3
45
6
7
8
R295
NC\TTL\33R
1
2
3
45
6
7
8
R294
NC\TTL\33R
1
2
3
45
6
7
8
R293
NC\TTL\33R
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U207
V386
C2015
NC\TTL\0.1U
C2007
NC\TTL\0.1U
C2006
NC\TTL\0.1U
C2004
NC\TTL\0.1U
C2202
NC\TTL\0.1U
C2001
NC\TTL\0.1U
L929
NC\TTL\600R
T_R1
T_R2
T_G0
T_R5
T_CLK
T_R0
T_HSYNC
T_B3 T_B2
T_B1
T_B0
T_G7 T_G6
T_G5 T_G4
T_G3
T_G2
T_R7
DV33A_LVDS_RECEIVER
CLK
D_VSYNC
B6
B4
B2
B0
G6
G4
G2
R6
R4
DE
D_HSYNC
B7
B5
B3
G1
VDD_PANEL
DV33A
DV33A
DV33A
DV33A
B0
B1
B2
G2
G3
G4
R0
T_DE
T_HSYNC
T_VSYNC
T_B0
T_B1
T_B2
T_B3
T_B4
T_B5
T_B6
T_B7
T_G0
T_G1
T_G2
T_G3
T_G4
T_G5
T_G7
T_R0
T_R1
T_R2
T_R3
T_R4
T_R5
T_R6
T_R7
T_B7 T_B6
T_B5
T_B4
T_G1
T_R6
T_R4 T_R3
T_DE
T_VSYNC
AP22
AN00
G0
R2
R0
B1
G7
G5
G3
G1
R7
R5
R3
R1
CLK
D_VSYNC
D_HSYNC
DE
B3
B4
B5
B6
B7
G0
G5
G6
G7
R1
R2
R3
R4
R5
R6
R7
T_G6
PWRDN
DV33A_LVDS_RECEIVER
PWRDN
T_CLK
LVD S RECEIVER
B19 B19
I_17950_039.eps
070508
Circuit Diagrams and PWB Layouts
45TCM2.0E LA 7.
Page 46
Circuit Diagrams and PWB Layouts
I_17950_040.eps
070508

Layout Small Signal Board v1 (Top Side)

46TCM2.0E LA 7.
Page 47
Circuit Diagrams and PWB Layouts
I_17950_041.eps
080508

Layout Small Signal Board v1 (Bottom Side)

47TCM2.0E LA 7.
Page 48

SSB v2: Tuner

8 76 543 21
Circuit Diagrams and PWB Layouts
48TCM2.0E LA 7.
B1
2
C122
DV33
DV33
NC/GND1
3
R148
0R
NC/100U
TUNER
NC
NC/GND2
NC/RFAGC
6
4
5
RF-AGC
C129
0.1U
L103
120R
C102
100U
6V3
8
OUT3
C103
7
OUT2
6
OUT1
5
OC
R95
NC/100R
Q105
2N7002
Q104
2N7002
TU
111412
TUNER_5V
R99
NC
U206
GND
NC/TPS2049
AV_5V
AV_5V
SCL
GND1
NC1
13
C125
22P
1
2
IN1
3
IN2
4
R96
EN
NC/100R
5V-TUNER-INPUT
R828
10K
TUNER_SDA0_5V
R829
10K
TUNER_SCL0_5V
SDA
15
AS
16
R132
C124
22P
R97
NC/4K7
17
NC
C100
IFAGC
XTALOUT
ANALOG_IF
IFOUT2
18
19
20
R135 4K7
R127
R126
1U
TUNER_5V
L104
NC/120
5V-TUNER-ON/OF
IFOUT1
21
100R
100R
R112
33R
L106
0
TUNER_5V
R124
100R
R125
100R
IF_AGC
R118
NC
R120
NC
C118
1000P
D100
Q103
TUNER_SDA0_5V
TUNER_SCL0_5V
5V-OUT
R109 2K2
0.01U
C104
2
BA592
1000P
C105
0.56UH
L101
C
B
C124ET
E
1000P
C106
L108
FAT_IN-
FAT_IN+
C123
0.01U
L100
1UH
2K2
R111
30R
R133
33R
D101
BA982
R113 6K8
R110 2K2
R117 NC
D102
BA982
AV_5V
R139 6K8
0R
R123
X101
IN
5V-OUT
Q102
BC847C
IN/GND
C
E
GND
R140 6K8
B
OUT1
54321
D103
BA982
R137 220K
R100 680K
X102
IN
OUT2
R119
IN/GND
R108
5K6
5K6
GND
0.1U
C137
RF-AGC
R141
22K
0.01U
C109
OUT1
54321
U100
0.01U
C108
TUNER_5V
5
VCC
U101
Y
1
NC\0R
OUT2
23
24
SIF2
VIF1
1
2
R149
SIF1
VIF2
C107
2
OP2
OP1
390P
Z
R101
330R
21
AFC
FMPLL
0.01U
C116
4
3
E
C138
4LVC1G66GV
GND
C111
0.22U
C110
20
19
VP
VPLL
DEEM
AFD
574133 22
6
MT5133-GPIO-AD
TUNER_5V
0.1U
BC847C
4M
1500P
0.47U
C114
18
AGND
DGND
1000P
15
VAGC
AUD CVBS
TOP
8 17
9 16
10
C128
C117 0.47U
Q106
R152
47K
REF
SDA
C
E
X100
C112
14
TAGC
SCL
11
20P
12
B
R121
22K
0.1U
C115
NC
SIOMAD
0.1U
R153
0R
TDA9886T
C127
0.1U
C140
5V-OUT
R114
R106
NC\6K8
R103
NC\1K5
22K
12K
R146
R147
NC
CVBS_OUT
R102
NC\180R
C
B
Q101
E
NC\BC847C
R104
NC\47R
R105 NC
0.01U
C3
0.01U
B
0.1U
C139
C119
R107
R138
C
E
CVBS-OUT
0R
220R
Q100
R145
12K
6V3
47U
ATV-IF-AGC
BC847C
R129
75R
L107
120R
TUNER_SCL0
TUNER_SDA0
C2
75R
R130
SIF
R93
NC\100R
D110
5V-OUT
0.01U
C113
0R
R116 100R
R115 100R
R94
NC\100R
ATV-IF-AGC
LL4148
6V3
47P
R128
C120
L102
100U
C121
0R
1P5
OSCL0
OSDA0
B01 B01
Z100
F
ANTPWR
1
E
D
0.1U
NC/0.1U
6V3
C126
C
B
TUNER_SDA0
TUNER_SCL0
A
120R
C101
TUNER_5V
CVBS0
R131
GND_TUNER
0.01U
C131
SIFP
SIFN
C132
0.01U
TUNER_SCL0_5V
TUNER_SDA0_5V
F
E
D
C
B
A
12345678
17953_521_090330.eps
090331
Page 49
Circuit Diagrams and PWB Layouts
GND
NRST
OSCI
VSS
TXD/IRQ2
PWMI
RXD/IRQ3
VIN
SCL2
SDA2
SDA1
AD3/IR
SCL1
HIN
OSCO VDD
AD0
INOUT
GND
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
OPTION for CEC Stand by Function
ISP PORT
R8350R
1
2
3
4
5
6
7
8
9
P805
1
2
3
4
P802
NC
R842
35KEY_5V
SW_UPDATE_CTL1
R83433R
STANDBY
R813
33R
R81233R
SHORT_PROTECT
+3V3SB
KEY
Q817
2N7002/NC
3K3
R819
3
2
1
U811
RT9166
POWER_ON
R823
33R
R814 33R
R824 33R
R820
33R
R825
33R
5V_KEY
+3V3SB_UP
+3V3SB
C872
100U
6V3
C809
100U
6V3
R143
10K
B
C
E
Q4
BT3904
R142
10K
600R
R833
NC
OIRI_MCU
OIRI_MCU
+3V3SB
5V_KEY
R817
NC
R22 0R
NC\1000P
C876
4
2
3
7
5
6
9
11
10
12
14
13
8
116
15
U810
WT6702F
L821
600R
L822
600R
5VSB
L823
600R L811 600R
5V_KEY
L809
120R
C802
1U
CEC_IRQ
CEC
OSDA0
OSCL0
KEY
STANDBY
3V3SB_EN
VSYNC
OSCO
OSCI
CEC_IRQ
HDMI_INT
HSYNC
R815
4K7
OSCL0_SB
R81010K
R830
33R
R822
33R
C824
1U
C825
0.1U
R806
27K
+3V3SB_UP
R807 10K
C871
1U
C875
1000P
C819
100P
X800 32K7
D801
LL4148
L820
600R
OSCI
+3V3SB_UP
+3V3SB_UP
+3V3SB_UP
+3V3SB_UP
DV33
Q810
2N7002
Q809
2N7002
R827
10K
R826
10K
C823
0.1U
R10 0R
C821
20P
C822
20P
R816
33R
C820
0.1U
R809 10K
R805
100R
OSCO
+3V3SB_UP
5VSB
C826
0.1U
OSDA0_SB
4K7
R144
OIRI
5V_KEY
OIRI
KEY_5335
17953_522_090330.eps
090331
MCU STANDBY
B02 B02
49TCM2.0E LA 7.

SSB v2: MCU Standby

Page 50
Circuit Diagrams and PWB Layouts
T
GND
GND
GND
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND
GND
D2B
D2A
G1
G2
S1
D1B
D1A
S2
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
GND/ADJ
OUT
VIN
4
BS
COMP
FB
GND
IN
SS
SW
NC2
NC1
EN
OUTVIN
ADJ/GND
BOOT
DRIVE
FB GND
LGATE
PHASE
VCC
UGATE
D1B
D1A
G2
G1
S2
D2B
D2A
S1
A
3 21
F
E
D
C
B
8 76554 3 21
F
E
D
C
B
A
4678
about 1mm
DIMMING
Back Light circuit
12V/4A
5V/2A
CONNECTOR
BL ON/OFF
POWER CINCH
R856 IS FOR 26"
19"20"22" NC
L800
NC
7
8
4
2
3
5
6
1
U808
NC
1
2
3 6
5
8
4
7
U807
NC
R852
4K7
R855
4K7
1
2
3
4
5
6
7
8
9
10
11
P804
1
2
3
4
5
6
7
P800
R2
510R
R849
10K
R850
4K7
R876
NC
R8013NC
R856
4K7
5VSB
D814
3V9
R10R
B
C
E
Q806
BT3904
R895
10K
B
C
E
Q805
BT3904
R5
10K
R4
10K
5V_OUTSIDE
5V_OUTSIDE
5VSB
R9NC
12V_IN
5V_PW
DV33A
+5V
12V
5VSB
C870
100U
6V3
C815
100U
6V3
C807
100U
6V3
C806
100U
6V3
C817
330U
16V
R8 47K
L816
120R
L13
200R
R882 15K
R801
330R
C839
0.1U
23
1
U809
NC/KD1084-33
R802
120R
AV33
R8001
10K
L802
200R
R889
4K7
D810
LL4148
AV33AV33
AV33
R890
2K7
DV33
R897
680R
R864
6K8
D818
LL4148
C804
4U7
C803 4U7
200R
L805
L804
200R
C801
1000U
16V
C800
1000U
16V
L801
15UH
C862
0.1U
C859
0.1U
C810
100U
16V
C816
100U
16V
L819
200R
R46
10K
R845
NC
R872
1K2
R871
NC
R831
2R7
0.1U C849
10K
R8011
2
8
7
6
4
10
5
3
1
9
U806
MP1411
C869
0.1U
C830
0.1U
C834
0.01U
R869
10R
R868
NC
R8012NC
R846
10K
R857 1K
C835
0.01U
R874 4K7
C813
100U
16V
C818
47U
6V3
C812
47U
6V3
C811
47U
6V3
C874
4U7
C814
47U
16V
AV12AV12
1
2
3
4
LD1117S33
U800
C853
0.1U
C858
1U
C852
1U
1
2
3
4
U801
LD1117S33
1
2
3
4
U803
LD1117S12
+5V
C829
0.1U
R854
0R
R8010
4K7
R865
0R
R8003
0R
3V3SB_EN
+3V3SB
5V_PW
0R
R860
R866
22K
1U
C854
C827
1U
7
8
4
2
3
5
6
1
Q800
A04803
R867
10R
NC
C833
12V
C805
1U
C863
NC
C837
0.1U
12V
R844
1K
R847
NC
R843
4K7
C844
0.1U
R870
220R
R883
51K
R884
1K
R879
1K
R893
4K7
L813
30R
L815
600R
CI_DV18
C865
0.1U
0.1U
C842
DV10
C867
0.1U
C868
0.01U
5VSB
BL_ON/OFF
R803
5R1
R804
6R8
4
123
U802
LD1117S
AV33
+5V
CI_VCC
R862
6K8
R861
3K
D804
LL4148
12V
5V_KEY
+5V
12V_IN
R896
8K2
AV_5V
AV25
1
2
3
4
U804
LD1117S25
AV9VAV9V
0.1U
C845
R885
6K2
C843
0.1U
C841
0.1U
C840
0.1U
D817
LL4148
B
C
E
Q807
BT3904
C846
0.1U
R8006
10K
R898
47K
R894
100K
R892
2K7
R891
4K7
R888
2K7
R887
2K2
R886
3K9
D816
LL4148
D812
LL4148
D811
LL4148
D809
LL4148
12V
C848
0.1U
4
1
2
3
U805
LD1117S50
C851
0.1U
0.1U
C850
C828
0.1U
B
C
E
Q803
BT3904
C860
0.1U
R851
10K
B
C
E
Q802
BT3904
R848
100R
B
C
E
Q801
BT3904
SELECT
12V_IN
R859
4K7
R858
2K7
D805
LL4148
D806
LL4148
DDRV
R863
3K
D807
LL4148
AV25
C832
0.1U
C831
0.1U
D808
LL4148
D803
SK24
C866 120P NC
C864
0.01U
600R
L814
Z805
5VSB
B
C
E
Q816
BT3904
ON/OFF
2R7
R832
BL_DIM
200R
L818
200R
L15
L14
200R
12V
R92
2K2
R91
3K9
AV_5V
+5V
DV33
+3V3SB
ON/OFF
SHORT_PROTECT
R3
1K
R7
10K
R6
10K
+5V
17953_523_090330.eps
090331
DC-DC
B03 B03
50TCM2.0E LA 7.

SSB v2: DC / DC

Page 51
Circuit Diagrams and PWB Layouts

SSB v2: Digital Channel Decoder

8 76 543 21
51TCM2.0E LA 7.
B04 B04
DIGITAL CHANNEL DECODER
DV33 DV33
FAT_IN-
C513
1000P
C568
NC/20P
F
R136
10K
TUNER_SCL0
TUNER_SDA0
DV33
NC/10K
MT5133-GPIO-AD
IF_AGC
CLOSE TO MT5133
C509
0.047U
R505
100R
MT5133_RESET
AV12
AV12
L500
600R
AV33
AV33
Digital 1.8V Bypass Caps
1U
C500
C517
0.1U
0.1U
C519
C516
Digital 3.3V Bypass Caps
L501
600R
1U
0.1U C523
C521
C501
Analog 3.3V Bypass Caps
L502
600R
1U
0.1U C526
C525
C502
ADVDD33_1
L503
600R
0.1U
C524
0.1U
0.1U
0.1U
DVDD12
0.1U
0.1U C515
C518
DVDD33DV33
0.1U
0.1U
C522
C520
AVDD33
1U
C503
0.1U
R134
NC/1K
1K
DVDD33
R503
10K
R150
NC
R504
R501
R502 0R
R506
0R
R151
10K
OSDA0
OSCL0
NC
C527
0.22U
C511
C514
1000P
C510
0.22U
C569
NC/20P
R508
R507
0R
0R
FAT_IN+
NC
L506
E
0.22U
C512
VCMEXT
ADVDD33_1
REFTOP
27P
C506
27M
1
2
3
R500
1M
R536
33R
27P
C507
XTALO
XTALI
AVDD33
DVDD12
8
7
6
DVDD33
X500
D
TS0INDATA7
TS0INDATA6
TS0INDATA5
1 2
3
4 5 6 7
8
9 10 11 12
U502
AVSS33_3 AVSS33_2 XTALI XTALO AVDD33_2 ALC_IN VDD1.2 DGND1.2 TSDATA7 TSDATA6 TSDATA5 VDD3.3
48
AVDD33_3
REFBOT
VCMEXT
REF_TOP
IN-
IN+
REFBOT
AVDD33
AVDD33_1
DVDD12
VDD1.2_3
AVSS33_1
TUNER_SCL
TUNER_SDA
3738394041424344454647
DGND1.2_1
RF_AGC
TUNER_SCL
TUNER_SDA
IF_AGC
VDD3.3_3
/RESET XTAL_SEL1 XTAL_SEL0
DGND3.3_1
VDD3.3_2 VDD1.2_2
HOST_SDA
HOST_SCL
GPIO0
MT5131_IF_AGC
36 35 34 33 32 31 30
29 28 27 26 25
C508
DVDD33
DVDD12
SIF_SDA SIF_SCL
45
TSDATA4
TSDATA3
TSDATA2
TSDATA1
TSDATA0
TSERR
TSVAL
TSSYNC
TSCLK
VDD3.3_1
DGND3.3
VDD1.2_1
R535
33R
C
TS0INDATA4
TS0INDATA3
TS0INDATA2
TS0INDATA1
TS0INDATA0
TS0INVALID
TS0INSYNC
TS0INCLK
1
2
3
45
R54233R
33R R543
R54433R
33R R545
MT5133
8
7
6
1314151617181920212223
L510
120R
24
DVDD33
DVDD12
B
F
E
D
C
B
120P/NC
C504
120P/NC
C505
A
A
12345678
17953_524_090330.eps
090331
Page 52
Circuit Diagrams and PWB Layouts

SSB v2: DVBT/ CI Decoder

8 76554 3 21
52TCM2.0E LA 7.
B05 B05
DVBT-CI-DECODER
CLOSE TO CI CONNECTOR
F
CI_VCC
R517
NC\10K
CI_INPACK#
R516
10K
E
1U
C551
L504
600R
C543
CI_VCC
R519
NC\10K
R518
10K
0.1U
CI_IOIS16#
CI_AV33CI_DV33
0.1U
C542
CI_IREQ#
0.1U
C533
R525
NC
R520
10K
CI_CD1# CI_CD2#
0.1U
C559
0.1U C532
C531
R521
10K
C1
1U
CLOSE TO MT8295
10P
TS_SYNCO
R53833R
126
127
128
GPIO13
GPIO14
GND33_5
VCC33_1
D15
CE1#
33
343638
353739
C530
TS_DATAO
33R R539
CI_TS_SYNCO
CI_TS_DATAO
124
125
TS_SYNCO
CE2#
TS_CKO
R54033R
CI_TS_CKO
123
TS_CKO
TS_DATAO
VS1#
A10
TS_VALIDO
R541
33R
L511 120R
5V-TUNER-ON/OF
5V-TUNER-INPUT
CI_DV33
CI_TS_VALIDO
CI_PDD3
118
119
120
117
121
122
GPIO10
GPIO11
GPIO12
CI_OEB
VCC33_5
TS_VALIDO
GND33_1
OE#
A11A9A8
IORD#
IOWR#
43
4144464850
404245
CI_PDD4
CI_PDD5
115
116
CI_DATA0
A17
D
GND
C
CI_GPIO0 CI_GPIO1
HDMIED_WP
HPDIN
CI_DV33 TS0INCLK TS0INSYNC
TS0INVALID
TS0INDATA0
GND TS0INDATA1 TS0INDATA2 TS0INDATA3 TS0INDATA4
CI_DV18
TS0INDATA5 TS0INDATA6
B
TS0INDATA7
HDMI_SEL
YPBPR_SW_IN
PWRDN_EN
GND
CI_CD1#
CI_D3 CI_OUTDATA3 CI_D4 CI_OUTDATA4 CI_D5 CI_OUTDATA5 CI_D6 CI_OUTDATA6 CI_D7
Z501
Z502
RESET_N
T
CI_GPIO14
T
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30 31 32
GPIO0 GPIO1 GPIO2 GPIO3 VCC33 T0CLK_I_ T0SYNC_I_ T0VALID_I_ T0DATA0_I_ GND33 T0DATA1_I_ T0DATA2_I_ T0DATA3_I_ T0DATA4_I_ VCC18 T0DATA5_I_ T0DATA6_I_ T0DATA7_I_ GPIO4 GPIO5 GPIO6 GND18 CD1# D3 D11 D4 D12 D5 D13 D6 D14 D7
CI_VCCCI_VCCCI_VCC
R522
10K
CI_VS2#
CI_WAIT#
R523
10K
CI_VS1#
CLOSE TO MT8295
0.1U
0.1U
0.1U
CLOSE TO MT8295
C528
CI_POWE#
114
CI_DATA1
47
C538
C539
C529
27P
27P
R509 1M
X501 27M
CI_RESET#
CI_OEB
GND
CI_XTALO
GND
CI_AV18
111
112
113
CI_INT
AVSS18_PLL
AVDD18_PLL
U501
A13
A18
A19
49515460565861
CI_ALE
CI_XTALI
CI_AV33
105
106
107
110
109
108
XTALI
CI_RB
XTALO
CI_CLE
RESETB
AVSS33_XTAL
AVDD33_XTAL
WE#
READY
A14
VCC33_2
A20
A21
A22
52
5355575962
GND
104
C535
CI_CLE
103
GND33_4
A16
0.1U
102
CI_ALE
CI_DATA3
A15
A23
R524
C560
CI_DV33
CI_INT
100
101
CI_DATA4
GND33_3
+5V+5V+5V
10K
0.1U
0.1U
C534
CI_RB
CI_POCE1#
989997
CI_DATA7
CI_DATA6
CI_DATA5
A12
A24
A25
63
NC
CI_DV33
VCC33_4
A7
64
0.1U
C537
R510
4K7
4K7
CI_WEB
CI_DATA2
CI_CEB
GPIO9 GPIO8 GPIO7
GND18_1
CD2#
VCC18_1
BVD1
BVD2
GND33_2
REG#
INPACK#
WAIT#
VCC33_3
RESET
VS2#
0.1U
C536
CI_GPIO1
R548
R513
0R
R5474K7
R546
R5144K7
96 95 94 93 92 91 90 89
WP
88 87
D2
86
D10
85
D1
84
D9
83
D0
82 81
D8
80
A0
79 78
A1
77 76 75
A2
74 73
A3
72 71
A4
70 69
A5
68 67 66
A6
65
L508
600R
CI_DV18CI_DV33
1U
C554
R511
4K7
CI_GPIO0
DV33
R512
10K
MTK_IC_RESET
CLOSE TO MT8295
OPWM1 OPWM2
CI_PDD2 CI_PDD6 CI_PDD7 CI_VCC_EN CI_VPP33_EN CI_VPP5_EN GND CI_IOIS16# CI_CD2# CI_D2 CI_OUTDATA2 CI_D1 CI_OUTDATA1 CI_D0 CI_DV18 CI_OUTDATA0 CI_A0 CI_OUTSYNC CI_A1 CI_OUTVALID GND CI_A2 CI_REG# CI_A3 CI_INPACK# CI_A4 CI_WAIT# CI_A5 CI_DV33 CI_RESET CI_A6 CI_OUTCLK
CI_DV33DV33 CI_DV18
LD1117S18
1
2
3
C556
6V3
47U
U500
3.3V: 0.2W (60mA)
1.8V: 0.2W (100mA)
GND/ADJ
OUT
VIN
4
4
CI_AV18CI_DV18
L505
600R
0.1U
C561
10P
CI_IOIS16#
C552
1U
CI_D3 CI_D4 CI_D5 CI_D6 CI_D7 CI_CE1# CI_A10 CI_OE# CI_A11 CI_A9 CI_A8 CI_A13 CI_A14 CI_WE# CI_IREQ#
CI_INVALID CI_INCLK CI_A12 CI_A7 CI_A6 CI_A5 CI_A4 CI_A3 CI_A2 CI_A1 CI_A0 CI_D0 CI_D1 CI_D2
C544
NC/0R
R531
0.1U C545
C540
CI_DV33
0.1U C541
CI_VCC
CI_VPP
0.1U
CLOSE TO CI CONNECTOR
+5V
L509
C557
6V3
47U
1U
C558
CI_VCC_EN
C546
0.1U
10K
R528
R527
0R
30R
5
4 3
VOUT
VIN EN/EN#
RT9711
GND
FLG
U503
2
1
R549
CI_CE1## CI_CE1#
CI_OE##
CI_WE##
100R
100R
100R
R550
R551
P500
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30 31 32 33 34
35 36 37 38 39
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
CI_CD1# CI_OUTDATA3 CI_OUTDATA4 CI_OUTDATA5 CI_OUTDATA6 CI_OUTDATA7 CI_CE2# CI_VS1# CI_IORD# CI_IOWR# CI_INSYNC CI_INDATA0 CI_INDATA1 CI_INDATA2 CI_INDATA3
CI_INDATA4 CI_INDATA5 CI_INDATA6 CI_INDATA7
CI_VS2#
CI_RESET CI_WAIT#
CI_REG# CI_OUTVALID CI_OUTSYNC CI_OUTDATA0 CI_OUTDATA1 CI_OUTDATA2 CI_CD2#
CI_VCC CI_VPP
NC\0R
R532
CI_INPACK#
CI_IORD##
CI_IOWR##
CI_VS2#
100R
100R
100R
R552
R553
R533
CLOSE TO MT8295
0.1U
L507
30R
C548
10P
C562
10P
C563
10P
C564
10P
C565
10P
C566
10P
C567
CI_VPP
100U
6V3
CI_OE#
CI_WE#
CI_IORD#
CI_IOWR#
CI_OUTCLK
C550
CI_VCC
0.1U
C547
F
E
D
C
B
MT8295
A
CI_CE1##
CI_DV33
CI_OUTDATA7
CI_CE2#
CI_A10
CI_VS1#
CI_OE##
CI_IORD##
CI_IOWR##
CI_A11
GND
CI_A9
CI_INSYNC
CI_INDATA0
CI_A8
CI_A13
CI_INDATA1
CI_A14
CI_WE##
CI_DV33
CI_INDATA2
CI_INDATA3
CI_IREQ#
CI_INVALID
CI_INDATA4
GND
CI_INDATA5
CI_INDATA6
CI_A12
CI_INDATA7
100R
R515
CI_A7
CI_INCLK
4678
3 21
17953_525_090330.eps
A
090331
Page 53

SSB v2: Audio Amplifier

8 76 543 21
Circuit Diagrams and PWB Layouts
53TCM2.0E LA 7.
B06 B06
F
E
D
AUDIO AMPLIFIER
AL1O
SPEAK-OUTL
AR1O
SPEAK-OUTR
NC
0R
R622
R621
R617
NC
R618 0R
R624
R623
100K
100K
1
Y600
PGND
2
R620
2K2
2K2
R619
L-
GND
GND
L_OUT
U600 TDA7266
OUT1-
VCC1
OUT1+ 1
3
2
1U
C612
C608
1U
2R7
R603
L600
L601
200R
C611
0.1U
200R
C610
C609
4700P
4700P
12V
IN1
4
NC1 5
2R7
MUTE 6
MUTE
R648
1
L+
STBY 7
SS
PGND
2
8
3
R+
S_GND
PW_GND
9
GND
16V
P600
4
IN2
12
0.1U
C615
VCC2
13
OUT2-
14
OUT2+
15
R_OUT
GND
GND
R-
R600
0R
Near the P502
R602
0R
R601
0R
Near the P502
PGND
PGND
NC2
10
NC3
11
C607
1000U
F
E
D
12V
R643
C
220R
R639
R641
4K7
4K7
B
A
BT3906
Q607
R640
16V
GND
BT3906
4K7
100U
C602
AMP_MUTE
R642
1K
GND
4K7
R625
LL4148
D600
D601
LL4148
HW_MUTE
R644
10K
BT3904
Q602
B
R630 10K
12V
C
E
GND
R632 10K
R627
R647
10K
10K
GND
R628 10K
22U
C606
16V
SS
NC
R631
MUTE
E
C
B
B
E
Q608
C
PGND
R659
100R
R629
100R
R656
R626
100R
100R
C600
3300P
GND GND
3300P
C601
0R/NC
L602
R6360R/NC
R637
600R
L603
600R
16V
100U
C616
HP_L
HP_R
R+
R_OUT
GND
C
EAR
1
P601
2
C614
C613
4700P/NC
C617
100U16V
4700P/NC
GND
B
3
9
8
7
6
L+
L_OUT
5 4
A
12345678
17953_526_090330.eps
090331
Page 54
Circuit Diagrams and PWB Layouts
GND
GND
GND
GND
GND
GND
AVSS25_SADC
IF_AGCTUNER_DATA
SIFP
RF_AGC
SIFN
TUNER_CLK
AF
AVDD25_SADC
RX0_CB
79
RX0_C
80
RX0_0B
81
RX0_0
82
RX0_1B
83
RX0_1
84
RX0_2B
85
RX0_2
86
EXT_RES
77
OPWR0_5V
73
AVDD33_HDMI
78
AVDD12_CVCC
74
GND
GND
AVDD12_KADCPLL
AVDD12_TVDPLL
AVDD12_KHDMIPLL
AVDD12_KAPLL AVDD12_SYSPLL AVDD12_KDMPLL AVDD12_DTDPLL
TP0 TN0
USB_VRT USB_DM USB_DP AVDD33_USB AVDD12_USB
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
C213
1U
C212
1U
C211
1U C210
1U
C208
1U
C207
1U
AVDD33_H
AVDD25_SADC
AVDD12_USB
AVDD33_USB
AVDD12_PLL
AV12
AV12
160 155 153 161 159 156 154
157 158
68 65 66 67 69
U203
MT5335PKU
R218
5K1
AV12
AV12
L217
600R
C251
0.1U
AVDD25_SADC
USB_VRT
AV33
AV33
U203
MT5335PKU
192195
164
193
166
194
167
165
163
U203
MT5335PKU
TS_SYNCO
TS_DATAO
TS_CKO
USB_D-
TS_VALIDO
SIFN
SIFP
USB_D+
AVDD12_USB
AVDD33_USB
USB_VRT
RX0_2
RX0_2B
RX0_0 RX0_1B
AV25
AV25
AV33
AV33
AV12
AV12
HDMI_5V
HDMI_5V
C252
0.1U
L216
600R
C228
1U
C248
0.1U
C230
1U
C255
0.1U
C250
0.1U
L220
600R
L219
600R
L218
600R
L215
600R
AVDD12_PLL
AVDD12_PLL
AVDD12_PLL AVDD12_PLL
AVDD12_PLL
AVDD12_PLL AVDD12_PLL
AVDD12_CVCC
AVDD33_H
RX0_0B
RX0_C
RX0_CB
RX0_1
C249
0.01U
C229
1U
C253
0.01U
C254
0.1U
AVDD12_CVCC
17953_527_090330.eps
090331
MT5335 VIDEO PROCESSOR
B07 B07
54TCM2.0E LA 7.

SSB v2: MT5335 Video Processor

Page 55
Circuit Diagrams and PWB Layouts

SSB v2: MT5335 Interface USB/HDMI

8 76 543 21
55TCM2.0E LA 7.
B08 B08
MT5335 INTERFACE - USB, HDMI
F
U203
USB_VRT
USB_D­USB_D+ AVDD33_USB AVDD12_USB
E
USB_VRT
5K1
157 158
R218
68 65 66 67 69
USB_VRT USB_DM USB_DP AVDD33_USB AVDD12_USB TP0 TN0
MT5335PKU
AVDD12_KADCPLL
AVDD12_TVDPLL
AVDD12_KHDMIPLL
AVDD12_KAPLL
AVDD12_SYSPLL
AVDD12_KDMPLL
AVDD12_DTDPLL
160 155 153 161 159 156 154
AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL
GND
AV12
U203
RF_AGC
IF_AGCTUNER_DATA
163 165
193 192195
D
SIFP SIFN
TS_VALIDO
TS_CKO
164 166 167
194
SIFP SIFN
AF
TUNER_CLK
AVDD25_SADC AVSS25_SADC
TS_DATAO
TS_SYNCO
AVDD25_SADC
GND
AV25
MT5335PKU
HDMI_5V
C
RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2
U203
79
RX0_CB
80
RX0_C
81
RX0_0B
82
RX0_0
83
RX0_1B
84
RX0_1
85
RX0_2B
86
RX0_2
EXT_RES
OPWR0_5V
AVDD33_HDMI
AVDD12_CVCC
77 73
78 74
AVDD33_H AVDD12_CVCC
HDMI_5V
AV33
AV12
MT5335PKU
B
AV12
AV33
AV12
AV25
AV33
AV12
AV12
AV33
1U
1U
1U
C228
C229
C230
L216
600R
L217
600R
L218
600R
L215
600R
L219
600R
L220
600R
1U
C207
AVDD33_USB
1U
C208
AVDD12_USB
1U
AVDD25_SADC
1U C210
C211
1U
C212
AVDD12_CVCC
1U
C213
AVDD12_PLL
AVDD33_H
C251
0.1U
C252
0.1U
C255
0.1U
C249
0.01U
C253
0.01U
C248
0.1U
C250
0.1U
GND
GND
GND
C254
0.1U
GND
GND
F
E
D
C
B
GND
A
A
12345678
17953_528_090330.eps
090331
Page 56
Circuit Diagrams and PWB Layouts

SSB v2: Interface LVDS TTL

8 76 543 21
56TCM2.0E LA 7.
B09 B09
F
E
Footprint is ACM-2012
A0N
A0P
A1N
A1P
D
C
B
A2N
A2P
CK1N CLK11-
CK1P
A3N
A3P
A4N
A4P
A5N
A5P
A6N
A6P
CK2N
A7N
A7P
INTERFACE LVDS TTL
L200
EXC24C
14
2
L201
EXC24C
14
2
L202
EXC24C
14
2
L203
EXC24C
14
2
L204
EXC24C
14
2
L205
14
2
L206
14
2
L207
14
2
L208
14
2
L209
14
2
3
3
3
3
3
NC
3
NC
3
NC
3
NC
3
NC
3
AN00
AP00
AN11
AP11
AN22
AP22
CLK11+
AN33
AP33
AN44
AP44
AN55
AP55
AN66
AP66
CLK22-
CLK22+CK2P
AN77
AP77
C328
C329
C320
C321
C322
C323
C324
C325
C326
C327
C330
C331
C332
C333
C334
C335
C336
C337
C338
C339
10P
10P
GND
10P
10P
10P
10P
10P
10P
10P
10P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
AV33
AV33
GND
GND
R222
0R
R223
0R
A0N A0P A1N A1P
A2N
A2P
CK1N
CK1P
A3N
A3P
A4N
A4P
A5N
A5P
A6N
A6P
CK2N
CK2P
A7N
A7P
MT5335PKU
AP00
AP11
AP22
CLK11+
AP33
R213NC
NC
R212
PANEL_CTL1
PANEL_CTL2
AP44
AP55
AP66
CLK22+
AP77
GND
U203
244 243 242 241 240 239 237 236 235 234 233 232 231 230 228 227 226 225 224 223 222 221
A0N A0P A2N A2P CK1N CK1P A3N A3P A4N A4P A5N A5P A6N A6P A7N A7P CK2N CK2P A8N A8P A9N A9P
AVDD33_LVDSA AVDD33_LVDSB
AVDD33_LVDSC
P202
39
37
35
33
31
29 30
27
25
23
21
19
17
15
13
11
9
7
5
3
12
VDD_PANEL
AVDD33_VPLL
TP2
TN2
40
38
36
34
32
28
26
24
22
20
18
16
14
12
10
8
6
4
220 229 238
217
218 219
AN00
AN11
AN22
CLK11-
AN33
AN44
AN55
AN66
CLK22-
AN77
0.1U
C260
AVDD33_LVDS AVDD33_LVDS AVDD33_LVDS
AVDD33_VPLL
CI_POCE1#
GND
12V
5V_OUTSIDE
+5V
R25NC
12V
35KEY_5V
R26 FOR 19" 22" PANEL
R25 FOR OTHER +5V SUPPLY PANEL
NC R26
L232
NC/30R
P209
5
3
6
4
16V
12
L233
30R
LVDSVDD_EN
AV33
AV33
AV33
AV33
GND
1U
1U
C231
C220
C202
220U
GND
L221
600R
L222
600R
0.1U
PANEL_SLT
LVDS OUT
C258
C
B
E
GND
1U
C214
C232
R219 10K
100K
Q204
C143ZT
AVDD33_LVDS
AVDD33_VPLL
1U
R221
NC
R232
1U
C209
Z210
T
C256
0.1U
C257
0.1U
DV33
1
S1
2
S2 3
S3
G
Q203
AO4459
C259
0.1U
DV33
GND
GND
R224 1K
R227
390R
8
D1
7
D2
6
D3
54
D4
VDD_PANEL
GND
A
GND
C261
0.1U
T
F
E
Z212
D
C
B
A
12345678
17953_529_090330.eps
090331
Page 57
Circuit Diagrams and PWB Layouts
GND
GND
GND
POCE0_ POOE_ PDD0 PDD1
U0RX
U0TX
JTMS
JTRST_
JTCK JTDO
JTDI
OIRI
PARB_ PDD2
VCCK VCCK1 VCCK2 VCCK3 VCCK4
VCCK5
VCCK6
VCCK7
VCC3IO_3
VCC3IO_3_1
VCC3IO_3_2
DVDD10 DVDD10_1
E-PAD
VCC2IO VCC2IO1 VCC2IO2 VCC2IO3 VCC2IO4 VCC2IO5 VCC2IO6 VCC2IO7 VCC2IO8 VCC2IO9
GND
GND
GND
GND
GND
GND
GND
GND
PO2
VCC
NC
CS#
PO1
PO0
WP#/ACC
PO3
GND
PO4
PO6
PO5
SO
HOLD# SCLK
SI
GND
GND
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
0
0
Trap MODE
NORMAL MODE
ICE MODE
OPWM2 AOBLK AOLRCK
0
00
1
0
TRAP MODE
CORE RESET 1 US
OPCTRL5
OPCTRL4
1
RS-232
DDRV_IC
C006
100U
6V3
R90
10K
R2011
0R
R2012
0R
AV33
R242
NC\4K7
+5V
4K7
R244
B
C
E
Q3
BT3904
21
R87
EZJZ1V270RA
1
2
3
4
P201
U0RX
R233
10K
4
2
3
7
5
6
9
11
10
12
14
13
8
116
15
U202
MX25L3205
1
2
3
45
6
7
8
R270
10K
12
4
6
8
12
14
16
18
20
10
3
5
7
9
11
13
15
17
19
P203
R235
1K
R239
33R
10K
R238
R237
10K
10K
R236
C267
0.1U
AOLRCK
AOBCK
OPWM2
3
2
1
4
P200
PDD0
R245
0R
0.1U
C007
DV33
CI_PDD2
CI_RB
C240
1U
1U
C235
L223
600R
R240
4K7
DDRV_IC
DV10
DV33
DV33
DV33
DV10
DV33
C264
0.1U
4K7
R241
JTRST#
JTAG_DBGACK
JTAG_DBGRQ
TVTREF#1
JTDO
JTCK
JTMS
JTDI
C265
0.1U
1U
C234
0.1U
C263
C262
0.1U
JTCK
JTMS
JTRST#
JTDI
U0RX U0TX
POCE0#
OIRI_MT5335
JTDO
POOE# PDD0 PDD1
1U
C236
1U
C237
C270
0.1U C269
0.1U C268
0.1U C272
0.1U C271
0.1U
C279
0.1U
1U
C239
1U
C238
C278
0.1U C277
0.1U C275
0.1U C274
0.1U C273
0.1U
POOE#
PDD1
14 48 57 58 61
206
213
246
247
197
64
70
162
257
10 12 16 18 27 30 52 54 55 56
U203
MT5335PKU
252 251 250 249
95 94
253 1 256 255 254
93
245 248
U203
MT5335PKU
R246
4K7
FRESET#
DV33
R289
10K
POCE0#
10K
R234
0.1U
C276
C266
0.1U
U0TX
12
EZJZ1V270RA
R88
4K7
R89
+5V
USB_D-
USB_D+
OIRI
OIRI_MT5335
17953_530_090330.eps
090331
FLASH MEMORY
B10 B10
57TCM2.0E LA 7.

SSB v2: Flash Memory

Page 58
Circuit Diagrams and PWB Layouts
RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15
RVREF0 RCS_
RA0 RA7
RWE_
RBA0
RA6
RBA1
RA5
RRAS_
RA8
RA10
RA4
RCAS_
RA12
RCKE
RA11
RA9 RA3 RA1 RA2
RCLK0_
RCLK0
GND
GND
GND
GND
GND
GND
GND
GND
GND/ADJ
OUT
VIN
4
GND
GND
A0 A1
A10/AP
A11 A12
A2 A3 A4 A5 A6 A7 A8 A9
BA0 BA1
CKE
CLK
DQ0 DQ1
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
LDM
LDQS
NC NC1 NC2 NC3
NC4 NC5 NC6
UDM
UDQS
VDD VDD1 VDD2 VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4
VREF
VSS
VSS1
VSS2
VSSQ
VSSQ1 VSSQ2
VSSQ3 VSSQ4
CLK
CAS
RAS
WE
CS
GND
REFENVCNTL
NC1
NC3
VOUT
NC2
VIN
A
3 21
F
E
D
C
B
8 76554 3 21
F
E
D
C
B
A
4678
1.25 x (1+120/110) = 2.6V
C349 IS CLOSE TO PIN33 OF DDR
+1V3D
R29
2R2
R27
2R2
+5V
R282R2
C280
0.1U
C349
220U
16V
L213
600R
DDRV
C315
100U
6V3
C200
100U
6V3
C216
1U
C316
1U
2
36
5
8
4
7
1
U200
RT9199
1
2
3
45
6
7
8
R272
47R
1
2
3
45
6
7
8
R286
75R
C217
47U
6V3
C215
4U7
16V
220U
C314
C304
0.1U
MEM_DQ12
MEM_DQ13
1
2
3
45
6
7
8
R282
75R
MEM_CAS#
MEM_RAS#
MEM_WE#
MEM_CS#
MEM_ADDR10
MEM_BA0
1
2
3
45
6
7
8
R281
75R
MEM_ADDR0
29 30
28 41 42
31 32 35 36 37 38 39
40
26 27
44
45
2 4
57 59 60 62 63 65
5 7
8
10 11 13 54 56
20
16
14 17 19 25
43 50 53
47
51
1
18
33
3
9 15 55 61
49
34
66
48
52
6 12
58 64
46
22
23
21
24
U204
32M*16DDR
MEM_DQ14
1
2
3
45
6
7
8
R271
47R
1
2
3
45
6
7
8
R274
47R
1
2
3
45
6
7
8
R287
75R
1
2
3
45
6
7
8
R285
75R
1
2
3
45
6
7
8
R288
75R
R256
75R
1
2
3
45
6
7
8
R283
75R
1
2
3
45
6
7
8
R280
75R
1
2
3
45
6
7
8
R284
75R
1
2
3
45
6
7
8
R279
47R
1
2
3
45
6
7
8
R278
47R
1
2
3
45
6
7
8
R277
47R
1
2
3
45
6
7
8
R276
47R
1
2
3
45
6
7
8
R275
47R
47R
R251
L226
600R
+1V3D
600R
L225
L224
600R
DDRV_IC
DDRV
MEM_VREF
+1V3D
DDRV
+1V3D
MEM_VREF
R250
47R
47R
R249
R248
47R
R269
1K
0R
R265
C306
0.1U
0.1U
C303
0.1U
C302
0.1U
C286
R263
120R
R262
110R
1
2
3
4
U201
LD1117S
R261
100R
MEM_DQ15
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
RDQ12
RDQ13
RDQ14
RDQ15
RDQS1
RDQM1
RDQM0
RDQS0
RDQ7
RDQ6
RDQ5
RDQ4
RDQ3
RDQ2
RDQ1
RDQ0
MEM_DQS1
MEM_DQM1
MEM_DQM0
MEM_DQS0
MEM_DQ7
MEM_DQ6
MEM_DQ5
MEM_DQ4
MEM_DQ3
MEM_DQ2
MEM_DQ1
MEM_DQ0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
R252
75R
MEM_ADDR8
MEM_ADDR9
MEM_ADDR11
MEM_ADDR12
MEM_CLKEN
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
MEM_BA1
RA9
RA10
RBA1
RBA0
RCS#
RA3
RA2
RA1
RA0
MEM_ADDR3
MEM_ADDR2
MEM_ADDR1
MEM_ADDR0
MEM_ADDR10
MEM_BA1
MEM_BA0
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#
RRAS#
RCAS#
RWE#
RA4
RA5
RA6
RA7
MEM_ADDR4
MEM_ADDR5
MEM_ADDR6
MEM_ADDR7
RA8
RA11
RA12
MEM_ADDR8
MEM_ADDR9
MEM_ADDR11
MEM_ADDR12
RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15
MEM_VREF RCS#
RA0 RA7
RWE#
RBA0
RA6
RBA1
RA5
RRAS#
RA8
RA10
RA4
RCAS#
RA12
RCKE
RA11
RA9 RA3 RA1 RA2
RCLK0#
RCLK0
0.1U
C281
C283
0.1U
0.1U
C282
C287
0.1U
C285
0.1U
0.1U
C284
C295
0.1U
0.1U
C294
C293
0.1U
0.1U
C292
C291
0.1U
0.1U
C290
C289
0.1U
0.1U
C288
C299
0.1U
0.1U
C298
C297
0.1U
0.1U
C296
C301
0.1U
0.1U
C300
R253
75R
MEM_ADDR13
R254
75R
75R
R255
75R
R257
R258
22R
R259
22R
R260
22R
R268
100K
C305
0.1U
100K
R267
0R
R266
0R
R264
MEM_CS#
MEM_WE#
MEM_RAS# MEM_CAS#
MEM_CLK0#
MEM_VREF
MEM_DQS1
MEM_DQM1
MEM_ADDR13
MEM_DQS0
MEM_DQM0
MEM_DQ9
MEM_DQ8
MEM_DQ7
MEM_DQ6
MEM_DQ5
MEM_DQ4
MEM_DQ3
MEM_DQ2
MEM_DQ15
MEM_DQ14
MEM_DQ13
MEM_DQ12
MEM_DQ11
MEM_DQ10
MEM_DQ1
MEM_DQ0
MEM_CLK0
MEM_CLKEN
MEM_BA1
MEM_BA0
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_ADDR3
MEM_ADDR2
MEM_ADDR12
MEM_ADDR11
MEM_ADDR10
MEM_ADDR1
MEM_ADDR0
RCKE
MEM_CLKEN
RCLK0
RCLK0#
MEM_CLK0
MEM_CLK0#
+1V3D
DDRV_IC
+5V
11 13
9
8
7 6 5 4
3
2 17 15 19 20 21 22 23 24 25 26
53 46
47 36 40 43 37 44
38
42 35 45 39 41
32 31 33 34
51 49 50
28 29
U203
MT5335PKU
RDQ8
RDQ9
RDQ10
RDQ11
54
72
1
3 6
8
47R
R273
17953_531_090330.eps
090331
SDRAM
B11 B11
58TCM2.0E LA 7.

SSB v2: SDRAM

Page 59
Circuit Diagrams and PWB Layouts
AIN0_L AIN0_R AIN1_L AIN1_R AIN2_L AIN2_R AIN3_L AIN3_R AVDD33_AADC AVSS33_AADC VMID_AADC REFP_AADC REFN_AADC
ASPDIF AOMCLK AOLRCK
AOBCK
AOSDATA0
AL1 AR1 AL2
AR2 AVDD33_KADAC0 AVDD33_KADAC1
AVSS33_KADAC0 AVSS33_KADAC1
ADAC_VCM
AVDD33_DIG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
A
L234
600R
L231
600R
C312
0.1U
C219
4U7
C218
4U7
AOMCLK
AR2O
AL1O
AR1O
SCT_R
VGA_L
GND
AV33
AV33
AV33
C313
0.1U
C311
0.1U
1U
C245
0.1U
C310
VIMD_AADC
C308
0.1U
1U
C242
1U
C241
C307
0.1U
L228
600R
L227
600R
AVDD33_AADC
GND
GND GND
AVDD33_ADAC0 AVDD33_ADAC1
ADAC_VCM
REFP_AADC
AVDD33_DIG
VIMD_AADC
A0SDATA0
AOLRCK
ADAC_VCM
C309
0.1U
1U
C243
L229
600R
AVDD33_DIG
GND
600R
L230
C244
1U
AVDD33_ADAC1
GND
1U
C246
AV33
AV33
VGA_R YPBPR_L YPBPR_R AIN2_L AIN2_R SCT_L
AL2O
ASPDIF
177 176 175 174 173 172 171 170 169 181 179 180 178
201 198 199 200 196 186 185 189 187 190 182 188 184 183 168
U203
MT5335PKU
AOBCK
AV33
AV33
AV33
AV33
AVDD33_ADAC0
GND
REFP_AADC
AVDD33_AADC
GND
GND
AV33
17953_532_090330.eps
090331
MT5335 INTERFACE - VGA
B12 B12

SSB v2: MT5335 Interface VGA

59TCM2.0E LA 7.
Page 60
Circuit Diagrams and PWB Layouts
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
LRCLK
DIN
BCLK
ENABLE
VMID
ROUT
AGND
DGND
DVDD
DEEMPH
FORMAT
MCLK
LOUT
AVDD
2IN+
2IN-
2OUT
VCC+
1IN+
1IN-
1OUT
VCC-
GND
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
DAC
R9018
470
R9017
470
AV9V_REF
AV9V_REF
C962
220U
16V
L16
600R
C903
47U
6V3
C912
1U
5
6
7
8
3
2
1
4
U1
RC4558
C9009
1U
C9015
1U
L931
30R
L930
30R
SPEAK-OUTR
R9021
10K
C9016
1U
C9014
0.1U
L900
600R
L901
600R
1
2
3
4
5
6
7
10
11
12
13
14
9
8
U907
WM8501
R9030
33R
R902833R
R902733R
R9019 47K
C9017
1U
C9010
0.1U
C9008
1U
R9022
10K/NC
DV33
AOMCLK
DV33
DV33
DV33
+5V
C913
1000P1000P
C914
SCT1_AUL_OUT
SCT1_AUR_OUT
R9026
NC/33K
R9020 10K
C9018
0.1U
ADCVA
R9024
10K
DACVL
DACVL
10K R9023
C9012
0.1U
C9013
0.1U
R9029
33R
NC/33K
R9025
AOLRCK
A0SDATA0
AOBCK
ADCVA
DACVL
C9011
1U
ADCVA
C902
47U
6V3
C901
1U
1U
C900
AV9V
OPAVREF
C910
1U
10K
R914
R904
10K
NC
C929
C925
2200P
C928
100P
C927
100P
C926
2200P
R908
10R
R900
100K
R907
5K1
R906
33K
R901
470R
100K
R902
470R
R903
R905
10K
33K
R909
5K1
R910
10R
R913
NC
C930
R915
10K
1U
C911
AR1O
AL1O
OPAVREF
OPAVREF
OPAVREF
SPEAK-OUTL
17953_533_090330.eps
090331
DIGITAL-ANALOG-CONVERTER
B13 B13
60TCM2.0E LA 7.

SSB v2: D/A Converter

Page 61

SSB v2: HDMI Switch

8 76554 3 21
Circuit Diagrams and PWB Layouts
61TCM2.0E LA 7.
B14 B14
F
E
D
C
B
HDMI SWITCH
P901
GND1
GND3
NC1
DDCDA
RX0-
NC1
HPD
RX1+
RX1-
RXC+
RXC-
NC2
VCC
P903
GND1
RX1+
RX1-
GND3
RXC+
RXC-
NC2
DDCDA
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
CEC-IN
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RX2+
RX2-
GND2
RX0+
RX0-
GND4
DDCCLK
GND5
HPD
RX2+
RX2-
GND2
RX0+
GND4
DDCCLK
GND5
R42 NC\0R
GND
+5V_HDMI0
R928
7K5
GND
HDMI1_SCL
HDMI1_SDA
+5V_HDMI1
R929
CEC
CEC-IN
1
R72
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20
DV33
DV33-HDMI
L9
600R
AV18-HDMI
R31
750R
EZJZ1V270RA
2
GND
C38
0.1U
R13 4K7
0.1U
C43
R15 4K7
GND
R16 NC\4K7
R11
4K7
R18 R19
100R 100R
R17
100R
R20
100R
GND
R12
NC\4K7
R14 4K7
0.1U
1U
C42
C39
GND
RX0_2
RX0_2B
RX0_1 RX0_1B
RX0_0
RX0_0B
RX0_C
RX0_CB
DV33
R32
NC\4K7
R33
R34
R35
100R
NC\100R
NC\100R
DV33
RESET_N
OSDA0
OSCL0
T
Z904
D108
GND
134
2
D3V3L4
5
DV18-HDMI
R21
4K7
GND
R59
4K7
60
AGND7
59
RXC2+
58
RXC2-
57
AVCC18D
56
HPD2
55
AVCC33C
54
CEC-A
NC\0RR41
53 52 51 50 49 48 47 46 45 44 43 42 41
CEC-D RPWR1 DSCL1 DSDA1 AVDD18B R1X2+ R1X2­AGND6 R1X1+ R1X1­AVCC33B R1X0+ R1X0-
7K5
6261656468
63
AVCC33D
R2X0+
R2X0-
R2X1-
AGND5
R1XC+
R1XC-
40
37
39
38
AVCC18C
R2X1+
HPD1
36
66
AGND8
35
67
R2X2-
I2CSEL/INT
34
R2X2+
DVCC18A
DGND1
33
70
69
AVDD18C
DSDA2
U904
SII9185
RPWR0
31
32
71
72
RPWR2
DSCL2
DSCL0
DSDA0
30
29
79
80
767473
75
78
77
TSCL
TSDA
AGND9
HPDIN
DGND2
DVCC18B
RSVDL
TPWR/I2CADDR
TX2+
TX2-
AGND1
TX1+
TX1-
AVCC18A
TX0+
TX0-
AGND2
TXC+
TXC-
EXTSWING
RESET#
LSDA LSCL
HPD0
AVCC18B
R0XC-
R0XC+
AGND3
AGND4
AVCC33A
AVDD18A
R0X2+
27
R0X2-
26
R0X1+
R0X1-
23
2221252428
R0X0+
R0X0-
DV33
GND
R30
NC\4K7
4K7 R51
GND
R52
BT3904
4K7
4K7
C
Q2
B
E
R55
R54 4K7
0.1U
GND
100R
R53
HDMI_SEL
T
Z907
CEC
CI_DV18 AV18-HDMI
HPDIN
OSDA1 OSCL1
HDMI_5V
U906
1
A0
C41
0.1U
2
A1
3
A2
4
GND
AT24C02
GND
U905
1
A0
C40
2
A1
3
A2
4
GND
AT24C02
GND
L11
600R
DV33-HDMI
D5V0S1
D104
+5V_HDMI1
VCC
WP
SCL
SDA
+5V_HDMI0
8
VCC
7
WP
6
SCL
5
SDA
C11
0.1U
D105
D5V0S1
CI_DV18
0.1U
C12
D106
L10
C13
D5V0S1
600R
0.1U
D107
DV18-HDMI
0.1U
0.1U
C20
C21
0.1U
0.1U
C14
C15
C16
10P
C134
C133
D5V0S1
1U
0.1U
C23
C22
0.1U
0.1U
C17
10P
10P
C136
C135
GND
T
Z903
R57 4K7
8
7
Z983
6
5
T
Z908
R56 4K7
T
Z982
R48
R47
47K
47K
T
HDMI1_SCL
HDMI1_SDA
T
Z901
R50
R49
47K
47K
HDMI0_SCL
HDMI0_SDA
T
T
Z906
R45
0R
HDMI0_SCL
HDMI0_SDA
R58
4K7
C19
T
Z905
10P
Z902
F
1U
E
D
C
B
D3V3L4
A
D109
A
1
3
4
5
2
GND
4678
3 21
17953_534_090330.eps
090331
Page 62
Circuit Diagrams and PWB Layouts
GND
GND
GND
GND
GND
T
T
T
T
T
GND
GND
T
T
T
T
T
T
GND GND
AOR
AIR
AOL
AGND
BGND
AIL
B
SWITCH
GGND
CLKOUT
G
DATA
RGND
DATAGND
R
BLNK
VGND
BLNKGND
VOUT
VIN
SHIELD
GND
GND
GND
A
12345678
F
E
D
C
B
A
8 76 543 21
F
E
D
C
B
NEARLY MT5335
Nearly Connector
Nearly 5335
21
R62
EZJZ1V270RA
21
R60
EZJZ1V270RA
21
R67
EZJZ1V270RA
21
R68
EZJZ1V270RA
21
R66
EZJZ1V270RA
21
R65
EZJZ1V270RA
21
R64
EZJZ1V270RA
1U
C965
1
2
3
12
13
14
15
4
5
6
7
16
17
18
19
8
9
20
21
10
11
P1
PB0P
Y0N
STC1_FB_IN
SCT1_R_IN
SCT1_G_IN
SCT1_FS_IN
Z927
Z922
Z924
SCT1_AUL_OUT
SCT1_AUR_IN
Z925
Z921
SCT1_AUR_OUT
Z926
SCT1_AUR_IN
SCT1_AUL_IN
SCART_FS_IN
R962 10K
R963
0R
SCT1_AUL_OUT
SCT1_AUR_OUT
L1
30R
SCT1_AV_IN
Z918
Z919
Z920
Z928
SOY0
SC0
GND_SV
SY0
Y0P
PBR0N
PR0P
SCT_R
SCT_L
R977
68R
C968
0.047U
R972
100R
75R
R968
C969
1U
C979
470P
L908
30R
L907
30R
C963
470P
C977
0.01U
L906
30R
C976
16P
75R
R976
R978
100R
R974
100R
C974
0.01U
R973
68R
L905
30R
C973
16P
75R
R975
C972
0.01U
C971
0.01U
75R
R971
C970
16P
L904
30R
R969
68R
R970
100R
L903
30R
C967
47P
R967 10K
R966 10K
C964
470P
R965
10K
R964
10K
L2
30R
R961
33K
R960 75R
C975
0.01U
C978
0.047U
C980
470P
Z923
SCT1_B_IN
SCT1_AUL_IN
SCT1_AV_OUT
C966
1U
1 2
EZJZ1V270RA
R63
SCT1_AV_IN
STC1_FB_IN
SCT1_FS_IN
21
R61
EZJZ1V270RA
SCT1_G_IN
SCT1_B_IN
SCT1_R_IN
17953_535_090330.eps
090331
I/O - SCART
B15 B15
62TCM2.0E LA 7.

SSB v2: I/O Scart

Page 63
Circuit Diagrams and PWB Layouts

SSB v2: I/O Side AV, S-Video, Audio

8 76 543 21
63TCM2.0E LA 7.
B16 B16
I/O - SIDE AV, SVIDEO, AUDIO
AV_5V
CVBS0
10R
C
E
470R
Q815
L925
BC847C
75R
R9004
SCT1_AV_OUT
C002
47P
GND
R924
0R
R923
0R
Q906
BC847C
C
B
E
GND
R9003
47U
10K
C001
C004
F
CVBS_OUT
D2SA
0R
NC
R918
R919
0.01U
R920
1K
1U
C003
GND
B
6V3
R9002 10K
E
9
R9001
Nearly Connector
Z975
7
T
P902
D
5
T
6
8
Z974
R70
EZJZ1V270RA
21
L915
30R
R947 75R
C958
47P
Close to MT5382p
100R
R921
4K7
Nearly 5335
R946
100R
R945
4K7
R944
C959
0.047U
C953
0.047U
CI_GPIO14
SY1
T
Z917
CVBS1
SY0 SC0 SY1 SC1
D2SA
CVBS2
132 130 129 128 127 126 125
136
U203
CVBS0 CVBS1 CVBS2
SY0 SC0 SY1 SC1
D2SA
MT5335PKU
DVDD25_VADC DVSS25_VADC
GND_TUNER
GD_CVBS
AVDD25_VADC
AVSS25_VADC
AVDD25_REF
AVSS25_REF AVDD25_VFE AVSS25_VFE
AV25
AV25
AV25
AV25
GND_SV
L911
L912
139 140 133 131 124
141 142 137 138 135 134
600R
600R
DVDD25_VADC GND
GND_CVBS GND_SV
AVDD25_VADC GND AVDD25_REF GND AVDD25_VFE GND
C916
1U
C920
DVDD25_VADC
AVDD25_VADC
C917
GND
L916
R9012 10K
30R
R9011 10K
GND
R949 75R
C9001
C9002
C960
47P
1U
1U
AIN2_L
AIN2_R
GND
R69
EZJZ1V270RA
10K
10K
21
R9010
R9009
C
Z981
Z980
T
T
P902
WHITE
RED
YELLOW
4
3
2
1
B
L926
L927
30R
30R
C9004
470P
C9003
470P
R948
100R
C961
0.047U SC1
AV25
AV25
AV25
AV25
L913
L914
600R
600R
1U
AVDD25_REF
C918
1U
AVDD25_VFE
C919
1U
1U
C954
0.1U
GND
C955
0.1U
GND
C956
0.1U
GND
C957
0.1U
GND
GND_TUNER
F
E
D
C
B
GND
T Z976
A
T
Z978
R71
L928
30R
21
EZJZ1V270RA
GND
GND
R9014 75R
C9007
47P
R9013
100R
C915
1U
C9006
0.047U
GND_CVBS
CVBS2
A
12345678
17953_536_090330.eps
090331
Page 64
Circuit Diagrams and PWB Layouts

SSB v2: MT5335 Interface YPbPr & VGA

8 76 543 21
64TCM2.0E LA 7.
B17 B17
MT5335 INTERFACE - YPbPr, VGA
Nearly 5335
Nearly Connector
WHITE
F
GREEN
RED
BLUE
RED
1
2
3
4
5
6
YPBPR_L_IN
Y_IN
YPBPR_R_IN
PB_IN
Y_IN
L4
30R
R982 75R
C731
16P
PR_IN
7
GND
0R
68R
100R
R984
R981
R983
VGA_R_IN
P907
10
VGA_L_IN
9
PB_IN
L5
30R
68R
R986
8
R985 75R
16P
C727
100R
R987
E
R74
EZJZ1V270RA
21
21
GND
R75
21
R76
D
EZJZ1V270RA
R77
21
EZJZ1V270RA
EZJZ1V270RA
PR_IN
GND
L6
30R
R988 75R
C724
68R
R989
16P
C728
4700P
C730
0.01U
C729
0.01U
C726
0.01U
C725
0.01U
C723
0.01U
SOY1
Y1P
Y1N
PB1P
PBR1N
PR1P
U203
SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1
Y1P Y1N
PB1P
PBR1N
PR1P
Z939
T
Z940
T
107 108 109 114 115 116 118 119 120 121 122 123
112 111
SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1 Y1P Y1N PB1P PBR1N PR1P
TN1 TP1
DVDD12_VGA
AVSS12_RGBADC
AVDD12_RGBADC
AVSS12_RGBFE
AVDD12_RGBFE
GN
VSYNC
HSYNC
SOG
RP RN BP BN GP
117 113 110 105 101
104 106 98 99 102 103 96 97 100
DVDD12_VGA GND AVDD12_RGBADC GND AVDD12_RGBFE
RP
RN
BP
BN GP GN
VSYNC
HSYNC
SOG
MT5335PKU
AV12
AV12
L909
600R
C987
1U
DVDD12_VGA
C988
0.1U
AV12
AV12
L910
600R
AVDD12_RGBADC
GND
F
E
D
GND
GND
C990
0.1U
C
C992
0.1U
B
C989
1U
Z929
GND
T
C
SPDIF_OUT
21
R73
BLACK
P904
2
1
B
YPBPR_L_IN
YPBPR_R_IN
L8
30R
L7
30R
C719
470P
C732
0.1U
EZJZ1V270RA
10K
10K
C722
470P
C993
R990
R991
33P
R980 100R
R992 10K
GND
R979
R993 10K
100R
C721
C720
1U
1U
ASPDIF
YPBPR_L
YPBPR_R
AV12
AV12
L3
600R
AVDD12_RGBFE
C991
1U
A
A
GND
12345678
17953_537_090330.eps
090331
Page 65

SSB v2: I/O VGA

8 76 543 21
Circuit Diagrams and PWB Layouts
65TCM2.0E LA 7.
B18 B18
F
E
D
C
I/O - VGA
P908
16
5
15
10
4
14
9
3
13
8
2
12
7
1
11
6
17
VGA_R_IN
VGA_L_IN
VGASCL_IN
VSYNC_IN
HSYNC_IN
VGASDA_IN
RED
GND
W/P_CTR
BLUE
GREEN
Z949
T
Z950
T
L924
L923
30R
30R
Z945
T
Z941
T
Z942
T
EZJZ1V270RA
R84
GND
C999
470P
T
21
Z943
T
Z944
T
R85
Z946
Z948
T
Z947
T
Z955
T
GND
21
21
R86
EZJZ1V270RA
R704
10K
R705
10K
C703
470P
R716
0R
VGA_PLUGPWR
3
12
D913 BAV70
C005
ESD_0402
EZJZ1V270RA
R706 10K
C702
C701
R707 10K
WP
8
7
6
5
5VSB
B
VGA_PLUGPWR
W/P
VGASCL
VGASDA
5VSB
R714 10K
C
Q905
C143ZT
E
GND
R715 10K
VGASDA_IN
T
R713 100R
Z973
T
Z972
Z971
T
5VSB
Nearly 5335
C996
Q903
C
B
VGA_PLUGPWR
U903
1
A0
2
A1
3
A2
4
GND
AT24C02
VGASCL_IN
R712
100R
R725 10K
VCC
SCL
SDA
C712
R998
Nearly Connector
L918
GREEN
W/P
+5V
BLUE
RED
1U
VGA_R
1U
VGA_L
L919
L920
30R
30R
30R
GND
GND
GND
R996 75R
R999 75R
R702 75R
C715
16P
C711
16P
C708
16P
0R
33R
100R
33R
100R
33R
100R
R719
R997
R720
R701
R721
R703
5VSB
4700P
C714
0.01U
C713
0.01U
C710
0.01U
C709
0.01U
C707
0.01U
C706
0.01U
5VSB
R708 10K
SOG
GP
GN
BN
RP
RN
BP
U0TX
GND
E
0.1U
C143ZT
SW_UPDATE_CTL1
T
C
Z970
Q904
B
5VSB
F
E
U0RX
C143ZT
E
D
C
R710 10K
B
GND
R80
HSYNC_IN
21
L921
30R
R82
EZJZ1V270RA
1 2
L922
30R
R83
EZJZ1V270RA
HSYNC
22K
R718
C705
10P
VSYNC_IN
R717
22K
VSYNC
EZJZ1V270RA
C704
10P
VGASCL_IN
21
GND
R709
100R
VGASCL
16P
C998
EZJZ1V270RA
VGASDA_IN
R81
21
GND
R711
100R
VGASDA
B
C997
16P
A
A
GND
GND
12345678
17953_538_090330.eps
090331
Page 66

SSB v2: LVDS Receiver

8 76 543 21
Circuit Diagrams and PWB Layouts
66TCM2.0E LA 7.
B19 B19
LVD S RECEIVER
DV33A
R293
T_R7
F
DV33A
L929
600R
C2001
DV33A_LVDS_RECEIVER
C2202
C2004
C2006
C2007
C2015
T_R6
T_R5
T_R4
T_R3
T_R2
T_R1
T_R0
0.1U
0.1U
GND
0.1U
0.1U
E
0.01 T_G7
T_G6
T_G5
T_G4
DV33A_LVDS_RECEIVER
U207
T_B5
T_HSYNC
T_VSYNC
D
C
T_DE
T_R6
AN00 AP00 AN11 AP11
AN22 AP22
CLK11­CLK11+
AN33 AP33
PWRDN
T_CLK
T_R0
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
RXOUT22 RXOUT23 RXOUT24 GND1 RXOUT25 RXOUT26 RXOUT27 LVDSGND1 RXIN0­RXIN0+ RXIN1­RXIN1+ LVDSVCC1 LVDSGND2 RXIN2­RXIN2+ RXCLKIN­RXCLKIN+ RXIN3­RXIN3+ LVDSGND3 PLLGND1 PLLVCC1 PLLGND2 PWRDWN RXCLKOUT RXOUT0
RXOUT21 RXOUT20 RXOUT19
RXOUT18 RXOUT17 RXOUT16
RXOUT15 RXOUT14 RXOUT13
RXOUT12 RXOUT11 RXOUT10
VCC4
GND5
VCC3
GND4
VCC2 RXOUT9 RXOUT8 RXOUT7
GND3 RXOUT6 RXOUT5 RXOUT4 RXOUT3
VCC1 RXOUT2 RXOUT1GND2
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30
29
T_B4 T_B3
T_B2
T_B1 T_B7 T_B6
T_B0 T_G5 T_G4
T_G3 T_G7 T_G6
T_G2 T_G1
T_G0
T_R5 T_R7 T_R4 T_R3
T_R2
T_R1
T_G3
T_G2
T_G1
T_G0
T_B7
T_B6
T_B5
T_B4
T_B3
T_B2
T_B1
T_B0
V386
T_DE
GND
T_VSYNC
T_HSYNC
DV33A
B
T_CLK
L239
120R
100R
1
2
3
45
R294
100R
1
2
3
45
R295
100R
1
2
3
45
R296
100R
1
2
3
45
R298
100R
1
2
3
45
R299
100R
1
2
3
45
R290
100R
1
2
3
45
R292
33R
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
D_VSYNC
D_HSYNC
CLK
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
C010
C011
C01210P
C01310P
C015
C01610P
C017
C01810P
C019
C020
C021
C02210P
C02
C4
C024
C025
C026
C02710P
C028
C02910P
C030
C031
C032
C014
VDD_PANEL
P205
40
39
0.1U
3738
R1
R3
R5
R7
30
R0
3536
R2
3334
R4
3132
R6
29
2728
G1
G3
G5
G7
3
20
G0
2526
G2
2324
G4
2122
G6
19
1718
B1
B3
B5
B7
10
B0
1516
B2
1314
B4
1112
B6
9
78
D_HSYNC
DE
4
2
56
3
1
D_VSYNC
PANEL_CTL2
CLK
GND
GND
F
GND
C2010
E
D
C
B
DV33A
R291
R23
AN00
AN11
AN22
A
CLK11-
AN33
100R
R24
100R
R2003
100R
R2004
100R
100R
R2005
AP00
AP11
AP22
CLK11+
AP33
PWRDN_EN
10K
PWRDN
C
Q5
B
C143ZT
E
GND
C2011
16P
GND
A
12345678
17953_539_090330.eps
090331
Page 67
Circuit Diagrams and PWB Layouts
17953_600_090330.eps
090330

Layout Small Signal Board v2 (Top Side)

67TCM2.0E LA 7.
Page 68
Circuit Diagrams and PWB Layouts
17953_601_090330.eps
090330

Layout Small Signal Board v2 (Bottom Side)

68TCM2.0E LA 7.
Page 69
vol-
vol+
menu
ch-
ch+
POWER
GND
5VIN
5VSB
KEY
1
2
3
4
P601
0
R701
R601 390R
R606
7K5
1 24
3
K601
1 24
3
K602
1 24
3
K603
1 24
3
K604
1 24
3
K605
1 24
3
K606
C601
0.1U
R603
1K5
R605
4K3
R604
2K7
R602
1K
I_17930_031.eps
250408
E E
KEYBOARD CONTROL
I_17930_032.eps
220408
Personal Notes:
E_06532_012.eps
131004

Keyboard Control Panel

Circuit Diagrams and PWB Layouts
69TCM2.0E LA 7.

Layout Keyboard Control Panel (Top Side)

Page 70

Inverter Panel

123 456 87
A
B
C
D
8
7
6
54
3
2
1
D
C
B
A
4
7
1
6
T1
1 2
CN2
4
7
1
6
T2
4
7
1
6
T3
D21
BAV99
R54
820
FB
D18
BAV99
R51
820
FB
D17
BAV99
R50
820
FB
C28
10pF
C29 10pF
C30 10pF
1 2
3
4 5 6
CN1
O/S
F1
5A
C1
220uF/25V
R17 100(1206)
R4
5.6K
C4
104
C14 105
A K
ZD1
8.2V
R19 100K
C15
103
C5
105
C9 331
C10
NC
C7
681
C6
105
C11
103
C8
NC
C12
104
R12 100
R1 300K
R7 20K
R8 33kR916k
R11 3K
R13 NC
R21
22
R18
100K
R22
22
R34 22K
R42 10
R43 10
C16
223
C22 105
S1
1
G1
2
S2
3
G2
4
D2
5
D2
6
D1
7
D1
8
U2
R23
0
R25 1K
FB
C3
220uF/25V
R5
47K
10
11
12
13
14
15
1
2
3
4
5
6
7
8 9
16
U1
R20
100K
R2 0
R6
270K
R36
22K
R44 10
R45
10
C17
223
C23 105
S1
1
G1
2
S2
3
G24D2
5
D2
6
D1
7
D1
8
U3
C25
225(1206)
4 7
1
6
T4
4 7
1
6
T5
4 7
1
6
T6
D22
BAV99
R55
820
FB
D20
BAV99
R53 820
FB
D19
BAV99
R52
820
FB
C31 10pF
C32
10pF
C33 10pF
C24
225(1206)
R38
22K
R46
10
R47 10
C18
223
C26 105
S1
1
G1
2
S2
3
G24D2
5
D2
6
D1
7
D1
8
U4
R40 22K
R48
10
R49
10
C19
223
C27 105
S1
1
G1
2
S2
3
G24D2
5
D2
6
D1
7
D1
8
U5
O/S 1
O/S 3
O/S2
O/S 4
O/S 5
O/S 6
R10 1M
C13
105
IC-Vcc
O/S 1
O/S 2
O/S 3
O/S 4
O/S 5
O/S 6
R29
NC
O/S
R16
1M\NC
Q3
2222
R15 100K
D4
BAV99
R27
100
IC-Vcc
Q8 2907
A K
ZD3
4.3V
C20
225(1206)
C21
225(1206)
1 2
CN5
R14 1M
C34
105
R3 100K
R24
NC
D8
2222
Q7 2907
A K
ZD2
4.3V
D7
2222
R33
NC
R31 NC
R30 560
R32 560
R26
NC
R35 150
R37 150
R39 150
R41 150
Q5 DTA143
Q4 DTA143
Q1
DTC143
D6
1N4148
D10 1 N4148
D12 1 N4148
D14 1 N4148
D16 1 N4148
D5 1N4148
D1/NC
BAW56K
D2/NC
BAW56K
D3/NC
BAW56K
D15
BAW56K
D13
BAW56K
D11
BAW56K
D9
BAW56K
1 2
3
4 5
CN3
CON5
1 2
3
4 5
CN4
CON5
C36
NC
C35
222
D23 BAV99
C53 222
C38 NC
D24
BAV99
C49
222
C50 NC
C46 222
C47 NC
C43
222
C44
NC
C40
222
C41 NC
B
Q11
2222
R58
10K
R59
30K
VCC / 8.2V
Q2
2N7002
Q10
DTA143
A
Q6
2N7002
R60
1K
C37
471
C39
471
C42
471
C51 471
C48
471
C45
471
U1A
LM393
U1B
LM393
B
B
R56 2K
R57
4.7K
C52 105
C55 105
R61
510K
R63
510K
C
C
D27
BAV99
A
D
D
D25
1N4148
D26
1N4148
R62
3K
R28
3K
C54 105
C56 104
R64
10K
I_17930_035.eps
220408
I I
INVERTER
Circuit Diagrams and PWB Layouts
70TCM2.0E LA 7.
Page 71
Circuit Diagrams and PWB Layouts
I_17930_037.eps
220408

Layout Inverter Panel (Top Side)

71TCM2.0E LA 7.

Layout Inverter Panel (Bottom Side)

I_17930_036.eps
220408
Page 72
IR
VCC GND
RW
GND
IR
+5V
LED1
LED2
2
13
D1
B
E
C
Q2
BT3906
R4
3K3
B
C
E
Q1
BT3904
4K7
R7
4K7
R2
6V3
47U
C3
1K
R3
R52
4K7
4K7
R1
E
C
B
BT3904
Q5
R51
4K7
D3
1
2
3
4
5
P1
G1
R6
100R
100R
R5
10U
C2
C1
10U
R9
4K7
I_17930_033.eps
220408
J J
IR & LED
I_17930_034.eps
220408
Personal Notes:
E_06532_012.eps
131004

IR LED Panel

Circuit Diagrams and PWB Layouts
72TCM2.0E LA 7.

Layout IR LED Panel (Top Side)

Page 73

8. Alignments

Alignments
EN 73TCM2.0E LA 8.
Index of this chapter:

8.1 Electrical Alignments

8.2 Hardware Alignments

8.3 Software Alignments

Note:
The Service Modes are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.
8.1 Electrical Alignments
Perform all electrical adjustments under the following conditions:
Power supply voltage (depends on region): – AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%). – AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%). – EU: 230 VAC / 50 Hz (± 10%). – LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%). – US: 120 VAC / 60 Hz (± 10%).
Connect the set to the mains via an isolation transformer with low internal resistance.
Allow the set to warm up for approximately 60 minutes.
Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heatsinks as ground.
Test probe: R
Use an isolated trimmer/screwdriver to perform alignments.
> 10 MΩ, Ci < 20 pF.
i
Table 8-2 Alignment for 26" with a colour analyser
Cool (11000K) Normal (9000K) Warm (6500K)
x (70 IRE) 0.278 +/- 0.003 0.289 +/- 0.003 0.314 +/- 0.003
y (70 IRE) 0.278 +/- 0.003 0.291 +/- 0.003 0.319 +/- 0.003

8.3.2 Display Code

When after an SSB or display exchange, the display option code is not set properly; it will result in a TV with “no display” or strange resolution. Therefore, it is required to set this display option code after such a repair. To do so, press (slowly) the following key sequence on a standard RC transmitter: “062598 directly followed by “MENU” and “xxx”, where “xxx” is a 3 digit decimal value of the panel type: see column “Display code” in table below. When ready, the set will go to stand-by. After this, perform a cold start.
LCD Panel: Display Code:
AUO 19” 096
CMO 19” - M190Z1-L01 094
LG 20” - LC201V02-SDD1 093
AUO 22” 097
CMO 22” - M220Z1-L03 022
AUO 26” - T260XW03 V3 030
AUO 26” VM 098
CMO 26” 095
8.2 Hardware Alignments
Not applicable.
8.3 Software Alignments

8.3.1 White Balance Adjustment (VGA Mode)

Only VGA input requires colour temperature adjustment as all other inputs or relative ones. Both WARM and COOL colour coordinates are also relatives to NORMAL colour temperature mode ones. Equipment requirements: Colour analyser (e.g Minolta CA-
210).
Pre conditions:
Picture Preset: Standard.
Black Expand: Off.
Tone: Normal.
Dynamic Contrast: Off.
Colour Temp Alignment
Apply a 1366×768@50Hz signal with white pattern, set “brightness” at 100%, and “contrast” at 50%. Adjust the R, G, and B sub-gain for the screen centre. The 1931 CIE chromaticity (x, y) co-ordinates shall be:
Table 8-1 Alignment for 19", 20", and 22" with colour
analyser
Cool (9000K) Normal (8 000K) Warm (6500K)
x (70 IRE) 0.289 +/- 0.003 0.296 +/- 0.003 0.314 +/- 0.003
y (70 IRE) 0.291 +/- 0.003 0.299 +/- 0.003 0.319 +/- 0.003
Page 74
EN 74 TCM2.0E LA9.
I_17951_012.eps
060808
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets

Index of this chapter:

9.1 Introduction

9.2 Block Diagram

9.3 Abbreviation List
9.4 IC Data Sheets
9.1 Introduction
This chassis is a digital derivative from the TCM1.0E LA chassis and supports DVB-T reception. It uses the Mediatek MT5335 main chip. It processes the following input/output signals:
Analog and digital RF signals (PAL B/G, D/K, I, SECAM B/ G, D/K, L/L, DVB-T)
SCART input signals (CVBS & RGB)
CMP input signals (YPbPr)
VGA input signals
HDMI input signals, v1.2 compliant, with HDCP, audio included as EIA-861B standard
S-Video input
Headphone output
SPDIF output.
9.2 Block Diagram
Notes:
•Only new circuits (circuits that are not published recently) are described.
Figures can deviate slightly from the actual situation, due to different set executions.
The platform is also designed for the lowest power consumption in off/stand-by mode (<0.3W) to fulfil new Philips CE environment policy requirement. The MT5335 is surrounded by a tuner, a video demodulator, a HDMI interface, SDR and flash memory, an audio amplifier, and optionally a stand-by microprocessor (26"). For the smaller set versions also the inverter board is serviceable.
For the block diagram, refer also to chapter 6 “Block diagrams, Test Point Overviews, and Waveforms”.

Figure 9-1 Block diagram

Page 75
Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 75TCM2.0E LA 9.

9.3 Abbreviation List

0/6/12 SCART switch control signal on A/V
board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3
format 1080i 1080 visible lines, interlaced 1080p 1080 visible lines, progressive scan 2DNR Spatial (2D) Noise Reduction 3DNR Temporal (3D) Noise Reduction AARA Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio ACI Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page ADC Analogue to Digital Converter AFC Automatic Frequency Control: control
signal used to tune to the correct
frequency AGC Automatic Gain Control: algorithm that
controls the video input of the feature
box AM Amplitude Modulation ANR Automatic Noise Reduction: one of the
algorithms of Auto TV AP Asia Pacific AR Aspect Ratio: 4 by 3 or 16 by 9 ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA ATV See Auto TV Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way AV External Audio Video AVC Audio Video Controller AVIP Audio Video Input Processor B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz BLR Board-Level Repair BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries B-TXT Blue TeleteXT C Centre channel (audio) CEC Consumer Electronics Control bus:
remote control bus on HDMI
connections CL Constant Level: audio output to
connect with an external amplifier CLR Component Level Repair COLUMBUS COlor LUMinance Baseband
Universal Sub-system ComPair Computer aided rePair CP Connected Planet / Copy Protection CSM Customer Service Mode CTI Color Transient Improvement:
manipulates steepness of chroma
transients CVBS Composite Video Blanking and
Synchronization DAC Digital to Analogue Converter DBE Dynamic Bass Enhancement: extra
low frequency amplification
DDC See “E-DDC” D/K Monochrome TV system. Sound
DFI Dynamic Frame Insertion DFU Directions For Use: owner's manual DMR Digital Media Reader: card reader DMSD Digital Multi Standard Decoding DNM Digital Natural Motion DNR Digital Noise Reduction: noise
DRAM Dynamic RAM DRM Digital Rights Management DSP Digital Signal Processing DST Dealer Service Tool: special remote
DTCP Digital Transmission Content
DVB-C Digital Video Broadcast - Cable DVB-T Digital Video Broadcast - Terrestrial DVD Digital Versatile Disc DVI(-d) Digital Visual Interface (d= digital only) E-DDC Enhanced Display Data Channel
EDID Extended Display Identification Data
EEPROM Electrically Erasable and
EMI Electro Magnetic Interference EPLD Erasable Programmable Logic Device EU Europe EXT EXTernal (source), entering the set by
FBL Fast BLanking: DC signal
FDS Full Dual Screen (same as FDW) FDW Full Dual Window (same as FDS) FLASH FLASH memory FM Field Memory or Frequency
FPGA Field-Programmable Gate Array FTV Flat TeleVision Gb/s Giga bits per second G-TXT Green TeleteXT H H_sync to the module HD High Definition HDD Hard Disk Drive HDCP High-bandwidth Digital Content
HDMI High Definition Multimedia Interface HP HeadPhone I Monochrome TV system. Sound
2
C Inter IC bus
I
2
I
D Inter IC Data bus
2
S Inter IC Sound bus
I IF Intermediate Frequency Interlaced Scan mode where two fields are used
carrier distance is 6.5 MHz
reduction feature of the set
control designed for service technicians
Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394
(VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display.
(VESA standard)
Programmable Read Only Memory
SCART or by cinches (jacks)
accompanying RGB signals
Modulation
Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding.
carrier distance is 6.0 MHz
to form one frame. Each field contains
Page 76
EN 76 TCM2.0E LA9.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
half the number of the total amount of lines. The fields are written in “pairs”,
causing line flicker. IR Infra Red IRQ Interrupt Request ITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz. ITV Institutional TeleVision; TV sets for
hotels, hospitals etc. JOP Jaguar Output Processor LS Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences LATAM Latin America LCD Liquid Crystal Display LED Light Emitting Diode L/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I LORE LOcal REgression approximation
noise reduction LPL LG.Philips LCD (supplier) LS Loudspeaker LVDS Low Voltage Differential Signalling Mbps Mega bits per second M/N Monochrome TV system. Sound
carrier distance is 4.5 MHz MIPS Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor MOP Matrix Output Processor MOSFET Metal Oxide Silicon Field Effect
Transistor, switching device MPEG Motion Pictures Experts Group MPIF Multi Platform InterFace MUTE MUTE Line NC Not Connected NICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe. NTC Negative Temperature Coefficient,
non-linear resistor NTSC National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air) NVM Non-Volatile Memory: IC containing
TV related data such as alignments O/C Open Circuit OSD On Screen Display OTC On screen display Teletext and
Control; also called Artistic (SAA5800) P50 Project 50: communication protocol
between TV and peripherals PAL Phase Alternating Line. Color system
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
3.575612 MHz and PAL N= 3.582056
MHz) PCB Printed Circuit Board (same as “PWB”) PCM Pulse Code Modulation PDP Plasma Display Panel PFC Power Factor Corrector (or Pre-
conditioner) PIP Picture In Picture PLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency POR Power On Reset, signal to reset the uP Progressive Scan Scan mode where all scan lines are
displayed in one frame at the same
time, creating a double vertical
resolution. PTC Positive Temperature Coefficient,
non-linear resistor PWB Printed Wiring Board (same as “PCB”) PWM Pulse Width Modulation QRC Quasi Resonant Converter QTNR Quality Temporal Noise Reduction QVCP Quality Video Composition Processor RAM Random Access Memory RGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced. RC Remote Control RC5 / RC6 Signal protocol from the remote
control receiver RESET RESET signal ROM Read Only Memory R-TXT Red TeleteXT SAM Service Alignment Mode S/C Short Circuit SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs SCL Serial Clock I SCL-F CLock Signal on Fast I SD Standard Definition SDA Serial Data I SDA-F DAta Signal on Fast I
2
C
2
C bus
2
C
2
C bus SDI Serial Digital Interface, see “ITU-656” SDRAM Synchronous DRAM SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz SIF Sound Intermediate Frequency SMPS Switched Mode Power Supply SoC System on Chip SOG Sync On Green SOPS Self Oscillating Power Supply S/PDIF Sony Philips Digital InterFace SRAM Static RAM SRP Service Reference Protocol SSB Small Signal Board STBY STand-BY SVGA 800x600 (4:3) SVHS Super Video Home System SW Software SWAN Spatial temporal Weighted Averaging
Noise reduction SXGA 1280x1024 TFT Thin Film Transistor THD Total Harmonic Distortion TMDS Transmission Minimized Differential
Signalling TXT TeleteXT TXT-DW Dual Window with TeleteXT UI User Interface uP Microprocessor UXGA 1600x1200 (4:3)
Page 77
Circuit Descriptions, Abbreviation List, and IC Data Sheets
V V-sync to the module VCR Video Cassette Recorder VESA Video Electronics Standards
Association VGA 640x480 (4:3) VL Variable Level out: processed audio
output toward external amplifier VSB Vestigial Side Band; modulation
method WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound WXGA 1280x768 (15:9) XTAL Quartz crystal XGA 1024x768 (4:3) Y Luminance signal Y/C Luminance (Y) and Chrominance (C)
signal YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y) YUV Component video
EN 77TCM2.0E LA 9.
Page 78
EN 78 TCM2.0E LA9.
I_17950_048.eps
080808
Block Diagram
Pin Configuration

9.4 IC Data Sheets

This section shows the internal block diagrams and pin layouts of ICs that are drawn as "black boxes" in the electrical diagrams (with the exception of "memory" and "logic" ICs).

9.4.1 Diagram B, MT5133

Circuit Descriptions, Abbreviation List, and IC Data Sheets
Figure 9-2 Block diagram & pin configuration
Page 79
Circuit Descriptions, Abbreviation List, and IC Data Sheets
TS
In
JPEG,MPEG
Component
Analog
Input
16-bit DDR
DRAM Bus
JTAG
IO Bus
USB2.0
UART
Serial IF
PWM
IrDA
PCR MS,SD,SM,xD
Audio DSP
Watchdog
CVBS/
YC Input
Audio I/F
SPDIF, I
2
S
RTC
2-D Graphic
Vplane
scaler
OSD
scaler
VADCx4
TS
Demux
TV
Decoder
HDMI In
I/F
LVDS
Audio Input
Mix and Post
Processing
DDR
DRAM
Controller
BIM
ARM
HDMI
Rx
Panel
VDO-In
NAND Flash
Audio DAC
CKGEN
Audio
Demod
De-interlace
Audio In
Audio
ADC
Serial Flash Servo ADC
Tuner
In
BScan
I_17950_049.eps
090508
Block Diagram
I_17950_050.eps
090508
Block Diagram

9.4.2 Diagram B, MT5335

EN 79TCM2.0E LA 9.

9.4.3 Diagram B, MT8295

Figure 9-3 Block diagram
Figure 9-4 Block diagram
Page 80
EN 80 TCM2.0E LA9.
Block Diagram
H_17370_074.eps
100807
DIGITAL VCO CONTROL AFC DETECTOR
RC VCO
VIF-PLL
VIF-AGCTUNER AGC
SUPPLY SIF-AGC
AUDIO PROCESSING
AND SWITCHES
NARROW-BAND
FM-PLL DEMODULATOR
SINGLE REFERENCE QSS MIXER
INTERCARRIER MIXER
AND AM DEMODULATOR
SOUND CARRIER
TRAPS
4.5 to 6.5 MHz
TAGC
C
VAGC(pos)
C
AGC(neg)
C
BL
VAGC
(1)
TOP
14 (15)
VPLL
19 (21) )32( 12)61( 51)71( 61)8( 9
4 (2)10 (9)
11 (10)
12 (11)18 (20)20 (22)
2 (31) 1 (30)
(18) 17
(7) 8 (3) 5
(4) 6
external reference signal
or 4 MHz crystal
REF AFC
AUD
CVBS
audio output
video output: 2 V (p-p) [1.1 V (p-p) without trap]
C
AF
SIOMADSDASCL
MAD
V
P
C
AGC
(6, 12, 13, 14, 17, 19, 25, 28, 29, 32) 13
n.c.AGND
7 (5) DGND
OUTPUT
PORTS
I
2
C-BUS TRANSCEIVER
22 (24)3 (1)
LLPMF2PO1PO
DEEM
AFD
sound intercarrier output
and MAD select
FM-PLL
filter
VIF-PLL
filter
de-emphasis
network
VIF2 VIF1
24 (27) 23 (26)
SIF2 SIF1
TDA9885 TDA9886
(1) Not connected for TDA9885. Pin numbers for TDA9885HN and TDA9886HN in parenthesis.
I_17930_072.eps
250408

9.4.4 Diagram B, SIL9185

Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.5 Diagram B, TDA9886

Figure 9-5 Block diagram
Figure 9-6 Block diagram
Page 81

9.4.6 Diagram B, V386

RxIN0-
RxIN0+
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
LVDS to TTL
De-serializer
RED
PLL
GREEN
BLUE
VSYNC
RxCLKOUT
PWRDWN
HSYNC
DATA ENABLE
CONTROL
8
8
8
V386
RxOUT0..27
12
1
11
2
10
RxOUT22
3
9
RxOUT23
4 5
6 7 8
16
15
14
13
56-pin TSSOP
17 18 19
20 21 22 23 24
25 26 27 28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RxOUT24
GND
RxOUT26 RxOUT27
RxOUT25
RxI N0-
RxI N0+
RxI N1-
RxI N1+
LVDS_VCC
LVDS_GND
RxI N2-
RxI N2+
RxCLKI N-
RxCLKI N+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
RxOUT2 RxOUT1
VCC
RxOUT8
RxOUT12
VCC
RxOUT3
RxOUT4
RxOUT5
GND RxOUT6
RxOUT7
RxOUT9
GND
RxOUT10
RxOUT11
VCC
RxOUT13
GND
RxOUT14
RxOUT15
RxOUT16
VCC
V386
PWRDWN
RxCLKOUT
RxOUT0
49
50
51
52
53
54
55
56
LVDS_GND
RxI N3-
RxI N3+
GND
RxOUT17
RxOUT18
RxOUT19
RxOUT20
RxOUT21
I_17950_051.eps
090508
Block Diagram
Pin Configuration
Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 81TCM2.0E LA 9.
Figure 9-7 Block diagram & pin configuration
Page 82
EN 82 TCM2.0E LA9.
I_17930_073.eps
250408

9.4.7 Diagram B, WM8501

Circuit Descriptions, Abbreviation List, and IC Data Sheets
Figure 9-8 Block diagram
Page 83

9.4.8 Diagram B, WT6702

Turbo 8031 MCU
Key Pad ADC
RTC
2nd SIIC
3rd SIIC
1st SIIC
PWM
Interrupt
Processor
4 IRQ
Processor
HV DPMS
Detector
Watchdog
timer
Reset
Processor
Clock
Processor
RC
Oscillator
Clock off &
Wake Up
GPIO
Processor
IR Detector
32K Oscillator
8K bytes code
flash
internal bus
8051
UART,Timer0,
Timer1
Internal 256
bytes SRAM
WT6702F_S200
20 19 18 17 16 15 14 13 12
1 2 3 4 5 6 7 8 9 10 11
GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2
GPIOA4/SCL3/P1.0 GPIOA5/SDA3/P1.1
GPIOA0/AD0 GPIOA3/AD3/IR
VDD_RTC VDD
HIN/GPIOB5 VIN/GPIOB4
IRQ1/P1.3/GPIOB3
TXD/IRQ2/GPIOB6
VSS
32KOSCO
32KOSCI
NRST
PWM1/GPIOC1
RXD/IRQ3/GPIOB7
WT6702F_S161
16 15 14 13 12 11
1 2 3 4 5 6 7
98
10
VDD
NIV/4BOIPG5BOIPG/NIH
TXD/IRQ2/GPIOB6
VSS
NRST
PWM1/GPIOC1
RXD/IRQ3/GPIOB7
GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2
GPIOA0/AD0 GPIOA3/AD3/IR
32KOSCO
32KOSCI
WT6702F_S240
22 21 20 19 18 17 16 15 14 13
HIN/GPIOB5 VIN/GPIOB4
GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2
GPIOA4/SCL3/P1.0 GPIOA5/SDA3/P1.1
IRQ0/P1.2/GPIOB2
IRQ1/P1.3/GPIOB3
TXD/IRQ2/GPIOB6
VSS
23
24
1 2 3 4 5 6 7 8 9 10 11 12
32KOSCO
32KOSCI
NRST
GPIOA0/AD0 GPIOA1/AD1 GPIOA2/AD2 GPIOA3/AD3/IR
PWM1/GPIOC1 PWM0/GPIOC0
RXD/IRQ3/GPIOB7
VDD_RTC VDD
Package Type Package Outline
SOP 16 pin 150mil SOP 20 pin 300mil
SSOP 20 pin 150mil
SOP 24 pin 300mil
I_17950_052.eps
090508
Block Diagram
Pin Configuration
Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 83TCM2.0E LA 9.
Figure 9-9 Block diagram & pin configuration
Page 84
EN 84 TCM2.0E LA9.
Address
Generator
Memory Array
Y-Decoder
X-Decoder
additional 4Kb
Data
Register
SRAM
Buffer
SI
CS#, ACC,
WP#,HOLD#
SCLK Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
SO
16-PIN SOP (300 mil)
1 2
3
4 5 6 7
8
HOLD#
VCC
NC PO2 PO1 PO0
CS#
SO/PO7
16 15 14 13 12 11 10
9
SCLK SI
PO6 PO5 PO4 PO3 GND WP#/ACC
I_17950_053.eps
090508
Block Diagram
Pin Configuration

9.4.9 Diagram B, MX25L3205

Circuit Descriptions, Abbreviation List, and IC Data Sheets
Figure 9-10 Block diagram & pin configuration
Page 85

9.4.10 Diagram B, TDA7266

1
2
4
Vref
7YB-TS
IN1
0.22μF
V
CC
133
+
-
-
+
OUT1+
OUT1-
15
14
12
6ETUM
IN2
0.22μF +
-
-
+
OUT2+
OUT2-
8
9
S-GND
PW-GND
470μF 100nF
1
2
3
4
5
6
7
9
10
11
8
N.C. N.C. S-GND PW-GND
OUT2+ OUT2­VCC IN2
ST-BY MUTE N.C. IN1 V
CC
OUT1­OUT1+
13
14
15
12
I_17950_054.eps
090508
Block Diagram
Pin Configuration
Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 85TCM2.0E LA 9.
Figure 9-11 Block diagram & pin configuration
Page 86
EN 86 TCM2.0E LA10.
Spare Parts List & CTN Overview

10. Spare Parts List & CTN Overview

For the latest spare part overview, please consult the Philips Service website.
Table 10-1 Sets described in this manual:
CTN Styling Published in:
19PFL5403/60 ME8 3122 785 17952
19PFL5403D/10 ME8 3122 785 17951
19PFL5403S/60 ME8 3122 785 17951
20HFL3330D/10 MG8 3122 785 17951
20PFL3403D/10 MG8 3122 785 17950
22PFL5403/60 ME8 3122 785 17952
22PFL5403D/10 ME8 3122 785 17951
22PFL5403S/60 ME8 3122 785 17952
26PFL3403D/10 MG8 3122 785 17951
26PFL5403/60 ME8 3122 785 17952
26PFL5403D/10 ME8 3122 785 17950
26PFL5403S/60 ME8 3122 785 17952

11. Revision List

Manual xxxx xxx xxxx.0
First release.
Manual xxxx xxx xxxx.1
All Chapters: Sets added (see table chapter 10).
Frontpage: Styling ME8 added.
Chapter 5: In SAM mode, item “Options” removed.
Chapter 5: Error 11 removed from error code overview.
Chapter 6: Wiring diagrams added.
Chapter 8: Display option codes added.
Chapter 9: Block diagram added.
Chapter 10: CTN overview added.
Manual xxxx xxx xxxx.2
All Chapters: Added Russian sets (xxPFLxxxx/60).
Chapter 5: Some textual changes in ComPair section.
Chapter 9: Abbreviation list updated.
Manual xxxx xxx xxxx.3
Chapter 7: Added the schematics and layouts of SSB version 2 decoder).
(U503 in diagram SSBv2, B05 DVBT/CI
Loading...