Philips SCN26562C4N48 Datasheet
INTEGRATED CIRCUITS
SCN26562
Dual universal serial communications
controller (DUSCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
DESCRIPTION
The Philips Semiconductors SCN26562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN26562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multi-function counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
DUSCC well suited for dual-speed channel applications. Data rates
up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
This document contains the electrical specifications for the
SCN26562. See SCN26562/SCN68562 User’s Guide for complete
functional description.
•Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
•Programmable data transfer mode: polled, interrupt, DMA, wait
•DMA interface
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
DMA EOPN input
•Interrupt capabilities
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions
•Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
•Modem controls
– RTS, CTS, DCD, and up to four general purpose pins per
channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
•On-chip oscillator for crystal
•TTL compatible
•Single +5V power supply
FEA TURES
General Features
•Dual full-duplex synchronous/asynchronous receiver and
transmitter
•Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
•Four character receiver and transmitter FIFOs
•0 to 4Mbit/sec data rate
•Programmable bit rate for each receiver and transmitter selectable
from:
– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
1995 May 01 853-0307 15179
Asynchronous Mode Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•Up to two stop bits programmable in 1/16-bit increments
•1X or 16X and Tx clock factors
•Parity, overrun, and framing error detection
•False start bit detection
•Start bit search 1/2-bit time after framing error detection
•Break generation with handshake for counting break characters
•Detection of start and end of received break
•Character compare with optional interrupt on match
•Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data
rate
2
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
Character-Oriented Protocol Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•LRC or CRC generation and checking
•Optional opening PAD transmission
•One or two SYN characters
•External sync capability
•SYN detection and optional stripping
•SYN or MARK line-fill on underrun
•Idle in MARK or SYNs
•Parity, FCS, overrun, and underrun error detection
BISYNC Features
•EBCDIC or ASCII header, text and control messages
•SYN, DLE stripping
•EOM (end of message) detection and transmission
•Auto transparent mode switching
•Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
•Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
•Character length: 5 to 8 bits
•Detection and transmission of residual character: 0–7 bits
•Automatic switch to programmed character length for I field
•Zero insertion and detection
•Optional opening PAD transmission
•Detection and generation of FLAG, ABORT, and IDLE bit patterns
•Detection and generation of shared (single) FLAG between
frames
•Detection of overlapping (shared zero) FLAGs
•ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun
•Idle in MARK or FLAGs
•Secondary address recognition including group and global
address
•Single- or dual-octet secondary address
•Extended address and control fields
•Short frame rejection for receiver
•Detection and notification of received end of message
•CRC generation and checking
•SDLC loop mode capability
ORDERING INFORMATION
VCC = +5V +5%, TA = 0°C to +70°C
DESCRIPTION
48-Pin Plastic Dual In-Line Package (DIP) SCN26562C4N48 SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SCN26562C4A52 SOT238-3
ABSOLUTE MAXIMUM RATINGS
SYMBOL
T
A
T
STG
V
CC
V
S
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature and thermal
resistance of 36°C/W junction to ambient for ceramic DIP, 40°C/W for plastic DIP, and 42°C/W for PLCC.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
Operating ambient temperature
Storage temperature -65 to +150 °C
Voltage from VCC to GND
Voltage from any pin to ground
1
PARAMETER RATING UNIT
2
3
3
Serial Data Rate =
4Mbps Maximum
0 to +70 °C
–0.5 to +7.0 V
–0.5 to VCC +0.5 V
DWG #
1995 May 01
3
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
PIN CONFIGURATIONS
IACKN
RTxDAKBN/
GPI1BN
IRQN
RDYN
RTSBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
RDN
RESETN
GND
1
2
A3
3
A2
4
A1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D7
19
D6
20
D5
21
D4
22
23
24
N PACKAGE
DIP
48
V
CC
47
A4
46
A5
45
A6
RTxDAKAN/
44
GPI1AN
43
X1/CLK
42
X2
RTSAN/
41
SYNOUTAN
40
TRxCA
39
RTxCA
DCDAN/
38
SYNIAN
37
RxDA
36
TxDA
TxDAKAN/
35
GPI2AN
RTxDRQAN/
34
GPO1AN
TxDRQAN/
33
GPO2AN/RTSAN
32
CTSAN/LCAN
31
D0
30
D1
29
D2
28
D3
27
EOPN
26
WRN
25
CEN
Figure 1. Pin Configurations
INDEX
CORNER
PIN FUNCTION PIN FUNCTION
A PACKAGE
7
1
8
PLCC
20
21
TOP VIEW
1 IACKN 27 CEN
2 A3 28 WRN
3 A2 29 EOPN
4A1 30D3
5 RTxDAKBN/ 31 D2
GPI1BN 32 D1
6 IRQN 33 D0
7NC 34NC
8 RDYN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/
SYNOUTBN GPO2AN/RTSAN
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/
SYNIBN GPI2AN
13 NC 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 NC
16 TxDAKBN/ 42 DCDAN/
GPI2BN SYNIAN
17 RTxDRQBN/ 43 RTxCA
GPO1BN 44 TRxCA
18 TxDRQBN/ 45 RTSAN/
GPO2BN/RTSBN SYNOUTAN
19 CTSBN/LCBN 46 X2
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 RDN 50 A5
25 RESETN 51 A4
26 GND 52 V
47
46
34
33
CC
SD00203
1995 May 01
4
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
BLOCK DIAGRAM
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
D0–D7
RDYN
WRN
RDN
A1–A6
CEN
RESETN
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
EOPN
BUS
BUFFER
MPU
INTERFACE
DMA
INTERFACE
INTERFACE/
OPERATION
CONTROL
ADDRESS
DECODE
R/W
DECODE
DMA
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
GSR
CMR1A/B
CMR2A/B
OMRA/B
INTERNAL BUS
DPLLA/B
BRG
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTCRA/B
CTPRHA/B
CTPRLA/B
CTHA/B
CTLA/B
TRANSMIT
A/B
TRANS CLK
MUX
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
4 DEEP
FIFO
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
TxD A/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
1995 May 01
TRxCA/B
RTxCA/B
IRQN
IACKN
X1/CLK
CONTROL
SPECIAL
FUNCTION
PINS
INTERRUPT
CONTROL
ICRA/B
IERA/B
IVR
IVRM
DUSCC
LOGIC
X2
OSCILLATOR
RECEIVER
A/B
RCVR CLK
MUX
RPRA/B
RTRA/B
S1RA/B
S2RA/B
RCVR
SHIFT REG
RECEIVER
4 DEEP
FIFO
CRC
ACCUM
BISYNC
COMPARE
LOGIC
RxD A/B
SD00204
Figure 2. Block Diagram
5
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE NAME AND FUNCTION
DIP PLCC
A1–A6 4–2,
D0–D7 31–28,
RDN 22 24 I Read strobe.
WRN 26 28 I Write strobe.
CEN 25 27 I Chip select.
RDYN 7 8 O Ready.
IRQN 6 6 O Interrupt request.
IACKN 1 1 I Interrupt acknowledge.
X1/CLK 43 47 I Crystal 1 or external clock.
X2 42 46 I Crystal 2.
RESETN 23 25 I Master reset.
RxDA, RxDB 37, 12 40, 14 I Channel A (B) receiver serial data.
TxDA, TxDB 36, 13 39, 15 O Channel A (B) transmitter serial data.
RTxCA,
RTxCB
TRxCA,
TRxCB
CTSA/BN,
LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
EOPN 27 29 I/O DMA transfer complete.
RTSA/BN,
SYNOUTA/BN
V
CC
GND 24 26 I Signal and power ground.
47–45
21–18
39, 10 43, 11 I/O Channel A (B) receiver/transmitter clock.
40, 9 44, 10 I/O Channel A (B) transmitter/receiver clock.
32, 17 35, 19 I/O Channel A (B) clear-to-send input or loop control output.
38, 11 42, 12 I Channel A (B) data carrier detected or external sync.
34, 15 37, 17 O Channel A (B) receiver/transmitter DMA service request or general purpose output.
33, 16 36, 18 O Channel A (B) transmitter DMA service request, general purpose output or request-to-send.
44, 5 48, 5 I Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1.
35, 14 38, 16 I Channel A (B) transmitter DMA acknowledge or general purpose input 2.
41, 8 45, 9 O Channel A (B) request-to-send or Sync detect.
48 52 I Power input.
4–2,
51–49
33–30,
23–20
I Address lines.
I/O Bidirectional data bus.
1995 May 01
6
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
5
100
5
IN
V
V
SCN26562Dual universal serial communications controller (DUSCC)
DC ELECTRICAL CHARACTERISTICS
1, 3
T
= 0°C to +70°C, VCC = 5.0V +5%
A
Input low voltage:
V
IL
All except X1/CLK 0.8 V
X1/CLK 0.4 V
Input high voltage:
V
IH
All except X1/CLK 2.0 V
X1/CLK 2.4 V
V
OL
Output low voltage:
All except IRQN IOL = 5.3mA V
IRQN IOL = 8.8mA 0.5 V
V
OH
Output high voltage: 0.5
(Except open drain outputs) IOH = –400µA 2.4 V
I
ILX1
I
IHX1
I
ILX2
I
IHX2
I
IL
I
I
I
OZH
I
OZL
I
ODL
X1/CLK input low current
X1/CLK input high current
X2 input low current
X2 input high current
Input low current
RESETN, TxDAKN, RxDAKN VIN = 0 –40 µA
Input leakage current VIN = 0 to V
Output off current high, 3-State data bus VIN = V
Output off current low , 3-State data bus VIN = 0 –5
Open drain output low current in off
state: EOPN
3
3
3
3
VIN = 0, X2 = GND
VIN = VCC, X2 = GND
VIN = 0, X1 = open
VIN = VCC, X1 = open
CC
CC
VIN = 0
IRQN, RDYN
I
ODH
I
CC
C
C
C
IN
OUT
I/O
Open drain output high current in off
state: EOPN, IRQN, RDYN
=
IN
Power supply current VO = 0 to V
Input capacitance
Output capacitance
Input/output capacitance
2
2
2
VCC = GND = 0 10 pF
VCC = GND = 0 15 pF
VCC = GND = 0 20 pF
CC
CC
NOTES:
1. Parameters are valid over specified temperature range.
2. These values were not explicitly tested; they are guaranteed by design and characterization data.
3. X1/CLK and X2 are not tested with a crystal installed.
LIMITS
Min Typ Max
CC
–5.
–
0.0 mA
1.0 mA
µA
100 µA
–5 5 µA
µA
µA
–25 µA
–120 µA
–5
5 µA
275 mA
V
AC ELECTRICAL CHARACTERISTICS
1, 2, 3, 4
T
= 0°C to +70°C, VCC = 5V +5%
A
LIMITS
SYMBOL PARAMETER
SCN26562C4 SCN26562C2
Min Max Min Max
t
RELREH
RESETN low to RESETN high 1.2 1.2 µs
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a
transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V . All time measurements are referenced at input voltages
of 0.4V and 2.4V and output voltages of 1.2V and 2.0V , as appropriate.
3. See Figure 17 for test conditions for outputs.
4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
RESETN
t
RELREH
SD00205
Figure 3. Reset Timing
1995 May 01
7
UNIT
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