Philips scn26562 DATASHEETS

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1

1995 May 1 853-0307 15179

DESCRIPTION

The Philips Semiconductors SCN26562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN26562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.

The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multi-function counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
DUSCC well suited for dual-speed channel applications. Data rates
up to 4Mbits per second are supported.

The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.

Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.

This document contains the electrical specifications for the
SCN26562. See SCN26562/SCN68562 User’s Guide for complete
functional description.

FEATURES
General Features

•Dual full-duplex synchronous/asynchronous receiver and

transmitter

•Multiprotocol operation

– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,

etc.

– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity

•Four character receiver and transmitter FIFOs

•0 to 4Mbit/sec data rate

•Programmable bit rate for each receiver and transmitter selectable

from:

– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock
– Digital phase-locked loop

•Parity and FCS (frame check sequence LRC or CRC) generation

and checking

•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,

Manchester

•Programmable channel mode: full- and half-duplex, auto-echo, or

local loopback

•Programmable data transfer mode: polled, interrupt, DMA, wait

•DMA interface

– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or

DMA EOPN input

•Interrupt capabilities

– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions

•Multi-function programmable 16-bit counter/timer

– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement

•Modem controls

– RTS, CTS, DCD, and up to four general purpose pins per

channel

– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD

•On-chip oscillator for crystal

•TTL compatible

•Single +5V power supply

Asynchronous Mode Features

•Character length: 5 to 8 bits

•Odd or even parity, no parity, or force parity

•Up to two stop bits programmable in 1/16-bit increments

•1X or 16X and Tx clock factors

•Parity, overrun, and framing error detection

•False start bit detection

•Start bit search 1/2-bit time after framing error detection

•Break generation with handshake for counting break characters

•Detection of start and end of received break

•Character compare with optional interrupt on match

•Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data

rate

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1995 May 1

2

Character-Oriented Protocol Features

•Character length: 5 to 8 bits

•Odd or even parity, no parity, or force parity

•LRC or CRC generation and checking

•Optional opening PAD transmission

•One or two SYN characters

•External sync capability

•SYN detection and optional stripping

•SYN or MARK line-fill on underrun

•Idle in MARK or SYNs

•Parity, FCS, overrun, and underrun error detection

BISYNC Features

•EBCDIC or ASCII header, text and control messages

•SYN, DLE stripping

•EOM (end of message) detection and transmission

•Auto transparent mode switching

•Auto hunt after receipt of EOM sequence (with closing PAD check

after EOT or NAK)

•Control character sequence detection for both transparent and

normal text

Bit-Oriented Protocol Features

•Character length: 5 to 8 bits

•Detection and transmission of residual character: 0–7 bits

•Automatic switch to programmed character length for I field

•Zero insertion and detection

•Optional opening PAD transmission

•Detection and generation of FLAG, ABORT, and IDLE bit patterns

•Detection and generation of shared (single) FLAG between

frames

•Detection of overlapping (shared zero) FLAGs

•ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun

•Idle in MARK or FLAGs

•Secondary address recognition including group and global

address

•Single- or dual-octet secondary address

•Extended address and control fields

•Short frame rejection for receiver

•Detection and notification of received end of message

•CRC generation and checking

•SDLC loop mode capability

ORDERING INFORMATION

VCC = +5V +5%, TA = 0°C to +70°C

DESCRIPTION

Serial Data Rate =

4Mbps Maximum

DWG #

48-Pin Plastic Dual In-Line Package (DIP) SCN26562C4N48 SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SCN26562C4A52 SOT238-3

ABSOLUTE MAXIMUM RATINGS

1

SYMBOL PARAMETER RATING UNIT

T

A

Operating ambient temperature

2

0 to +70 °C

T

STG

Storage temperature -65 to +150 °C

V

CC

Voltage from VCC to GND

3

–0.5 to +7.0 V

V

S

Voltage from any pin to ground

3

–0.5 to VCC +0.5 V

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature and thermal
resistance of 36°C/W junction to ambient for ceramic DIP, 40°C/W for plastic DIP, and 42°C/W for PLCC.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1995 May 1

3

PIN CONFIGURATIONS

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

19
20

28
27
26
25

21
22
23
24

IACKN

A3
A2
A1

RTxDAKBN/

IRQN

RDYN

RTSBN/

TRxCB
RTxCB

DCDBN/

TxDAKBN/

RTxDRQBN/

TxDRQBN/

CTSBN/LCBN

D7
D6
D5
D4

RDN

RESETN

GND

CEN

EOPN

D3

D2

D1

D0

CTSAN/LCAN

TxDRQAN/

RTxDRQAN/

TxDAKAN/

TxDA

DCDAN/

RTxCA

TRxCA

RTSAN/

X2

X1/CLK

RTxDAKAN/

A6

A5

A4

V

CC

N PACKAGE

GPI1BN

SYNOUTBN

SYNIBN

RxDB

TxDB

GPI2BN

GPO1BN

GPO2BN/RTSBN

WRN

GPO2AN/RTSAN

GPO1AN

GPI2AN

RxDA

SYNIAN

SYNOUTAN

GPI1AN

DIP

PIN FUNCTION PIN FUNCTION

1 IACKN 27 CEN
2 A3 28 WRN
3 A2 29 EOPN
4 A1 30 D3
5 RTxDAKBN/ 31 D2

GPI1BN 32 D1
6 IRQN 33 D0
7 NC 34 NC
8 RDYN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/

SYNOUTBN GPO2AN/RTSAN
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/

SYNIBN GPI2AN
13 NC 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 NC
16 TxDAKBN/ 42 DCDAN/

GPI2BN SYNIAN
17 RTxDRQBN/ 43 RTxCA

GPO1BN 44 TRxCA
18 TxDRQBN/ 45 RTSAN/

GPO2BN/RTSBN SYNOUTAN
19 CTSBN/LCBN 46 X2
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 RDN 50 A5
25 RESETN 51 A4

26 GND 52 V

CC

1

46

20

33

47

34

21

8

PLCC

7

TOP VIEW

INDEX

CORNER

A PACKAGE

SD00203

Figure 1. Pin Configurations

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1995 May 1

4

BLOCK DIAGRAM

D0–D7

RDYN

RDN

A1–A6

CEN

RESETN

BUS

BUFFER

CHANNEL
MODE AND
TIMING A/B

DPLL CLK

MUX A/B

DPLLA/B

CTCRA/B
CTPRHA/B
CTPRLA/B

RxD A/B

TxD A/B

CONTROL

INTERNAL BUS

BRG

COUNTER

TIMER A/B

C/T CLK

MUX A/B

CTHA/B
CTLA/B

TRANS CLK

MUX

TRANSMIT

A/B

TPRA/B
TTRA/B

TX SHIFT

REG

TRANSMIT

4 DEEP

FIFO

CRC

GENERATOR

SPEC CHAR

GEN LOGIC

RCVR CLK

MUX

RCVR

SHIFT REG
RECEIVER

4 DEEP

FIFO
CRC

ACCUM

RECEIVER

A/B

RPRA/B
RTRA/B
S1RA/B
S2RA/B

BISYNC

COMPARE

LOGIC

ADDRESS

DECODE

DMA

CONTROL

INTERFACE/
OPERATION

CONTROL

CCRA/B
PCRA/B
RSRA/B

TRSRA/B

ICTSRA/B

R/W

DECODE

GSR
CMR1A/B
CMR2A/B

OMRA/B

MPU

INTERFACE

WRN

RTxDRQAN/GPO1AN

DMA

INTERFACE

RTxDRQBN/GPO1BN

TxDRQAN/GPO2AN

TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN

TxDAKAN/GPI2AN
TxDAKBN/GPI2BN

EOPN

TRxCA/B

SPECIAL

FUNCTION

PINS

RTxCA/B
CTSAN/LCAN
CTSBN/LCBN

DCDBN/SYNIBN

DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN

INTERRUPT

CONTROL

ICRA/B
IERA/B

IVR

IVRM

IRQN

IACKN

X1/CLK

X2

OSCILLATOR

DUSCC

LOGIC

SD00204

Figure 2. Block Diagram

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1995 May 1

5

PIN DESCRIPTION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

DIP PLCC

A1–A6 4–2,

47–45

4–2,

51–49

I Address lines.

D0–D7 31–28,

21–18

33–30,

23–20

I/O Bidirectional data bus.

RDN 22 24 I Read strobe.
WRN 26 28 I Write strobe.
CEN 25 27 I Chip select.
RDYN 7 8 O Ready.
IRQN 6 6 O Interrupt request.
IACKN 1 1 I Interrupt acknowledge.
X1/CLK 43 47 I Crystal 1 or external clock.
X2 42 46 I Crystal 2.
RESETN 23 25 I Master reset.
RxDA, RxDB 37, 12 40, 14 I Channel A (B) receiver serial data.
TxDA, TxDB 36, 13 39, 15 O Channel A (B) transmitter serial data.
RTxCA,

RTxCB

39, 10 43, 11 I/O Channel A (B) receiver/transmitter clock.

TRxCA,
TRxCB

40, 9 44, 10 I/O Channel A (B) transmitter/receiver clock.

CTSA/BN,
LCA/BN

32, 17 35, 19 I/O Channel A (B) clear-to-send input or loop control output.

DCDA/BN,
SYNIA/BN

38, 11 42, 12 I Channel A (B) data carrier detected or external sync.

RTxDRQA/BN,
GPO1A/BN

34, 15 37, 17 O Channel A (B) receiver/transmitter DMA service request or general purpose output.

TxDRQA/BN,
GPO2A/BN,
RTSA/BN

33, 16 36, 18 O Channel A (B) transmitter DMA service request, general purpose output or request-to-send.

RTxDAKA/BN,
GPI1A/BN

44, 5 48, 5 I Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1.

TxDAKA/BN,
GPI2A/BN

35, 14 38, 16 I Channel A (B) transmitter DMA acknowledge or general purpose input 2.

EOPN 27 29 I/O DMA transfer complete.
RTSA/BN,

SYNOUTA/BN

41, 8 45, 9 O Channel A (B) request-to-send or Sync detect.

V

CC

48 52 I Power input.

GND 24 26 I Signal and power ground.

Philips Semiconductors Product specification

SCN26562Dual universal serial communications controller (DUSCC)

1995 May 1

6

DC ELECTRICAL CHARACTERISTICS

1, 3

T

A

= 0°C to +70°C, VCC = 5.0V +5%

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

V

IL

V

IH

Input low voltage:
All except X1/CLK

X1/CLK
Input high voltage:
All except X1/CLK

X1/CLK

2.0

2.4

0.8

0.4

V

CC

V
V

V
V

V

OL

V

OH

Output low voltage:
All except IRQN

IRQN
Output high voltage:
(Except open drain outputs)

IOL = 5.3mA
I

OL

= 8.8mA

IOH = –400µA 2.4

0.5

0.5

V
V

V

I

ILX1

I

IHX1

X1/CLK input low current

3

X1/CLK input high current

3

VIN = 0, X2 = GND

V

IN

= VCC, X2 = GND

–5.5

0.0

1.0

mA
mA

I

ILX2

I

IHX2

X2 input low current

3

X2 input high current

3

VIN = 0, X1 = open

V

IN

= VCC, X1 = open

–100

100

µA
µA

I

IL

Input low current
RESETN, TxDAKN, RxDAKN

VIN = 0 –40 µA

I

I

Input leakage current VIN = 0 to V

CC

–5 5 µA

I

OZH

I

OZL

Output off current high, 3-State data bus
Output off current low, 3-State data bus

VIN = V

CC

VIN = 0 –5

5

µA
µA

I

ODL

I

ODH

Open drain output low current in off
state: EOPN

IRQN, RDYN
Open drain output high current in off
state: EOPN, IRQN, RDYN

VIN = 0

V

IN

= V

CC

–120

–5

–25

5

µA
µA

µA

I

CC

Power supply current VO = 0 to V

CC

275 mA

C

IN

C

OUT

C

I/O

Input capacitance

2

Output capacitance

2

Input/output capacitance

2

VCC = GND = 0
V

CC

= GND = 0

V

CC

= GND = 0

10
15
20

pF
pF
pF

NOTES:

1. Parameters are valid over specified temperature range.

2. These values were not explicitly tested; they are guaranteed by design and characterization data.

3. X1/CLK and X2 are not tested with a crystal installed.

AC ELECTRICAL CHARACTERISTICS

1, 2, 3, 4

T

A

= 0°C to +70°C, VCC = 5V +5%

LIMITS

SYMBOL

PARAMETER

SCN26562C4 SCN26562C2

UNIT

Min Max Min Max

t

RELREH

RESETN low to RESETN high 1.2 1.2 µs

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a
transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V . All time measurements are referenced at input voltages
of 0.4V and 2.4V and output voltages of 1.2V and 2.0V , as appropriate.

3. See Figure 17 for test conditions for outputs.

4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.

t

RELREH

RESETN

SD00205

Figure 3. Reset Timing